Semiconductor chip, method of manufacturing semiconductor chip and semiconductor package including semiconductor chip

Abstract

To provide a semiconductor chip, a method of manufacturing the semiconductor chip, and a semiconductor package including the semiconductor chip.SOLUTION: A semiconductor chip 100 includes: a semiconductor substrate 102 having a first surface and a second surface 102F opposite to the first surface; an interconnect structure 152 disposed on the second surface of the semiconductor substrate; a plurality of conductive patterns 162 apart from the semiconductor substrate with the interconnect structure therebetween and each connected to the interconnect structure; a compensation pattern 174 apart from the plurality of conductive patterns on the interconnect structure in a horizontal direction and farther from the second surface of the semiconductor substrate than the plurality of conductive patterns; and an insulating spacer 164 placed between the plurality of conductive patterns and the compensation pattern.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor chip, a method for manufacturing the semiconductor chip, and a semiconductor package including the semiconductor chip.

Background Art

[0002] In response to the rapid development of the electronics industry and user needs, electronic devices are becoming smaller and lighter. As a result, high integration is required for semiconductor chips used in electronic devices, and the design rules for components of semiconductor chips are further decreasing. Structures for improving the reliability of thin semiconductor chips and semiconductor packages including the same have been proposed.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The problem to be solved by the technical idea of the present invention is to provide a semiconductor chip with improved reliability.

[0004] Another problem to be solved by the technical idea of the present invention is to provide a method for manufacturing a semiconductor chip with improved reliability.

[0005] Another problem to be solved by the technical idea of the present invention is to provide a semiconductor package including a semiconductor chip with improved reliability.

Means for Solving the Problems

[0006] A semiconductor chip according to one aspect of the technical idea of the present invention includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a wiring structure disposed on the second surface of the semiconductor substrate; a plurality of conductive patterns spaced apart from the semiconductor substrate via the wiring structure and respectively connected to the wiring structure; a compensation pattern horizontally spaced apart from the plurality of conductive patterns on the wiring structure and farther from the second surface of the semiconductor substrate than the plurality of conductive patterns; and an insulating spacer interposed between the plurality of conductive patterns and the compensation pattern.

[0007] A semiconductor chip according to one aspect of the technical idea of the present invention includes a semiconductor substrate; a wiring structure disposed on the upper surface of the semiconductor substrate and including a plurality of wiring lines, a plurality of wiring vias, and a wiring insulating film surrounding the plurality of wiring lines and the plurality of wiring vias; a plurality of conductive patterns horizontally spaced apart from each other on the wiring structure and having a thickness along the vertical direction thicker than the plurality of wiring lines; an insulating spacer covering the plurality of conductive patterns and the wiring structure; a compensation pattern horizontally spaced apart from the plurality of conductive patterns via the insulating spacer on the insulating spacer; a front insulating film covering the plurality of conductive patterns, the compensation pattern, and the insulating spacer; and a plurality of front bonding pads passing through the front insulating film and the insulating spacer and respectively contacting the plurality of conductive patterns.

[0008] A semiconductor package according to one aspect of the technical idea of the present invention includes a first semiconductor chip and a second semiconductor chip joined to each other. The first semiconductor chip includes a first semiconductor substrate including a first surface and a second surface opposite to each other; a plurality of first back bonding pads on the first surface of the first semiconductor substrate; and a first back insulating film on the first surface of the first semiconductor substrate surrounding sidewalls of the plurality of first back bonding pads. The second semiconductor chip includes a second semiconductor substrate including a first surface opposite to the first semiconductor substrate and a second surface facing the first surface of the first semiconductor substrate; a wiring structure on the second surface of the second semiconductor substrate; a front wiring layer separated from the second semiconductor substrate through the wiring structure; a second front insulating film interposed between the front wiring layer and the first back insulating film and joined to the first back insulating film; and a plurality of second front bonding pads passing through the second front insulating film and joined to the plurality of first back bonding pads. The front wiring layer includes a first surface in contact with the wiring structure and a second surface opposite to the first surface, and a plurality of conductive patterns horizontally spaced apart from each other; a first surface facing the wiring structure and a second surface in contact with the second front insulating film opposite to the first surface, and a compensation pattern horizontally spaced apart from the plurality of conductive patterns; and an insulating spacer interposed between the plurality of conductive patterns and the compensation pattern and in contact with the second surface of the plurality of conductive patterns and the first surface of the compensation pattern. The plurality of second front bonding pads pass through the insulating spacer and are in contact with the second surface of the plurality of conductive patterns.

[0009] According to one aspect based on the technical idea of the present invention, a method for manufacturing a semiconductor chip includes: forming a plurality of conductive patterns horizontally spaced apart on a wiring structure formed on one surface of a semiconductor substrate; forming an insulating spacer that conformally covers the plurality of conductive patterns and the wiring structure; forming a compensation material film that covers the uneven structure formed by the plurality of conductive patterns and the insulating spacer; planarizing the compensation material film until the insulating spacer is exposed to form a compensation pattern; forming a front insulating film that covers the insulating spacer and the compensation pattern; forming a plurality of first openings that penetrate the front insulating film and the insulating spacer to expose the plurality of conductive patterns; and forming a plurality of front bonding pads that each fill the plurality of first openings.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and overlapping descriptions thereof are omitted.

[0012] FIG. 1 is a cross-sectional view showing a semiconductor chip 100 according to an embodiment based on the technical idea of the present invention. FIG. 2 is an enlarged view of the region displayed as "EXA1" in FIG. 1. FIG. 3 is an enlarged view of the region displayed as "EXA2" in FIG. 2. FIGS. 4A, 4B, and 4C are plan views showing a partial configuration of the semiconductor chip 100 according to an exemplary embodiment.

[0013] Referring to FIGS. 1 to 4, the semiconductor chip 100 includes a semiconductor substrate 102, an interconnect structure 152, a frontside interconnect layer 160, a frontside dielectric layer 182, and a plurality of frontside bonding pads 184. According to an exemplary embodiment, the frontside interconnect layer 160 includes a plurality of conductive patterns 162, insulating spacers 164, and compensation patterns 174.

[0014] The semiconductor substrate 102 includes a first surface 102B and a second surface 102F that are opposite to each other. The first surface 102B of the semiconductor substrate 102 is the backside surface of the semiconductor substrate 102, and the second surface 102F of the semiconductor substrate 102 may be the frontside surface of the semiconductor substrate 102. The first surface 102B of the semiconductor substrate 102 is the non-active surface of the semiconductor substrate 102, and the second surface 102F of the semiconductor substrate 102 may be the active surface of the semiconductor substrate 102.

[0015] Hereinafter, the direction parallel to the first surface 102B of the semiconductor substrate 102 is defined as the horizontal direction (X direction and / or Y direction), and the direction perpendicular to the first surface 102B of the semiconductor substrate 102 is defined as the vertical direction (Z direction). Also, the horizontal width means the length along the horizontal direction (X direction and / or Y direction), the vertical height means the length along the vertical direction (Z direction), and the vertical level means the distance from the first surface 102B of the semiconductor substrate 102 in the Z direction or along the Z direction.

[0016] Unless otherwise specified in this specification, the upper surface refers to the surface facing upward in the drawings, and the lower surface refers to the surface facing downward in the drawings. For example, in FIGS. 1 to 3, the first surface 102B of the semiconductor substrate 102 faces downward, and the second surface 102F is arranged to face upward. In this case, the first surface 102B, for example, the inactive surface of the semiconductor substrate 102, is also referred to as the lower surface of the semiconductor substrate 102. The second surface 102F, for example, the active surface of the semiconductor substrate 102, is referred to as the upper surface of the semiconductor substrate 102. In contrast, in the semiconductor package 1000 described later with reference to FIGS. 11 to 13, the semiconductor substrates 202 and 302 of the plurality of semiconductor chips 200 and 300 each have a face-down arrangement in which the active surface faces downward. In this case, the active surface is also referred to as the lower surface of the semiconductor substrates 202 and 302.

[0017] The semiconductor substrate 102 is formed from a semiconductor wafer. The semiconductor substrate 102 includes, for example, silicon (Si). Alternatively, the semiconductor substrate 102 includes a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The semiconductor substrate 102 includes a conductive region, for example, a well doped with impurities, or a structure doped with impurities. Further, the semiconductor substrate 102 may have various semiconductor elements formed on the second surface 102F and an element isolation structure such as an STI (shallow trench isolation) structure.

[0018] The various semiconductor devices (not shown) include memory devices and / or logic devices. Memory devices include, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), flash memory, EEPROM (Electrically Erasable and Programmable Read-Only Memory), PRAM (Phase-change Random Access Memory), MRAM (Magnetic Random Access Memory), or RRAM (Resistive Random Access Memory) devices. Logic devices include, for example, AND, NAND, OR, NOR, XOR (exclusive OR), XNOR (exclusive NOR), INV (inverter), ADD (adder), DLY (delay), FIL (filter), multiplexer (MXT / MXIT), OAI (OR / AND / INVERTER), AO (AND / OR), AOI (AND / OR / INVERTER), D flip-flop, reset flip-flop, master-slave flip-flop, latch, counter, or buffer devices. Also, logic devices may include a CPU (Central Processing Unit), MPU (Micro-Processor Unit), GPU (Graphic Processing Unit), or AP (Application Processor), etc.

[0019] In some embodiments, the second surface 102F is covered by the interlayer insulating film 104. For example, the interlayer insulating film 104 is configured to surround a plurality of semiconductor elements (not shown) formed on the second surface 102F of the semiconductor substrate 102 and insulate and protect the plurality of semiconductor elements (not shown) from each other. In some embodiments, the interlayer insulating film 104 includes a silicon oxide film, a silicon nitride film, or a combination thereof, but is not limited to the examples described above. In this specification, a layer including a plurality of semiconductor elements (not shown) and the interlayer insulating film 104 surrounding them is referred to as a semiconductor element layer.

[0020] According to an exemplary embodiment, the wiring structure 152 and the front wiring layer 160 are sequentially disposed on the interlayer insulating film 104. The wiring structure 152 is disposed on the second surface 102F of the semiconductor substrate 102. For example, the wiring structure 152 is disposed spaced apart from the semiconductor substrate 102 via the interlayer insulating film 104 on the second surface 102F of the semiconductor substrate 102. Although not shown, the plurality of semiconductor elements (not shown) may be connected to the wiring structure 152 via contacts (not shown) penetrating the interlayer insulating film 104.

[0021] According to an exemplary embodiment, the wiring structure 152 includes a first wiring layer 122 and a second wiring layer 142 sequentially stacked on the second surface 102F of the semiconductor substrate 102.

[0022] In some embodiments, the first wiring layer 122 includes a plurality of first interconnect lines 124, a plurality of first interconnect vias 126, and a first wiring insulating film 128. The plurality of first interconnect lines 124 and the plurality of first interconnect vias 126 are surrounded by the first wiring insulating film 128. The plurality of first interconnect lines 124 are spaced apart from each other in the vertical direction (Z direction) within the first wiring insulating film 128 and each extend in the horizontal direction (X direction and / or Y direction). For example, the plurality of first interconnect lines 124 are arranged at different vertical levels to form a multi-layer wiring structure. The plurality of first interconnect vias 126 extend from between the plurality of first interconnect lines 124 arranged at different vertical levels and electrically connect between the plurality of wiring lines located at different vertical levels.

[0023] In some embodiments, the second wiring layer 142 includes second wiring lines 144, a plurality of second interconnect vias 146, and a second wiring insulating film 148 surrounding the second wiring lines 144 and the plurality of second interconnect vias 146. In some embodiments, the second wiring lines 144 extend in the horizontal direction (X direction and / or Y direction). In some embodiments, the second wiring lines 144 not only have a linear shape but also include dot-shaped pad structures. The plurality of second interconnect vias 146 extend in the vertical direction (Z direction) within the second wiring insulating film 148. Some of the plurality of second interconnect vias 146 connect between the plurality of first interconnect lines 124 and the second wiring lines 144, and some of the other plurality of second interconnect vias 146 connect between the plurality of conductive patterns 162 and the second wiring lines 144.

[0024] In FIG. 2, the semiconductor chip 100 is illustrated as including five first wiring lines 124 arranged at different vertical levels, but is not limited thereto. For example, the semiconductor chip 100 may include one to four, or six or more first wiring lines 124. In FIG. 2, the semiconductor chip 100 is illustrated as including one second wiring line 144, but is not limited thereto. For example, the semiconductor chip 100 may include a plurality of second wiring lines 144 spaced apart in the vertical direction (Z direction) within the second wiring insulating film 148. In this case, the plurality of second wiring vias 146 connect between the plurality of second wiring lines 144 within the second wiring insulating film 148, between the lowermost second wiring line 144 and the uppermost first wiring line 124, and between the uppermost second wiring line 144 and the plurality of conductive patterns 162.

[0025] In some embodiments, the plurality of first wiring lines 124, the plurality of first wiring vias 126, the second wiring line 144, and the plurality of second wiring vias 146 each include a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof.

[0026] In some embodiments, the plurality of first wiring lines 124 and the plurality of first wiring vias 126 of the first wiring layer 122 may be formed of a material different from that of the second wiring line 144 and the plurality of second wiring vias 146 of the second wiring layer 142. In some other embodiments, the plurality of first wiring lines 124 and the plurality of first wiring vias 126 of the first wiring layer 122 may be formed of the same material as that of the second wiring line 144 and the plurality of second wiring vias 146 of the second wiring layer 142.

[0027] In some embodiments, the second wiring line 144 of the second wiring layer 142 has a vertical thickness thicker than that of the first wiring line 124 of the first wiring layer 122, and the second wiring via 146 of the second wiring layer 142 has a horizontal width larger than that of the first wiring via 126 of the first wiring layer 122.

[0028] In some embodiments, the first wiring insulating film 128 and the second wiring insulating film 148 each include an oxide film such as TEOS (tetraethyl orthosilicate), PSG (phosphor silicate glass), BPSG (boro-phosphor silicate glass), USG (undoped silicate glass), PE-TEOS (plasma enhanced-TEOS), HDP-CVD (high density plasma-chemical vapor deposition), a carbon-containing oxide film such as SiOC, SiCOH, a silicon nitride film, a carbon-containing nitride film, or a combination thereof.

[0029] According to an exemplary embodiment, a front wiring layer 160 is disposed on the upper surface 142u of the second wiring layer 142, and a front insulating film 182 is disposed on the front wiring layer 160. For example, the front wiring layer 160 may be spaced apart from the substrate 102 via the wiring structure 152. In some embodiments, the upper surface 142u of the second wiring layer 142 is parallel to the second surface 102F of the substrate 102. For example, the upper surface 142u of the second wiring layer 142 extends flatly in the horizontal direction (X direction and / or Y direction).

[0030] According to an exemplary embodiment, a plurality of conductive patterns 162 are disposed spaced apart from each other on the upper surface 142u of the second wiring layer 142. The plurality of conductive patterns 162 each have a first surface 162a facing the semiconductor substrate 102 and a second surface 162b facing away from the semiconductor substrate 102. The plurality of conductive patterns 162 are in contact with the upper surface 142u of the second wiring layer 142. According to an exemplary embodiment, the first surface 162a of the plurality of conductive patterns 162 is in contact with a part of the plurality of second wiring vias 146 that is exposed on the upper surface 142u of the second wiring layer 142, and the plurality of conductive patterns 162 are electrically connected to the wiring lines 124 and 144 and the wiring vias 126 and 146 of the wiring structure 152. The first surface 162a of the plurality of conductive patterns 162 includes a portion in contact with the second wiring insulating film 148. In FIGS. 1 to 3, the first surface 162a is referred to as the lower surface of the plurality of conductive patterns 162, and the second surface 162b is referred to as the upper surface of the plurality of conductive patterns 162.

[0031] According to an exemplary embodiment, the insulating spacer 164 covers the plurality of conductive patterns 162 and the upper surface 142u of the second wiring layer 142. In some embodiments, the insulating spacer 164 is in contact with a portion of the second surface 162b, the sidewall 162s of the plurality of conductive patterns 162, and the upper surface 142u of the second wiring layer 142 that does not overlap perpendicularly with the plurality of conductive patterns 162. In some embodiments, the insulating spacer 164 includes a portion interposed between the front insulating film 182 and the plurality of conductive patterns 162. For example, the second surface 162b of the plurality of conductive patterns 162 includes a portion facing the front insulating film 182 via the insulating spacer 164.

[0032] According to an exemplary embodiment, the compensation pattern 174 is disposed on the insulating spacer 164 and spaced apart from the plurality of conductive patterns 162 in the horizontal direction (X direction and / or Y direction). The insulating spacer 164 is interposed between the plurality of conductive patterns 162 and the compensation pattern 174.

[0033] The compensation pattern 174 has a first surface 174a facing the semiconductor substrate 102 and a second surface 174b facing away from the semiconductor substrate 102. According to an exemplary embodiment, the first surface 174a of the compensation pattern 174 and the sidewall 174s are in contact with the insulating spacer 164. The compensation pattern 174 faces the upper surface 142u of the second wiring layer 142 through the insulating spacer 164. For example, the insulating spacer 164 includes a portion interposed between the compensation pattern 174 and the wiring structure 152.

[0034] According to an exemplary embodiment, the plurality of conductive patterns 162 are disposed closer to the semiconductor substrate 102 than the compensation pattern 174. In some embodiments, the first surface 174a of the compensation pattern 174 is disposed at a vertical level higher than the first surface 162a of the plurality of conductive patterns 162 but lower than the second surface 162b of the plurality of conductive patterns 162. For example, the first surface 162a of the plurality of conductive patterns 162 is closer to the second surface 102F of the semiconductor substrate 102 than the first surface 174a of the compensation pattern 174.

[0035] According to an exemplary embodiment, a front insulating film 182 is disposed on the front wiring layer 160. The second surface 174b of the compensation pattern 174 and the uppermost surface 164um of the insulating spacer 164 are covered by the front insulating film 182. For example, the uppermost surface 164um of the insulating spacer 164 may be the upper surface of a portion of the insulating spacer 164 that does not vertically overlap with the compensation pattern 174. For example, the uppermost surface 164um of the insulating spacer 164 may be the upper surface of a portion of the insulating spacer 164 that is farthest from the second surface 102F of the semiconductor substrate 102.

[0036] In some embodiments, the second surface 174b of the compensation pattern 174 is disposed at a vertical level higher than the second surface 162b of the plurality of conductive patterns 162. For example, the second surface 162b of the plurality of conductive patterns 162 is closer to the second surface 102F of the semiconductor substrate 102 than the second surface 174b of the compensation pattern 174.

[0037] According to an exemplary embodiment, the sidewall 174s of the compensation pattern 174 faces the sidewalls 162s of the plurality of conductive patterns 162 via the insulating spacer 164. According to an exemplary embodiment, the sidewalls 162s of the plurality of conductive patterns 162 are separated from the sidewall 174s of the compensation pattern 174 by a first isolation distance da1 in the horizontal direction (X direction and / or Y direction). In some embodiments, a first conductive pattern 162 and a second conductive pattern 162, which are selected from the plurality of conductive patterns 162 and are separated from each other via the compensation pattern 174, are each separated from the compensation pattern 174 by the first isolation distance da1. In some embodiments, portions of the sidewalls 162s of the plurality of conductive patterns 162 that face the compensation pattern 174 all have an equal first isolation distance da1.

[0038] According to an exemplary embodiment, the first surface 174a of the compensation pattern 174 is separated from the wiring structure 152 by a second isolation distance da2 in the vertical direction (Z direction) via the insulating spacer 164. In some embodiments, the second isolation distance da2 is substantially equal to the first isolation distance da1.

[0039] In some embodiments, the distance along the vertical direction (Z direction) between the second surface 162b of the plurality of conductive patterns 162 and the front insulating film 182 is substantially equal to the second isolation distance da2. In some other embodiments, the distance along the vertical direction (Z direction) between the second surface 162b of the plurality of conductive patterns 162 and the front insulating film 182 is different from the second isolation distance da2. For example, the distance along the vertical direction (Z direction) between the second surface 162b of the plurality of conductive patterns 162 and the front insulating film 182 is smaller than the distance along the vertical direction (Z direction) between the first surface 174a of the compensation pattern 174 and the wiring structure 152.

[0040] In FIGS. 1 to 3, the vertical cross-sections of the plurality of conductive patterns 162 and the compensation patterns 174 are illustrated as having rectangles respectively, but the technical idea of the present invention is not limited thereto. In some embodiments, the horizontal width of the plurality of conductive patterns 162 becomes wider as it is closer to the second surface 102F of the semiconductor substrate 102, and the vertical cross-section of the plurality of conductive patterns 162 has a trapezoidal shape. For example, the side walls 162s of the plurality of conductive patterns 162 have an inclination with respect to the second surface 102F of the semiconductor substrate 102 and the vertical direction (Z direction). In this case, the side walls 174s of the compensation pattern 174 have an inclination with respect to the second surface 102F of the semiconductor substrate 102 and the vertical direction (Z direction) so as to correspond to the side walls 162s of the plurality of conductive patterns 162. For example, the horizontal width of the portion interposed between two adjacent conductive patterns 162 among the compensation patterns 174 becomes narrower as it is closer to the second surface 102F of the semiconductor substrate 102.

[0041] In FIGS. 4A, 4B, and 4C, the planar arrangement relationships of the plurality of conductive patterns 162, the compensation patterns 174, and the insulating spacers 164 in the front wiring layer 160 are illustrated. According to an exemplary embodiment, the compensation pattern 174 has a plurality of holes HP that accommodate the plurality of conductive patterns 162. The inner walls / inner boundaries of the plurality of holes HP are constituted by the side walls 174s of the compensation pattern 174. At least one or more conductive patterns 162 are arranged in each of the plurality of holes HP. In a plan view, the compensation pattern 174 is arranged so as to surround the plurality of conductive patterns 162. According to an exemplary embodiment, the compensation pattern 174 can fill a region in the front wiring layer 160 where the plurality of conductive patterns 162 are not arranged, thereby reducing the deviation of the pattern density due to the region of the front wiring layer 160.

[0042] Referring to FIG. 4A, the first group of conductive patterns 162 among the plurality of conductive patterns 162 are each arranged one by one in a plurality of holes HP. The first group of conductive patterns 162 are arranged spaced apart from each other in the horizontal direction (X direction and / or Y direction) via compensation patterns 174, and the first group of conductive patterns 162 are each surrounded by an insulating spacer 164. For example, the compensation pattern 174 is interposed between each of the first group of conductive patterns 162. In some embodiments, the first group of conductive patterns 162 are each arranged at a first isolation distance da1 from the inner boundary of the corresponding hole HP among the plurality of holes HP in a plan view. For example, in a plan view, each of the first group of conductive patterns 162 can be in an independent island shape. In some embodiments, a first pattern interval dpw1, which is the distance between two conductive patterns 162 selected from the first group of conductive patterns 162 and arranged adjacent to each other, is greater than twice the first isolation distance da1. For example, the first pattern interval dpw1 can be the horizontal distance between two conductive patterns 162 arranged adjacent to each other via the compensation pattern 174.

[0043] Referring to FIG. 4B, a second group of the plurality of conductive patterns 162 is disposed within a single hole HP. The second group of conductive patterns 162 is relatively densely arranged with respect to each other when compared with the first group of conductive patterns 162 described with reference to FIG. 4A. In some embodiments, two adjacent conductive patterns 162 among the second group of conductive patterns 162 have a second pattern interval dpw2 that is smaller than the first pattern interval dpw1. For example, the second pattern interval dpw2 is smaller than twice the first isolation distance da1. For example, the second pattern interval dpw2 is the horizontal distance between two adjacent conductive patterns 162 arranged adjacent to each other via the insulating spacer 164. In some embodiments, a compensation pattern 174 may not be disposed between two adjacent conductive patterns 162 among the second group of conductive patterns 162, and the two conductive patterns 162 may be separated from each other via the insulating spacer 164. A first conductive pattern 162 selected from the second group of conductive patterns 162 is disposed on the central side of the second group of conductive patterns 162 and is surrounded by other adjacent peripheral conductive patterns 162. In this case, the distance between the side wall 162s of the first conductive pattern 162 and the side wall 174s of the compensation pattern 174 is greater than the first isolation distance da1. In some embodiments, among the second group of densely arranged conductive patterns 162, each side wall 162s of the conductive pattern 162 disposed on the outer periphery includes a portion facing the side wall 174s of the compensation pattern 174. In this case, each of the side walls 162s of the conductive pattern 162 is separated from the compensation pattern 174 by the first isolation distance da1.

[0044] Referring to FIG. 4C, the plurality of conductive patterns 162 includes a plurality of groups spaced apart from each other in the horizontal direction (X direction and / or Y direction). In some embodiments, the plurality of groups are respectively disposed within corresponding ones of the plurality of holes HP, and the plurality of groups are spaced apart from each other via a compensation pattern 174. In some embodiments, some of the conductive patterns 162 of the plurality of groups are arranged in a row along a horizontal direction. In some embodiments, some other of the conductive patterns 162 of the plurality of groups are arranged in a zigzag along a horizontal direction. Within each hole HP, the conductive patterns 162 constituting each group are spaced apart from adjacent conductive patterns 162 by a second pattern interval dpw2. The plurality of groups are respectively disposed within one hole HP, but different from the conductive patterns 162 of FIG. 4B, the conductive patterns 162 constituting each group all have sidewalls 162s facing the compensation pattern 174. In some embodiments, the conductive patterns 162 of a third group selected from the plurality of groups and the conductive patterns 162 of a fourth group are spaced apart from each other via a compensation pattern 174. A first conductive pattern 162 selected from the conductive patterns 162 of the third group and adjacent to the conductive patterns 162 of the fourth group, and a second conductive pattern 162 selected from the conductive patterns 162 of the fourth group and disposed adjacent to the third group are spaced apart by a first pattern interval dwp1 via a compensation pattern 174.

[0045] In FIGS. 4A to 4C, the plurality of conductive patterns 162 are illustrated as having a rectangular pad shape with different widths along the first horizontal direction (X direction) and the second horizontal direction (Y direction), but the present invention is not limited thereto. For example, the plurality of conductive patterns 162 may have a planar shape such as a square, a rhombus, or a circle. Also, in FIGS. 4A to 4C, different from the illustrated example, the plurality of conductive patterns 162 may each have a line shape extending in the horizontal direction (X direction and / or Y direction). In FIGS. 4A to 4C, the planar arrangement relationship of the plurality of conductive patterns 162, the insulating spacers 164, and the compensation patterns 174 according to an exemplary embodiment is illustrated, but the technical idea of the present invention is not limited thereto, and various modifications and changes can be made by those skilled in the art within the technical idea and scope of the present invention.

[0046] In some embodiments, the plurality of conductive patterns 162 and the compensation patterns 174 each include a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof.

[0047] In some embodiments, the plurality of conductive patterns 162 and the compensation patterns 174 are made of the same material. In some other embodiments, the plurality of conductive patterns 162 and the compensation patterns 174 are made of different materials. In some embodiments, the plurality of conductive patterns 162 are made of the same material as the second wiring lines 144 of the second wiring layer 142 and the plurality of second wiring vias 146.

[0048] In some embodiments, the insulating spacer 164 includes an oxide film such as TEOS (tetraethyl orthosilicate), PSG (phosphor silicate glass), BPSG (boro-phosphor silicate glass), USG (undoped silicate glass), PE-TEOS (plasma enhanced-TEOS), HDP-CVD (high density plasma-chemical vapor deposition), a carbon-containing oxide film such as SiOC, SiCOH, a silicon nitride film, a carbon-containing nitride film, or a combination thereof.

[0049] The wiring structure 152 and the front wiring layer 160 constitute a Back End Of Line (BEOL) structure provided on the second surface 102F of the semiconductor substrate 102. In some embodiments, the thickness of the interconnects constituting the BEOL structure is greater as the distance from the second surface 102F of the semiconductor substrate 102 is greater. In some embodiments, the thickness along the vertical direction (Z direction) of the plurality of conductive patterns 162 is greater than the thickness along the vertical direction (Z direction) of each of the plurality of first wiring lines 124 and second wiring lines 144. In some other embodiments, the vertical thickness of the plurality of conductive patterns 162 is substantially equal to the vertical thickness of the second wiring lines 144 and greater than the vertical thickness of the plurality of first wiring lines 124. The semiconductor chip 100 according to an exemplary embodiment includes a compensation pattern 174 interposed between the plurality of conductive patterns 162, and can uniformly induce the pattern density for each region in the front wiring layer 160. Thereby, the surface distortion phenomenon of the front surface 100F of the semiconductor chip 100 that may occur when the plurality of conductive patterns 162 are concentratedly arranged only in a partial region in a plan view is reduced. The compensation pattern 174 according to some embodiments includes a material such as a metal having a relatively high thermal conductivity, and also improves the heat dissipation characteristics of the semiconductor chip 100.

[0050]

[0051] ​According to an exemplary embodiment, a plurality of front bonding pads 184 penetrate through the front insulating film 182 and the insulating spacer 164 and are respectively in contact with at least a part of the plurality of conductive patterns 162. The plurality of front bonding pads 184 are arranged spaced apart from each other in the horizontal direction (X direction and / or Y direction) and are exposed on the front surface 100F of the semiconductor chip 100. The plurality of front bonding pads 184 are connected to the wiring structure 152 via the plurality of conductive patterns 162.

[0052] In some embodiments, each of the plurality of front bonding pads 184 is in contact with the second surface 162b of the corresponding conductive pattern 162 among the plurality of conductive patterns 162. In some embodiments, the sidewalls of the plurality of front bonding pads 184 include a portion in contact with the front insulating film 182 and a portion in contact with the insulating spacer 164. The insulating spacer 164 covers a portion of the second surface 162b of the plurality of conductive patterns 162 that is not in contact with the plurality of front bonding pads 184. In some embodiments, the sidewalls of the plurality of front bonding pads 184 include a portion facing the compensation pattern 174 via the insulating spacer 164.

[0053] In some embodiments, the plurality of front bonding pads 184 include chromium (Cr), tungsten (W), titanium (Ti), copper (Cu), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or a combination thereof.

[0054] In some embodiments, the front insulating film 182 includes at least one of SiO, SiN, SiCN, SiCO, and a polymer material. For example, the polymer material can be BCB, PI, PBO, silicon, or epoxy. In some embodiments, the front insulating film 182 has a multi-layer structure including a plurality of insulating material layers laminated in the vertical direction (Z direction).

[0055] Referring to FIG. 1, the semiconductor chip 100 includes a passivation layer 192 and a backside dielectric layer 194 sequentially stacked on the first surface 102B of the semiconductor substrate 102. The semiconductor chip 100 includes a plurality of through electrodes 106 that penetrate the semiconductor substrate 102 and the passivation layer 192 in the vertical direction (Z direction), and a plurality of backside bonding pads 196 that are respectively in contact with the plurality of through electrodes 106 on the lower surface of the passivation layer 192 and are surrounded by the backside dielectric layer 194. For example, the sidewalls of the plurality of backside bonding pads 196 are surrounded by the backside dielectric layer 194.

[0056] In some embodiments, the plurality of through electrodes 106 have a columnar shape that extends through the semiconductor substrate 110, the interlayer dielectric film 104, and the passivation layer 192. In some embodiments, one end of the plurality of through electrodes 106 along the vertical direction (Z direction) penetrates the interlayer dielectric film 104 and is connected in contact with the lowermost first wiring line 124 among the plurality of first wiring lines 124. The other ends of the plurality of through electrodes 106 along the vertical direction (Z direction) are respectively connected in contact with the plurality of backside bonding pads 196.

[0057] Although not shown, the plurality of vias 106 may each include a conductive plug extending in the vertical direction (Z direction) and a conductive barrier layer disposed on the outer surface of the conductive plug. In some embodiments, the conductive plug includes copper (Cu), nickel (Ni), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or a combination thereof. In some embodiments, the conductive barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), cobalt (Co), or a combination thereof. In some embodiments, the semiconductor chip 100 includes via insulating films interposed between the plurality of vias 106 and the semiconductor substrate 102, between the plurality of vias 106 and the interlayer insulating film 104, and between the plurality of vias 106 and the passivation layer 192. In some embodiments, the via insulating film includes a HARP (high aspect ratio process) oxide based on O3 / TEOS (ozone / tetra-ethyl ortho-silicate), but is not limited to the examples described above.

[0058] In some embodiments, the passivation layer 192 and the backside insulating film 194 each include an oxide and / or a nitride. In some embodiments, the passivation layer 120 includes at least one of SiO, SiN, SiCN, SiCO, and a polymer material. For example, the polymer material includes BCB (benzocyclobutene), PI (Polyimide), PBO (Polybenzoxazole), silicone, or epoxy. For example, the passivation layer 192 and the backside insulating film 194 each have a multi-layer structure including a plurality of insulating material layers laminated in the vertical direction (Z direction).

[0059] In some embodiments, the plurality of front bonding pads 184 include chromium (Cr), tungsten (W), titanium (Ti), copper (Cu), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or combinations thereof.

[0060] According to an exemplary embodiment, the semiconductor chip 100 includes a front wiring layer 160 disposed on the second surface 102F of the semiconductor substrate 102 and closest to the front surface 100F of the semiconductor chip 100. In a plan view, the regions in the front wiring layer 160 where the plurality of conductive patterns 162 are not disposed are filled by the compensation pattern 174, but the compensation pattern 174 may be separated from the plurality of conductive patterns 162 via the insulating spacer 164. The first surface 162a of the plurality of conductive patterns 162 is in contact with the upper surface of the wiring structure 152 (e.g., the upper surface 142u of the second wiring layer 142), but the compensation pattern 174 is separated from the wiring structure 152 via the insulating spacer 164. The compensation pattern 174 and the insulating spacer 164 can be formed to conformally cover the upper surface 142u of the second wiring layer 142 and the plurality of conductive patterns 162 after the plurality of conductive patterns 162 are formed, and the first isolation distance da1 between the compensation pattern 174 and the plurality of conductive patterns 162 can be adjusted with a low process difficulty.

[0061] FIG. 5A is a cross-sectional view showing a partial region of a semiconductor chip 100a according to another partial embodiment of the present invention. Specifically, FIG. 5A shows a region corresponding to the region displayed in “EXA1” of FIG. 1. FIG. 5B is an enlarged view of the region displayed in “EXB1” of FIG. 5A. In FIGS. 5A and 5B, the same reference numerals as those in FIGS. 1 to 4C denote the same members, and overlapping descriptions thereof are omitted here.

[0062] Referring to FIGS. 5A and 5B, the insulating spacer 164 includes a first spacer film 164a and a second spacer film 164b sequentially stacked on the upper surface of the wiring structure 152 (e.g., the upper surface 142u of the second wiring layer 142).

[0063] According to an exemplary embodiment, the first spacer film 164a covers and contacts the upper surface 142u of the second wiring layer 142, the side walls 162s of the plurality of conductive patterns 162, and a part of the second surface 162b of the plurality of conductive patterns 162. According to an exemplary embodiment, the second spacer film 164b covers and contacts the first surface 174a and the side walls 174s of the compensation pattern 174 on the first spacer film 164a, but may not cover the second surface 162b of the plurality of conductive patterns 162. For example, the second spacer film 164b does not overlap perpendicularly with the second surface 162b of the plurality of conductive patterns 162.

[0064] In some embodiments, the second spacer film 164b separates the plurality of conductive patterns 162 in the horizontal direction (X direction and / or Y direction). In some embodiments, the second surface 162b of the plurality of conductive patterns 162 is separated from the front insulating film 182 through the first spacer film 164a. In some embodiments, the first spacer film 164a and the second spacer film 164b are interposed between the side walls 162s of the plurality of conductive patterns 162 and the side walls 174s of the compensation pattern 174. In some embodiments, the first isolation distance da1 is the sum of the thickness of the first spacer film 164a and the thickness of the second spacer film 164b.

[0065] In some embodiments, the first spacer film 164a and the second spacer film 164b are interposed between the compensation pattern 174 and the wiring structure 152. For example, the second isolation distance da2 is the sum of the thickness of the first spacer film 164a and the thickness of the second spacer film 164b. In some embodiments, the distance along the vertical direction (Z direction) between the second surface 162b of the plurality of conductive patterns 162 and the front insulating film 182 is smaller than the second isolation distance da2. In some embodiments, the distance along the vertical direction (Z direction) between the second surface 162b of the plurality of conductive patterns 162 and the front insulating film 182 is substantially equal to the thickness of the first spacer film 164a.

[0066] In some embodiments, the top surfaces of the first spacer film 164a and the second spacer film 164b are each in contact with the front insulating film 182, and constitute the top surface 164um of the insulating spacer 164. In some embodiments, the top surfaces of the first spacer film 164a and the second spacer film 164b are coplanar.

[0067] In some embodiments, the sidewalls of the plurality of front bonding pads 184 may be in contact with the first spacer film 164a and the front insulating film 182, but not in contact with the second spacer film 164b.

[0068] In FIGS. 5A and 5B, the thickness of the first spacer film 164a is illustrated as being thinner than the thickness of the second spacer film 164b, but the present invention is not limited thereto. In some embodiments, the thickness of the first spacer film 164a is equal to or greater than the thickness of the second spacer film 164b. In FIGS. 5A and 5B, the insulating spacer 164 is illustrated as including two spacer films 164a and 164b, but the technical idea of the present invention is not limited thereto. For example, the insulating spacer 164 may include three or more spacer films.

[0069] FIG. 6 is a cross-sectional view showing a partial region of a semiconductor chip 100b according to still other embodiments of the present invention. Specifically, FIG. 6 shows a region corresponding to the region displayed in "EXA1" of FIG. 1. In FIG. 6, the same reference numerals as those in FIGS. 1 to 4C and FIGS. 5A and 5B denote the same members, and overlapping descriptions thereof are omitted here.

[0070] Referring to FIG. 6, the insulating spacer 164 of the semiconductor chip 100b covers the sidewalls 162s of the plurality of conductive patterns 162, but may not cover the second surfaces 162b of the plurality of conductive patterns 162. According to an exemplary embodiment, the plurality of front bonding pads 184 penetrate the front insulating film 182 and are in contact with the plurality of conductive patterns 162. In some embodiments, the sidewalls of the plurality of front bonding pads 184 are surrounded by the front insulating film 182. In some embodiments, the portions of the second surfaces 162b of the plurality of conductive patterns 162 that do not contact the plurality of front bonding pads 184 are in contact with the front insulating film 182.

[0071] In some embodiments, the second surfaces 162b of the plurality of conductive patterns 162 and the second surfaces 174b of the compensation pattern 174 are arranged at the same vertical level. In some embodiments, the second surfaces 162b of the plurality of conductive patterns 162, the second surfaces 174b of the compensation pattern 174, and the uppermost surface 164um of the insulating spacer 164 are coplanar. In some embodiments, the thickness of the plurality of conductive patterns 162 along the vertical direction (Z direction) is greater than the thickness of the compensation pattern 174 along the vertical direction (Z direction). In some embodiments, the sidewalls 174s of the compensation pattern 174 face the plurality of conductive patterns 162, but may not face the plurality of front bonding pads 184.

[0072] FIG. 7 is a cross-sectional view showing a partial region of a semiconductor chip 100c according to still other some embodiments of the present invention. Specifically, FIG. 7 shows a region corresponding to the region displayed in "EXA1" of FIG. 1. In FIG. 7, the same reference numerals as those in FIGS. 1 to 4C, FIGS. 5A and 5B, and FIG. 6 denote the same members, and redundant descriptions thereof are omitted here.

[0073] Referring to FIG. 7, the semiconductor chip 100c includes a plurality of first front dummy pads 186 that penetrate the front insulating film 182 and are in contact with the compensation pattern 174. For example, the plurality of first front dummy pads 186 are in contact with the second surface 174b of the compensation pattern 174. In some embodiments, the plurality of first front dummy pads 186 are exposed on the front surface 100F of the semiconductor chip 100, and the upper surfaces of the plurality of first front dummy pads 186 are coplanar with the upper surfaces of the plurality of front bonding pads 184. In some embodiments, the plurality of first front dummy pads 186 are spaced apart from the plurality of front bonding pads 184 via the front insulating film 182.

[0074] The plurality of first front dummy pads 186 are arranged on the compensation pattern 174 that does not overlap vertically with the plurality of front bonding pads 184, and can reduce the pattern density deviation by region in the front insulating film 182. Only one first front dummy pad 186 is illustrated in FIG. 7, but the plurality of first front dummy pads 186 may be arranged spaced apart from each other on the compensation pattern 174 extending in the horizontal direction (X direction and / or Y direction).

[0075] FIG. 8A is a cross-sectional view showing a partial region of a semiconductor chip 100d according to still other embodiments of the present invention. Specifically, FIG. 8A shows a region corresponding to the region displayed in "EXA1" of FIG. 1. FIG. 8B is a plan view showing a partial configuration of the semiconductor chip 100d according to still other embodiments of the present invention. In FIGS. 8A and 8B, the same reference numerals as those in FIGS. 1 to 7 denote the same members, and overlapping descriptions thereof are omitted here.

[0076] Referring to FIGS. 8A and 8B, the semiconductor chip 100d includes a plurality of dummy patterns 163 and a plurality of second front dummy pads 187. According to an exemplary embodiment, the plurality of dummy patterns 163 and the plurality of second front dummy pads 187 generally have the same structure as the plurality of conductive patterns 162 and the plurality of front bonding pads 184 described with reference to FIGS. 1 to 7, respectively. However, the plurality of dummy patterns 163 may not be in contact with the plurality of second wiring vias 146 and / or the second wiring lines 144 of the second wiring layer 142. For example, the plurality of dummy patterns 163 may not be connected to the conductive structures 124, 126, 144, 146 that make up the wiring structure 152. The plurality of dummy patterns 163 and the plurality of second front dummy pads 187 are not electrically connected to the conductive structures 124, 126, 144, 146, and in a plan view, they can fill the regions where the plurality of conductive patterns 162 are not arranged, thereby improving the topological characteristics of the front surface 100F of the semiconductor chip 100.

[0077] For example, the plurality of dummy patterns 163 may be in contact with the upper surface 142u of the second wiring layer 142, spaced apart from each other, and spaced apart from the plurality of conductive patterns 162. The plurality of dummy patterns 163 are spaced apart from the compensation pattern 174 via the insulating spacer 164. The insulating spacer 164 includes a portion interposed between the plurality of dummy patterns 163 and the front insulating film 182. For example, the upper surfaces of the plurality of dummy patterns 163 are spaced apart from the front insulating film 182 via the insulating spacer 164. The plurality of second front dummy pads 187 each penetrate through the front insulating film 182 and the insulating spacer 164 and are in contact with the plurality of dummy patterns 163 individually. The side walls of the plurality of second front dummy pads 187 include a portion facing the front insulating film 182 and a portion facing the compensation pattern 174. In some embodiments, the insulating spacer 164 includes a portion in contact with the side walls 163s of the plurality of dummy patterns 163 and a portion in contact with the side walls of the plurality of second front dummy pads 187.

[0078] Referring to FIG. 8B, in plan view, a plurality of dummy patterns 163 are surrounded by an insulating spacer 164 and surrounded by a compensation pattern 174 via the insulating spacer 164. As illustrated in FIG. 8B, a first group of dummy patterns 163 selected from the plurality of dummy patterns 163 are each disposed within one hole HP and have an independent island shape. For example, the first group of dummy patterns 163 are each separated from the compensation pattern 174 by a first isolation distance da1.

[0079] In some embodiments, a second group of dummy patterns 163 selected from the plurality of dummy patterns 163 are disposed within one hole HP and are adjacent to each other. For example, two dummy patterns 163 selected from the second group of dummy patterns 163 are separated from each other via an insulating spacer 164. A third pattern interval dpw3, which is the distance between two dummy patterns 163 selected from the second group of dummy patterns 163 and disposed adjacent to each other, is smaller than twice the first isolation distance da1.

[0080] In some embodiments, a third group of dummy patterns 163 selected from the plurality of dummy patterns 163 are disposed within one hole HP and are adjacent to a part of the conductive pattern 162. For example, the third group of dummy patterns 163 are each separated from an adjacent conductive pattern 162 or another dummy pattern 163 via an insulating spacer 164. For example, a fourth pattern interval dpw4, which is the distance between one selected from the third group of dummy patterns 163 and the adjacent conductive pattern 162, is smaller than twice the first isolation distance da1.

[0081] In some embodiments, some of the plurality of dummy patterns 163 are separated from other parts selected from the plurality of dummy patterns 163 or the conductive pattern 162 via the compensation pattern 174. For example, the first dummy pattern 163 selected from the plurality of dummy patterns 163 and disposed within the first hole HP among the plurality of holes HP is separated from another dummy pattern 163 or the conductive pattern 162 disposed within the second hole HP selected from the plurality of holes HP and disposed adjacent to the first hole HP by the fifth pattern interval dpw5. For example, the fifth pattern interval dpw5 is greater than twice the first isolation distance da1. In some embodiments, the first dummy pattern 163 is disposed between the first conductive pattern 162 and the second conductive pattern 162 disposed in different holes HP. The compensation pattern 174 includes a portion interposed between the first conductive pattern 162 and the first dummy pattern 163 and a portion interposed between the second conductive pattern 162 and the first dummy pattern 163, and is separated from the first dummy pattern 163, the first conductive pattern 162, and the second conductive pattern 162 via the insulating spacer 164.

[0082] In FIG. 8B, the planar arrangement relationship of the plurality of conductive patterns 162, the plurality of dummy patterns 163, the insulating spacer 164, and the compensation pattern 174 according to an exemplary embodiment is illustrated, but the technical idea of the present invention is not limited thereto, and various modifications and changes can be made by those skilled in the art within the technical idea and scope of the present invention.

[0083] Hereinafter, a specific example of a method for manufacturing a semiconductor chip according to an embodiment based on the technical idea of the present invention will be described with reference to specific examples.

[0084] FIGS. 9A to 9F are cross-sectional views shown in process order to explain a method of manufacturing a semiconductor chip 100 according to an exemplary embodiment of the present invention. Specifically, FIGS. 9A to 9F are cross-sectional views in the order of processes of a portion corresponding to the region displayed in “EXA1” of FIG. 1. Referring to FIGS. 9A to 9F, an exemplary method of manufacturing the semiconductor chip 100 illustrated in FIGS. 1 to 4C will be described. In FIGS. 9A to 9F, the same reference numerals as those in FIGS. 1 to 4C denote the same members, and redundant descriptions thereof will be omitted here.

[0085] Referring to FIG. 9A, after forming a plurality of semiconductor elements on the second surface 102F of the semiconductor substrate 102, an interlayer insulating film 104 is formed, and a plurality of through electrodes 106 penetrating a part of the semiconductor substrate 102 and the interlayer insulating film 104 are formed. For example, the plurality of through electrodes 106 penetrate the interlayer insulating film 104 and extend into the semiconductor substrate 102, and are partially embedded in the semiconductor substrate 102.

[0086] Next, a wiring structure 152 is formed on the second surface 102F of the semiconductor substrate 102. For example, a first wiring layer 122 and a second wiring layer 142 are sequentially formed on the interlayer insulating film 104 and the plurality of through electrodes 106.

[0087] In some embodiments, the first wiring layer 122 is formed by a damascene process using an electroplating method, and the second wiring layer 142 is formed by a photolithography process in which a metal material is deposited by PVD (Physical Vapor Deposition) and then patterned. In some other embodiments, both the first wiring layer 122 and the second wiring layer 142 are formed by a damascene process.

[0088] Next, after forming a compensation material film covering the upper surface 142u of the second wiring layer 142, a pattern mask (not shown) for exposing a partial region of the compensation material film is formed on the compensation material film. Using the pattern mask (not shown) as an etching mask, a partial region of the compensation material film is removed to form a plurality of conductive patterns 162 on the upper surface 142u of the second wiring layer 142. Next, the pattern mask (not shown) is removed by an ashing process or the like. In some embodiments, the plurality of conductive patterns 162 are in contact with a part of a plurality of second wiring vias 146 exposed through the upper surface 142u of the second wiring layer 142.

[0089] Referring to FIG. 9B, an insulating spacer 164 is formed to conformally cover the surface of the result of FIG. 9A. In some embodiments, the insulating spacer 164 conformally covers a portion of the second surface 162b, sidewalls 162s of the plurality of conductive patterns 162, and the upper surface 142u of the second wiring layer 142 that does not overlap perpendicularly with the plurality of conductive patterns 162. In some embodiments, the thickness of the insulating spacer 164 is substantially equal to the first isolation distance da1 (see FIG. 3).

[0090] In some embodiments, the vertical level of the first portion of the insulating spacer 164 that overlaps perpendicularly with the plurality of conductive patterns 162 is higher than the vertical level of the second portion of the insulating spacer 164 that contacts the upper surface 142u of the second wiring layer 142. For example, the upper surface of the second portion is disposed closer to the second surface 102F of the semiconductor substrate 102 than the upper surface of the first portion, and the plurality of conductive patterns 162 and the insulating spacer 164 form a concavo-convex structure including a plurality of convex portions CC1 and concave portions CC2.

[0091] Referring to FIG. 9C, a compensation material film 172 is formed to cover the upper surface of the concavo-convex structure in the result of FIG. 9B. In some embodiments, the compensation material film 172 is formed to have a sufficient thickness so as to fill the concave portions CC2 of the concavo-convex structure. For example, the upper surface of the portion of the compensation material film 172 disposed in a region that does not overlap perpendicularly with the plurality of conductive patterns 162 is disposed at a higher vertical level than the upper surfaces of the plurality of convex portions CC1 of the concavo-convex structure.

[0092] In some embodiments, when two adjacent conductive patterns 162 among the plurality of conductive patterns 162 are separated by a second pattern interval dpw2 (see FIG. 4B), the conductive patterns 162 form one convex portion CC1. For example, in FIGS. 4A to 4C, the plurality of holes HP are regions where one selected from the plurality of convex portions CC1 is formed, and the compensation pattern 174 is formed from a compensation material film 172 (see FIG. 9C) that fills the concave portion CC2 defined between the plurality of convex portions CC1 by a process described later.

[0093] Referring to FIG. 9D, in the result of FIG. 9C, the compensation material film 172 is planarized until the insulating spacer 164 is exposed to form the compensation pattern 174. In some embodiments, the planarization process includes a Chemical Mechanical Polishing (CMP) process, an etch-back process, or a combination thereof.

[0094] In some embodiments, the insulating spacer 164 functions as a stopper for a grinding process that removes and planarizes the compensation material film 172. The grinding process is performed until the uppermost surface um of the insulating spacer 164 is exposed, and the second surface 174b of the compensation pattern 174 and the uppermost surface um of the insulating spacer 164 are located at the same vertical level. In some embodiments, the plurality of conductive patterns 162 may be surrounded by the insulating spacer 164 and not exposed.

[0095] In some embodiments, although the compensation pattern 174 is separated from the plurality of conductive patterns 162 via the insulating spacer 164, it fills the concave portion CC2 (FIG. 9B) of the uneven structure to reduce the pattern density deviation by region in the front wiring layer 160.

[0096] In some other embodiments, in the result of FIG. 9C, the compensation material film 172 and the insulating spacer 164 are planarized until a plurality of conductive patterns 162 are exposed. In this case, the portion of the insulating spacer 164 that covers the second surface 162b of the plurality of conductive patterns 162 is removed, and the second surface 162b of the plurality of conductive patterns 162 and the second surface 174b of the compensation pattern 174 can be in the same plane. Then, the same steps as those described later with reference to FIGS. 9E and 9F are performed, and the semiconductor chip 100b described with reference to FIG. 6 can be manufactured.

[0097] Referring to both FIGS. 9E and 9F, in the result of FIG. 9D, a front insulating film 182 covering the front wiring layer 160 is formed. For example, the front insulating film 182 is in contact with the uppermost surface 164um of the insulating spacer 164 and the second surface 174b of the compensation pattern 174.

[0098] Next, a plurality of first openings op1 are formed to at least partially expose the second surface 162b of the plurality of conductive patterns 162. In some embodiments, the plurality of first openings op1 are formed by forming a pattern mask on the front insulating film 182 and then removing a part of the front insulating film 182 and a part of the insulating spacer 164 by an etching process.

[0099] Referring to FIGS. 9F and FIGS. 1 to 4C together, in the result of FIG. 9F, a plurality of front bonding pads 184 that individually fill the plurality of first openings op1 can be formed. In some embodiments, after forming a metal seed layer covering the inner walls and the bottom surfaces of the plurality of first openings op1, a metal core layer is formed from the metal seed layer by an electroplating process to form the plurality of front bonding pads 184.

[0100] Next, a part of the semiconductor substrate 102 can be removed to expose a plurality of through electrodes 106, and the first surface 102B of the semiconductor substrate 102 can be formed. In some embodiments, the ends of the plurality of through electrodes 106 on the side of the first surface 102B penetrate the semiconductor substrate 102 and protrude from the first surface 102B of the semiconductor substrate 102. Next, after forming a passivation layer 192 covering the first surface 102B of the semiconductor substrate 102 and the exposed portions of the plurality of through electrodes 106, a polishing process can be performed to expose the plurality of through electrodes 106. For example, the lower surfaces of the passivation layer 192 and the plurality of through electrodes 106 are on the same plane. Next, after forming a back insulating film 194 covering the lower surface of the passivation layer 192 and the lower surfaces of the plurality of through electrodes 106, a plurality of back bonding pads 196 respectively connected to the plurality of through electrodes 106 can be formed by penetrating the back insulating film 194.

[0101] A method of manufacturing a semiconductor chip 100 according to an exemplary embodiment can form a concavo-convex structure including a plurality of conductive patterns 162 and insulating spacers 164, and then form a compensation pattern 174 filling the concave portions CC2 of the concavo-convex structure. Since the compensation pattern 174 is self-aligned by being separated from the plurality of conductive patterns 162 by a first isolation distance da1 which is the thickness of the insulating spacer 164, the plurality of conductive patterns 162 and the compensation pattern 174 can be separated with a low process difficulty, and the topological characteristics of the front surface 100F of the semiconductor chip 100 can be improved.

[0102] FIGS. 10A to 10C are cross-sectional views for explaining a method of manufacturing a semiconductor chip 100a according to another part of the embodiments of the present invention. Specifically, FIGS. 10A to 10C are cross-sectional views according to the process order of the portion corresponding to the region shown in "EXA1" of FIG. 1. With reference to FIGS. 10A to 10C, an exemplary method of manufacturing the semiconductor chip 100a illustrated in FIGS. 5A and 5B will be described. In FIGS. 10A to 10C, the same reference numerals as those in FIGS. 1 to 9F denote the same members, and overlapping descriptions thereof will be omitted here.

[0103] In the manner described with reference to FIG. 9A, a wiring structure 152 including a first wiring layer 122 and a second wiring layer 142 can be formed on the second surface 102F of the semiconductor substrate 102, and the process can be carried out up to the step of forming a plurality of conductive patterns 162 on the upper surface 142u of the second wiring layer 142.

[0104] Referring to FIG. 10A, a first spacer film 164a and a second spacer film 164b that conformally cover the result of FIG. 9A are sequentially formed to form an insulating spacer 164. For example, the first spacer film 164a conformally covers a portion of the second surface 162b and sidewalls 162s of the plurality of conductive patterns 162 and the upper surface 142u of the second wiring layer 142 that do not overlap perpendicularly with the plurality of conductive patterns 162. The second spacer film 164b is disposed on the first spacer film 164a, and the first spacer film 164a is covered by the second spacer film 164b. The second spacer film 164b is separated from the plurality of conductive patterns 162 and the wiring structure 152 via the first spacer film 164a. In some embodiments, the plurality of conductive patterns 162, the first spacer film 164a, and the second spacer film 164b form a concavo-convex structure including convex portions CC1 and concave portions CC2.

[0105] Referring to FIG. 10B, a compensation material film 172 that covers the upper surface of the concavo-convex structure can be formed on the result of FIG. 10A. The compensation material film 172 fills the concave portions CC2 of the concavo-convex structure and is separated from the plurality of conductive patterns 162 and the wiring structure 152 via the first spacer film 164a and the second spacer film 164b.

[0106] Referring to FIG. 10C, the result of FIG. 10B can be planarized until the first spacer film 164a is exposed, and the compensation pattern 174 can be formed. In the planarization process, a part of the compensation material film 172 and a part of the second spacer film 164b are removed. For example, the first spacer film 164a functions as a stop film for the planarization process. In FIG. 10B, the second spacer film 164b that overlaps perpendicularly with the plurality of conductive patterns 162 is removed, and the second surface 162b of the plurality of conductive patterns 162 is covered by the first spacer film 164a. In some embodiments, the first spacer film 164a is separated from the compensation pattern 174 via the second spacer film 164b. The uppermost surface 164um of the insulating spacer 164 is composed of the uppermost surface of the first spacer film 164a and the uppermost surface of the second spacer film 164b.

[0107] Next, in the result of FIG. 10C, as described with reference to FIGS. 9E and 9F, after forming a front insulating film 182 covering the upper surfaces of the first spacer film 164a, the second spacer film 164b, and the compensation pattern 174 respectively, a plurality of first openings op1 can be formed. Next, a plurality of front bonding pads 184 filling the plurality of first openings op1 can be formed, and the semiconductor chip 100a described with reference to FIGS. 5A and 5B can be formed.

[0108] FIG. 11 is a cross-sectional view for explaining a method of manufacturing a semiconductor chip 100c according to another part of the embodiments of the present invention. Specifically, FIG. 11 is a partial cross-sectional view corresponding to the region shown in "EXA1" of FIG. 1. Referring to FIG. 11, an exemplary manufacturing method of the semiconductor chip 100c illustrated in FIG. 6 will be described. In FIG. 11, the same reference numerals as those in FIGS. 1 to 10C denote the same members, and overlapping descriptions thereof are omitted here.

[0109] In the method as described with reference to FIGS. 9A to 9E, a wiring structure 152 is formed on the second surface 102F of the semiconductor substrate 102, and after forming a front wiring layer 160 including a plurality of conductive patterns 162, a compensation pattern 174, and an insulating spacer 164 on the wiring structure 152, a front insulating film 182 can be formed on the front wiring layer 160.

[0110] Referring to FIG. 11, in the result of FIG. 9E, a plurality of first openings op1 for exposing at least a part of the second surface 162b of the plurality of conductive patterns 162 and a plurality of second openings op2 for exposing at least a part of the second surface 174b of the compensation pattern 174 can be formed. For example, the plurality of first openings op1 and the plurality of second openings op2 are formed together in the same process.

[0111] Next, a plurality of front bonding pads 184 filling the plurality of first openings op1 and a plurality of first front dummy pads 186 filling the plurality of second openings op2 can be formed to form the semiconductor chip 100c described with reference to FIG. 7. In some embodiments, the plurality of front bonding pads 184 and the plurality of first front dummy pads 186 are formed together in the same process. For example, after forming a metal seed layer covering the inner walls and bottom surfaces of the plurality of first openings op1 and the plurality of second openings op2 respectively, and the upper surface of the front insulating film 182, a metal core layer is formed from the metal seed layer by electroplating. Then, polishing is performed until the front insulating film 182 is exposed, and the plurality of front bonding pads 184 and the plurality of first front dummy pads 186 can be formed.

[0112] FIGS. 12A to 12E are cross-sectional views shown in the order of processes for explaining a method of manufacturing a semiconductor chip 100d according to still other embodiments of the present invention. Specifically, FIGS. 12A to 12E are cross-sectional views according to the order of processes of a portion corresponding to the region displayed as “EXA1” in FIG. 1. Referring to FIGS. 12A to 12E, an exemplary method of manufacturing the semiconductor chip 100d illustrated in FIGS. 8A and 8B will be described. In FIGS. 12A to 12E, the same reference numerals as those in FIGS. 1 to 11 denote the same members, and overlapping descriptions thereof will be omitted here.

[0113] Referring to FIG. 12A, after forming a wiring structure 152 including a first wiring layer 122 and a second wiring layer 142 on the second surface 102F of the semiconductor substrate 102 in the same manner as described with reference to FIG. 9A, a plurality of conductive patterns 162 and a plurality of dummy patterns 163 can be formed on the wiring structure 152.

[0114] In some embodiments, the plurality of conductive patterns 162 are formed to be connected to the second wiring line 144 in contact with a part of the plurality of second wiring vias 146, while the plurality of dummy patterns 163 may be formed not to be in contact with the plurality of second wiring vias 146. For example, the plurality of dummy patterns 163 may be in contact with the second wiring insulating film 148 and may not be connected to the second wiring line 144.

[0115] In some embodiments, the plurality of dummy patterns 163 are formed in the same process as the plurality of conductive patterns 162, and the plurality of conductive patterns 162 and the plurality of dummy patterns 163 are made of equal materials. In some embodiments, the upper surface of the plurality of dummy patterns 163 is disposed at the same vertical level as the second surface 162b of the plurality of conductive patterns 162.

[0116] Referring to FIG. 12B, an insulating spacer 164 is formed on the result of FIG. 12A to cover a portion of the upper surface 142u of the second wiring layer 142 where the plurality of conductive patterns 162 and the plurality of dummy patterns 163 do not vertically overlap. For example, the insulating spacer 164 covers the upper surface and side walls of each of the plurality of dummy patterns 163.

[0117] In some embodiments, the portion of the insulating spacer 164 that covers the plurality of conductive patterns 162 and the plurality of dummy patterns 163 is disposed at a higher vertical level than the portion that does not cover the plurality of conductive patterns 162 and the plurality of dummy patterns 163. The plurality of conductive patterns 162, the plurality of dummy patterns 163, and the insulating spacer 164 constitute a concavo-convex structure including convex portions CC1 and concave portions CC2.

[0118] Referring to both FIGS. 12C and 12D, in the result of FIG. 12B, a compensation material film 172 covering the concavo-convex structure can be formed. For example, the compensation material film 172 fills the concave portion CC2 of the concavo-convex structure. Next, the compensation material film 172 is planarized until the insulating spacer 164 is exposed to form a compensation pattern 174. The second surface 174b of the compensation pattern 174 and the uppermost surface 164um of the insulating spacer 164 can be in the same plane.

[0119] Referring to FIG. 12E, after forming a front insulating film 182 covering the second surface 174b of the exposed compensation pattern 174 and the uppermost surface 164um of the insulating spacer 164 in the result of FIG. 12D, a part of the front insulating film 182 and a part of the insulating spacer 164 are removed to form a plurality of first openings op1 for exposing the plurality of conductive patterns 162 respectively, and a plurality of third openings op3 for exposing the plurality of dummy patterns 163 respectively. In some embodiments, the plurality of first openings op1 and the plurality of third openings op3 are formed together in the same process. Next, a plurality of front bonding pads 184 filling the plurality of first openings op1 and a plurality of second front dummy pads 187 filling the plurality of third openings op3 can be formed.

[0120] FIG. 13 is a cross-sectional view showing a semiconductor package 1000 according to an exemplary embodiment of the present invention. FIG. 14 is an enlarged view of the region shown in "EXC1" of FIG. 11.

[0121] Referring to FIGS. 13 and 14, the semiconductor package 1000 includes a first semiconductor chip 200 and a plurality of second semiconductor chips 300. The plurality of second semiconductor chips 300 are vertically stacked on the first semiconductor chip 200 in the vertical direction (Z direction). FIG. 5 shows that the semiconductor package 1000 includes four second semiconductor chips 300, but the number of second semiconductor chips 300 is not limited thereto. For example, the semiconductor package 1000 includes two or more second semiconductor chips 300. In an exemplary embodiment, the semiconductor package 1000 includes a multiple of four second semiconductor chips 300. In this specification, the semiconductor package 1000 may also be referred to as a sub-semiconductor package.

[0122] According to an exemplary embodiment, the first semiconductor chip 200 is electrically connected to the lowermost second semiconductor chip 300 among the plurality of second semiconductor chips 300, exchanges signals, and provides power and ground. Two adjacent second semiconductor chips 300 among the plurality of second semiconductor chips 300 are electrically connected, exchange signals, and provide power and ground.

[0123] According to an exemplary embodiment, the first semiconductor chip 200 includes a first semiconductor substrate 202 having active surfaces 202F and inactive surfaces 202B opposite to each other, a first wiring structure 252 formed on the active surface 202F of the first semiconductor substrate 202 and including a plurality of wiring lines and a plurality of wiring vias, a plurality of first through electrodes 206 connected to a part of the plurality of wiring lines of the first wiring structure 252 and penetrating the first semiconductor substrate 202, a plurality of first back bonding pads 296 connected to the plurality of first through electrodes 206 on the inactive surface 202B of the first semiconductor substrate 202, and a first back insulating film 294 surrounding the side walls of each of the plurality of first back bonding pads 296. Although not shown in FIG. 13, the first semiconductor chip 200 includes a first passivation layer (not shown) surrounding the upper end side walls of the plurality of through electrodes 106 on the inactive surface 202B of the first semiconductor substrate 202, and a first interlayer insulating film (not shown) for protecting a plurality of semiconductor elements between the active surface 202F of the first semiconductor substrate 202 and the first wiring structure 252.

[0124] The active surface 202F of the first semiconductor substrate 202 may be the front surface of the first semiconductor substrate 202, and the inactive surface 202B of the first semiconductor substrate 202 may be the back surface of the first semiconductor substrate 202. In FIG. 13, the active surface 202F of the first semiconductor substrate 202 has a face-down arrangement so as to face downward, and the active surface 202F of the first semiconductor substrate 202 is referred to as the lower surface of the first semiconductor substrate 202.

[0125] According to an exemplary embodiment, the first semiconductor chip 200 includes a first front wiring layer 260 and a first front insulating film 282 that are sequentially stacked on the lower surface of the first wiring structure 252. The first front wiring layer 260 is separated from the first semiconductor substrate 202 via the first wiring structure 252. According to an exemplary embodiment, the first front wiring layer 260 includes a plurality of first conductive patterns 262, a first compensation pattern 274, and a first insulating spacer 264 interposed between the plurality of first conductive patterns 262 and the first compensation pattern 274. The plurality of first conductive patterns 262 are disposed closer to the active surface 202F of the first semiconductor substrate 202 than the first compensation pattern 274. The first insulating spacer 264 includes a portion interposed between the first compensation pattern 274 and the first wiring structure 252, a portion interposed between the plurality of first conductive patterns 262 and the first front insulating film 282, and a portion interposed between the plurality of first conductive patterns 262 and the first compensation pattern 274. The first front insulating film 282 is in contact with the lower surface of the first compensation pattern 274 but is separated from the plurality of first conductive patterns 262 via the first insulating spacer 264. According to an exemplary embodiment, the first semiconductor chip 200 includes a plurality of first front bonding pads 284 that penetrate through the first front insulating film 282 and the first insulating spacer 264 and are respectively in contact with the plurality of first conductive patterns 262. In some embodiments, the first front bonding pad 284 includes a first portion surrounded by the first front insulating film 282 and the first insulating spacer 264, and a second portion disposed on the lower surface of the first front insulating film 282. The side wall of the first portion faces the first compensation pattern 274 via the first insulating spacer 264. According to an exemplary embodiment, the semiconductor package 1000 includes a plurality of connection bumps 286 respectively attached to the plurality of first front bonding pads 284 of the first semiconductor chip 200.

[0126] The first semiconductor substrate 202 has components that are substantially the same as or similar to the semiconductor substrate 102 shown in FIGS. 1 and 2. The plurality of first through electrodes 206 have components that are substantially the same as or similar to the plurality of through electrodes 106 shown in FIGS. 1 and 2. The first wiring structure 252 has components that are substantially the same as or similar to the wiring structure 152 shown in FIGS. 1 to 3. The plurality of first back bonding pads 296 have components that are substantially the same as or similar to the plurality of back bonding pads 196 shown in FIG. 1. The first back insulating film 294 has components that are substantially the same as or similar to the back insulating film 194 shown in FIG. 1. The first passivation layer (not shown) has components that are substantially the same as or similar to the passivation layer 192 shown in FIG. 1. Therefore, detailed descriptions thereof are omitted. The plurality of first conductive patterns 262, the first insulating spacers 264, and the first compensation patterns 274 have components that are substantially the same as or similar to the plurality of conductive patterns 162, insulating spacers 164, and compensation patterns 174 shown in FIGS. 1 to 4C, respectively. The first front insulating film 282 has components that are substantially the same as or similar to the front insulating film 182 shown in FIGS. 1 to 3. The plurality of first front bonding pads 284 have components that are substantially the same as or similar to the plurality of front bonding pads 184 shown in FIGS. 1 to 3. Therefore, detailed descriptions thereof are omitted.

[0127] According to an exemplary embodiment, the second semiconductor chip 300 includes a second semiconductor substrate 302 having mutually opposite active surfaces 302F and inactive surfaces 302B, a second wiring structure 352 formed on the active surface 302F of the second semiconductor substrate 302 and including a plurality of wiring lines and a plurality of wiring vias, a plurality of second through electrodes 306 connected to a part of the plurality of wiring lines of the second wiring structure 352 and penetrating the second semiconductor substrate 302, a second passivation layer 392 formed on the inactive surface 302B of the second semiconductor substrate 302, a plurality of second back bonding pads 396 connected to the plurality of second through electrodes 306 on the second passivation layer 392, and a second back insulating film 394 surrounding sidewalls of each of the plurality of second back bonding pads 396. According to an exemplary embodiment, the second semiconductor chip 300 includes a second interlayer insulating film 304 interposed between the second semiconductor substrate 302 and the second wiring structure 352 for protecting semiconductor elements formed on the active surface 302F of the second semiconductor substrate 302.

[0128] The active surface 302F of the second semiconductor substrate 302 may be the front surface of the second semiconductor substrate 302, and the inactive surface 302B of the second semiconductor substrate 302 may be the back surface of the second semiconductor substrate 302. In FIGS. 13 and 14, the active surface 302F of the second semiconductor substrate 302 has a face-down arrangement facing downward, and the active surface 302F of the second semiconductor substrate 302 is referred to as the lower surface of the second semiconductor substrate 302.

[0129] According to an exemplary embodiment, the second semiconductor chip 300 includes a second front wiring layer 360 and a second front insulating film 382 that are sequentially stacked on the lower surface of the second wiring structure 352. The second front wiring layer 360 is spaced apart from the second semiconductor substrate 302 via the second wiring structure 352. According to an exemplary embodiment, the second front wiring layer 360 includes a plurality of second conductive patterns 362, a second compensation pattern 374, and a second insulating spacer 364 interposed between the plurality of second conductive patterns 362 and the second compensation pattern 374. The plurality of second conductive patterns 362 are disposed closer to the active surface 302F of the second semiconductor substrate 302 than the second compensation pattern 374. The second insulating spacer 364 includes a portion interposed between the second compensation pattern 374 and the second wiring structure 352, a portion interposed between the plurality of second conductive patterns 362 and the second front insulating film 382, and a portion interposed between the plurality of second conductive patterns 362 and the second compensation pattern 374. The second front insulating film 382 contacts the lower surface of the second compensation pattern 374 but is spaced apart from the plurality of first conductive patterns 262 via the second insulating spacer 364. According to an exemplary embodiment, the second semiconductor chip 300 includes a plurality of second front bonding pads 384 that penetrate through the second front insulating film 382 and the second insulating spacer 364 and are respectively in contact with the plurality of second conductive patterns 362. In some embodiments, the sidewalls of the plurality of front bonding pads 384 are surrounded by the second front insulating film 382 and the second insulating spacer 364. The sidewalls of the plurality of second front bonding pads 384 include a portion facing the second compensation pattern 374 via the second insulating spacer 364.

[0130] The second semiconductor substrate 302 is a component having substantially the same or similar components as the semiconductor substrate 102 shown in FIGS. 1 and 2. The plurality of second through electrodes 306 are components having substantially the same or similar components as the plurality of through electrodes 106 shown in FIGS. 1 and 2. The second wiring structure 352 is a component having substantially the same or similar components as the wiring structure 152 shown in FIGS. 1 to 3. The plurality of second back bonding pads 396 are components having substantially the same or similar components as the plurality of back bonding pads 196 shown in FIG. 1. The second back insulating film 394 is a component having substantially the same or similar components as the back insulating film 194 shown in FIG. 1. The second passivation layer 392 is a component having substantially the same or similar components as the passivation layer 192 shown in FIG. 1. Detailed descriptions thereof are omitted herein. The plurality of second conductive patterns 362, the second insulating spacers 364, and the second compensation patterns 374 are components having substantially the same or similar components as the plurality of conductive patterns 162, the insulating spacers 164, and the compensation patterns 174 shown in FIGS. 1 to 4C, respectively. The second front insulating film 382 is a component having substantially the same or similar components as the front insulating film 182 shown in FIGS. 1 to 3. The plurality of second front bonding pads 384 are components having substantially the same or similar components as the plurality of front bonding pads 184 shown in FIGS. 1 to 3. Therefore, detailed descriptions thereof are omitted.

[0131] In some embodiments, the uppermost second semiconductor chip 300 among the plurality of second semiconductor chips 300 may not include the plurality of second through electrodes 306, the second passivation layer 392, the second back insulating film 394, and the plurality of second back bonding pads 396. In some embodiments, the vertical height of the uppermost second semiconductor chip 300 among the plurality of second semiconductor chips 300 has a value greater than the vertical height of each of the remaining second semiconductor chips 300. The vertical heights of the remaining second semiconductor chips 300 have generally the same value.

[0132] In some embodiments, a semiconductor package 1000 including a first semiconductor chip 200 and a plurality of second semiconductor chips 300 is referred to as a HBM (High Bandwidth Memory) DRAM semiconductor chip. For example, the first semiconductor chip 200 includes a serial-parallel conversion circuit and is a buffer chip for controlling the plurality of second semiconductor chips 300, and the plurality of second semiconductor chips 300 are core chips including DRAM memory cells. In an exemplary embodiment, the first semiconductor chip 200 is referred to as a master chip, and each of the plurality of second semiconductor chips 300 is referred to as a slave chip.

[0133] In some other embodiments, at least one of the first semiconductor chip 200 and the plurality of second semiconductor chips 300 is a memory semiconductor chip. At least one of the first semiconductor chip 200 and the plurality of second semiconductor chips 300 is a logic chip. The logic chip includes a central processing unit (CPU) chip, a graphic processing unit (GPU) chip, and an application processor (AP) chip.

[0134] As shown in FIG. 14, two adjacent second semiconductor chips 300 in the vertical direction (Z direction) are bonded by a direct bonding method, for example, a hybrid direct bonding method. A plurality of second back bonding pads 396 of the lower second semiconductor chip 300 among the two adjacent second semiconductor chips 300 are aligned and bonded in the vertical direction (for example, the Z direction) with a plurality of second front bonding pads 384 of the upper second semiconductor chip 300 among the two adjacent second semiconductor chips 300. Further, the second back insulating film 394 of the lower second semiconductor chip 300 is bonded to the second front insulating film 382 of the upper second semiconductor chip 300. The surface of the back insulating film 394 of the lower second semiconductor chip 300 and the surface of the second front insulating film 382 of the second semiconductor chip 300 can each have a bonding force suitable for bonding through plasma treatment and / or wet treatment. For example, the bonding between two adjacent second semiconductor chips 300 is achieved by bringing the bonding surface of the lower second semiconductor chip 300 into contact with the bonding surface of the upper second semiconductor chip 300 and then applying heat to bond each of the plurality of second back bonding pads 396 and the second back insulating film 394 of the lower second semiconductor chip 300 to each of the plurality of second front bonding pads 384 and the second front insulating film 382 of the upper second semiconductor chip 300.

[0135] In some embodiments, the first semiconductor chip 200 and the lowermost second semiconductor chip 300 are bonded by a direct bonding method substantially the same as or similar to the bonding method between two adjacent second semiconductor chips 300 in the aforementioned vertical direction (Z direction). For example, a plurality of first back bonding pads 296 of the first semiconductor chip 200 and a plurality of second front bonding pads 384 of the lowermost second semiconductor chip 300 are aligned and bonded in the vertical direction (for example, the Z direction). For example, the upper surface of the first back insulating film 294 of the first semiconductor chip 200 is bonded to the lower surface of the second front insulating film 382 of the second semiconductor chip 300.

[0136] According to an exemplary embodiment, the semiconductor package 1000 further includes a molding layer 810 disposed on the first semiconductor chip 200 and covering the side surfaces of the plurality of second semiconductor chips 300. The molding layer 810 covers a part of the upper surface of the first semiconductor chip 200 not covered by the plurality of second semiconductor chips 300. In an exemplary embodiment, the molding layer 810 may not cover the upper surface of the uppermost second semiconductor chip 300. In another exemplary embodiment, the molding layer 810 may be formed to further cover the upper surface of the uppermost second semiconductor chip 300. The molding layer 810 includes, for example, an epoxy molding compound EMC.

[0137] In a semiconductor package according to a comparative example, when two semiconductor chips that do not include a compensation pattern according to an exemplary embodiment are bonded by a direct bonding method, the topology of the bonding interface of the two semiconductor chips deteriorates due to the residual stress of the plurality of conductive patterns in the front wiring layer, and the bonding reliability between the semiconductor chips decreases.

[0138] According to an exemplary embodiment of the present invention, the compensation pattern 374 can fill the empty regions between the plurality of conductive patterns 362 in the front wiring layer 360 to equalize the pattern density of the front wiring layer 360. Thereby, when two or more semiconductor chips are bonded by a direct bonding method, the surface strain of the bonding interface is improved, the generation of voids or peeling of the insulating film at the bonding surface is suppressed, and the bonding reliability between the two bonded semiconductor chips is improved.

[0139] FIG. 15 is a cross-sectional view showing a semiconductor package 2000 according to an exemplary embodiment of the present invention.

[0140] Referring to FIG. 15, the semiconductor package 2000 includes an interposer 500, a main board 600 on which the interposer 500 is mounted, at least one sub-semiconductor package 1000 attached to the interposer 500 and including a first semiconductor chip 200 and a plurality of second semiconductor chips 300, and a third semiconductor chip 400. In FIG. 14, the sub-semiconductor package 1000 corresponds to the semiconductor package 1000 described with reference to FIGS. 13 and 14. In this specification, the semiconductor package 2000 may also be referred to as a system.

[0141] According to an exemplary embodiment, the sub-semiconductor package 1000 is attached to the interposer 500 via a plurality of first connection bumps 286. The plurality of first connection bumps 286 are attached to a plurality of first front bonding pads 284 and are electrically connected to a plurality of first conductive patterns 262 of the first semiconductor chip 200 and a plurality of wiring lines and a plurality of wiring ratios of the first wiring structure 252 described with reference to FIG. 13. The plurality of first connection bumps 286 provide at least one of signals, power, or ground for the sub-semiconductor package 1000.

[0142] FIG. 15 shows that the semiconductor package 2000 includes two sub-semiconductor packages 1000, but is not limited thereto. For example, the semiconductor package 2000 may include one sub-semiconductor package 1000 or three or more sub-semiconductor packages 1000.

[0143] The third semiconductor chip 400 includes a third semiconductor substrate 410 on which semiconductor elements are formed on the active surface, and a plurality of connection pads 420. In an exemplary embodiment, each of the plurality of connection pads 420 includes at least one of aluminum, copper, and nickel. The third semiconductor chip 400 is attached to the interposer 500 via a plurality of second connection bumps 460. The plurality of second connection bumps 460 are attached to the plurality of connection pads 420. The third semiconductor chip 400 may be a logic chip. For example, the third semiconductor chip 400 may be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0144] The third semiconductor substrate 410 has components generally similar to those of the first semiconductor substrate 202 or the second semiconductor substrate 302 shown in FIG. 13, and the second connection bumps 460 have components similar to those of the first connection bumps 286, and detailed descriptions thereof are omitted.

[0145] According to an exemplary embodiment, the interposer 500 includes a base layer 510, a plurality of first upper surface pads 522 and a plurality of first lower surface pads 524 respectively disposed on the upper and lower surfaces of the base layer 510, and a plurality of first wiring paths 530 that electrically connect the first upper surface pads 522 and the first lower surface pads 524 via the base layer 510. The base layer 510 includes a semiconductor, glass, ceramics, or plastic. For example, the base layer 510 includes silicon. The plurality of first wiring paths 530 include wiring layers connected to the plurality of first upper surface pads 522 and / or the plurality of first lower surface pads 524 on the upper and / or lower surfaces of the base layer 510 and / or internal through electrodes provided inside the base layer 510 to electrically connect the plurality of first upper surface pads 522 and the plurality of first lower surface pads 524. A plurality of first connection bumps 286 that electrically connect the sub-semiconductor package 1000 and the interposer 500, or a plurality of second connection bumps 460 that electrically connect the third semiconductor chip 400 and the interposer 500 may be connected to the plurality of first upper surface pads 522.

[0146] A first underfill layer 820 is interposed between the sub-semiconductor package 1000 and the interposer 500, and a second underfill layer 480 is interposed between the third semiconductor chip 400 and the interposer 500. The first underfill layer 820 surrounds the first connection bump 265, and the second underfill layer 480 surrounds the second connection bump 460.

[0147] The semiconductor package 2000 further includes a package molding layer 900 on the interposer 500 that surrounds the side surfaces of the sub-semiconductor package 1000 and the third semiconductor chip 400. The package molding layer 900 includes, for example, an epoxy molding compound EMC. In an exemplary embodiment, the package molding layer 900 covers the upper surfaces of the sub-semiconductor package 1000 and the third semiconductor chip 400. In other exemplary embodiments, the package molding layer 900 may not cover the upper surfaces of the sub-semiconductor package 1000 and the third semiconductor chip 400. For example, a heat dissipation member is attached onto the sub-semiconductor package 1000 and the third semiconductor chip 400 via a thermal interface material (TIM) layer.

[0148] A plurality of board connection terminals 540 are attached onto the plurality of first bottom pads 524. The plurality of board connection terminals 540 electrically connect the interposer 500 and the main board 600.

[0149] The main board 600 includes a base board layer 610, a plurality of second upper pads 622 and a plurality of second bottom pads 624 disposed on the upper surface and the lower surface of the base board layer 610 respectively, and a plurality of second wiring paths 630 that electrically connect the plurality of second upper pads 622 and the plurality of second bottom pads 624 via the base board layer 610.

[0150] In an exemplary embodiment, the main board 600 is a printed circuit board. For example, the main board 600 is a multi-layer printed circuit board. The base board layer 610 includes at least one substance selected from phenolic resin, epoxy resin, and polyimide.

[0151] On the upper and lower surfaces of the base board layer 610, a solder resist layer (not shown) is formed to expose a plurality of second upper surface pads 622 and a plurality of second lower surface pads 624. A plurality of board connection terminals 540 are connected to the plurality of second upper surface pads 622, and a plurality of external connection terminals 640 are connected to the plurality of second lower surface pads 624. The plurality of board connection terminals 540 electrically connect between the plurality of first lower surface pads 524 and the plurality of second upper surface pads 622. The plurality of external connection terminals 640 connected to the plurality of second lower surface pads 624 electrically and physically connect between the semiconductor package 2000 and an external device.

[0152] In an exemplary embodiment, the semiconductor package 2000 does not include the main board 600, and a plurality of board connection terminals 540 of the interposer 500 can perform the function of external connection terminals.

[0153] As described above, the present invention has been described in detail with reference to preferred embodiments. However, the present invention is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art within the technical idea and scope of the present invention.

Explanation of Reference Numerals

[0154] 100: Semiconductor chip 102: Semiconductor substrate 100F: Front surface 102B: First surface 102F: Second surface 104: Interlayer insulating film 106: Through electrode 122: First wiring layer 124: First wiring line 126: First wiring via 128: First wiring insulation film 142: Second wiring layer 142u: Upper surface 144: Second wiring line 146: Second wiring via 148: Second wiring insulation film 152: Wiring structure 160: Front wiring layer 162: Conductive pattern 162a: First surface 162b: Second surface 164: Insulating spacer 174: Compensation pattern 174a: First surface 174b: Second surface 182: Front insulating film 184: Front bonding pad

Claims

1. a semiconductor substrate having a first surface and a second surface opposite the first surface; a wiring structure disposed on the second surface of the semiconductor substrate; a plurality of conductive patterns spaced apart from the semiconductor substrate via the wiring structure and each connected to the wiring structure; a compensation pattern that is horizontally spaced apart from the plurality of conductive patterns on the wiring structure and is farther away from the second surface of the semiconductor substrate than the plurality of conductive patterns; an insulating spacer interposed between the plurality of conductive patterns and the compensation pattern; 4. A semiconductor chip comprising:

2. 2. The semiconductor chip of claim 1, wherein the insulating spacer includes a portion interposed between the compensation pattern and the wiring structure.

3. a front insulating film covering the conductive patterns, the compensation pattern, and the insulating spacer; a plurality of front bonding pads penetrating the front insulating film and contacting the conductive patterns, respectively; The semiconductor chip of claim 1 further comprising:

4. Each of the conductive patterns includes a first surface facing the semiconductor substrate and a second surface opposite the semiconductor substrate; the compensation pattern includes the semiconductor substrate, a first surface facing the semiconductor substrate, and a second surface opposite the semiconductor substrate; the second surfaces of the conductive patterns are spaced apart from the front insulating film via the insulating spacer; The semiconductor chip of claim 3 , wherein the first surface of the compensation pattern contacts the insulating spacer.

5. 4. The semiconductor chip according to claim 3, wherein a sidewall of the compensation pattern includes a portion facing the front bonding pads via the insulating spacer.

6. Each of the conductive patterns includes a first surface facing the semiconductor substrate and a second surface opposite the semiconductor substrate; the compensation pattern includes a first surface facing the semiconductor substrate and a second surface opposite the semiconductor substrate; The semiconductor chip according to claim 1 , wherein the second surfaces of the plurality of conductive patterns and the second surface of the compensation pattern are disposed on the same plane.

7. Each of the conductive patterns includes a first surface facing the semiconductor substrate and a second surface opposite the semiconductor substrate; the compensation pattern includes a first surface facing the semiconductor substrate and a second surface opposite the semiconductor substrate; The insulating spacer is a first spacer film covering the second surface and side walls of the conductive patterns on the wiring structure and in contact with the conductive patterns; a second spacer film covering the first surface and a sidewall of the compensation pattern on the first spacer film and in contact with the compensation pattern; 2. The semiconductor chip according to claim 1 ,

8. a front insulating film covering the conductive patterns, the compensation pattern, and the insulating spacer; a plurality of front bonding pads each penetrating the front insulating film and contacting the second surface of the conductive patterns; Further comprising: the second surfaces of the conductive patterns are spaced apart from the front insulating film via the first spacer film; 8. The semiconductor chip of claim 7, wherein the sidewalls of the conductive patterns are spaced apart from the sidewalls of the compensation pattern via the first spacer layer and the second spacer layer.

9. a front insulating film covering the conductive patterns, the compensation pattern, and the insulating spacer; a plurality of front bonding pads penetrating the front insulating film and contacting the conductive patterns, respectively; a first front dummy pad penetrating the front insulating film and contacting the compensation pattern; The semiconductor chip of claim 1 further comprising:

10. a dummy pattern interposed between a first conductive pattern and a second conductive pattern selected from the plurality of conductive patterns on the wiring structure; Further comprising: the compensation pattern includes a portion interposed between the first conductive pattern and a dummy pattern and a portion interposed between the second conductive pattern and the dummy pattern, 2. The semiconductor chip of claim 1, wherein the compensation pattern is spaced apart from the first conductive pattern, the second conductive pattern, and the dummy pattern via the insulating spacer.

11. A semiconductor substrate; a wiring structure disposed on an upper surface of the semiconductor substrate, the wiring structure including a plurality of wiring lines, a plurality of wiring vias, and a wiring insulating film surrounding the plurality of wiring lines and the plurality of wiring vias; a plurality of conductive patterns spaced apart horizontally on the wiring structure and having a vertical thickness greater than the thickness of the plurality of wiring lines; an insulating spacer covering the plurality of conductive patterns and the wiring structure; a compensation pattern spaced apart from the plurality of conductive patterns in the horizontal direction on the insulating spacer with the insulating spacer interposed therebetween; a front insulating film covering the conductive patterns, the compensation pattern, and the insulating spacer; a plurality of front bonding pads each penetrating the front insulating film and the insulating spacer and contacting the conductive patterns; 4. A semiconductor chip comprising:

12. The semiconductor chip of claim 11 , wherein a bottom surface of the compensation pattern is located at a lower vertical level than top surfaces of the plurality of conductive patterns.

13. The semiconductor chip according to claim 11 , wherein the compensation pattern is disposed so as to surround the plurality of conductive patterns in a plan view.

14. the plurality of conductive patterns include a first conductive pattern and a second conductive pattern disposed adjacent to each other with the compensation pattern interposed therebetween; 12. The semiconductor chip according to claim 11, wherein in a plan view, a first distance between the first conductive pattern and the compensation pattern is equal to a second distance between the second conductive pattern and the compensation pattern.

15. In a plan view, the compensation pattern includes a plurality of holes; 12. The semiconductor chip according to claim 11, wherein the conductive patterns are individually disposed in the holes, respectively, to have an independent island shape.

16. the compensation pattern has holes that accommodate the conductive patterns in a plan view; The plurality of conductive patterns include A first conductive pattern; a first group of conductive patterns having a sidewall surrounding the first conductive pattern and facing the compensation pattern in a plan view; Including, the first group of conductive patterns are each spaced a first distance from the compensation pattern; 12. The semiconductor chip of claim 11, wherein a distance between one of the first group of conductive patterns and the first conductive pattern is less than twice the first separation distance.

17. a dummy pattern interposed between a first conductive pattern and a second conductive pattern selected from the plurality of conductive patterns on the wiring structure; Further comprising: the first conductive pattern, the second conductive pattern, and the dummy pattern are disposed in holes of the compensation pattern in a plan view; the first conductive pattern, the second conductive pattern, and the dummy pattern are each spaced apart from the compensation pattern by a first separation distance; 12. The semiconductor chip of claim 11, wherein a first distance between the first conductive pattern and the dummy pattern and a second distance between the second conductive pattern and the dummy pattern are each less than twice the first separation distance.

18. A semiconductor package including a first semiconductor chip and a second semiconductor chip bonded to each other, The first semiconductor chip is a first semiconductor substrate including opposed first and second surfaces; a first plurality of backside bonding pads on the first surface of the first semiconductor substrate; a first back surface insulating film surrounding sidewalls of the first plurality of back surface bonding pads on the first surface of the first semiconductor substrate; Including, The second semiconductor chip is a second semiconductor substrate including a first surface opposite to the first semiconductor substrate and a second surface opposing the first surface of the first semiconductor substrate; a wiring structure on the second surface of the second semiconductor substrate; a front wiring layer separated from the second semiconductor substrate via the wiring structure; a second front insulating film interposed between the front wiring layer and the first rear insulating film and bonded to the first rear insulating film; a plurality of second front bonding pads that penetrate the second front insulating film and are connected to the plurality of first back bonding pads; Including, The front wiring layer is a plurality of conductive patterns including a first surface in contact with the wiring structure and a second surface opposite to the first surface, the conductive patterns being spaced apart from one another in a horizontal direction; a compensation pattern including a first surface facing the wiring structure and a second surface contacting the second front insulating film opposite to the first surface, the compensation pattern being spaced apart from the conductive patterns in the horizontal direction; an insulating spacer interposed between the conductive patterns and the compensation pattern and in contact with the second surface of the conductive patterns and the first surface of the compensation pattern, The semiconductor package, wherein the second front surface bonding pads extend through the insulating spacer and contact the second surface of the conductive patterns.

19. 20. The semiconductor package of claim 18, wherein a sidewall of the compensation pattern includes a portion facing the second front bonding pads with the insulating spacer interposed therebetween.

20. The insulating spacer is a first spacer film covering the second surface and side walls of the conductive patterns on the wiring structure; a second spacer layer spaced apart from the conductive patterns via the first spacer layer and covering the first surface and sidewalls of the compensation pattern; Including, the second surfaces of the conductive patterns are spaced apart from the second front insulating film via the first spacer film; 20. The semiconductor package of claim 18, wherein the sidewalls of the conductive patterns are spaced apart from the sidewalls of the compensation pattern via the first spacer layer and the second spacer layer.

Images