Power semiconductor element and electric power conversion equipment including the same

Abstract

To provide a power semiconductor element having a technical effect of controlling the thickness or width of a channel and power conversion equipment including the same.SOLUTION: A power semiconductor element includes: a substrate 110; a first conductivity type epi layer 115 disposed on the substrate; a JFET region 137 disposed on the first conductivity type epi layer; a plurality of second conductivity type second wells 135 disposed in the JFET region, spaced apart from each other; a first conductivity type source region 140 disposed on the second conductivity type second wells; a gate insulating layer 150 disposed on the first conductivity type source region; a gate 155 disposed on the gate insulating layer; and a second conductivity type first well 130 disposed under the gate insulating layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The embodiments relate to a power semiconductor device and a power conversion device including the same.

Background Art

[0002] A power semiconductor is one of the core elements that determine the efficiency, speed, durability, and reliability of a power electronics system.

[0003] Recently, with the development of the power electronics industry, the silicon (Si) power semiconductors previously used have reached their physical limits, and active research has been conducted on wide bandgap (WBG) power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) to replace them.

[0004] WBG power semiconductor devices have a bandgap energy approximately three times that of Si power semiconductor devices, thereby having characteristics such as a low intrinsic carrier concentration, a high breakdown electric field (about 4 to 20 times), a high thermal conductivity (about 3 to 13 times), and a high electron saturation velocity (about 2 to 2.5 times).

[0005] Due to such characteristics, they can operate in high-temperature and high-voltage environments and have a high switching speed and low switching losses. Among them, GaN (gallium nitride) power semiconductor devices can be used in low-voltage systems, and SiC (silicon carbide) power semiconductor devices are suitable for high-voltage systems.

[0006] Conventional SiC MOSFETs can be classified according to their structures into MOSFETs with a trench structure, MOSFETs with a vertical doubly implanted structure (DIMOSFETs), or MOSFETs with a lateral diffused structure, etc. DIMOSFETs are sometimes also called Planar MOSFETs or VDMOSFETs.

[0007] On the other hand, in MOSFETs, it is difficult to control the channel thickness, doping concentration, etc., which leads to the problem of leakage current occurring in the channel. This is related to the problems of degradation of the electrical performance and reliability of the device.

Summary of the Invention

Problems to be Solved by the Invention

[0008] One of the technical problems of the embodiment is to control the channel thickness or width in the SiC MOSFET.

[0009] Another technical problem of the embodiment is to prevent the channel leakage current in the SiC MOSFET.

[0010] Another technical problem of the embodiment is to improve the electrical performance of the SiC MOSFET.

[0011] The technical problems of the embodiment are not limited to those described in this item and include those that can be understood from the description of the invention.

Means for Solving the Problems

[0012] The power semiconductor device according to the embodiment may include a substrate 110, a first conductivity type epi-layer 115 disposed on the substrate 110, a JFET region 137 disposed on the first conductivity type epi-layer 115, a plurality of second conductivity type second wells 135 disposed in the JFET region 137 at intervals from each other, a first conductivity type source region 140 disposed on the second conductivity type second well 135, a gate insulating layer 150 disposed on the first conductivity type source region 140, a gate 155 disposed on the gate insulating layer 150, and a second conductivity type first well 130 disposed under the gate insulating layer.

[0013] Also, in the embodiment, the second conductivity type first well 130 is disposed at intervals from the second conductivity type second well 135.

[0014] Also, in the embodiment, the JFET region 137 can be located between the second conductivity type first well 130 and the second conductivity type second well 135.

[0015] Also, in the embodiment, the horizontal width of the gate insulating layer 150 may be larger than the horizontal width of the second conductivity type first well 130.

[0016] Also, in the embodiment, the first conductivity type source region 140 can be in contact with the JFET region 137.

[0017] Also, in the embodiment, the upper surface of the second conductivity type first well 130 can be in contact with the gate insulating layer 150, and the side surface can be in contact with the first conductivity type source region 140.

[0018] Also, in the embodiment, the thickness of the second conductivity type first well 130 may be thinner than the thickness of the first conductivity type source region 140.

[0019] Also, in the embodiment, the height of the upper surface of the second conductivity type first well 130 may be the same as the height of the upper surface of the first conductivity type source region 140.

[0020] In addition, a power semiconductor device according to another embodiment includes a substrate 110, a first conductivity type epi-layer 115 disposed on the substrate 110, a CSL region 138 disposed on the first conductivity type epi-layer 115, a plurality of second conductivity type second wells 135 spaced apart from each other in the CSL region 138, a first conductivity type source region 140 disposed on the second conductivity type second wells 135, a gate 155 disposed between the plurality of second conductivity type second wells 135, and a gate insulating layer 150 surrounding the gate, and may further include a second conductivity type first well 130 disposed on a side surface of the gate insulating layer 150.

[0021] In addition, in an embodiment, the second conductivity type first well 130 can be separated from the second conductivity type second well 135.

[0022] In addition, in an embodiment, a side surface of the gate insulating layer 150 can be in contact with the first conductivity type source region 140 and the second conductivity type first well 130.

[0023] In addition, in an embodiment, an upper surface of the second conductivity type first well 130 is in contact with the first conductivity type source region 140, and the CSL region 138 can be located between the second conductivity type first well 130 and the second conductivity type second well 135.

Advantages of the Invention

[0024] The power semiconductor device according to the embodiment has a technical effect of being able to control the thickness or width of a channel.

[0025] For example, the embodiment can control the thickness or width of the channel by controlling the thickness or width of the second conductivity type first well 130 and the second conductivity type second well 135.

[0026] In addition, the embodiment has a technical effect of being able to improve the electrical performance of a SiC MOSFET.

[0027] For example, the embodiment widely forms the width of the channel to reduce the on-resistance (Ron ) can be reduced to improve the electrical performance.

[0028] In addition, the embodiment has a technical effect of preventing the leakage current of the channel.

[0029] For example, in the embodiment, PN junctions are formed at the upper and lower parts of the channel, and depletion is formed at the upper and lower parts in the off state, and the leakage current of the channel can be prevented by channel blocking.

[0030] The technical effects of the embodiment are not limited to those described in this item, and include those that can be grasped from the description of the invention.

Brief Description of the Drawings

[0031]

Figure 1

Figure 2

Figure 3

Figure 4a

Figure 4b

Figure 4c

Figure 4d

Figure 4e

Figure 5a

Figure 5b

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0032] Hereinafter, the embodiments disclosed in this specification will be described in detail with reference to the accompanying drawings. The suffixes “module” and “section” for the components used in the following description are given or mixed for the purpose of facilitating the preparation of the specification, and do not have meanings or roles that are distinguishable from each other by themselves. Also, the accompanying drawings are for the purpose of facilitating the understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the accompanying drawings. Also, when an element such as a layer, region, or substrate is referred to as being “on” another component, this includes the case where it is directly on another element or there may be another intermediate element therebetween.

[0033] In the specification or claims, the meaning of “Configuration A includes at least one of a, b, and / or c” means (1) when Configuration A includes a, (2) when Configuration A includes b, (3) when Configuration A includes c, (4) when Configuration A includes a and b, (5) when Configuration A includes b and c, (6) when Configuration A includes a and c, and (7) when Configuration A includes all of a, b, and c.

[0034] Singular expressions include not only singular but also plural expressions unless the context clearly indicates otherwise. For example, the meaning of “Configuration A includes one structure” can include the meaning of “Configuration A includes one or more structures”.

[0035] FIG. 1 is an exemplary configuration diagram of a power conversion device 1000 according to an embodiment.

[0036] The power conversion device 1000 according to the embodiment can receive a DC power supply from a battery or a fuel cell and convert it into an AC power supply, and can supply the AC power supply to a predetermined load. For example, the power conversion device 1000 according to the embodiment can include an inverter, receive a DC power supply from a battery, convert it into a three-phase AC power supply, and supply it to the motor M. The motor M can provide power to an electric vehicle, a fuel cell vehicle, or the like.

[0037] The power conversion device 1000 according to the embodiment can include a power semiconductor element 100. The power semiconductor element 100 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto, and can include an IGBT (Insulated Gate Bipolar Transistor).

[0038] For example, the power conversion device 1000 can include a plurality of power semiconductor elements 100a, 100b, 100c, 100d, 100e, 100f, and can include a plurality of diodes (not shown). Each of the plurality of diodes may be internally present in the form of an internal diode in each of the power semiconductor elements 100a, 100b, 100c, 100d, 100e, 100f, but is not limited thereto, and may be separately arranged.

[0039] The embodiment can convert a DC power supply into an AC power supply by on / off control of a plurality of power semiconductor elements 100a to 100f. For example, the power conversion device 1000 according to the embodiment can turn on the first power semiconductor element 100a and turn off the second power semiconductor element 100b in the first time interval of one cycle to supply a positive-polarity power supply to the motor M, and turn off the first power semiconductor element 100a and turn on the second power semiconductor element 100b in the second time interval of one cycle to supply a negative-polarity power supply to the motor M.

[0040] In an embodiment, a group of power semiconductor devices arranged in series between a high-voltage line and a low-voltage line on the input side can be referred to as an arm. For example, the first power semiconductor device 100a and the second power semiconductor device 100b constitute the first arm, the third power semiconductor device 100c and the fourth power semiconductor device 100d constitute the second arm, and the fifth power semiconductor device 100e and the sixth power semiconductor device 100f can constitute the third arm.

[0041] The upper and lower power semiconductor devices in the arm are controlled so as not to be turned on simultaneously. For example, in the first arm, the first power semiconductor device 100a and the second power semiconductor device 100b do not turn on simultaneously but turn on and off alternately.

[0042] A high power supply is applied to each of the power semiconductor devices 100a to 100f in the off state. For example, when the first power semiconductor device 100a is on and the second power semiconductor device 100b is off, the input voltage is applied to the second power semiconductor device 100b as it is. The voltage input to the second power semiconductor device 100b is a relatively high voltage, and the breakdown voltage of each of the power semiconductor devices 100a to 100f can be designed to a high level so as to withstand such a high voltage.

[0043] Each of the power semiconductor devices 100a to 100f can conduct a high current in the on state. The motor M is driven by a relatively high current, and such a high current is supplied to the motor M through the power semiconductor that is on.

[0044] The high voltage applied to each of the power semiconductor devices 100a to 100f can induce a high switching loss. The high current flowing through the power semiconductor devices 100a to 100f can induce a high conduction loss. In order to release the heat generated by such losses, the power semiconductor devices 100a to 100f can be packaged in a power semiconductor module including a heat dissipation means.

[0045] The power semiconductor device 100 of the embodiment may be a SiC (Silicon Carbide) power semiconductor device, capable of operating in a high-temperature and high-voltage environment, and having a high switching speed and low switching loss.

[0046] On the other hand, the power conversion device 1000 according to the embodiment may include a plurality of power semiconductor modules.

[0047] For example, a plurality of power semiconductor devices 100a to 100f illustrated in FIG. 1 are packaged in one power semiconductor module, or the power semiconductor devices constituting each arm are packaged in one power semiconductor module.

[0048] For example, the first power semiconductor device 100a, the second power semiconductor device 100b, the third power semiconductor device 100c, the fourth power semiconductor device 100d, the fifth power semiconductor device 100e, and the sixth power semiconductor device 100f illustrated in FIG. 1 are packaged in one power semiconductor module.

[0049] In addition, additional power semiconductor devices arranged in parallel with each of the power semiconductor devices 100a to 100f may be further included to increase the current capacity. In such a case, the number of power semiconductor devices included in the power semiconductor module is more than six.

[0050] The power conversion device 1000 according to the embodiment may also include power semiconductor devices in the form of diodes in addition to the power semiconductor devices 100a to 100f in the form of transistors. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor device 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor device 100b. And such diodes may also be packaged together in one power semiconductor module. Further, the diodes may be arranged in the form of internal diodes in each power semiconductor device.

[0051] Next, the power semiconductor elements constituting each arm are packaged in one power semiconductor module.

[0052] For example, the first power semiconductor element 100a and the second power semiconductor element 100b constituting the first arm are packaged in the first power semiconductor module, the third power semiconductor element 100c and the fourth power semiconductor element 100d constituting the second arm are packaged in the second power semiconductor module, and the fifth power semiconductor element 100e and the sixth power semiconductor element 100f constituting the third arm are packaged in the third power semiconductor module.

[0053] In addition, additional power semiconductor elements arranged in parallel with each of the power semiconductor elements 100a to 100f can be further included to increase the current capacity. In this case, the number of power semiconductor elements included in each power semiconductor module is more than two. And each arm includes, in addition to the power semiconductor elements 100a to 100f in transistor form, power semiconductor elements in diode form (not shown), and such diodes may also be packaged together in one power semiconductor module. Also, the diodes may be arranged in the form of internal diodes in each power semiconductor element.

[0054] Next, FIG. 2 is a cross-sectional view of one of the power semiconductor elements 100 according to the embodiment.

[0055] The power semiconductor element 100 according to the embodiment can include a source electrode 190 disposed above a predetermined semiconductor epitaxial layer 120, a gate electrode 175, and a drain electrode 105 disposed below the semiconductor epitaxial layer 120.

[0056] In the form of a MOSFET, the source electrode 190 or the gate electrode 175 can include an Al-based metal, and the drain electrode 105 can include a Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, NiV / Ag, V (vanadium) / Ni / Ag, etc., but is not limited thereto.

[0057] Next, FIG. 3 is a cross-sectional view of a power semiconductor device according to an embodiment. Referring to FIG. 3, the power semiconductor device according to the embodiment can include a substrate 110, a first conductivity type epi layer 115, a second conductivity type first well 130, a second conductivity type second well 135, a first conductivity type source region 140, a JFET region 137, a gate insulating layer 150, and a source electrode 162. The “first conductivity type epi layer” can be referred to as the “epi layer”, and the “second conductivity type first well” can be referred to as the “first well”. Also, in other configurations, the expressions of “first conductivity type” or “second conductivity type” may be omitted.

[0058] Specifically, in the embodiment, a drain electrode (not shown) may be disposed under the substrate 110. Also, the first conductivity type epi layer 115 is disposed on the substrate 110. The first conductivity type epi layer 115 may be an N-type drift region, but is not limited thereto. The substrate 110 and the first conductivity type epi layer 115 can include a 4H-SiC material, but are not limited thereto.

[0059] Also, a JFET region 137 is disposed on the first conductivity type epi layer 115. A plurality of second conductivity type second wells 135 are disposed spaced apart from each other in the JFET region 137. A first conductivity type source region 140 and a second conductivity type contact region 145 are disposed on the second conductivity type second well 135. The second conductivity type second well 135 and the first conductivity type source region 140 can partially overlap. Also, the second conductivity type second well 135 and the second conductivity type contact region 145 can partially overlap.

[0060] Also, a second conductivity type first well 130 is disposed on the second conductivity type second well 135. The second conductivity type second well 135 can be separated from the second conductivity type first well 130. A JFET region 137 can be located between the second conductivity type second well 135 and the second conductivity type first well 130.

[0061] Further, the height of the upper surface of the second-conductivity-type first well 130 may be the same as the height of the upper surface of the first-conductivity-type source region 140, but is not limited thereto. Also, a gate insulating layer 150 is disposed on the second-conductivity-type first well 130. The horizontal width of the gate insulating layer 150 may be larger than the horizontal width of the second-conductivity-type first well 130. The gate insulating layer 150 is disposed to cover the second-conductivity-type first well 130 and the first-conductivity-type source region 140. Also, the gate insulating layer 150 can cover a part of the second-conductivity-type contact region 145. Also, a source electrode 162 is disposed on a side portion of the gate insulating layer 150 so as to be in contact with the second-conductivity-type contact region 145. The source electrode 162 is electrically connected to the first-conductivity-type first source region 140 (see FIG. 4e).

[0062] Also, a gate 155 is disposed on the gate insulating layer 150. The horizontal width of the gate 155 may be smaller than the horizontal width of the gate insulating layer 150. Also, an interlayer insulating layer 160 is disposed to cover the gate 155. Also, a source electrode 162 is disposed on the second-conductivity-type contact region 145.

[0063] On the other hand, one of the technical problems of the embodiment is to increase the channel mobility in the MOSFET. On the other hand, in the MOSFET structure studied internally, it is difficult to control the depth, thickness, doping concentration, etc. of the channel, so the problem of channel leakage current has been studied.

[0064] In order to solve the above problems, in the embodiment, the second-conductivity-type first well 130 is disposed under the gate insulating layer 150. Specifically, the first-conductivity-type source region 140 is in contact with the JFET region 137, and a channel is formed through the JFET region 137 under the gate insulating layer 150 via the second-conductivity-type first well 130 and the second-conductivity-type second well 135.

[0065] FIGS. 5A and 5B are drawings showing in detail the left channel region Ch of FIG. 3.

[0066] For example, FIG. 5a is a detailed view of the channel region Ch in the On state of the power semiconductor device of the embodiment, and FIG. 5b is a detailed view of the channel region Ch in the Off state of the power semiconductor device of the embodiment.

[0067] Referring to FIG. 5b, in the off-state MOSFET, depletion occurs at the upper and lower parts of the channel. Specifically, in the second-conductivity-type first well 130 located at the upper part, a depletion 130D occurs in the lower direction, and in the second-conductivity-type second well 135 located at the lower part, a depletion 135D occurs in the upper direction. Thereby, in the embodiment, depletion occurs at the upper and lower parts of the channel in the off state, and there is a special technical effect that channel blocking is performed in the off state to effectively prevent the leakage current of the channel.

[0068] In addition, the embodiment has a technical effect that the width W of the channel can be controlled by controlling the thickness of the second-conductivity-type first well 130 or the thickness of the second-conductivity-type second well 135.

[0069] For example, the vertical distance between the second-conductivity-type first well 130 and the second-conductivity-type second well 135 can be controlled to be larger than the thickness of the second-conductivity-type first well 130.

[0070] Thereby, in the embodiment, since the upper second-conductivity-type first well 130 generates a depletion 130D in the lower direction and the lower second-conductivity-type second well 135 generates a depletion 135D in the upper direction, the leakage current of the channel can be effectively prevented. Therefore, the width W of the channel can be formed wider than before to reduce the on-resistance (R on ), and there is a technical effect that the electrical performance can be improved.

[0071] In FIG. 3, a SiC planar MOSFET is illustrated, but the technical features of the present invention are applicable to Trench MOSFET, SJ-MOSFET, IGBT, Diode, etc.

[0072] Hereinafter, with reference to FIGS. 4a to 4e, the manufacturing process of the power semiconductor device according to the embodiment will be described, and the technical features of the embodiment will be described in more detail.

[0073] First, referring to FIG. 4a, a first conductivity type epi-layer 115 can be formed on the substrate 110.

[0074] The substrate 110 and the first conductivity type epi-layer 115 can include, but are not limited to, SiC (Silicon Carbide).

[0075] For example, the substrate 110 and the first conductivity type epi-layer 115 can include, but are not limited to, a 4H-SiC material. For example, the substrate 110 and the first conductivity type epi-layer 115 can include 3C-SiC or 6H-SiC. Also, the first conductivity type may be N-type, and the second conductivity type may be P-type, but is not limited thereto. The first conductivity type epi-layer 115 may be an N-type drift region, but is not limited thereto. Also, a drain electrode (not shown) may be disposed under the substrate 110.

[0076] For example, the first conductivity type epi-layer 115 can include a plurality of layers having different concentrations and can have the function of a current spreading layer (CSL). For example, the first conductivity type epi-layer 115 can include a first conductivity type buffer layer (not shown) and a first conductivity type drift layer (not shown).

[0077] Also, a second conductivity type first well 130 is formed on the first conductivity type epi-layer 115. The second conductivity type first well 130 is formed by an implant process, but is not limited thereto. For example, the second conductivity type first well 130 has a P-type dopant of about 1×10 16 cm -3It may be ion-implanted at a concentration of ~ about 2×1018 cm-3. For example, Al, boron, or the like may be implanted, but it is not limited thereto.

[0078] Next, referring to FIG. 4b, a second-conductivity-type second well 135 can be formed under the second-conductivity-type first well 130 by an implant process. The second-conductivity-type second well 135 is disposed separately on the lower surface of the second-conductivity-type first well 130.

[0079] For example, the second-conductivity-type second well 135 may be ion-implanted at a concentration of about 1×10 17 cm -3 ~ about 2×10 19 cm -3 For example, Al, boron, or the like may be implanted, but it is not limited thereto.

[0080] Also, a first-conductivity-type source region 140 can be formed on the second-conductivity-type second well 135 by an implant process. The first-conductivity-type source region 140 is formed to penetrate the second-conductivity-type first well 130. Also, the first-conductivity-type source region 140 is formed to penetrate a part of the second-conductivity-type second well 135. The horizontal width of the first-conductivity-type source region 140 may be smaller than the horizontal width of the second-conductivity-type second well 135.

[0081] For example, the first-conductivity-type first source region 140 may be formed by ion-implanting an N-type dopant such as nitrogen or phosphorus at a concentration of about 1×10 19 cm -3 ~ about 7×10 19 cm -3 by a self-aligned method.

[0082] In an embodiment, the second-conductivity-type first well 130 having a top P-Well function can be in contact with the first-conductivity-type source region 140, whereby the second-conductivity-type first well 130 can be electrically contacted with the source electrode. Thereby, the second-conductivity-type first well 130 can function to maintain the zero potential of the second-conductivity-type second well 135.

[0083] Next, referring to FIG. 4c, a second-conductivity-type contact region 145 can be formed on a side portion of the first-conductivity-type source region 140. A lower surface of the second-conductivity-type contact region 145 is formed lower than a lower surface of the first-conductivity-type source region 140 and can be in contact with the second-conductivity-type second well 135. Also, an upper surface of the second-conductivity-type contact region 145 can have the same height as an upper surface of the first-conductivity-type source region 140. The second-conductivity-type contact region 145 can be contacted with the source electrode hereafter. Also, the second-conductivity-type contact region 145 can function to maintain the zero potential of the second-conductivity-type second well 135 and can function as a body diode.

[0084] Also, a JFET region 137 is formed by ion implantation in the first conductivity type under the second-conductivity-type first well 130. The JFET region 137 can be an area between the plurality of second-conductivity-type second wells 135. The JFET region 137 can be in contact with a side surface of the first-conductivity-type source region 140. Also, the JFET region 137 can be in contact with the second-conductivity-type first well 130 and the second-conductivity-type second well 135. The JFET region 137 can be located between the second-conductivity-type first well 130 and the second-conductivity-type second well 135. Hereafter, a channel is formed between a lower surface of the second-conductivity-type first well 130 and an upper surface of the second-conductivity-type second well 135 (see FIG. 3). Also, a lower surface of the JFET region 137 can be located higher than a lower surface of the second-conductivity-type second well 135.

[0085] Next, referring to FIG. 4d, a gate insulating layer 150 is disposed on the second conductivity type first well 130. The gate insulating layer 150 may be a thermal oxide film or a deposited oxide film, but is not limited thereto. The gate insulating layer 150 is formed to cover the second conductivity type first well 130, the first conductivity type source region 140, and the second conductivity type contact region 145. Also, the second conductivity type first well 130 can be positioned between the gate insulating layer 150 and the JFET region 137.

[0086] Also, a gate 155 is formed on the gate insulating layer 150. The horizontal width of the gate 155 may be larger than the horizontal width of the second conductivity type first well 130. The gate insulating layer 150 can be positioned between the gate 155 and the second conductivity type first well 130.

[0087] Also, an interlayer insulating layer 160 is disposed to cover the gate 155.

[0088] Next, referring to FIG. 4e, a part of the interlayer insulating layer 160 is removed. Also, a part of the gate insulating layer 150 is removed, and the first conductivity type source region 140 and the second conductivity type contact region 145 can be exposed. At this time, a source electrode 162 is formed in the region where the gate insulating layer 150 is removed. The source electrode 162 can be in contact with the first conductivity type source region 140 and the second conductivity type contact region 145.

[0089] In addition, a part of the interlayer insulating layer 160 can be removed to expose a part of the gate 155. Thereafter, a gate pad electrode (not shown) is formed on the exposed gate 155. Also, a source pad electrode (not shown) is formed on the source electrode 162. Subsequently, a first passivation layer (not shown) is formed so as to cover a part of the gate pad electrode and the source pad electrode. Further, a second passivation layer (not shown) is formed to cover the remaining parts of the gate pad electrode and the source pad electrode and also to cover the first passivation layer. A part of the gate pad electrode and the source pad electrode can be exposed.

[0090] Subsequently, an upper pad is formed on the exposed gate pad electrode and the source pad electrode. Also, a drain electrode (not shown), which is a back surface electrode, is formed under the substrate 110, and a back surface pad electrode is formed under the back surface electrode.

[0091] FIG. 5a is an enlarged view of the left channel region Ch of the power semiconductor device according to the embodiment of FIG. 3. Referring to FIG. 5a, a channel region Ch is formed between the second-conductivity-type second well 135 and the second-conductivity-type first well 130. A current path is formed through the first-conductivity-type source region 140 via the source electrode 162, through the channel and the JFET region 137. In the embodiment, the width W of the channel may be the interval between the second-conductivity-type first well 130 and the second-conductivity-type second well 135.

[0092] On the other hand, in the embodiment, since the JFET region 137 in contact with the first-conductivity-type source region 140 has the second-conductivity-type first well 130 and the second-conductivity-type second well 135 at the upper and lower parts respectively, a PN junction is formed at the upper and lower parts of the off-state MOSFET, and depletion occurs respectively.

[0093] For example, referring to FIG. 5b, in the OFF state of the MOSFET, the p-type first well 130 located at the top has a depletion region 130D generated in the downward direction, and the p-type second well 135 located at the bottom has a depletion region 135D generated in the upward direction. As a result, in the embodiment, depletion occurs at the top and bottom of the channel in the OFF state, and channel blocking is performed in the OFF state to block the leakage current of the channel.

[0094] Accordingly, according to the embodiment, the depletion regions can meet each other at the AA' line, which is approximately the middle line of the channel. Therefore, in the embodiment, since depletion is formed in the channel direction by the gate insulating layer 150, there is a special technical effect that channel blocking is performed in the OFF state to effectively prevent the leakage current of the channel.

[0095] In addition, the embodiment has a technical effect that the width W of the channel can be controlled by controlling the thickness of the p-type first well 130 or the thickness of the p-type second well 135.

[0096] For example, the vertical distance between the p-type first well 130 and the p-type second well 135 can be controlled to be larger than the thickness of the p-type first well 130.

[0097] As a result, in the embodiment, the upper p-type first well 130 has a depletion region 130D generated in the downward direction, and the lower p-type second well 135 has a depletion region 135D generated in the upward direction, so that the leakage current of the channel can be effectively prevented. Therefore, the width W of the channel can be formed wider than before to reduce the on-resistance (R on ), and there is a technical effect that the electrical performance can be improved.

[0098] Next, FIG. 6 is a graph showing the ion implantation concentration gradient at the BB' line in FIG. 5a.

[0099] Referring to FIG. 6, at the boundary between the first well 130 of the second conductivity type (Top P-well), which is the point where the P-type and N-type are changed, the ion implantation concentration decreases rapidly. On the Y-axis of FIG. 6, the first well 130 of the second conductivity type may be of P-type concentration, and the JFET region 137 may be of N-type concentration.

[0100] On the other hand, a channel region is formed between the first well 130 of the second conductivity type and the second well 135 of the second conductivity type, and the concentration can be constant in the channel region. Also, at the boundary between the channel region and the second well 135 of the second conductivity type, the ion implantation concentration increases rapidly.

[0101] On the Y-axis of FIG. 6, the second well 135 of the second conductivity type may be of P-type concentration.

[0102] In an embodiment, the vertical distance between the first well 130 of the second conductivity type and the second well 135 of the second conductivity type can be controlled to be greater than the thickness of the first well 130 of the second conductivity type.

[0103] Thereby, in the embodiment, the distance between the first well 130 of the second conductivity type and the second well 135 of the second conductivity type is the width W of the channel region, and the width W of the channel region may be thicker than the thickness of the first well 130 of the second conductivity type, which is the upper P-well.

[0104] For example, the width W of the channel region can have a thickness of 1.5 to 3 times the thickness of the first well 130 of the second conductivity type, which is the upper P-well. Also, preferably, the width W of the channel region can have a thickness of 2.0 to 2.5 times the thickness of the first well 130 of the second conductivity type, which is the upper P-well, but it is not limited thereto.

[0105] According to the embodiment, since the width W of the channel region can be controlled to be thicker than the thickness of the first well 130 of the second conductivity type, which is the upper P-well, the on-resistance (R onIt is possible to reduce ), and there is a special technical effect that can improve the electrical performance accordingly.

[0106] Also, in the embodiment, the concentration of the second-conductivity-type first well 130 may be lower than the concentration of the second-conductivity-type second well 135. For example, the first well 130 of the second conductivity type is ion-implanted at a concentration of about 1×10 16 cm -3 ~ about 2×1018 cm-3.

[0107] Also, the second well 135 of the second conductivity type may be ion-implanted at a concentration of P-type dopant of about 1×10 17 cm -3 ~ about 2×10 19 cm -3 , but it is not limited thereto.

[0108] Next, FIG. 7 is a cross-sectional view of a power semiconductor device according to a second embodiment. The power semiconductor device of the second embodiment may be a trench MOSFET. Referring to FIG. 7, a first-conductivity-type epi-layer 115 is disposed on a substrate 110. Also, a CSL (current spreading layer) region 138 is disposed on the first-conductivity-type epi-layer 115. Also, a plurality of second-conductivity-type second wells 135 are disposed spaced apart on the CSL region 138. The CSL region 138 is doped with the first conductivity type on the first-conductivity-type epi-layer 115 and grown by an epitaxial process, but it is not limited thereto.

[0109] Also, a first-conductivity-type source region 140 is disposed on the second-conductivity-type second well 135. A trench-type gate 155 is disposed between the plurality of second-conductivity-type second wells 135. Also, a gate insulating layer 150 is disposed so as to surround the gate 155.

[0110] On the other hand, the second embodiment can further include a second-conductivity-type first well 130 disposed on a side surface of the gate insulating layer 150. The side surface of the gate insulating layer 150 can be in contact with the first-conductivity-type source region 140 and the second-conductivity-type first well 130.

[0111] The second-conductivity-type first well 130 is disposed under the first-conductivity-type source region 140. Also, the second-conductivity-type first well 130 can be separated from the second-conductivity-type second well 135 by a predetermined distance.

[0112] A CSL region 138 can be located between the second-conductivity-type first well 130 and the second-conductivity-type second well 135. Thereby, in the second embodiment, a channel region Ch is formed between the second-conductivity-type first well 130 and the second-conductivity-type second well 135. The horizontal width of the channel can correspond to the isolation distance between the second-conductivity-type first well 130 and the second-conductivity-type second well 135.

[0113] On the other hand, in the second embodiment, depletion does not occur only in the second-conductivity-type second well 135 in the channel direction, but also in the second-conductivity-type first well 130 in the channel direction.

[0114] Thereby, PN junctions are formed on both sides in the channel region and depletion occurs, so that there is a technical effect that channel blocking can be easily implemented in an off-state MOSFET to prevent leakage current of the channel. Also, there is a technical effect that the horizontal width of the channel can be controlled by controlling the horizontal widths of the second-conductivity-type first well 130 and the second-conductivity-type second well 135.

[0115] The power semiconductor device according to the embodiment has a technical effect of being able to control the thickness or width of the channel.

[0116] For example, in the embodiment, the thickness or width of the channel can be controlled by controlling the thickness or width of the second-conductivity-type first well 130 and the second-conductivity-type second well 135.

[0117] In addition, the embodiment has a technical effect of improving the electrical performance of the SiC MOSFET.

[0118] For example, in the embodiment, the width of the channel can be formed wider to reduce the on-resistance (R on ) and improve the electrical performance.

[0119] In addition, the embodiment has a technical effect of preventing the leakage current of the channel.

[0120] For example, in the embodiment, PN junctions are formed at the upper and lower parts of the channel, and depletion is formed at the upper and lower parts in the off state to prevent the leakage current of the channel by channel blocking.

[0121] Although the embodiments of the present invention have been described above with reference to the embodiments, those skilled in the art should easily understand that the present invention can be variously modified and changed without departing from the idea and scope of the present invention described in the following claims.

Description of Reference Numerals

[0122] Ch: Channel region 110: Substrate 115: Epitaxial layer of the first conductivity type 130: First well of the second conductivity type 135: Second well of the second conductivity type 137: JFET region 138: CSL region 140: Well of the first conductivity type 145: Contact region of the second conductivity type 150: Gate insulating layer 155: Gate 160: Interlayer insulating layer 162: Source electrode

Claims

1. A substrate; a first conductivity type epitaxial layer disposed on the substrate; a junction field effect transistor (JFET) region disposed on the first conductivity type epitaxial layer; a plurality of second wells of a second conductivity type spaced apart from one another in the JFET region; a first conductivity type source region disposed on the second conductivity type second well; a gate insulating layer disposed on the first conductivity type source region; a gate disposed on the gate insulating layer; a first well of a second conductivity type disposed under the gate insulating layer; the JFET region is located between the first well of the second conductivity type and the second well of the second conductivity type.

2. The power semiconductor device according to claim 1 , wherein the first well of the second conductivity type is spaced apart from the second well of the second conductivity type.

3. The power semiconductor device according to claim 1 , wherein a horizontal width of the gate insulating layer is greater than a horizontal width of the second conductive type first well.

4. the first conductivity type source region is in contact with the JFET region; The power semiconductor device according to claim 1 , wherein an upper surface of the first well of the second conductivity type is in contact with the gate insulating layer, and a side surface of the first well of the second conductivity type is in contact with the source region of the first conductivity type.

5. The power semiconductor device according to claim 1 , wherein a thickness of the second conductive type first well is thinner than a thickness of the first conductive type source region.

6. The power semiconductor device of claim 1 , wherein a vertical distance between the first well of the second conductivity type and the second well of the second conductivity type is greater than a thickness of the first well of the second conductivity type.

7. a second conductive type contact region disposed on the second conductive type second well; The power semiconductor device according to claim 1 , wherein the second conductive type contact region is in contact with the second conductive type second well and the first conductive type source region.

8. A substrate; a first conductivity type epitaxial layer disposed on the substrate; a current spreading layer region disposed on the first conductivity type epitaxial layer; a plurality of second wells of a second conductivity type spaced apart from one another in the current spreading layer region; a first conductivity type source region disposed on the second conductivity type second well; a trench-shaped gate disposed between the plurality of second conductive type second wells; a gate insulating layer surrounding the gate; a first well of a second conductivity type disposed on a side of the gate insulating layer; the current spreading layer region is located between the first well of the second conductivity type and the second well of the second conductivity type.

9. the first well of the second conductivity type is separated from the second well of the second conductivity type; The power semiconductor device according to claim 8 , wherein a side surface of the gate insulating layer contacts the first conductive type source region and the second conductive type first well.

10. A power conversion device comprising the power semiconductor device according to claim 1 .

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