Display device

Abstract

To provide good interface characteristics in a thin film transistor with an oxide semiconductor layer without introducing an impurity such as moisture, and propose a semiconductor device having a thin film transistor with high electrical characteristics and reliability, and a method for mass-producing the semiconductor device with high efficiency.SOLUTION: Oxygen radical treatment is performed on the surface of a gate insulating layer. Therefore, the oxygen concentration has a peak at the interface between a gate insulating layer and a semiconductor layer, and the oxygen concentration in the gate insulating layer has a concentration gradient, and the oxygen concentration increases as it approaches the interface between the gate insulating layer and the semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter referred to as TFTs) using an oxide semiconductor film in a channel formation region, and a method for manufacturing the same. For example, it relates to an electronic device mounted with an electro-optical device typified by a liquid crystal display panel or a light-emitting display device having an organic light-emitting element as a component. display panel or a light-emitting display device having an organic light-emitting element as a component. mounted thereon.

[0002] Note that in this specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and the electro-optical device, semiconductor circuit, and electronic device are all semiconductor devices. mounted thereon.

Background Art

[0003] In recent years, active matrix display devices (liquid crystal display devices, light-emitting display devices, and electrophoretic display devices ) provided with switching elements composed of TFTs for each display pixel arranged in a matrix have been actively developed. The active matrix display device is provided with a switching element for each pixel (or one dot ), and is advantageous because it can be driven at a low voltage when the pixel density is increased compared to the simple matrix method. ), and is advantageous because it can be driven at a low voltage when the pixel density is increased compared to the simple matrix method. ).

[0004] In addition, techniques for manufacturing thin film transistors (TFTs) and the like using an oxide semiconductor film in a channel formation region and applying them to electronic devices and optical devices have attracted attention. For example, TFTs using zinc oxide (ZnO) as the oxide semiconductor film, and T FTs using InGaO3(ZnO) as the oxide semiconductor film are mentioned. Techniques for forming these TFTs using an oxide semiconductor film on a light-transmissive substrate and using them as switching elements of an image display device are disclosed in Patent Document 1 and Patent Document 2 m using InGaO3(ZnO) as the oxide semiconductor film are mentioned. Techniques for forming these TFTs using an oxide semiconductor film on a light-transmissive substrate and using them as switching elements of an image display device are disclosed in Patent Document 1 and Patent Document 2 formed on a light-transmissive substrate and used as a switching element of an image display device are disclosed in Patent Document 1 and Patent Document 2 . [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] Thin film transistors using oxide semiconductor films in the channel formation region, such as instability of the oxide semiconductor film interface, However, thin-film transistors using IGZO have been The interface characteristics of transistors have not been discussed at all. In addition, there is uncertainty about reliability. The cause of this was unknown.

[0007] Therefore, one aspect of the present invention is to provide a method for manufacturing a semiconductor device using indium (In), gallium (Ga), and zinc (Zn) In a thin film transistor using an oxide semiconductor film containing One of the objectives of the present invention is to provide good interface characteristics without any problem.

[0008] In addition, when hydrogen is contained in the gate insulating layer in contact with the oxide semiconductor film, There is a risk that the hydrogen diffuses and reacts with oxygen in the oxide semiconductor film to become an H2O component.

[0009] In addition, when the oxygen concentration in the gate insulating layer is low, the oxygen concentration in the oxide semiconductor film may be reduced. There is.

[0010] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device using indium (In), gallium (Ga), and zinc (Zn). In a thin film transistor using an oxide semiconductor film containing One of the problems is to provide a structure for inclusion.

[0011] In addition, for a thin-film transistor using an oxide semiconductor film in a channel formation region, a high operation speed, a relatively simple manufacturing process, and sufficient reliability are required.

[0012] When forming a thin-film transistor, source electrodes and drain electrodes are made of a low-resistance metal material. In particular, when manufacturing a display device that performs large-area display, the problem of signal delay due to the resistance of the wiring becomes prominent. Therefore, as a material for the wiring and electrodes, it is desirable to use a metal material with a low electrical resistance value. If a thin-film transistor structure is adopted in which source electrodes and drain electrodes made of a metal material with a low electrical resistance value are in direct contact with an oxide semiconductor film, the contact resistance may increase. One of the factors considered for the increase in contact resistance is that a Schottky junction is formed at the contact surface between the source electrodes and drain electrodes and the oxide semiconductor film.

[0013] In addition, a capacitance is formed at the portion where the source electrodes and drain electrodes are in direct contact with the oxide semiconductor film, and the frequency characteristics (referred to as f characteristics) are reduced, which may prevent the high-speed operation of the thin-film transistor.

[0014] One aspect of the present invention is to provide a thin-film transistor using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), and a method for manufacturing the same, which reduces the contact resistance of the source electrode or the drain electrode. One of the problems is to provide a thin-film transistor and a method for manufacturing the same.

[0015] In addition, improving the operating characteristics and reliability of a thin-film transistor using an oxide semiconductor film containing In, Ga, and Zn is also one of the problems. Another problem is to improve the reliability.

[0016] In addition, reducing the variation in the electrical characteristics of a thin-film transistor using an oxide semiconductor film containing In, Ga, and Zn is also one of the problems. In particular, in a liquid crystal display device, when the variation between individual elements is large, display unevenness may occur due to the variation in the TFT characteristics. There is a risk of occurrence.

[0017] In addition, also in a display device having a light-emitting element, when the variation in the off-current (I on ) of the TFT (the TFT that supplies current to the light-emitting element arranged in the driving circuit or the pixel) arranged so that a constant current flows through the pixel electrode is large, there is a risk of luminance variation occurring in the display screen.

[0018] As described above, one aspect of the present invention aims to solve at least one of the above problems.

Means for Solving the Problems

[0019] One aspect of the present invention is to perform oxygen radical treatment on the surface of the gate insulating layer. Therefore, it has a peak in the oxygen concentration at the interface between the gate insulating layer and the semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient, and the oxygen concentration increases as it approaches the interface between the gate insulating layer and the semiconductor layer.

[0020] In addition, an oxygen-excess oxide semiconductor film is used as the semiconductor layer, and a source region and a drain region using an oxygen-deficient oxide semiconductor film are provided between the semiconductor layer and the source electrode layer and the drain electrode layer, and a reverse staggered type (bottom gate structure) thin-film transistor is included. ​

[0021] The semiconductor layer, source region, and drain region are made of an oxide semiconductor containing In, Ga, and Zn. In addition, any one of In, Ga, and Zn can be used in combination with tungsten, molybdenum, or It may be replaced by lithium, titanium, nickel, or aluminum.

[0022] In this specification, a semiconductor formed using an oxide semiconductor film containing In, Ga, and Zn is The semiconductor layer is also referred to as the "IGZO semiconductor layer."

[0023] By performing oxygen radical treatment on the gate insulating layer, oxygen radicals are bombarded into the gate insulating layer. The gate insulating layer near the interface with the oxygen-excess oxide semiconductor layer is thicker than the bulk GI. Contains excess oxygen.

[0024] By performing oxygen radical treatment, the gate insulating layer and the vicinity of the interface with the oxide semiconductor layer are also improved. In this case, the gate insulating layer may have an oxygen excess region.

[0025] The gate insulating layer having an oxygen-excess region and the oxygen-excess oxide semiconductor layer are compatible with each other and have a good interface. characteristics can be obtained.

[0026] In addition, in order to stack a gate insulating layer having an oxygen excess region and an oxygen excess oxide semiconductor layer, In this case, it is preferable to carry out continuous film formation.

[0027] The oxygen radicals may be supplied by a plasma generator using a gas containing oxygen; Alternatively, the oxygen may be supplied by an ozone generator. The surface of the thin film can be modified by irradiating the thin film with oxygen or water.

[0028] Further, without being limited to oxygen radical treatment, radical treatment of argon and oxygen may be performed. The radical treatment of argon and oxygen means introducing argon gas and oxygen gas to generate plasma to modify the surface of the thin film.

[0029] Ar atoms (Ar) in the reaction space where an electric field is applied and discharge plasma is generated are excited or ionized by electrons (e) in the discharge plasma, and become argon radicals (Ar ) or argon ions (Ar * ) or electrons (e). Argon radicals (Ar ) are in a highly energetic metastable state and react with surrounding atoms of the same or different types, exciting or ionizing those atoms and causing a reaction to occur in an avalanche-like phenomenon as they try to return to the stable state. When oxygen is present in the vicinity at that time, oxygen atoms (O) are excited or ionized, becoming oxygen radicals (O + ) or oxygen ions (O * ) or oxygen (O ). The oxygen radicals (O ) react with the material on the surface of the thin film that is the object to be treated, performing surface modification or reacting with organic substances on the surface to remove the organic substances, and plasma treatment is * ) or oxygen ions (O + ) and oxygen (O * ). The oxygen radicals (O ) react with the material on the surface of the thin film that is the object to be treated, performing surface modification or reacting with organic substances on the surface to remove the organic substances, and plasma treatment is performed. Note that radicals of inert gases have the characteristic that their metastable state is maintained longer compared to radicals of reactive gases. Therefore, it is common to use inert gases to generate plasma.

[0030] Also, the gate insulating layer is formed by a sputtering method using a silicon target and introducing Ar gas and oxygen gas, and it is most preferable to form an insulating layer containing a large amount of oxygen. On the other hand, when forming the gate insulating layer by a plasma CVD (PCVD) method using TEOS gas or the like, the gate ​​​​​​​When hydrogen contained in the insulating layer reacts with oxygen in the oxide semiconductor layer, it tends to produce H2O or OH, which may become an inhibitory factor as a carrier killer and lead to deterioration of reliability. That is, when using an insulating film containing hydrogen as a gate insulating layer by the PCV D method, there is a risk that hydrogen in the gate insulating layer will react with oxygen in the oxygen-excess semiconductor layer, which is not preferable. Therefore, the hydrogen concentration in the gate insulating layer should preferably be such that the concentration peak obtained by analysis using SIMS (Secondary Ion Mass Spectrometer) is 2×10 cm 19 or less. Further, a comparative example in which oxygen radical treatment is performed on a gate insulating layer with a low oxygen concentration is shown in FIG. 3. In this case, however, there is a risk of absorbing oxygen in the oxygen-excess semiconductor layer, which is not preferable. -3 Therefore, as shown in the oxygen concentration distribution in FIG. 1(A), oxygen radical treatment is performed on the interface on the gate insulating layer side to dope oxygen, and then, after forming the IGZO film, heat treatment (200 °C to 6 00 °C) is carried out. FIG. 1(A) is a schematic diagram of the oxygen concentration near the interface between the gate insulating layer and the semiconductor layer before heat treatment. FIG. 1(B) is a schematic diagram of the oxygen concentration near the interface between the gate insulating layer and the semiconductor layer after heat treatment. By performing heat treatment from the state shown in FIG. 1(A) to the state shown in FIG. 1(B), it has the effect of preventing excess oxygen in the gate

[0031] insulating layer from drifting to the IGZO film side and preventing oxygen in the IGZO film from drifting to the GI side. The interface can be stabilized by oxygen radicals on the surface of the gate insulating layer. It is clarified that one of the causes of instability in terms of reliability lies at the interface between the gate insulating layer and the IGZO film, and it is necessary to modify the gate insulating layer rather than the IGZO film, and then perform heat treatment

[0032] ​​​​​​​​​Stabilizes reliability based on theory.

[0033] Also, after performing plasma treatment on the surface of the gate insulating layer to nitride it with SiN, oxygen radical treatment may be performed to reduce the diffusion of hydrogen in the gate insulating layer into the IGZO film. The surface As the plasma treatment for nitriding with SiN, by exciting the plasma with microwaves, nitrogen radicals (which may include NH radicals) can be used to nitride the surface of the gate insulating layer, or a method such as performing reverse sputtering in a nitrogen atmosphere may be used. Also, FIG. 2 is a schematic diagram of the oxygen concentration near the interface between the gate insulating layer and the semiconductor layer after performing oxygen radical treatment after nitriding the surface.

[0034] Note that FIGS. 1, 2, and 3 are schematic diagrams for briefly explaining the concept of one embodiment of the present invention and it goes without saying that they are not particularly limited.

[0035] Also, an ohmic contact is required between the source electrode layer and the IGZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible. Similarly, an ohmic contact is required between the drain electrode layer and the I GZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible.

[0036] Therefore, by intentionally providing source regions and drain regions having a higher carrier concentration than the IGZO semiconductor layer between the source electrode layer and the drain electrode layer and the IGZO semiconductor layer, an ohmic contact is formed.

[0037] Using an oxygen-excess oxide semiconductor layer as the semiconductor layer, and using oxygen as the source regions and drain regions An oxygen-deficient oxide semiconductor layer is used. The oxygen-deficient oxide semiconductor layers of the source region and the drain region have crystal grains.

[0038] By positively providing an oxygen-deficient oxide semiconductor layer having crystal grains as the source region or the drain region, a good junction is formed between the source electrode layer or the drain electrode layer, which is a metal layer, and the IGZO film, enabling a thermally stable operation compared to a Schottky junction. Also, for supplying carriers to the channel (source side), or stably absorbing carriers from the channel (drain side), or to prevent the formation of a resistance component at the interface with the source electrode layer (or drain electrode layer), it is important to positively provide a source region or a drain region having crystal grains. To maintain good mobility even at a high drain voltage, reducing the resistance is also important.

[0039] A 400-nm IGZO film was formed on a glass substrate by DC sputtering, and XRD (X-ray diffraction) measurement was performed. The film-forming conditions were a pressure of 0.4 Pa, a power of 500 W, a film-forming temperature of room temperature, an argon gas flow rate of 10 sccm, an oxygen flow rate of 5 sccm, and a target of In2O3:Ga2O3:ZnO = 1:1:1 was used. Also, this ratio of the target was intentionally used to obtain an amorphous IGZO film.

[0040] Figure 37 is the XRD measurement chart. The chart immediately after film formation corresponds to what is indicated as as-depo in Figure 37. Also, Figure 37 shows the chart after heat treatment at 350 °C for 1 hour in a nitrogen atmosphere after film formation, and the chart after heat treatment at 500 °C for 1 hour in a nitrogen atmosphere after film formation. ​​​​​​​​​, for comparing the chart after heat treatment at 600 °C for 1 hour in a nitrogen atmosphere after film formation with the chart after heat treatment at 7 00 °C for 1 hour in a nitrogen atmosphere, for convenience, they are illustrated side by side .

[0041] In the sample after heat treatment at 700 °C, clear crystal peaks are observed in the range of 30 - 35° and 55 ~ 60°. Also, a 400 nm IGZO film was formed, and the sample after heat treatment at 7 00 °C for 1 hour in a nitrogen atmosphere was cut out at the end face by FIB (Focused Ion beam) and observed in cross section with a high-resolution transmission electron microscope (Hitachi, Ltd. "H9000-NAR": TE M) with an acceleration voltage of 300 kV. The result of observation at 500,000 times magnification is shown in Fig. 48 , and crystal grains can be confirmed. Also, a cross-sectional observation was performed with a scanning transmission electron microscope (Hitachi, Ltd. "HD-270 0": STEM) with an acceleration voltage of 200 kV, and the photographed image observed at 6 million times magnification is shown in Fig. 49. In Fig. 49, a clear lattice image can be confirmed, which corresponds to the fact that a peak indicating crystal was observed in the XRD measurement .

[0042] In addition, in order to examine the presence or absence of crystal grains, the size of crystal grains, and the distribution state of crystal grains, a 50 nm IGZO film was formed on a glass substrate by DC sputtering method, and the end face was cut out by FIB , and a cross-sectional observation was performed with a high-resolution transmission electron microscope (Hitachi, Ltd. "H9000-NAR": TEM) with an acceleration voltage of 300 kV

[0043] Using a target with In2O3:Ga2O3:ZnO = 1:1:1, the film formation conditions were as follows: the pressure was 0.4 Pa, the power was 500 W, the film formation temperature was room temperature, the argon gas flow rate was 5 s ccm, and the oxygen flow rate was 45 sccm. Sample 1 was sputter-deposited under oxygen-excessive conditions ​​, only the argon gas flow rate was set to 40 sccm without introducing oxygen gas, and other conditions were the same. Sample 2 prepared by performing sputter film formation under oxygen-deficient conditions and sample 1 were each subjected to cross-sectional observation.

[0044] The result of observing sample 1 at 500,000 times magnification is shown in Fig. 38, and the result of observing sample 2 at 500,000 times magnification is shown in Fig. 39. In sample 1, no crystal grains can be confirmed in the IGZO film, but in sample 2 crystal grains with a diameter of 1 nm to 10 nm, typically about 2 nm to 4 nm, are scattered in the IGZO film, which can be confirmed. The crystal grains of sample 2 have a smaller size than those in the cross-sectional observation photograph of the sample heat-treated at 700 °C shown in Fig. 48. This result indicates that, in order to obtain an amorphous IGZO film, although a target with In2O3:Ga2O3:ZnO = 1:1:1 was intentionally used, an IGZO film containing crystal grains was obtained immediately after film formation.

[0045] In addition, after the film formation conditions of sample 1, sample 3 subjected to heat treatment at 350 °C for 1 hour in a nitrogen atmosphere and, after the film formation conditions of sample 2, sample 4 subjected to heat treatment at 350 °C for 1 hour in a nitrogen atmosphere were prepared and each subjected to cross-sectional observation.

[0046] The result of observing sample 3 at 500,000 times magnification is shown in Fig. 40, and the result of observing sample 4 at 500,000 times magnification is shown in Fig. 41. Also, in sample 3, no crystal grains can be confirmed in the IGZO film, but in sample 4 crystal grains with a diameter of about 1 nm to 10 nm, typically about 2 nm to 4 nm, are scattered in the IGZO film, which can be confirmed.

[0047] In addition, when XRD measurement was performed using samples 1 to 4, as-depo shown in Fig. 37 ​​​and the sample that was heat-treated at 350°C for 1 hour in a nitrogen atmosphere, respectively, similarly Results were obtained in which no peak clearly indicating crystals could be confirmed.

[0048] Thus, in Sample 1 with oxygen-excessive sputtering film formation conditions, crystal grains were not confirmed in the TEM photograph, and the reason why crystal grains were confirmed in Sample 2 with oxygen-deficient conditions in the TEM photograph is shown below. In Sample 2 with oxygen-deficient conditions, when the sputtering target was struck with Ar, the stoichiometric ratio grains that would originally crystallize were given the plasma energy of Ar ions, and crystallization or particle growth occurred during flight (from the target to the substrate). Therefore, crystal grains in the film during film formation are also observed at the corners. Also, when heat-treated at 350°C, the amorphous component around the crystal grains reacts with oxygen, and as shown in Fig. 41, the grain boundaries of the crystal grains become blurred compared to Fig. 39, that is, they tend to become unclear. It is considered that the orderliness of the crystals within the amorphous component develops and grows more around the crystal grains. Shown.

[0049] In Sample 2 with oxygen-deficient conditions, when the sputtering target was struck with Ar, the stoichiometric ratio grains that would originally crystallize were given the plasma energy of Ar ions, and crystallization or particle growth occurred during flight (from the target to the substrate). to the substrate), crystallization or particle growth takes place. Therefore, the crystal grains in the film during film formation are also observed at the corners. Also, when heat-treated at 350°C, the amorphous component around the crystal grains reacts with oxygen, and as shown in Fig. 41, the grain boundaries of the crystal grains become blurred compared to Fig. 39, that is, they tend to become unclear. It is observed that the orderliness of the crystals within the amorphous component develops and grows more around the crystal grains. Therefore, an IGZO film with a lower oxygen concentration is formed under oxygen-deficient conditions, and it is considered that the N+ type is composed of a higher concentration carrier region. It is observed that the grain boundaries of the crystal grains become blurred compared to Fig. 39, that is, they tend to become unclear. The orderliness of the crystals within the amorphous component is considered to develop and grow more around the crystal grains. It is considered that the orderliness of the crystals within the amorphous component develops and grows more around the crystal grains. It is considered that the orderliness of the crystals within the amorphous component develops and grows more around the crystal grains.

[0050] Therefore, it can be said that by appropriately adjusting the component ratio of the target, the film formation pressure (0.1 Pa to 2.0 Pa), the power (250 W to 3000 W: 8-inch φ), the temperature (room temperature to 100°C), the film formation conditions of the reactive sputtering

[0051] target, etc., the density and diameter size of the crystal grains can be adjusted within the range of 1 nm to 10 nm. target, etc., the density and diameter size of the crystal grains can be adjusted within the range of 1 nm to 10 nm. target, etc., the density and diameter size of the crystal grains can be adjusted within the range of 1 nm to 10 nm. It can be said that it can be adjusted within the range of 1 nm to 10 nm.

[0052] On the other hand, in Sample 1 under oxygen-excessive conditions, even if we attempt to induce crystal growth by applying plasma energy while sputtering the target, since oxygen is excessive at the same time, each element reacts strongly with oxygen and cannot follow the crystal growth mechanism of IGZO, and all components are deposited on the substrate in a glassy (amorphous) state. Of course, the conditions intermediate between oxygen-deficient conditions and oxygen-excessive conditions have the process adjusted according to the degree of oxygen incorporation during sputter deposition. Also, since the sputtering method applies strong energy to the target with Ar ions, it is considered that strong strain energy is inherent in the deposited IGZO film. To release this strain energy, heat treatment is performed at 200°C to 600°C, typically 300°C to 500°C. This heat treatment causes atomic-level rearrangement. Since the strain that inhibits carrier movement is released by this heat treatment, film deposition and heat treatment (including photo annealing) are important. Note that the heat treatment at 200°C to 600°C does not lead to single-crystal growth due to large atomic movement as in the case of heat treatment above 700°C.

[0053] At heating temperatures of 700°C or higher, distinct crystal growth is observed, and crystal peaks are also observed by XRD as shown in Fig. 37. On the other hand, in both oxygen-deficient conditions and oxygen-excessive conditions, for reasons that are unclear, whether it is because the crystal components or the degree of crystallization is small, or because of other factors, no crystal grains are observed in the XRD measurement as shown in Fig. 37. The crystal grains observed in Figs. 39 and 41 are further magnified in Figs. 42 and 43.

[0054] Moreover, since the sputtering method applies strong energy to the target with Ar ions, it is considered that strong strain energy is inherent in the deposited IGZO film. To release this strain energy, heat treatment is performed at 200°C to 600°C, typically 300°C to 500°C. This heat treatment causes atomic-level rearrangement. Since the strain that inhibits carrier movement is released by this heat treatment, film deposition and heat treatment (including photo annealing) are important. Note that the heat treatment at 200°C to 600°C does not lead to single-crystal growth due to large atomic movement as in the case of heat treatment above 700°C. At heating temperatures of 700°C or higher, distinct crystal growth is observed, and crystal peaks are also observed by XRD as shown in Fig. 37. On the other hand, in both oxygen-deficient conditions and oxygen-excessive conditions, for reasons that are unclear, whether it is because the crystal components or the degree of crystallization is small, or because of other factors, no crystal grains are observed in the XRD measurement as shown in Fig. 37.

[0055] At heating temperatures of 700°C or higher, distinct crystal growth is observed, and crystal peaks are also observed by XRD as shown in Fig. 37. On the other hand, in both oxygen-deficient conditions and oxygen-excessive conditions, for reasons that are unclear, whether it is because the crystal components or the degree of crystallization is small, or because of other factors, no crystal grains are observed in the XRD measurement as shown in Fig. 37. As shown in Fig. 37, due to either a small amount of crystal components or the degree of its crystallization, or a small crystal grain size, or other factors, it is unclear, but no crystal grains are observed. The crystal grains observed in Figs. 39 and 41 are further magnified in Figs. 42 and 43.

[0056] The crystal grains observed in Figs. 39 and 41 are further magnified in Figs. 42 and 43. 。Figure 42 is a cross-sectional TEM photograph (8 million times magnification) of Sample 2 under oxygen-deficient conditions. Figure 43 is a cross-sectional TEM photograph (8 million times magnification) of Sample 4 under oxygen-deficient conditions and further heat-treated 。In both Figure 42 and Figure 43, a clear lattice image is confirmed in the crystal grains, and a single crystal with a three-layer structure is clearly observed.

[0057] Also, Figures 44, 45, 46, and 47 are enlarged versions of Figures 38 and 40 。Figure 44 is a cross-sectional TEM photograph (2 million times magnification) of Sample 1 under oxygen-excessive conditions, and the 80 0 million times magnification photograph is Figure 46. Figure 45 is a cross-sectional TEM photograph (2 million times magnification) of Sample 3 under oxygen-excessive conditions and further heat-treated and the 8 million times magnification photograph is Figure 47. In Figures 44, 45, 46, and 47, no crystal grains can be confirmed.

[0058] One form of the semiconductor device of the present invention has a thin film transistor having a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source region and a drain region on the oxide semiconductor layer, and a source electrode layer and a drain electrode layer on the source region and the drain region, has a peak in the oxygen concentration at the interface between the gate insulating layer and the oxide semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient, and the oxygen concentration increases as it approaches the interface between the gate insulating layer and the oxide semiconductor layer. One form of the semiconductor device of the present invention has a thin film transistor having a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source region and a drain region on the oxide semiconductor layer, and a source electrode layer and a drain electrode layer on the source region and the drain region and includes a thin film transistor having a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source region and a drain region on the oxide semiconductor layer, and a source electrode layer and a drain electrode layer on the source region and the drain region has a peak in the oxygen concentration at the interface between the gate insulating layer and the oxide semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient, and the oxygen concentration increases as it approaches the interface between the gate insulating layer and the oxide semiconductor layer. The oxygen concentration of the gate insulating layer has a concentration gradient, and the oxygen concentration increases as it approaches the interface between the gate insulating layer and the oxide semiconductor layer. As it approaches the interface between the gate insulating layer and the oxide semiconductor layer, the oxygen concentration increases.

[0059] One form of the semiconductor device of the present invention has a thin film transistor having a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source region and a drain region on the oxide semiconductor layer, and a source electrode layer and a drain electrode layer on the source region and the drain region and includes a thin film transistor having a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source region and a drain region on the oxide semiconductor layer, and a source electrode layer and a drain electrode layer on the source region and the drain region has a peak in the oxygen concentration at the interface between the gate insulating layer and the oxide semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient, and the oxygen concentration increases as it approaches the interface between the gate insulating layer and the oxide semiconductor layer. having a stud, having a peak of oxygen concentration at the interface between the gate insulating layer and the oxide semiconductor layer, and having a gate The oxygen concentrations of the gate insulating layer and the oxide semiconductor layer have a concentration gradient, and the oxygen concentration increases as it approaches the interface between the gate insulating layer and the oxide semiconductor layer.

[0060] In the above configuration, the oxygen concentration of the oxide semiconductor layer is higher than the oxygen concentrations of the source region and the drain region. When the oxide semiconductor layer is an oxygen-excess oxide semiconductor layer, and the source region and the drain region are oxygen-deficient oxide semiconductor layers, the carrier concentrations of the source region and the drain region can be made higher than that of the oxide semiconductor layer. layer.

[0061] Also, it is preferable to use a titanium film for the source electrode layer and the drain electrode layer. For example, using a stack of a titanium film, an aluminum film, and a titanium film results in low resistance and makes it difficult for hillocks to occur in the aluminum film. film.

[0062] One form of the method for manufacturing a semiconductor device of the present invention is to form a gate electrode layer on a substrate, form a gate insulating layer on the gate electrode layer, expose the gate insulating layer to oxygen radicals for modification, form an oxide semiconductor layer on the modified gate insulating layer, form a source region and a drain region on the oxide semiconductor layer, form a source electrode layer and a drain electrode layer on the source region and the drain region, and form the gate insulating layer and the oxide semiconductor layer continuously without exposing them to the atmosphere. region, and form a source electrode layer and a drain electrode layer on the source region and the drain region, and form the gate insulating layer and the oxide semiconductor layer continuously without exposing them to the atmosphere. The gate insulating layer, the semiconductor layer, the source region and the drain region, and the source electrode layer and the drain electrode

[0063] layer can be formed continuously without being exposed to the atmosphere. By continuously forming the film, it is possible to reduce defects caused by impurities in the atmosphere becoming dust and mixing into the interface. layer can be formed continuously without being exposed to the atmosphere. By continuously forming the film, it is possible to reduce defects caused by impurities in the atmosphere becoming dust and mixing into the interface. layer can be formed continuously without being exposed to the atmosphere. By continuously forming the film, it is possible to reduce defects caused by impurities in the atmosphere becoming dust and mixing into the interface.

[0064] A gate insulating layer, a semiconductor layer, a source region and a drain region, a source electrode layer and a drain electrode The layer may be formed by a sputtering method.

[0065] When film formation is continuously performed using such a sputtering method, productivity is high and the reliability of the thin film interface is stable. Further, when the gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere and contain a large amount of oxygen, it is possible to reduce a decrease in reliability due to deterioration and a shift of thin film transistor characteristics to the normal-on side.

[0066] One embodiment of a method for manufacturing a semiconductor device of the present invention includes forming a gate electrode layer on a substrate, forming a gate insulating layer on the gate electrode layer, exposing the gate insulating layer to oxygen radicals for modification, and forming an oxide semiconductor layer on the modified gate insulating layer, forming a source region and a drain region on the oxide semiconductor layer, heating the oxide semiconductor layer, the source region and the drain region at 200° C. or higher and 600° C. or lower, and forming a source electrode layer and a drain electrode layer on the source region and the drain region, wherein the gate insulating layer and the oxide semiconductor layer are continuously formed without being exposed to the atmosphere.

Advantages of the Invention

[0067] According to one embodiment of the present invention, a thin film transistor having a small photocurrent, a small parasitic capacitance, and a high on-off ratio can be obtained, and a thin film transistor having good dynamic characteristics can be manufactured. Thus, it is possible to provide a semiconductor device having a thin film transistor with high electrical characteristics and high reliability.

Brief Description of the Drawings

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Figure 49

Embodiments for Carrying Out the Invention

[0069] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same reference numerals are commonly used for the same part or parts having the same function among different drawings, and the repeated description thereof will be omitted.

[0070] (Embodiment 1) In this embodiment, a thin-film transistor and its manufacturing process will be described with reference to FIGS. 5 to 8.

[0071] The bottom-gate structure thin-film transistors 170a, 170b, and 170c of this embodiment are shown in FIGS. 5 and 6. FIG. 5(A1) is a plan view, and FIG. 5(A2) is a cross-sectional view taken along line A1-A2 in FIG. 5(A1). FIG. 5(B1) is a plan view, and FIG. 5(B2) is a cross-sectional view taken along line B1-B2 in FIG. 5(B1 ). FIG. 6(A1) is a plan view, and FIG. 6(A2) is a cross-sectional view taken along line C1-C2 in FIG. 6(A1).

[0072] In FIG. 5, on a substrate 100, a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 1 03, source regions or drain regions 104a and 104b, and a source electrode layer or a drain electrode layer 105a and 105b are provided with a thin film transistor 170a.

[0073] Oxygen radical treatment is performed on the surface of the gate insulating layer 102. Therefore, there is a peak in the oxygen concentration at the interface between the gate insulating layer 102 and the semiconductor layer 103, and the oxygen concentration of the gate insulating layer 102 has a concentration gradient, and the oxygen concentration increases as it approaches the interface between the gate insulating layer 102 and the semiconductor layer 103.

[0074] Also, an oxygen-excess oxide semiconductor film containing In, Ga, and Zn is used as the semiconductor layer 103, and a source region or a drain region 104 formed of an oxygen-deficient oxide semiconductor layer is intentionally provided between the source electrode layer or the drain electrode layers 105a and 105b and the semiconductor layer 103 which is an IGZO semiconductor layer to form an ohmic contact. Also either one of In, Ga , and Zn may be replaced with tungsten, molybdenum, titanium, nickel, or aluminum as the semiconductor layer 103, the source regions or the drain regions 104a and 104b.

[0075] As the source regions or the drain regions 104a and 104b, an oxygen-deficient oxide semiconductor film having crystal grains containing In, Ga, and Zn is used.

[0076] The IGZO for the channel is set to a carrier concentration range such that it does not become normally-on as a thin film transistor. Therefore, the IGZO film within the carrier concentration range of the present invention is used as the channel of the semiconductor layer By using it as a ruthenium, a highly reliable thin film transistor can be obtained.

[0077] Also, the source region or the drain region may have a laminated structure. The source region and the drain region When laminating, the carrier concentration may be set within a concentration range that increases toward the source electrode layer and the drain electrode layer side. Impurity elements may be included in the source region and the drain region to form source regions and drain regions with a high carrier concentration.

[0078] The thin film transistor 170a in FIGS. 5(A1) and (A2) is an example in which the source region or the drain region 10 4a, 104b and the source electrode layer or the drain electrode layer 105a, 105b are etched using different masks, and the source region or the drain region 104a, 104b and the source electrode layer or the drain electrode layer 105a, 105b have different shapes.

[0079] The thin film transistor 170b in FIGS. 5(B1) and (B2) is an example in which the source region or the drain region 10 4a, 104b and the source electrode layer or the drain electrode layer 105a, 105b are etched using the same mask, and the source region or the drain region 104a, 104b and the source electrode layer or the drain electrode layer 105a, 105b reflect similar shapes.

[0080] Also, in the thin film transistors 170a and 170b in FIGS. 5(A1), (A2), (B1), and (B2), on the semiconductor layer 103, the ends of the source electrode layer or the drain electrode layer 105a, 105b and the ends of the source region or the drain region 104a, 104b do not match, and this is an example in which the source region or the drain region 104a, 104b is partially exposed.

[0081] ​​​​On the other hand, in the thin film transistor 170c of FIGS. 6(A1) and (A2), an example is shown in which the semiconductor layer 103 and the source region or drain regions 104a and 104b are etched using the same mask, and the ends of the semiconductor layer 103 and the source region or drain regions 104a and 104b coincide. Note that in the thin film transistor 170c of FIGS. 6(A1) and (A2), an example is also shown in which, on the semiconductor layer 103, the ends of the source electrode layer or drain electrode layers 105a and 105b coincide with the ends of the source region or drain regions 104a and 104b. Furthermore, a thin film transistor 171d in which the source electrode layer or drain electrode layer has a stacked structure is shown in FIG. 15. The thin film transistor 171d has a stack of source electrode layers or drain electrode layers 105a1, 105a2, and 105a3, and a stack of source electrode layers or drain electrode layers 105b1, 105b2, and 105b3. For example, titanium films can be used for the source electrode layer or drain electrode layers 105a1 and 105b1, aluminum films can be used for 105a2 and 105b2, and titanium films can be used for 105a3 and 105b3. In the thin film transistor 171d, the source electrode layer or drain electrode layers 105a1 and 105b1 are used as an etch stopper, and the source electrode layer or drain electrode layers 105a2, 105a3, 105b2, and 105b3 are etched by wet etching to be formed. Using the same mask as the above wet etching, the source electrode layer or drain electrode layers 105a1, 105b1, the source region or drain regions 104a and 104b, and the semiconductor layer 103 are etched by dry etching to be formed.

[0082]

[0083]

[0084] ​​​​​​​​​​​​​​​Therefore, the source electrode layer or drain electrode layer 105a1 coincides with the end of the source region or drain region 10 4a, and the source electrode layer or drain electrode layer 105b1 coincides with the end of the source region or drain region 10 4b, respectively. The source electrode layers or drain electrode layers 105a2 and 105a3, and the source electrode layers or drain electrode layers 105b2 and 105b3 have ends that recede from the source electrode layers or drain electrode layers 105a1 and 105b1.

[0085] Thus, when the selectivity in the etching process between the conductive film used for the source and drain electrode layers and the source region or drain region and the semiconductor layer is low, a conductive film that functions as an etch stop layer can be laminated, and the etching process can be performed multiple times under different etching conditions. That's all.

[0086] Figures 4(A) and (B) show examples of thin film transistors 170d and 170e in which the gate electrode layer 101 is larger than the semiconductor layer 103, the source region or drain region 10 4a and 104b, and the source electrode layer or drain electrode layer 105a and 105b. Also, insulating films 107a and 107b are formed as protective films on the thin film transistors 170d and 170e. On the gate electrode layer 101, the semiconductor layer 103, the source region or drain region 104a and 10 4b, and the source electrode layer or drain electrode layer 105a and 105b are formed. The manufacturing method of the thin film transistor 170a in Figures 5(A1) and (A2) will be described with reference to Figures 7(A) to (G). An insulating film 107a and 107b are formed as protective films on the thin film transistors 170d and 170e.

[0087] The manufacturing method of the thin film transistor 170a in Figures 5(A1) and (A2) will be described with reference to Figures 7(A) to (G). That's all.

[0088] The gate electrode layer 101, the gate insulating layer 102, and the semiconductor film 111 are formed on the substrate 100. See FIG. 7(A). The substrate 100 is made of barium borosilicate glass, aluminoborosilicate glass, etc. Glass or aluminosilicate glass, made by the fusion or float process. In addition to alkali-free glass and ceramic substrates, we also offer heat-resistant substrates that can withstand the processing temperatures of this manufacturing process. A plastic substrate having a metal substrate such as a stainless steel alloy may be used. A substrate having an insulating film on its surface may be used. The size of the substrate 50 is 320 mm x 4 00mm, 370mm×470mm, 550mm×650mm, 600mm×720mm , 680mm×880mm, 730mm×920mm, 1000mm×1200mm, 1 100mm×1250mm, 1150mm×1300mm, 1500mm×1800mm , 1900mm×2200mm, 2160mm×2460mm, 2400mm×2800 mm, or 2850mm x 3050mm, etc. can be used.

[0089] An insulating film may be formed as a base film on the substrate 100. The base film may be formed by a sputtering method. A single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film, Alternatively, it may be formed by laminating layers.

[0090] The gate electrode layer 101 may be made of titanium, molybdenum, chromium, tantalum, tungsten, or aluminum. The gate electrode layer 101 is formed using a metal material such as sulphur dioxide or an alloy material thereof. A conductive film is formed on the substrate 100 by a sputtering method or a vacuum deposition method, and then photolithography is performed on the conductive film. A mask is formed by a printing technique or an inkjet method, and a conductive film is etched using the mask. It can be formed by etching. It can also be formed by etching conductive nanoparticles such as silver, gold, and copper. Using a nozzle, ejecting by an inkjet method, and firing to form the gate electrode layer 101 This can be achieved. Note that, as a barrier metal for improving the adhesion of the gate electrode layer 101 and preventing diffusion into the substrate and the underlying film, a nitride film of the above metal material may be provided between the substrate 100 and the gate electrode layer 101. Also, the gate electrode layer 101 may have a single-layer structure or a stacked structure. For example, a stack of a molybdenum film and an aluminum film, a stack of a molybdenum film and an alloy film of aluminum and neodymium, a stack of a titanium film and an aluminum film, a stack of a titanium film, an aluminum film, and a titanium film, etc. may be used starting from the substrate 100 side. Since a semiconductor film and wiring are formed on the gate electrode layer 101, it is desirable to process the end portion so that it has a tapered shape to prevent step discontinuity. The gate insulating layer 102 and the semiconductor film 111 can be continuously formed without being exposed to the atmosphere. When forming the films continuously, each stacked interface can be formed without being contaminated by atmospheric components or contaminant impurity elements floating in the atmosphere. In an active matrix type display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of the thin film transistors, the threshold voltage (Vth) is important. If the threshold voltage value is high even though the field-effect mobility is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, in a state where the driving voltage is low, the switching function as a thin film transistor cannot be achieved.

[0091] Since a semiconductor film and wiring are formed on the gate electrode layer 101, it is desirable to process the end portion so that it has a tapered shape to prevent step discontinuity. Since a semiconductor film and wiring are formed on the gate electrode layer 101, it is desirable to process the end portion so that it has a tapered shape to prevent step discontinuity.

[0092] The gate insulating layer 102 and the semiconductor film 111 can be continuously formed without being exposed to the atmosphere. When forming the films continuously, each stacked interface can be formed without being contaminated by atmospheric components or contaminant impurity elements floating in the atmosphere. When forming the films continuously, each stacked interface can be formed without being contaminated by atmospheric components or contaminant impurity elements floating in the atmosphere. When forming the films continuously, each stacked interface can be formed without being contaminated by atmospheric components or contaminant impurity elements floating in the atmosphere.

[0093] In an active matrix type display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of the thin film transistors, the threshold voltage (Vth) is important. If the threshold voltage value is high even though the field-effect mobility is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, in a state where the driving voltage is low, the switching function as a thin film transistor cannot be achieved. In an active matrix type display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of the thin film transistors, the threshold voltage (Vth) is important. If the threshold voltage value is high even though the field-effect mobility is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, in a state where the driving voltage is low, the switching function as a thin film transistor cannot be achieved. Among the electrical characteristics of the thin film transistors, the threshold voltage (Vth) is important. If the threshold voltage value is high even though the field-effect mobility is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, in a state where the driving voltage is low, the switching function as a thin film transistor cannot be achieved. If the threshold voltage value is high even though the field-effect mobility is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, in a state where the driving voltage is low, the switching function as a thin film transistor cannot be achieved. If the threshold voltage value is high even though the field-effect mobility is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, in a state where the driving voltage is low, the switching function as a thin film transistor cannot be achieved. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, in a state where the driving voltage is low, the switching function as a thin film transistor cannot be achieved. It cannot be added and may become a load. Also, if the threshold voltage value is negative, a so-called normally-on state where current flows between the source electrode and the drain electrode even when the gate voltage is 0V is likely to occur.

[0094] In the case of an n-channel thin-film transistor, it is desirable to have a transistor in which a channel is formed and drain current flows only after a positive voltage is applied to the gate voltage. A transistor in which a channel is not formed unless the driving voltage is increased, or a transistor in which a channel is formed and drain current flows even in a negative voltage state is not suitable as a thin-film transistor used in a circuit.

[0095] Therefore, it is desirable that a channel is formed at a positive threshold voltage as close as possible to 0V for the gate voltage of a thin-film transistor using an oxide semiconductor film containing In, Ga, and Zn.

[0096] The threshold voltage of a thin-film transistor is considered to be greatly affected by the interface of the oxide semiconductor layer, that is, the interface between the oxide semiconductor layer and the gate insulating layer.

[0097] Therefore, by forming these interfaces in a clean state, it is possible to improve the electrical characteristics of the thin-film transistor and prevent the complication of the manufacturing process, and realize a thin-film transistor having both mass productivity and high performance.

[0098] In particular, when moisture in the air exists at the interface between the oxide semiconductor layer and the gate insulating layer, problems such as deterioration of the electrical characteristics of the thin-film transistor, variation in the threshold voltage, and tendency to become normally-on occur. By continuously forming the oxide semiconductor layer and the gate insulating layer, such hydrogen compounds can be eliminated.

[0099] Also, the surface of the gate insulating layer 102 is subjected to oxygen radical treatment to modify the surface of the gate insulating layer 102 into an oxygen-rich region.

[0100] As the oxygen radical treatment of the surface of the gate insulating layer 102, plasma treatment such as reverse sputtering may be performed. Reverse sputtering is a method of forming a plasma on the substrate by applying a voltage to the substrate side in an atmosphere of oxygen or an atmosphere of oxygen and argon to modify the surface without applying a voltage to the target side. Also, the gate insulating layer may be nitrided, and plasma treatment such as reverse sputtering may be performed in a nitrogen atmosphere.

[0101] Therefore, the surface of the gate insulating layer 102 is modified by oxygen radicals, and the gate insulating layer 102 and the semiconductor film 111 are continuously formed by sputtering under reduced pressure without exposure to the atmosphere, thereby realizing a thin film transistor having a good interface, low leakage current, and high current driving ability.

[0102] Also, the gate insulating layer 102 and the semiconductor film 111, which is an oxide semiconductor film containing In, Ga, and Zn, are preferably formed in an oxygen atmosphere (or an atmosphere containing 90% or more of oxygen and 10% or less of a rare gas (such as argon or helium)).

[0103] When continuously forming a film in this way using the sputtering method, the productivity is high and the reliability of the thin film interface is stabilized. Also, when the gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere to contain a large amount of oxygen, it is possible to reduce the decrease in reliability due to deterioration and the phenomenon that the thin film transistor becomes normally on.

[0104] ​​​​​​​​​​​​The gate insulating layer 102 can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film , or a silicon nitride oxide film. The thin film transistor 170c shown in FIGS. 6(A1) and (A2) is an example in which the gate insulating layer 102 is laminated.

[0105] As the gate insulating layer 102, a silicon nitride film or a silicon nitride oxide film and a silicon oxide film or a silicon oxynitride film can be laminated in this order. Note that the gate insulating layer is not limited to two layers, and three layers can be laminated in the order of a silicon nitride film or a silicon nitride oxide film, a silicon oxide film or a silicon oxynitride film, and a silicon nitride film or a silicon nitride oxide film from the substrate side. Also, the gate insulating layer can be formed of a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film.

[0106] Further, as the gate insulating layer 102, a silicon nitride film may be formed on the gate electrode layer 101 by sputtering, and a silicon oxide film may be laminated on the silicon nitride film by sputtering.

[0107] Here, the silicon oxynitride film means a film having a higher oxygen content than nitrogen in its composition. Also, the silicon nitride oxide film means a film having a higher nitrogen content than oxygen in its composition.

[0108] Further, as the gate insulating layer 102, a compound containing at least two kinds of oxides, nitrides, oxynitrides, or nitride oxides of aluminum, yttrium, or hafnium, or a compound thereof can also be used.

[0109] Further, the gate insulating layer 102 may contain a halogen element such as chlorine or fluorine. Gate The concentration of halogen elements in the insulating layer 102 is 1×10 15 atoms / cm 3 More than 1×10 20 atoms / cm 3 The following would suffice.

[0110] In this embodiment, in order to reduce hydrogen in the gate insulating layer 102, 02 is sputtered using a silicon single crystal target and argon and oxygen gases. The hydrogen in the gate insulating layer 102 diffuses and reacts with the excess oxygen in the semiconductor film 111. It is extremely important to prevent the channel from becoming an I-type by forming the H2O component in succession. It is also important to prevent moisture from adhering to the interface between the gate insulating layer 102 and the semiconductor film 111. Therefore, the chamber is evacuated with a cryopump or other device to achieve a minimum pressure of 1×10 -7 ~1×10 -10 Torr (approx. 1×10 -5 Pa or more 1×10 -8 Ultra-high vacuum (Pa) It is preferable to perform sputtering in a so-called UHV region. When the gate insulating layer and the semiconductor film 111 are successively laminated so as not to expose the interface therebetween to the air, The surface of 102 is treated with oxygen radicals to make the surface an oxygen-excess region. In the heat treatment for improving the reliability in the process, oxygen is supplied to modify the semiconductor film 111 interface. It is effective in creating a supply source.

[0111] In addition, an oxygen excess region is formed by performing oxygen radical treatment on the gate insulating layer 102. The oxygen concentration at the surface of the semiconductor film 111 is lower than that in the inside of the gate insulating layer 102. In addition, the concentration of oxygen radicals is higher than that of oxygen radicals. When this occurs, the oxygen concentration at the interface between the gate insulating layer 102 and the semiconductor film 111 increases.

[0112] If the semiconductor film 111 is laminated after performing oxygen radical treatment on the gate insulating layer 102 and then heat treatment is carried out, the oxygen concentration on the gate insulating layer 102 side of the semiconductor film 111 also becomes high.

[0113] As the semiconductor film 111, an oxide semiconductor film containing In, Ga, and Zn is formed. For example, as the semiconductor film 111, an oxide semiconductor film containing In, Ga, and Zn can be formed with a film thickness of 50 nm using a sputtering method. As a specific example of conditions, an oxide semiconductor target containing In, Ga, and Zn with a diameter of 8 inches can be used, and the distance between the substrate and the target can be 170 mm, the pressure can be 0.4 Pa, the DC (direct current) power supply can be 0.5 kW, and film formation can be carried out in an argon or oxygen atmosphere. Moreover, when using a pulsed DC power supply, dust can be reduced, and it is preferable because the film thickness distribution also becomes uniform.

[0114] Film formation can be carried out using an oxide semiconductor target containing In, Ga, and Zn in a rare gas atmosphere or in an oxygen atmosphere. Here, in order to include as much oxygen as possible in the IGZO film, an oxide semiconductor containing In, Ga, and Zn is used as the target, and in an atmosphere where oxygen is abundant, or in an atmosphere where oxygen is 90% or more and Ar is 10% or less, pulsed DC sputtering of the sputtering method is carried out to form an oxygen-excessive IGZO film.

[0115] In this way, without exposing to the atmosphere, by continuously forming an oxygen-excessive gate insulating layer 102 and an oxygen-excessive semiconductor film 111, the interface state between the oxygen-excessive films is stabilized, and T The reliability of the FT can be improved. When the substrate is exposed to the atmosphere before the formation of the IGZO film , moisture and the like adhere, which has an adverse effect on the interface state, resulting in variations in the threshold value and deterioration of electrical characteristics , and there is a risk of causing symptoms such as becoming a normally-on TFT. Moisture is a hydrogen compound. By continuously forming the film without exposure to the atmosphere, the presence of the hydrogen compound at the interface can be excluded. Therefore, by continuously forming the film, variations in the threshold value can be reduced , deterioration of electrical characteristics can be prevented, and the shift of the TFT to the normally-on side can be reduced , desirably eliminated.

[0116] Next, the semiconductor film 111 is processed by etching using the mask 113 to form the semiconductor layer 112 . (See FIG. 7(B).) The semiconductor layer 112 can be formed by forming the mask 113 by photolithography technology or the droplet discharge method and etching the semiconductor film 111 using the mask 113. By etching the end portion of the semiconductor layer 112 into a shape having a taper, disconnection of the wiring due to the step shape

[0117] can be prevented. Next, a semiconductor film 114, which is an oxygen-deficient oxide semiconductor film containing In, Ga, and Zn, is formed on the gate insulating layer 102 and the semiconductor layer 112 (see FIG. 7(C)). A mask 116 is formed on the semiconductor film 114

[0118] . The mask 116 is formed by photolithography technology or the inkjet method. The semiconductor film 114 is processed by etching using the mask 116 to form the semiconductor film 115 (see FIG. 7(D)). The semiconductor film 115 has a film thickness of 2 to 100 n . . It is preferable to set it as m (preferably 20 to 50 nm). The semiconductor film 114 is formed in an atmosphere of a noble gas (preferably argon). .

[0119] In addition, for the etching of the IGZO semiconductor films such as the semiconductor film 111 and the semiconductor film 115, organic acids such as citric acid and oxalic acid can be used as the etchant. For example, a 50-nm semiconductor film 111 can be etched in 150 seconds using ITO07N (manufactured by Kanto Chemical Co., Inc.). . .

[0120] A conductive film 117 is formed on the semiconductor film 115 (see Fig. 7(E)).

[0121] The conductive film 117 is preferably formed as a single layer or a laminate of aluminum or an aluminum alloy added with a heat resistance improving element or a hillock preventing element such as copper, silicon, titanium, neodymium, scandium, or molybdenum. Also, the film on the side in contact with the semiconductor film having an n-type conductivity type is formed of titanium, tantalum, molybdenum, tungsten, or a nitride of these elements, and a laminate structure in which aluminum or an aluminum alloy is formed thereon may be used. Further, a laminate structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched by titanium, tantalum, molybdenum, tungsten, or a nitride of these elements may also be used. Here, as the conductive film 117, a laminated conductive film of a titanium film, an aluminum film, and a titanium film is used. . . . . . . . .

[0122] Using a laminate of a titanium film, an aluminum film, and a titanium film results in low resistance and makes it difficult for hillocks to occur in the aluminum film. .

[0123] The conductive film 117 is formed by sputtering or vacuum evaporation. Also, the conductive film 117 is silver, gold,​ It may be formed by ejection and firing using a screen printing method, an inkjet method, etc. with a conductive nanopaste such as copper. It may be formed by ejection and firing using a screen printing method, an inkjet method, etc. with a conductive nanopaste such as copper.

[0124] Next, a mask 118 is formed on the conductive film 117. Using the mask 118, the conductive film 117 is etched and separated to form the source electrode layer or drain electrode layers 105a and 105b (see Fig. 7(F)). As shown in Fig. 7 of the present embodiment, when the conductive film 117 is wet-etched, since the conductive film 117 is etched isotropically, the end of the mask 118 and the ends of the source electrode layer or drain electrode layers 105a and 105b do not match as well and are more recessed. Next, using the mask 118, the semiconductor film 115 having an n-type conductivity type is etched to form the source region or drain regions 104a and 104b (see Fig. 7(G)). Note that, although it depends on the etching conditions, in the etching process of the semiconductor film 115, the exposed region of the semiconductor layer 112 is also partially etched to become the semiconductor layer 103. Therefore, the channel region of the semiconductor layer 103 between the source region or drain regions 104a and 104b becomes a region with a thin film thickness as shown in Fig. 7(G). In the semiconductor layer 103 which is an IGZO semiconductor layer, the region with a thin film thickness is 2 nm or more and 200 nm or less, preferably 20 nm or more and 150 nm or less.

[0125] Furthermore, similar to the gate insulating layer 102, oxygen radical treatment may be performed on the semiconductor layer 103. By performing oxygen radical treatment on the channel formation region of the exposed semiconductor layer 103, the surface of the semiconductor layer can be made an oxygen-excess region.

[0126] Fig. 4(B) shows a thin film transistor in which oxygen radical treatment is performed on the channel formation region of the semiconductor layer 103. Displayer 170e is shown. In the thin film transistor 170e, the exposed region of the semiconductor layer 103 which is the channel formation region is modified into an oxygen-excess region by oxygen radical treatment. By making the surface of the semiconductor layer an oxygen-excess region, the incorporation of hydrogen into the semiconductor layer can be prevented, and also

[0127] the back channel can be made an oxygen-deficient region to prevent conduction between the source and drain and reduce the off-current. Since the semiconductor layer in the back channel portion can also be made an oxygen-excess region in this way, similar to the oxygen radical treatment of the gate insulating layer, it is effective to perform oxygen radical treatment on the semiconductor layer in the back channel portion. the back channel becomes an oxygen-deficient region to prevent conduction between the source and drain and reduce the off-current. In this way, since the semiconductor layer in the back channel portion can also be made an oxygen-excess region, similar to the oxygen radical treatment of the gate insulating layer, it is effective to perform oxygen radical treatment on the semiconductor layer in the back channel portion. Since the semiconductor layer in the back channel portion can also be made an oxygen-excess region in this way, similar to the oxygen radical treatment of the gate insulating layer, it is effective to perform oxygen radical treatment on the semiconductor layer in the back channel portion. Performing oxygen radical treatment on the semiconductor layer in the back channel portion is effective.

[0128] The ends of the source electrode layer or drain electrode layers 105a, 105b do not coincide with the ends of the source region or drain region 104a, 104b and are offset, and the ends of the source region or drain region 104a, 104b are formed outside the ends of the source electrode layer or drain electrode layers 105a, 105b. The ends of the source electrode layer or drain electrode layers 105a, 105b do not coincide with the ends of the source region or drain region 104a, 104b and are offset, and the ends of the source region or drain region 104a, 104b are formed outside the ends of the source electrode layer or drain electrode layers 105a, 105b. The ends of the source electrode layer or drain electrode layers 105a, 105b do not coincide with the ends of the source region or drain region 104a, 104b and are offset, and the ends of the source region or drain region 104a, 104b are formed outside the ends of the source electrode layer or drain electrode layers 105a, 105b. The ends of the source region or drain region 104a, 104b are formed.

[0129] After that, the mask 118 is removed. Through the above steps, the thin film transistor 170a can be formed. The thin film transistor 170a can be formed.

[0130] Next, the manufacturing process of the thin film transistor 170b shown in FIGS. 5(B1)(B2) is shown in FIG. 8.

[0131] FIG. 8(A) shows the state where the mask 113 is removed in the process of FIG. 7(B). A semiconductor film 114 and a conductive film 121 are sequentially laminated on the semiconductor layer 112 (see FIG. 8(B)). In this case, the semiconductor film 114 and the conductive film 121 can be continuously formed by sputtering without exposing them to the atmosphere. A semiconductor film 114 and a conductive film 121 are sequentially laminated on the semiconductor layer 112 (see FIG. 8(B)). In this case, the semiconductor film 114 and the conductive film 121 can be continuously formed by sputtering without exposing them to the atmosphere. In this case, the semiconductor film 114 and the conductive film 121 can be continuously formed by sputtering without exposing them to the atmosphere. It can be done.

[0132] A mask 122 is formed on the semiconductor film 114 and the conductive film 121, and the conductive film 121 is wet-etched to form the source electrode layer or the drain electrode layer 105a, 105 b (see Fig. 8(C)).

[0133] Next, the semiconductor film 114 is dry-etched to form the source region or the drain region 104a , 104b (see Fig. 8(D)). In the same process, a part of the semiconductor layer 112 is also etched to become the semiconductor layer 103. As shown in Fig. 8, when the same mask is used for the etching to form the source region or the drain region 104a, 104b and the source electrode layer or the drain electrode layer 105a, 105b, the number of masks can be reduced, and thus the process can be simplified and the cost can be reduced.

[0134] An insulating film may also be formed as a protective film on the thin film transistors 170a, 170b, 170c in the same manner as on the thin film transistors 170d, 1 70e. The protective film can be formed in the same manner as the gate insulating layer. The protective film is for preventing the intrusion of contaminants such as organic substances, metal substances, and water vapor floating in the air, and a dense film is preferred. For example, an oxide film (silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film) and a nitride film (silicon nitride film, silicon oxynitride film, aluminum nitride film, aluminum oxynitride film) may be laminated on the thin film transistors 170a, 170b, 170c, 170d, 170e. The silicon oxide film may be formed by DC sputtering under a nitrogen and argon atmosphere using a silicon target, and the aluminum nitride film and the aluminum oxynitride film may be formed by RF sputtering using an aluminum nitride target. , the aluminum oxide film may be formed by RF sputtering using an aluminum oxide target. Also, vacuum baking may be performed before forming the protective film. It may be formed. Also, vacuum baking may be performed before forming the protective film.

[0135] Also, it is preferable to perform a heat treatment on the semiconductor layer 103 and oxide semiconductor films such as the source region or drain regions 104a and 104b after film formation. The heat treatment may be performed at any process as long as it is after film formation, but it can be performed immediately after film formation, after forming the conductive film 117, after forming the protective film, etc. Also, it may be performed in combination with other heat treatments. Also, the heat treatment temperature may be 200°C or higher and 600°C or lower, preferably 300°C or higher and 500°C or lower. When continuously forming the semiconductor layer 103 and the source region or drain regions 104a and 104b as shown in FIG. 6, a heat treatment may be performed after lamination. The heat treatment may be performed a plurality of times in a separate process for the semiconductor layer 103 and the source region or drain regions 104a and 104b. It may be formed. Also, vacuum baking may be performed before forming the protective film. It may be formed. Also, vacuum baking may be performed before forming the protective film. It may be formed. Also, vacuum baking may be performed before forming the protective film. It may be formed. Also, vacuum baking may be performed before forming the protective film. It may be formed. Also, vacuum baking may be performed before forming the protective film. It may be formed. Also, vacuum baking may be performed before forming the protective film. It may be formed. Also, vacuum baking may be performed before forming the protective film.

[0136] The ends of the source electrode layer or drain electrode layer 105a and 105b and the ends of the source region or drain regions 104a and 104b do not coincide and are offset, so that the distance between the ends of the source electrode layer or drain electrode layer 105a and 105b is increased, thereby preventing leakage current and short circuits between the source electrode layer or drain electrode layer 105a and 105b. Therefore, a thin film transistor with high reliability and high breakdown voltage can be manufactured. It may be formed. Also, vacuum baking may be performed before forming the protective film. It may be formed. Also, vacuum baking may be performed before forming the protective film. It may be formed. Also, vacuum baking may be performed before forming the protective film. It may be formed. Also, vacuum baking may be performed before forming the protective film.

[0137] Also, the ends of the source region or drain regions 104a and 104b and the ends of the source electrode and drain electrode may be made to coincide as in the thin film transistor 170c of FIGS. 6(A1) and (A2). The etch for forming the source electrode layer or drain electrode layer 105a and 105b It may be formed. Also, vacuum baking may be performed before forming the protective film. It may be formed. Also, vacuum baking may be performed before forming the protective film. Etching for forming a channel and source region or drain regions 104a and 104b When performed by dry etching, it can be shaped like the thin film transistor 170c in FIGS. 6(A1) and (A2). Also, when etching a semiconductor film 115 having an n-type conductivity type using the source electrode and the drain electrode as a mask to form the source region or drain regions 104a and 10 4b, it can be shaped like the thin film transistor 170c in FIGS. 6(A1) and (A2). .

[0138] In the case of a stacked structure including a gate electrode layer, a gate insulating layer, a semiconductor layer (oxygen-excessive oxide semiconductor layer containing In, Ga, and Zn), a source electrode layer, and a drain electrode layer without providing a source region or drain region (oxygen-deficient oxide semiconductor layer containing In, Ga, and Zn), the distance between the gate electrode layer and the source electrode layer or the drain electrode layer becomes short, and the parasitic capacitance generated therebetween increases . Further, this increase in parasitic capacitance becomes more prominent due to the thinning of the semiconductor layer . In the present embodiment, since a thin film transistor having a stacked structure including a gate electrode layer, a gate insulating layer, a semiconductor layer, a source region or drain region, a source electrode layer, and a drain electrode layer is used, even if the thickness of the semiconductor layer is thin, the parasitic capacitance can be suppressed . According to the present embodiment, a thin film transistor having a small photocurrent, a small parasitic capacitance, and a high on / off ratio can be obtained, and a thin film transistor having good dynamic characteristics can be manufactured. Therefore, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided .

[0139]

[0140]

[0140] (Embodiment 2) This embodiment is an example of a thin film transistor with a multi-gate structure according to one aspect of the present invention. Therefore, the other operations can be performed in the same manner as in Embodiment 1, and the description of the same parts or parts having similar functions as in Embodiment 1, and the repetition of the processes will be omitted. In this embodiment, the thin film transistor used in the semiconductor device will be described with reference to FIGS. 9(A)(B) to FIGS. 11(A)(B). FIG. 9(A) is a plan view showing the thin film transistor, and FIG. 9(B) corresponds to a cross-sectional view showing the thin film transistor 170a along line E1-E2 in FIG. 9(A).

[0141] As shown in FIGS. 9(A)(B), a thin film transistor 171a with a multi-gate structure including a gate electrode layer 151a, 151b, a gate insulating layer 152, semiconductor layers 153a, 153b, source regions or drain regions 154a, 154b, 154c, and a source electrode layer or drain electrode layer 155a, 155b is provided on a substrate 150. The semiconductor layers 153a, 153b are oxygen-excess oxide semiconductor layers containing In, Ga, and Zn, and the source regions or drain regions 154a, 154b, 154c are oxygen-deficient oxide semiconductor layers containing In, Ga, and Zn. The source regions or drain regions 154a, 154b, 154c have a higher carrier concentration than the semiconductor layers 153a, 153b.

[0142] The gate insulating layer 152 having an oxygen-excess region and the semiconductor layers 153a, 153b which are oxygen-excess oxide semiconductor layers are compatible with each other, and good interface characteristics can be obtained.

[0143]

[0144]

[0145]

[0146] ​​​​​​​​​​​ After the formation of the gate insulating layer 152, the surface of the gate insulating layer 152 is subjected to oxygen radical treatment to form an oxygen excess region. Also, the gate insulating layer 152 and the semiconductor layers 153a and 153b are formed by continuous film formation .

[0147] The oxygen-deficient oxide semiconductor layers of the source region and the drain regions 154a, 154b, and 154c have crystal grains with a size of 1 nm or more and 10 nm or less, and have a higher carrier concentration than the semiconductor layers 153a and 153b.

[0148] One of the semiconductor layer 153a and the semiconductor layer 153b is electrically connected via the source region or the drain region 154c, and the other semiconductor layer 153a is connected to the source electrode layer or the drain electrode layer 155a via the source region or the drain in region 154a, and the semiconductor layer 153 b is electrically connected to the source electrode layer or the drain electrode layer 15 5b via the source region or the drain region 154b.

[0149] FIG. 10 shows a thin film transistor 171b having a multi-gate structure with another configuration. FIG. 10(A) is a plan view showing the thin film transistor 171b, and FIG. 10(B) corresponds to a cross-sectional view showing the thin film transistor 171b taken along line F1 - F2 in FIG. 10(A). In the thin film transistor 171b of FIG. 10, a wiring layer 156 formed in the same process as the source electrode layer or the drain electrode layers 155a and 155b is provided on the source region or the drain region 154c, and the semiconductor layer 153a and the semiconductor layer 153b are electrically connected by the source region or the drain region 154c and the wiring layer 1 56. 56.

[0150] FIG. 11 shows a thin film transistor 171c having a multi-gate structure with another configuration. FIG. 11(A) is a plan view showing the thin film transistor 171c, and FIG. 11(B) corresponds to a cross-sectional view showing the thin film transistor 171c along the line G1-G2 in FIG. 11(A). In the thin film transistor 171c of FIG. 11, an example is shown in which the semiconductor layer 153a and the semiconductor layer 153b are formed as a single continuous semiconductor layer 153. The semiconductor layer 153 is provided so as to straddle the gate electrode layers 151a and 151b with the gate insulating layer 152 therebetween.

[0151] Thus, in the multi-gate structure thin film transistor according to one embodiment of the present invention, the semiconductor layer formed on each gate electrode layer may be provided continuously, or a plurality of semiconductor layers may be electrically connected and provided via a source region or a drain region and a wiring layer or the like.

[0152] The multi-gate structure thin film transistor according to one embodiment of the present invention has a small off-current, and a semiconductor device including such a thin film transistor can be provided with high electrical characteristics and high reliability.

[0153] In the present embodiment, an example of a double gate structure with two gate electrode layers is shown as the multi-gate structure, but one embodiment of the present invention can also be applied to a triple gate structure having more gate electrode layers or the like.

[0154] In the present embodiment, a thin film transistor having a stacked structure of a gate electrode layer, a gate insulating layer, a semiconductor layer (oxygen-excess oxide semiconductor layer), a source region and a drain region (oxygen-deficient oxide semiconductor layer), a source electrode layer and a drain electrode layer is used, and by using a source region and a drain region having a high carrier concentration having crystal grains in the oxygen-deficient oxide semiconductor layer, the semiconductor ​​​​​​​​​​​​​The film thickness of the layer can be kept thin while suppressing parasitic capacitance. Even if it is a thin film, since the ratio to the gate insulating layer is sufficient, the parasitic capacitance is sufficiently suppressed.

[0155] According to this embodiment, a thin film transistor with low photocurrent, small parasitic capacitance, and a high on-off ratio can be obtained, and a thin film transistor with good dynamic characteristics can be fabricated. Therefore, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided.

[0156] This embodiment can be implemented in appropriate combination with other embodiments.

[0157] (Embodiment 3) This embodiment is an example in which a source region and a drain region are stacked in a thin film transistor according to one form of the present invention. Therefore, other operations can be performed in the same manner as in Embodiment 1 or Embodiment 2, and descriptions of the same parts or parts having the same functions as those in Embodiment 1 or Embodiment 2, and repeated descriptions of processes are omitted.

[0158] In this embodiment, the thin film transistor 173 used in the semiconductor device will be described with reference to FIG. 12.

[0159] As shown in FIG. 12, a thin film transistor 173 including a gate electrode layer 101, a semiconductor layer 103, source regions or drain regions 106a and 106b which are second source regions or drain regions, source regions or drain regions 104a and 104b which are first source regions or drain regions, and source electrode layers or drain electrode layers 105a and 105b is provided on a substrate 100.

[0160] The thin film transistor 173 of this embodiment has a source region or drain region 104a, 4b and the source or drain electrode layer 105a, 105b. The source and drain regions 106a and 106b are provided as the source and drain regions. It is being done.

[0161] The semiconductor layer 103 is an oxygen-excess oxide semiconductor layer containing In, Ga, and Zn. The drain regions 104a, 104b, 106a, 106b are made of In, Ga, and Zn. The oxygen-deficient oxide semiconductor layer includes:

[0162] The source or drain regions 104a and 104b and the source or drain electrode layer 10 The source region or drain region 106a, 106b provided between the first and second gate electrodes 5a, 105b is Contains impurity elements.

[0163] The impurity elements contained in the source and drain regions 106a and 106b are, for example, Indium, gallium, zinc, magnesium, aluminum, titanium, iron, tin, calcium Zn, Scandium, Yttrium, Zirconium, Hafnium, Boron, Thallium, Gel These impurity elements (e.g., magnesium, lead, etc.) can be used. When the source or drain region contains a metal such as aluminum or titanium, it acts as a blocker of oxygen. The oxygen concentration in the semiconductor layer can be adjusted to an optimal range by heat treatment after film formation. In this embodiment, the source region or drain region 106a, 106b can be held in the An oxygen-deficient oxide semiconductor layer containing In, Ga, and Zn, which contains titanium, is used.

[0164] When an oxygen-deficient oxide semiconductor layer containing titanium is provided as the source region or drain regions 106a and 106b, an aluminum film can be directly formed on the source region or drain regions 106a and 106b as the source electrode layer and drain electrode layer, and a titanium film can be formed on the aluminum film.

[0165] The thin-film transistor having a multilayer source region or drain region according to one embodiment of the present invention can operate at a higher speed, and a semiconductor device including such a thin-film transistor can be provided with high electrical characteristics and high reliability.

[0166] This embodiment can be implemented in appropriate combination with other embodiments.

[0167] (Embodiment 4) This embodiment is an example in which the shape and manufacturing method of the thin-film transistor are partially different in Embodiment 1. Therefore, other operations can be performed in the same manner as in Embodiment 1, and descriptions of the same parts or parts having similar functions as in Embodiment 1, and repetitions of steps are omitted.

[0168] In this embodiment, the thin-film transistor 174 used in the display device and its manufacturing process will be described with reference to FIGS. 13 and 14. FIG. 13(A1) is a plan view of the thin-film transistor 174, and FIGS. 13(A2) and 14 are cross-sectional views corresponding to the thin-film transistor and its manufacturing process along line D1-D2 in FIG. 13(A1). As shown in FIGS. 13(A) and (B), a thin-film transistor 174 including a gate electrode layer 101, a semiconductor layer 103, source regions or drain regions 104a and 104b, and source electrode layers or drain electrode layers 105a and 105b is provided on a substrate 100.

[0169] ​

[0170] The semiconductor layer 103 is an oxygen-excess oxide semiconductor layer containing In, Ga, and Zn, and the source region or drain regions 104a, 104b are oxygen-deficient oxide semiconductor layers. The source region or drain regions 104a, 104b have a higher carrier concentration than the semiconductor layer 103.

[0171] After the formation of the gate insulating layer 102, an oxygen radical treatment is performed on the surface of the gate insulating layer 102 to form an oxygen-excess region. Also, the gate insulating layer 102 and the semiconductor layer 103 are formed continuously.

[0172] The gate insulating layer 102 having an oxygen-excess region and the semiconductor layer 103, which is an oxygen-excess oxide semiconductor layer, have good compatibility and can obtain good interface characteristics.

[0173] The oxygen-deficient oxide semiconductor layers of the source region and drain regions 104a, 104b have crystal grains with a size of 1 nm or more and 10 nm or less, and have a higher carrier concentration than the semiconductor layer 103.

[0174] The semiconductor layer 103 is electrically connected to the source electrode layer or drain electrode layer 105a through the source region or drain region 104a, and is electrically connected to the source electrode layer or drain electrode layer 105b through the source region or drain region 104b.

[0175] The manufacturing process of the thin film transistor 174 will be described with reference to FIG. 14. A gate electrode layer 101 is formed on a substrate 100. Next, a gate insulating layer 102 is formed on the gate electrode layer 101, and after performing an oxygen radical treatment on the surface of the gate insulating layer 102, a semiconductor film 131, which is an oxygen-excess oxide semiconductor film containing In, Ga, and Zn, and an oxygen-deficient oxide containing In, Ga, and Zn are formed. ​​​​​The semiconductor film 132, which is an oxide semiconductor film, and the conductive film 133 are formed in this order (see Fig. 14(A)). 。

[0176] The gate insulating layer 102, the semiconductor film 131 which is an oxygen-excess oxide semiconductor film containing In, Ga, and Zn, the semiconductor film 132 which is an oxygen-deficient oxide semiconductor film containing In, Ga, and Zn, and the conductive film 133 can be continuously formed without exposing them to the air. By continuously forming the films without exposing them to the air, each laminated interface can be formed without being contaminated by atmospheric components or contaminant element in the air, so that the variation in thin film transistor characteristics can be reduced.

[0177] In this embodiment, an example of performing exposure using a halftone mask to form the mask 135 is shown. A resist is formed to form the mask 135. As the resist, a positive resist or a negative resist can be used. Here, a positive resist is used for illustration.

[0178] Next, using a halftone mask as a photomask, the resist is irradiated with light to expose the resist.

[0179] A halftone mask is a mask capable of performing three exposure levels on an exposed portion, an intermediate exposed portion, and an unexposed portion, and by one exposure and development process, a resist mask having regions of a plurality of (typically two types) thicknesses can be formed. Therefore, by using a halftone mask, the number of photomasks can be reduced.

[0180] Typical examples of halftone masks include a grayscale mask and a halftone mask.

[0181] ​​​​​​ A grayscale mask is composed of a substrate having translucency, a light-shielding portion formed thereon, and a diffraction grating. In the light-shielding portion, the light transmittance is 0%. On the other hand, for the diffraction grating, by setting the intervals between light-transmitting portions such as slits, dots, and meshes to be equal to or less than the resolution limit of the light used for exposure, the light transmittance can be controlled. Note that either a periodic slit, dot, mesh, or an aperiodic slit, dot, mesh can be used for the diffraction grating. As the substrate having translucency, a substrate having translucency such as quartz can be used. The light-shielding portion and the diffraction grating can be formed using a light-absorbing light-shielding material such as chromium or chromium oxide. When the grayscale mask is irradiated with exposure light, in the light-shielding portion, the light transmittance is 0%, and in the region where the light-shielding portion and the diffraction grating are not provided, the light transmittance is 100%. Also, in the diffraction grating, it can be adjusted within the range of 10 to 70%. The adjustment of the light transmittance in the diffraction grating can be achieved by adjusting the intervals and pitches of the slits, dots, or meshes of the diffraction grating. A halftone mask is composed of a substrate having translucency, a semi-transmissive portion formed thereon, and a light-shielding portion. For the semi-transmissive portion, MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light-shielding portion can be formed using a light-absorbing light-shielding material such as chromium or chromium oxide. When the halftone mask is irradiated with exposure light, in the light-shielding portion, the light transmittance is 0%.

[0182] For the substrate having translucency, a substrate having translucency such as quartz can be used. The light-shielding portion and the diffraction grating can be formed using a light-absorbing light-shielding material such as chromium or chromium oxide.

[0183] When the grayscale mask is irradiated with exposure light, in the light-shielding portion, the light transmittance is 0%, and in the region where the light-shielding portion and the diffraction grating are not provided, the light transmittance is 100%. Also, in the diffraction grating, it can be adjusted within the range of 10 to 70%. The adjustment of the light transmittance in the diffraction grating can be achieved by adjusting the intervals and pitches of the slits, dots, or meshes of the diffraction grating.

[0184] A halftone mask is composed of a substrate having translucency, a semi-transmissive portion formed thereon, and a light-shielding portion. For the semi-transmissive portion, MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light-shielding portion can be formed using a light-absorbing light-shielding material such as chromium or chromium oxide.

[0185] When the halftone mask is irradiated with exposure light, in the light-shielding portion, the light transmittance is 0%. In the region where the light-shielding portion and the semi-transmissive portion are not provided, the light transmittance is 100%. Also , in the semi-transmissive portion, it can be adjusted within the range of 10 to 70%. The adjustment of the light transmittance in the semi-transmissive portion can be achieved by adjusting according to the material of the semi-transmissive portion.

[0186] After exposure using a multi-tone mask and then development, as shown in FIG. 14(B), a mask 135 having regions with different film thicknesses can be formed.

[0187] Next, using the mask 135, the semiconductor film 131, the semiconductor film 132 having an n-type conductivity type, and the conductive film 133 are etched and separated. As a result, a semiconductor film 136, a semiconductor film 137 having an n-type conductivity type, and a conductive film 138 can be formed (see FIG. 14(B)).

[0188] Next, the mask 135 is ashed. As a result, the area of the mask is reduced and the thickness becomes thinner. At this time, the resist of the mask in the region with a thin film thickness (the region overlapping with a part of the gate electrode layer 101) is removed, and a separated mask 139 can be formed (see FIG. 14(C)).

[0189] Using the mask 139, the conductive film 138 is etched to form a source electrode layer or a drain electrode layer 105a, 105b. When the conductive film 138 is wet-etched as in this embodiment, since the conductive film 138 is etched isotropically, the end of the mask 139 and the ends of the source electrode layer or the drain electrode layer 105a, 105b do not coincide and are more recessed, and the semiconductor film 137 having an n-type conductivity type and the semiconductor film 136 protrude outside the source electrode layer or the drain electrode layer 105a, 105b. Next, using the mask 139, the n-type conductivity type and the semiconductor film 136 are formed in a protruding shape. Etch the semiconductor film 137 and the semiconductor film 136 to form the source region or the drain regions 104a and 104b and the semiconductor layer 103 (see Fig. 14(D)). Note that only a part of the semiconductor layer 103 is etched to form a semiconductor layer having a groove portion. The formation process of the source region or the drain regions 104a and 104b and the groove portion of the semiconductor layer 103 can be formed in the same process. Similarly, the end portion of the semiconductor layer 103 has a shape in which a part is etched and exposed. After that, the mask 139 is removed.

[0190]

[0191] Through the above steps, the thin film transistor 174 shown in Figs. 13(A) and (B) can be manufactured.

[0192] As in this embodiment, when using a resist mask having a plurality (typically two types) of thickness regions formed by a multi-tone mask, the number of resist masks can be reduced, so that the process can be simplified and the cost can be reduced.

[0193] This embodiment can be implemented in appropriate combination with other embodiments.

[0194] (Embodiment 5) In this embodiment, in a display device which is an example of the semiconductor device of the present invention, an example of manufacturing at least a part of a drive circuit and a thin film transistor disposed in a pixel portion on the same substrate will be described below.

[0195] The thin film transistor disposed in the pixel portion is formed according to any one of Embodiments 1 to 4. Further, since the thin film transistor shown in any one of Embodiments 1 to 4 is an n-channel type TFT, among the drive circuits, those constituted by n-channel type TFTs ​​​​​​​​​​​ A part of the driver circuit capable of performing this is formed on the same substrate as the thin film transistor of the pixel portion.

[0196] FIG. 1 is a block diagram of an active matrix liquid crystal display device, which is an example of a semiconductor device of the present invention. An example is shown in FIG. 16A. The display device shown in FIG. A pixel portion 5301 having a plurality of pixels, and a scanning line driver circuit 5302 for selecting each pixel. and a signal line driver circuit 5303 for controlling input of a video signal to a selected pixel.

[0197] The pixel portion 5301 includes a signal line driver circuit 5303 and a plurality of signal lines arranged in a column direction. The signal line driver circuit 5303 is connected to the signal line driver circuit 5303 by lines S1 to Sm (not shown). A plurality of scanning lines G1 to Gn (not shown) are arranged extending from 5302 in the row direction. The scanning line driver circuit 5302 is connected to the signal lines S1 to Sm and the scanning lines G1 to Gn. The image sensor has a plurality of pixels (not shown) arranged in a matrix. Signal line Sj (any one of signal lines S1 to Sm), scanning line Gi (any one of scanning lines G1 to Gn) Either one of them is connected.

[0198] In addition, the thin film transistor shown in any one of the first to fourth embodiments is an n-channel The signal line driver circuit is configured with n-channel TFTs. He explains.

[0199] The signal line driver circuit shown in FIG. 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613 and a wiring 56 Each of the switch groups 5602_1 to 5602_M includes It has a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 5603c.

[0200] The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, a third wiring 5613 and wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 561 3 and the wirings 5621_1 to 5 621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film tran sistor 5603c and is connected to three signal lines. For example, the wiring 5621 _J (any one of the wirings 5621_1 to 5621_M) in the Jth column is connected to the signal lines Sj-1, signal line Sj, and signal line S j+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c included in the switch group 5602 _J.

[0201] Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

[0202] Note that it is desirable that the driver IC 5601 is formed on a single crystal substrate. Furthermore it is desirable that the switch groups 5602_1 to 5602_M are formed on the same substrate as the pixel portion. Therefore, it is advisable to connect the driver IC 5601 and the switch groups 5602_1 to 5602_ M via an FPC or the like.

[0203] ​ Next, the operation of the signal line driving circuit shown in FIG. 17 will be described with reference to the timing chart of FIG. 18. Note that the timing chart of FIG. 18 shows the timing chart when the scanning line Gi in the i-th row is selected. Further, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driving circuit in FIG. 17 operates in the same manner as in FIG. 18 even when scanning lines of other rows are selected. Next, the operation of the signal line driving circuit shown in FIG. 17 will be described with reference to the timing chart of FIG. 18. Note that the timing chart of FIG. 18 shows the timing chart when the scanning line Gi in the i-th row is selected. Further, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driving circuit in FIG. 17 operates in the same manner as in FIG. 18 even when scanning lines of other rows are selected. Next, the operation of the signal line driving circuit shown in FIG. 17 will be described with reference to the timing chart of FIG. 18. Note that the timing chart of FIG. 18 shows the timing chart when the scanning line Gi in the i-th row is selected. Further, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driving circuit in FIG. 17 operates in the same manner as in FIG. 18 even when scanning lines of other rows are selected. Next, the operation of the signal line driving circuit shown in FIG. 17 will be described with reference to the timing chart of FIG. 18. Note that the timing chart of FIG. 18 shows the timing chart when the scanning line Gi in the i-th row is selected. Further, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driving circuit in FIG. 17 operates in the same manner as in FIG. 18 even when scanning lines of other rows are selected. Next, the operation of the signal line driving circuit shown in FIG. 17 will be described with reference to the timing chart of FIG. 18. Note that the timing chart of FIG. 18 shows the timing chart when the scanning line Gi in the i-th row is selected. Further, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driving circuit in FIG. 17 operates in the same manner as in FIG. 18 even when scanning lines of other rows are selected. Next, the operation of the signal line driving circuit shown in FIG. 17 will be described with reference to the timing chart of FIG. 18. Note that the timing chart of FIG. 18 shows the timing chart when the scanning line Gi in the i-th row is selected. Further, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driving circuit in FIG. 17 operates in the same manner as in FIG. 18 even when scanning lines of other rows are selected.

[0204] Note that the timing chart of FIG. 18 shows the case where the wiring 5621_J in the J-th column is connected to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. Note that the timing chart of FIG. 18 shows the case where the wiring 5621_J in the J-th column is connected to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. Note that the timing chart of FIG. 18 shows the case where the wiring 5621_J in the J-th column is connected to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. Note that the timing chart of FIG. 18 shows the case where the wiring 5621_J in the J-th column is connected to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c.

[0205] Note that the timing chart of FIG. 18 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column. Note that the timing chart of FIG. 18 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column. Note that the timing chart of FIG. 18 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column. Note that the timing chart of FIG. 18 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column. Note that the timing chart of FIG. 18 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column.

[0206] Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is Input to signal line Sj-1 and input to wiring 5621_J during the second sub-selection period T2 The video signal input to wiring 5621_J during the second sub-selection period T2 is input to signal line Sj, and the video signal input to wiring 5621 _J during the third sub-selection period T3 is input to signal line Sj+1. Further, during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, the video signals input to wiring 5621_ J are respectively denoted as Data_j-1, Data_j, and Data_j+ 1.

[0207] As shown in FIG. 18, during the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to wiring 5621_J is input to signal line Sj-1 through the first thin film transistor 5603a. During the second sub-selection period T2 , the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to wiring 5621_J is input to signal line Sj through the second thin film transistor 5603b . During the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to wiring 5621_J is input to signal line Sj+1 through the third thin film transistor 56 03c.

[0208] From the above, the signal line driving circuit in FIG. 17 divides one gate selection period into three, so that a video signal is input from one wiring 5621 to three signal lines during one gate selection period. This can be achieved. Therefore, in the signal line driving circuit of FIG. 17, the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed can be made approximately 1 / 3 compared to the number of signal lines. By reducing the number of connections to approximately 1 / 3, the signal line driving circuit of FIG. 17 can improve reliability, yield, etc. In addition, as shown in FIG. 17, if one gate selection period is divided into a plurality of sub-selection periods, and a video signal can be input from a certain one wiring to each of the plurality of signal lines in each of the plurality of sub-selection periods, the arrangement, number, driving method, etc. of the thin film transistors are not limited. For example, when inputting a video signal from one wiring to three or more signal lines in each of three or more sub-selection periods, wiring for controlling the thin film transistors and the thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period is divided into two or three sub-selection periods.

[0209] As another example, as shown in the timing chart of FIG. 19, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3. Further, the timing chart of FIG. 19 shows the timing when the scanning line Gi of the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the wiring 562 of the J-th column. In each of the plurality of sub-selection periods, a video signal can be input from a certain one wiring to each of the plurality of signal lines. Then, the arrangement, number, driving method, etc. of the thin film transistors are not limited.

[0210] For example, when inputting a video signal from one wiring to three or more signal lines in each of three or more sub-selection periods, wiring for controlling the thin film transistors and the thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period is divided into two or three sub-selection periods.

[0211] As another example, as shown in the timing chart of FIG. 19, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3. Furthermore, the timing chart of FIG. 19 shows the timing when the scanning line Gi of the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c and the wiring 562 of the J-th column. It shows the signal 5821_J input to 1_J. As shown in FIG. 19, during the precharge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603 b and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp applied to the wiring 5621_J is input to the signal lines Sj - 1, signal line Sj, and signal line Sj + 1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. During the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j - 1 input to the wiring 5621_J is input to the signal line Sj - 1 through the first thin film transistor 5603a. 1, signal line Sj, and signal line Sj + 1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. During the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j - 1 input to the wiring 5621_J is input to the signal line Sj - 1 through the first thin film transistor 5603a. 1, signal line Sj, and signal line Sj + 1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. During the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j - 1 input to the wiring 5621_J is input to the signal line Sj - 1 through the first thin film transistor 5603a. thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j - 1 input to the wiring 5621_J is input to the signal line Sj - 1 through the first thin film transistor 5603a. membrane transistor 5603c are turned off. At this time, Data_j - 1 input to the wiring 5621_J is input to the signal line Sj - 1 through the first thin film transistor 5603a. a_j - 1 is input to the signal line Sj - 1 through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film film transistor 5603a and the third thin film transistor 5603c are turned off. At this time , Data_j input to the wiring 5621_J is input to the signal line Sj through the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5 603b are turned off. At this time, Data_j + 1 input to the wiring 5621_J is input to the signal line Sj + 1 through the third thin film transistor 5603c.

[0212] From the above, the signal line driving circuit of FIG. 17 to which the timing chart of FIG. 19 is applied provides a precharge selection period before the sub-selection period, thereby precharging the signal line. By providing a precharge selection period before the sub-selection period, the signal line is precharged. Therefore, the video signal can be written to the pixels at high speed. In FIG. 19, for those similar to FIG. 18, common reference numerals are used, and detailed descriptions of the same parts or parts having similar functions are omitted.

[0213] Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register and a buffer. In some cases, it may also have a level shifter. In the scanning line driving circuit, when a clock signal (CLK) and a start pulse signal (SP ) are input to the shift register, a selection signal is generated. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. To the scanning line, the gate electrodes of the transistors of the pixels for one line are connected. And since the transistors of the pixels for one line must be turned on all at once, a buffer capable of flowing a large current is used.

[0214] A form of the shift register used in a part of the scanning line driving circuit will be described with reference to FIGS. 20 and 21.

[0215] FIG. 20 shows the circuit configuration of the shift register. The shift register shown in FIG. 20 is composed of a plurality of flip-flops 5701_i (any one of flip-flops 5701_1 to 5701_n). Also, it operates when a first clock signal, a second clock signal, a start pulse signal, and a reset signal are input.

[0216] The connection relationship of the shift register in FIG. 20 will be described. The shift register in FIG. 20 is the flip-flop 5701_i at the i-th stage (any one of flip-flops 5701_1 to 5701_n of ​​​​​​​Either one) is such that the first wiring 5501 shown in FIG. 21 is connected to the seventh wiring 5717_i-1, the second wiring 5502 shown in FIG. 21 is connected to the seventh wiring 5717_i+1, the third wiring 5503 shown in FIG. 21 is connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in FIG. 21 is connected to the fifth wiring 5715.

[0217] Also, the fourth wiring 5504 shown in FIG. 21 is connected to the second wiring 5712 in the odd-numbered stage flip-flops and to the third wiring 5713 in the even-numbered stage flip-flops, and the fifth wiring 5505 shown in FIG. 21 is connected to the fourth wiring 5714.

[0218] However, the first wiring 5501 shown in FIG. 21 of the first-stage flip-flop 5701_1 is connected to the first wiring 5711, and the second wiring 5502 shown in FIG. 21 of the nth-stage flip-flop 5701_n is connected to the sixth wiring 5716.

[0219] Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 may be referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 may be referred to as the first power line and the second power line, respectively.

[0220] Next, the details of the flip-flop shown in FIG. 20 are shown in FIG. 21. The flip-flop shown in FIG. 21 includes a first thin-film transistor 5571, a second thin-film transistor 5572, a third thin-film transistor 5573, a fourth thin-film transistor 5574, a fifth thin-film transistor 5575, a sixth thin-film transistor 5576, a seventh thin-film transistor 5577, and and has an eighth thin film transistor 5578. The first thin film transistor 5571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5577, and the eighth thin film transistor 5578 are n-channel type transistors, and are assumed to be in a conductive state when the voltage between the gate and the source (Vgs) exceeds the threshold voltage (Vth).

[0221] Next, the connection configuration of the flip-flop shown in FIG. 20 is shown below.

[0222] The first electrode (one of the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the fifth wiring 5504, and the second electrode (the other of the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503.

[0223] The first electrode of the second thin film transistor 5572 is connected to the fourth wiring and the sixth wiring 5506, and the second electrode of the second thin film transistor 5572 is connected to the third wiring 5503.

[0224] The first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505, and the third thin film transistor 5573's second electrode is connected to the gate electrode of the second thin film transistor 5572 and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505.

[0225] The first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506, and the fourth thin film transistor 5574's second electrode is connected to the gate electrode of the second thin film transistor 5572​​ is connected to, and the gate electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the first thin film transistor 5 571.

[0226] The first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, and the second electrode of the fifth thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501 .

[0227] The first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, and the second electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5 572.

[0228] The first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, and the second electrode of the seventh thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502 . The first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506 and the second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572, and the gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550 1.

[0229] Note that the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574 the second electrode of the fifth thin film transistor 5575, the sixth thin film transistor Set the connection point of the second electrode of 5576 and the second electrode of the seventh thin film transistor 5577 as node 5543. Furthermore, set the connection points of the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574, the gate electrode of the sixth thin film transistor 5576, and the second electrode of the eighth thin film transistor 5578 as node 5544.

[0230] Note that the first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5 504 may be respectively referred to as the first signal line, the second signal, the third signal line, and the fourth signal line. Furthermore, the fifth wiring 5505 may be referred to as the first power supply line, and the sixth wiring 5506 may be referred to as the second power supply line.

[0231] Also, it is possible to fabricate the signal line driving circuit and the scanning line driving circuit only with the n-channel type TFTs shown in any one of Embodiments 1 to 4. Since the n-channel type TFTs shown in any one of Embodiments 1 to 4 have a large mobility of the transistor, it is possible to increase the driving frequency of the driving circuit. Also, since the n-channel type TFTs shown in any one of Embodiments 1 to 4 have a reduced parasitic capacitance due to the source region or the drain region which is an oxygen-deficient oxide semiconductor layer containing indium, gallium, and zinc, they have high frequency characteristics (referred to as f characteristics). For example, a scanning line driving circuit using the n-channel type TFTs shown in any one of Embodiments 1 to 4 can operate at high speed, so it is also possible to increase the frame frequency or realize black screen insertion.

[0232] Furthermore, a higher frame frequency can be achieved by increasing the channel width of the transistors in the scanning line driving circuit or by arranging a plurality of scanning line driving circuits. When arranging a plurality of scanning line driving circuits, the scanning line driving circuit for driving the scanning lines of even rows is arranged on one side, and the scanning line driving circuit for driving the scanning lines of odd rows is arranged on the opposite side, thereby enabling the realization of a higher frame frequency.

[0233] Also, when manufacturing an active matrix light-emitting display device which is an example of the semiconductor device of the present invention, since a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of the block diagram of the active matrix light-emitting display device is shown in FIG. 16(B).

[0234] The light-emitting display device shown in FIG. 16(B) has a pixel portion 5401 having a plurality of pixels each provided with a display element on a substrate 5400, a first scanning line driving circuit 5402 and a second scanning line driving circuit 5404 for selecting each pixel, and a signal line driving circuit 5 403 for controlling the input of a video signal to the selected pixel.

[0235] When the video signal input to the pixel of the light-emitting display device shown in FIG. 16(B) is in digital format, the pixel becomes a light-emitting or non-light-emitting state by switching the on and off of the transistor. Therefore, gradation display can be performed using an area gradation method or a time gradation method. The area gradation method is a driving method for performing gradation display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based on a video signal. The time gradation method is a method in which the pixel emits light This is a driving method for performing gradation display by controlling the period.

[0236] Since the light-emitting element has a higher response speed than a liquid crystal element, etc., it is more suitable for the time gradation method than the liquid crystal element. Specifically, when performing display by the time gradation method, one frame period is divided into a plurality of sub-frame periods. Then, according to the video signal, the light-emitting element of the pixel is made to emit light or not emit light in each sub-frame period. By dividing into a plurality of sub-frame periods, the total length of the period during which the pixel actually emits light within one frame period can be controlled by the video signal, and gradation can be displayed. In the light-emitting display device shown in FIG. 16(B), when two, a switching TFT and a current control TFT, are arranged for one pixel, the signal input to the first scanning line, which is the gate wiring of the switching TFT, is generated by the first scanning line driving circuit 5402, and the signal input to the second scanning line, which is the gate wiring of the current control TFT, is generated by the second scanning line driving circuit 5404. However, the signal input to the first scanning line and the signal input to the second scanning line may both be generated by one scanning line driving circuit. Also, for example, depending on the number of transistors each switching element has, the first scanning line used to control the operation of the switching element may be provided in plurality for each pixel. In this case, the signals input to the plurality of first scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of each scanning line driving circuit. By dividing into a plurality of sub-frame periods, the total length of the period during which the pixel actually emits light within one frame period can be controlled by the video signal, and gradation can be displayed. In the light-emitting display device, among the driving circuits, it may be composed of n-channel type TFTs. It can be controlled and gradation can be displayed.

[0237] In the light-emitting display device shown in FIG. 16(B), when two, a switching TFT and a current control TFT, are arranged for one pixel, the signal input to the first scanning line, which is the gate wiring of the switching TFT, is generated by the first scanning line driving circuit 5402, and the signal input to the second scanning line, which is the gate wiring of the current control TFT, is generated by the second scanning line driving circuit 5404. However, the signal input to the first scanning line and the signal input to the second scanning line may both be generated by one scanning line driving circuit. Also, for example, depending on the number of transistors each switching element has, the first scanning line used to control the operation of the switching element may be provided in plurality for each pixel. In this case, the signals input to the plurality of first scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of each scanning line driving circuit. The signal input to the first scanning line, which is the gate wiring of the switching TFT, is generated by the first scanning line driving circuit 5402, and the signal input to the second scanning line, which is the gate wiring of the current control TFT, is generated by the second scanning line driving circuit 5404. The signal input to the second scanning line, which is the gate wiring of the current control TFT, is generated by the second scanning line driving circuit 5404. However, the signal input to the first scanning line and the signal input to the second scanning line may both be generated by one scanning line driving circuit. Also, for example, depending on the number of transistors each switching element has, the first scanning line used to control the operation of the switching element may be provided in plurality for each pixel. In this case, the signals input to the plurality of first scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of each scanning line driving circuit. However, the signal input to the first scanning line and the signal input to the second scanning line may both be generated by one scanning line driving circuit. Also, for example, depending on the number of transistors each switching element has, the first scanning line used to control the operation of the switching element may be provided in plurality for each pixel. In this case, the signals input to the plurality of first scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of each scanning line driving circuit. Also, for example, depending on the number of transistors each switching element has, the first scanning line used to control the operation of the switching element may be provided in plurality for each pixel. In this case, the signals input to the plurality of first scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of each scanning line driving circuit. The signals input to the plurality of first scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of each scanning line driving circuit. In this case, the signals input to the plurality of first scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of each scanning line driving circuit.

[0238] Also, in the light-emitting display device, among the driving circuits, it may be composed of n-channel type TFTs. A part of the drive circuit that can be formed on the same substrate as the thin-film transistor in the pixel portion. . Further, the signal line drive circuit and the scan line drive circuit can also be fabricated using only the n-channel type TFTs shown in any one of Embodiments 1 to 4.

[0239] In addition, the drive circuit described above is not limited to a liquid crystal display device or a light-emitting display device, and may also be used for an electronic paper that drives electronic ink by using an element electrically connected to a switching element. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as being as easy to read as paper, having lower power consumption compared to other display devices, and being able to have a thin and light shape.

[0240] Although various forms of electrophoretic displays can be considered, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or solute. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless).

[0241] Thus, an electrophoretic display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region. An electrophoretic display does not require a polarizing plate or a counter substrate that are necessary for a liquid crystal display device, and the thickness and weight are halved.

[0242] A dispersion of the above microcapsules in a solvent is called an electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also , color display is also possible by using color filters and particles having dyes.

[0243] Further, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, an active matrix substrate obtained by any one of the thin film transistors of Embodiment 1 to Embodiment 4 can be used. In addition, by applying an electric field to the microcapsules, display can be performed. For example, an active matrix substrate obtained by any one of the thin film transistors of Embodiment 1 to Embodiment 4 can be used. This is possible.

[0244] Note that the first particles and the second particles in the microcapsules are made of a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, a material selected from these, or a composite material of these may be used. This is possible.

[0245] By the above steps, a highly reliable display device can be manufactured as a semiconductor device.

[0246] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. This is possible.

[0247] (Embodiment 6) Here, an example of manufacturing an inverted staggered type thin film transistor in which at least a stack of a gate insulating layer and an oxygen-excess oxide semiconductor layer is continuously formed without being exposed to the atmosphere is shown below. Here, the steps up to the step of continuously forming a film are shown, and the subsequent steps are the same as those of Embodiment 1 to Embodiment 4. Here, the steps up to the step of continuously forming a film are shown, and the subsequent steps are the same as those of Embodiment 1 to Embodiment 4. The thin film transistor may be fabricated according to any one of them.

[0248] In this specification, continuous film formation means that, in a series of processes from the first film formation process performed by sputtering to the second film formation process performed by sputtering, the atmosphere where the substrate to be processed is placed does not come into contact with a contaminated atmosphere such as air, and is always controlled in a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere). By performing continuous film formation, film formation can be performed while avoiding reattachment of moisture or the like to the cleaned substrate to be processed. Performing a series of processes from the first film formation process to the second film formation process in the same chamber is considered to be within the scope of continuous film formation in this specification.

[0249] When performing a series of processes from the first film formation process to the second film formation process in different chambers, after completing the first film formation process, the substrate is transported between the chambers without coming into contact with air, and performing the second film formation is also considered to be within the scope of continuous film formation in this specification.

[0250] In addition, when performing a series of processes from the first film formation process to the second film formation process in different chambers, after completing the first film formation process, the substrate is transported between the chambers without coming into contact with air, and performing the second film formation is also considered to be within the scope of continuous film formation in this specification.

[0251] Note that even if there is a substrate transfer process, an alignment process, a slow cooling process, or a process of heating or cooling the substrate to the temperature required for the second process between the first film formation process and the second film formation process, it is considered to be within the scope of continuous film formation in this specification.

[0252] However, if a process using a liquid such as a cleaning process, wet etching, or resist formation is between the first film formation process and the second film formation process, it is not considered to be within the scope of continuous film formation as defined in this specification.

[0253] When performing continuous film formation without coming into contact with air, a multi-chamber type manufacturing apparatus as shown in Fig. 22 It is preferable to use a manufacturing apparatus.

[0254] In the central part of the manufacturing apparatus, a transfer mechanism (typically a transfer robot 81) for transferring substrates is provided. A transfer chamber 80 is provided, and a cassette chamber 82 for setting a cassette case for storing a plurality of substrates to be carried into and out of the transfer chamber is connected to the transfer chamber 80.

[0255] In addition, a plurality of processing chambers are connected to the transfer chamber via gate valves 83 to 88, respectively. Here, an example is shown in which five processing chambers are connected to a transfer chamber 80 having a hexagonal upper surface shape. Note that by changing the upper surface shape of the transfer chamber, the number of processing chambers that can be connected can be changed. For example, if it is square, three processing chambers can be connected, and if it is octagonal, seven processing chambers can be connected.

[0256] Among the five processing chambers, at least one processing chamber is a sputtering chamber for performing sputtering. The sputtering chamber is provided with at least a sputtering target, a power application mechanism for sputtering the target, a gas introduction means, a substrate holder for holding the substrate at a predetermined position, etc. inside the chamber. In addition, in order to make the inside of the sputtering chamber in a reduced pressure state, pressure control means for controlling the pressure in the chamber is provided in the sputtering chamber.

[0257] The sputtering method includes an RF sputtering method using a high-frequency power source for the sputtering power supply, a DC sputtering method, and there is also a pulsed DC sputtering method for applying a bias pulsewise. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

[0258] There is also a multi-source sputtering apparatus that can install multiple targets made of different materials. Multi-source sputtering The apparatus can deposit different material films in the same chamber in a laminated manner, or discharge multiple types of materials simultaneously in the same chamber to form a film.

[0259] In addition, there is a sputtering apparatus that uses the magnetron sputtering method with a magnet mechanism inside the chamber or an ECR sputtering apparatus that uses plasma generated using microwaves without using glow discharge. The sputtering chamber appropriately uses various sputtering methods described above.

[0260] As the sputtering chamber, various sputtering methods described above are appropriately used.

[0261] In addition, as a film formation method, there are a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to the substrate during film formation. Among the five processing chambers, one of the other processing chambers is a heating chamber that performs preheating of the substrate before sputtering, a cooling chamber that cools the substrate after sputtering, or a chamber that performs plasma processing. The sputtering chamber appropriately uses various sputtering methods described above.

[0262] Next, an example of the operation of the manufacturing apparatus will be described. A substrate cassette containing a substrate 94 with the film-forming surface facing downward is set in the cassette chamber 82, and the cassette chamber is depressurized by the vacuum evacuation means provided in the cassette chamber 82. In addition,

[0263] in advance, each processing chamber and the inside of the transfer chamber 80 are depressurized by the vacuum evacuation means provided therein.

[0264] By doing so, while the substrate is being transferred between the processing chambers, it does not come into contact with the atmosphere. The cassette chamber is evacuated by the vacuum evacuation means provided in the cassette chamber 82 to a reduced pressure state. Previously, each processing chamber and the inside of the transfer chamber 80 have been evacuated to a reduced pressure state by the vacuum evacuation means provided therein. By doing this, while the substrate is being transferred between the processing chambers, it does not come into contact with the atmosphere. It can be maintained in a clean state without any problems.

[0265] Note that the substrate 94 with the film-forming surface facing downward has at least a gate electrode provided in advance. An underlying insulating film may be provided between the gate electrode and the substrate. For example, as the underlying insulating film, although not particularly limited, a silicon nitride film, a silicon oxynitride film, etc. obtained by a sputtering method can be used. When a glass substrate containing an alkali metal is used as the substrate 94, the underlying insulating film has the effect of suppressing the intrusion of mobile ions such as sodium from the substrate into the semiconductor region above, and changing the electrical characteristics of the TFT. Here, a silicon nitride film covering the gate electrode is formed by plasma CVD method, and a substrate on which the first layer of gate insulating layer is formed is used. The silicon nitride film formed by plasma CVD method is dense, and by using it as the first layer of gate insulating layer, the generation of pinholes and the like can be suppressed. Note that here an example of a laminated gate insulating layer is shown, but it is not particularly limited, and a single layer or a laminate of three or more layers may be used.

[0266]

[0267] Next, the gate valve 83 is opened, and the first substrate 94 is taken out from the cassette by the transfer robot 81, the gate valve 84 is opened, and it is transferred into the first processing chamber 89, and the gate valve 84 is closed. In the first processing chamber 89, the substrate is heated by a heating heater or lamp heating to remove moisture and the like adhering to the substrate 94. In particular, since the electrical characteristics of the TFT may change if moisture is contained in the gate insulating layer, heating before sputter film formation is effective. Note that if moisture has been sufficiently removed at the stage of setting the substrate in the cassette chamber 82, this heat treatment is unnecessary.

[0268] ​​​​​​​​​​​​ Also, plasma processing means may be provided in the first processing chamber 89 to perform plasma processing on the surface of the gate insulating layer of the first layer. Further, heating means may be provided in the cassette chamber 82 to perform heating for removing moisture in the cassette chamber 82.

[0269] Next, the gate valve 84 is opened, and the substrate is transported to the transport chamber 80 by the transport robot 81. The gate valve 85 is opened, and the substrate is transported into the second processing chamber 90, and the gate valve 85 is closed.

[0270] Here, the second processing chamber 90 is a sputtering chamber using the RF magnetron sputtering method.

[0271] In the second processing chamber 90, a silicon nitride film (SiNx film) is formed as the gate insulating layer of the first layer.

[0272] After forming the SiNx film, without exposing it to the atmosphere, the gate valve 85 is opened, and the substrate is transported to the transport chamber 80 by the transport robot 81. The gate valve 86 is opened, and the substrate is transported into the third processing chamber 91, and the gate valve 86 is closed.

[0273] Here, the third processing chamber 91 is a sputtering chamber using the RF magnetron sputtering method.

[0274] In the third processing chamber 91, a silicon oxide film (SiOx film) is formed as the gate insulating layer of the second layer. As the gate insulating layer, in addition to the silicon oxide film, an aluminum oxide film (Al2O3 film), a magnesium oxide film (MgOx film), an aluminum nitride film (AlNx film), a yttrium oxide film (YOx film), etc. can be used.

[0275] In order to reduce hydrogen in the gate insulating layer, the gate insulating layer was grown using a single crystal Si target. The hydrogen in the gate insulating layer is deposited by sputtering using argon gas and oxygen gas. The diffusion of oxygen into the IGZO film and reaction with the excess oxygen in the film to form the H2O component results in the I-type channel. This is extremely important in preventing water from entering the interface between the gate insulating layer and the IGZO film by successive deposition. It is also important to prevent the deposition of chemicals. Therefore, the inside of the chamber is evacuated with a cryopump or the like. Exhaust and reach a minimum pressure of 1 x 10 -7 ~1×10 -10 Torr (approx. 1×10 -5 Pa Top 1×10 -8 It is preferable to perform sputtering in an ultra-high vacuum region (up to 100 Pa), i.e., in the so-called UHV region. In addition, the gate insulating layer and the IGZO film are stacked continuously to prevent the interface from being exposed to the air. When this is done, the surface of the gate insulating layer is subjected to oxygen radical treatment to make the surface an oxygen excess region. In the subsequent heat treatment to improve reliability, the oxygen in the IGZO film interface is modified. It is effective in creating a source of supply for

[0276] In addition, by providing an oxygen excess region by performing oxygen radical treatment on the gate insulating layer, The oxygen concentration on the surface of the IGZO side is higher than the oxygen concentration inside the gate insulating layer. In addition, the oxygen radical treatment was performed more efficiently than the non-treatment. The oxygen concentration at the interface between the insulating layer and the IGZO film increases.

[0277] By performing oxygen radical treatment on the gate insulating layer, laminating the IGZO film, and then performing heat treatment, the IGZO The oxygen concentration on the gate insulating layer side of the O film is also high.

[0278] Also, a small amount of a halogen element, such as fluorine or chlorine, may be added to the gate insulating layer in the film to fix mobile ions such as sodium. As a method, a gas containing a halogen element is introduced into the chamber and sputtering is performed. However, when introducing a gas containing a halogen element, it is necessary to provide a detoxification facility in the exhaust means of the chamber. The concentration of the halogen element contained in the gate insulating layer is preferably in the range of 1×10 cm or more and 1×10 cm or less as obtained by analysis using SIMS (Secondary Ion Mass Spectrometer). After forming the SiOx film, without exposing it to the atmosphere, open the gate valve 86 and transfer the substrate to the transfer chamber 80 by the transfer robot 81, open the gate valve 87 and transfer it into the fourth processing chamber 92, and close the gate valve 87. Here, the fourth processing chamber 92 is a sputtering chamber using the DC magnetron sputtering method. In the fourth processing chamber 92, oxygen radical treatment on the surface of the gate insulating layer, formation of an oxygen-excess oxide semiconductor layer (IGZO film) as the semiconductor layer, and formation of an oxygen-deficient oxide semiconductor layer as the source region and drain region are performed. As the oxygen radical treatment on the surface of the gate insulating layer, plasma treatment such as reverse sputtering may be performed. Reverse sputtering is a method of modifying the surface by forming plasma on the substrate surface by applying a voltage to the substrate side in an atmosphere of oxygen or oxygen and argon without applying a voltage to the target side. Also, the gate insulating layer may be nitrided, and reverse sputtering or the like may be performed in a nitrogen atmosphere. For the oxygen radical treatment on the surface of the gate insulating layer, plasma treatment such as reverse sputtering can be carried out. Reverse sputtering is a method of modifying the surface by forming plasma on the substrate surface by applying a voltage to the substrate side in an atmosphere of oxygen or oxygen and argon without applying a voltage to the target side. Also, the gate insulating layer may be nitrided, and reverse sputtering or the like may be carried out in a nitrogen atmosphere. cm 15 cm -3 cm 20 cm -3 or less is preferable. is preferable.

[0279] After forming the SiOx film, without exposing it to the atmosphere, open the gate valve 86 and transfer the substrate to the transfer chamber 80 by the transfer robot 81, open the gate valve 87 and transfer it into the fourth processing chamber 92, and close the gate valve 87. Here, the fourth processing chamber 92 is a sputtering chamber using the DC magnetron sputtering method. In the fourth processing chamber 92, oxygen radical treatment on the surface of the gate insulating layer, formation of an oxygen-excess oxide semiconductor layer (IGZO film) as the semiconductor layer, and formation of an oxygen-deficient oxide semiconductor layer as the source region and drain region are performed. Here, the fourth processing chamber 92 is a sputtering chamber using the DC magnetron sputtering method. In the fourth processing chamber 92, oxygen radical treatment on the surface of the gate insulating layer, formation of an oxygen-excess oxide semiconductor layer (IGZO film) as the semiconductor layer, and formation of an oxygen-deficient oxide semiconductor layer as the source region and drain region are performed.

[0280] Here, the fourth processing chamber 92 is a sputtering chamber using the DC magnetron sputtering method. In the fourth processing chamber 92, oxygen radical treatment on the surface of the gate insulating layer, formation of an oxygen-excess oxide semiconductor layer (IGZO film) as the semiconductor layer, and formation of an oxygen-deficient oxide semiconductor layer as the source region and drain region are performed. For the oxygen radical treatment on the surface of the gate insulating layer, plasma treatment such as reverse sputtering can be carried out. Reverse sputtering is a method of modifying the surface by forming plasma on the substrate surface by applying a voltage to the substrate side in an atmosphere of oxygen or oxygen and argon without applying a voltage to the target side. Also, the gate insulating layer may be nitrided, and reverse sputtering or the like may be carried out in a nitrogen atmosphere. For the oxygen radical treatment on the surface of the gate insulating layer, plasma treatment such as reverse sputtering can be carried out. Reverse sputtering is a method of modifying the surface by forming plasma on the substrate surface by applying a voltage to the substrate side in an atmosphere of oxygen or oxygen and argon without applying a voltage to the target side. Also, the gate insulating layer may be nitrided, and reverse sputtering or the like may be carried out in a nitrogen atmosphere. For the oxygen radical treatment on the surface of the gate insulating layer, plasma treatment such as reverse sputtering can be carried out. Reverse sputtering is a method of modifying the surface by forming plasma on the substrate surface by applying a voltage to the substrate side in an atmosphere of oxygen or oxygen and argon without applying a voltage to the target side. Also, the gate insulating layer may be nitrided, and reverse sputtering or the like may be carried out in a nitrogen atmosphere.

[0281] For the oxygen radical treatment on the surface of the gate insulating layer, plasma treatment such as reverse sputtering can be carried out. Reverse sputtering is a method of modifying the surface by forming plasma on the substrate surface by applying a voltage to the substrate side in an atmosphere of oxygen or oxygen and argon without applying a voltage to the target side. Also, the gate insulating layer may be nitrided, and reverse sputtering or the like may be carried out in a nitrogen atmosphere. Reverse sputtering is a method in which a voltage is applied to the substrate side in an atmosphere of oxygen or oxygen and argon without applying a voltage to the target side to form plasma on the substrate surface and modify the surface. Reverse sputtering is a method in which a voltage is applied to the substrate side in an atmosphere of oxygen or oxygen and argon without applying a voltage to the target side to form plasma on the substrate surface and modify the surface. Reverse sputtering is a method in which a voltage is applied to the substrate side in an atmosphere of oxygen or oxygen and argon without applying a voltage to the target side to form plasma on the substrate surface and modify the surface. Also, the gate insulating layer may be nitrided, and reverse sputtering or the like may be carried out in a nitrogen atmosphere. Plasma treatment may be performed.

[0282] Using an oxide semiconductor target containing In, Ga, and Zn, film formation can be carried out in a noble gas atmosphere or in an oxygen atmosphere. Here, in order to incorporate as much oxygen as possible into the IGZO film, an oxide semiconductor containing In, Ga, and Zn is used as the target, and pulsed DC sputtering is performed in an oxygen-only atmosphere or in an atmosphere where oxygen is 90% or more and Ar is 10% or less to form an oxygen-excess IGZO film.

[0283] In this way, without exposure to the atmosphere, by continuously forming an oxygen-excess SiOx film and an oxygen-excess IGZO film, the interface state between the oxygen-excess films is stabilized, and the reliability of the TFT can be improved. If the substrate is exposed to the atmosphere before the formation of the IGZO film, moisture and the like adhere, which has an adverse effect on the interface state, causing variations in the threshold value, deterioration of electrical characteristics, and symptoms such as the TFT becoming a normally-on TFT. Moisture is a hydrogen compound, and by continuously forming films without exposure to the atmosphere, the presence of hydrogen compounds at the interface can be excluded. Therefore, by continuously forming films, variations in the threshold value can be reduced, deterioration of electrical characteristics can be prevented, and the shift of the TFT to the normally-on side can be reduced or preferably eliminated.

[0284] Also, both an artificial quartz target and an oxide semiconductor target containing In, Ga, and Zn are installed in the sputtering chamber of the third processing chamber 91, and lamination can be performed in the same chamber by sequentially laminating using a shutter. is provided between the target and the substrate. When film formation is to be performed, the shutter of the target for film formation is opened, and when film formation is not to be performed, the target is closed by the shutter. The advantages of laminating within the same chamber include the reduction in the number of chambers used and the prevention of particles, etc. from adhering to the substrate during substrate transfer between different chambers. If it is not the process of using a grayscale mask, at this stage, the substrate is unloaded from the manufacturing apparatus through the cassette chamber and etched and processed for the oxygen-excess IGZO film using photolithography technology. However, if it is the process of using a grayscale mask, continuous film formation as shown below is

[0285] performed Subsequently, in the fourth processing chamber 92, sputtering by pulsed DC sputtering is performed in an atmosphere of only a rare gas to form an oxygen-deficient IGZO film in contact with the oxygen-excess IGZO film. This oxygen-deficient IGZO film has a lower oxygen concentration in the film than the oxygen-excess IGZO film. This oxygen-deficient IGZO film functions as a source region or a drain region.

[0286] Next, without being exposed to the atmosphere, the gate valve 87 is opened and the substrate is transported into the fourth processing chamber 92, and then the gate valve 87 is closed.

[0287] Next, without being exposed to the atmosphere, the gate valve 87 is opened and the substrate is transported into the transfer chamber 80 by the transfer robot 81, then the gate valve 88 is opened and the substrate is transported into the fifth processing chamber 93, and then the gate valve 88 is closed.

[0288]

[0289] Here, the fifth processing chamber 93 is a sputtering chamber using DC magnetron sputtering ​​​​​​​​- is performed. In the fifth processing chamber 93, a metal multilayer film that will become a source electrode layer or a drain electrode layer (conductive film) is formed. In the sputtering chamber of the fifth processing chamber 93, both a titanium target and an aluminum target are installed, and they are sequentially laminated using a shutter to perform continuous film formation within the same chamber. Here, an aluminum film is laminated on the titanium film, and furthermore, a titanium film is laminated on the aluminum film.

[0290] Thus, when using a grayscale mask, without being exposed to the atmosphere, an oxygen-excessive Si Ox film, an oxygen-excessive IGZO film, an oxygen-deficient IGZO film, and a metal multilayer film can be continuously formed in this way. In particular, the interface state of the oxygen-excessive IGZO film becomes more stable, improving the reliability of the TFT can be improved. If the substrate is exposed to the atmosphere before and after the formation of the IGZO film, moisture, etc. adheres, adversely affecting the interface state, causing variations in the threshold value, deterioration of electrical characteristics, and symptoms such as the TFT becoming a normally-on type. Moisture is a hydrogen compound, and by continuously forming the film without being exposed to the atmosphere, the presence of hydrogen compounds at the interface of the IGZO film can be excluded. Therefore, by continuously forming four layers, variations in the threshold value can be reduced, deterioration of electrical characteristics can be prevented, and the shift of the TFT to the normally-on side can be reduced, preferably eliminated.

[0291] Also, by continuously forming the film of the oxygen-deficient IGZO film and the metal multilayer film that will become the source electrode layer and the drain electrode layer without being exposed to the atmosphere, a good interface state can be realized between the oxygen-deficient IGZO film and the metal multilayer film, and the contact resistance can be reduced.

[0292] In addition, both an artificial quartz target and an oxide semiconductor target containing In, Ga, and Zn are installed in the sputtering chamber of the third processing chamber 91, and are sequentially introduced using a shutter to switch the gases to be introduced and perform continuous film formation of three layers to perform lamination within the same chamber This is also possible. The advantages of laminating within the same chamber include reducing the number of chambers to be used and preventing particles and the like from adhering to the substrate while transporting the substrate between different chambers This is a point that can be achieved.

[0293] The above steps are repeated to perform a film formation process on the substrates in the cassette case to complete the processing of a plurality of substrates After that, the vacuum in the cassette chamber is released to the atmosphere, and the substrates and the cassette are taken out.

[0294] Also, in the first processing chamber 89, heat treatment after film formation of an oxygen-excess IGZO film and an oxygen-deficient IGZO film, specifically, heat treatment at 200°C to 600°C, preferably 300°C to 500°C can be performed. By performing this heat treatment, the electrical characteristics of the reverse staggered thin film transistor can be improved. This heat treatment is not particularly limited as long as it is after film formation of the oxygen-excess IGZO film and the oxygen-deficient IGZO film. For example, it can be performed immediately after film formation of the oxygen-excess IGZO film and the oxygen-deficient IGZO film, or immediately after metal multilayer film formation.

[0295] Next, each laminated film is etched using a graytone mask. It may be formed using dry etching or wet etching, or may be selectively etched separately in multiple etching steps.

[0296] The semiconductor layer, source region, drain region, source electrode layer, and drain electrode layer are etched After the formation of the insulating film, vacuum baking may be performed before forming the protective film.

[0297] In addition, the semiconductor layer, the source region, the drain region, the source electrode layer, and the drain electrode layer are etched. After the formation of the protective film by the exposure process, oxygen radical treatment may be performed before the formation of the protective film. By performing oxygen radical treatment on the channel formation region of the semiconductor layer, The layer surface can be the oxygen excess region.

[0298] By making the surface of the semiconductor layer an oxygen-excess region, hydrogen is prevented from being mixed into the semiconductor layer. The back channel becomes an oxygen-deficient region, preventing conduction between the source and drain, and thus reducing the off-state current. In this way, the semiconductor layer in the back channel portion is also made into an oxygen excess region. Therefore, the back channel semiconductor can be treated with oxygen radicals in the same way as the gate insulating layer. It is effective to subject the conductor layer to oxygen radical treatment.

[0299] The subsequent steps are the same as those of the first to fourth embodiments described above. This makes it possible to fabricate thin film transistors of this type.

[0300] Here, we have taken the example of a multi-chamber manufacturing device, but if the sputtering chamber is Using in-line manufacturing equipment connected in series, continuous film formation is performed without exposure to the atmosphere. This is also fine.

[0301] The apparatus shown in FIG. 22 is a so-called face-down type in which the substrate is set with the surface on which the film is to be formed facing downward. However, the substrate may be placed vertically in the processing chamber. The advantage of this treatment chamber is that it has a smaller footprint than a face-down treatment chamber. Furthermore, this is effective when using a large-area substrate that may bend due to its own weight.

[0302] (Embodiment 7) The thin film transistor of the present invention is manufactured, and the thin film transistor is installed in a pixel portion and further in a driving circuit. A semiconductor device having a display function (also called a display device) can be manufactured using the above-mentioned organic EL display device. The thin film transistor of the present invention is integrated with a part or the whole of a driver circuit on the same substrate as a pixel portion. A system on panel can be formed.

[0303] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0304] The display device includes a panel in which a display element is sealed, and a controller for the panel. The display device according to the present invention further includes a module in which an IC or the like including the display device is mounted. In the manufacturing process, a display element substrate corresponds to a form before the display element is completed. The child substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, only the pixel electrodes of the display element may be formed, or the pixel electrodes may be formed. Even if the conductive film is formed after etching and before forming the pixel electrode, Good, and all forms apply.

[0305] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0306] In this embodiment, a liquid crystal display device is shown as an example of a semiconductor device according to one embodiment of the present invention.

[0307] 23(A) and (B) show an active matrix type liquid crystal display device to which the present invention is applied. FIG. 23A is a plan view of a liquid crystal display device, and FIG. 23B is a diagram showing the line in FIG. 1 is a cross-sectional view of a thin film transistor 201 used in the semiconductor device. The thin film transistor shown in FIG. 2 can be fabricated in the same manner as in FIG. 1, and the gate insulating film is treated with oxygen radicals. A highly reliable thin film transistor including an oxygen-rich oxide semiconductor layer and an oxygen-deficient oxide semiconductor layer on an insulating layer. Also, the thin film transistor shown in the first, third or fourth embodiment A transistor can also be applied as the thin film transistor 201 of this embodiment.

[0308] The liquid crystal display device of this embodiment shown in FIG. 23(A) includes a source wiring layer 202 and a multi-gate structure. The thin film transistor 201 includes a reverse staggered type, a gate wiring layer 203, and a capacitance wiring layer 204. .

[0309] In addition, in FIG. 23(B), the liquid crystal display device of the present embodiment includes a thin film of a multi-gate structure transistor 201, insulating layer 211, insulating layer 212, insulating layer 213, and an electrode layer 255 used for a display element, an insulating layer 261 that functions as an alignment film, and a substrate 2 00 provided with a polarizing plate 268, and an insulating layer 263 that functions as an alignment film, an electrode layer 265 used for a display element, a coloring layer 264 that functions as a color filter, and a substrate 266 provided with a polarizing plate 267 are opposed to each other with a liquid crystal layer 2 62 interposed therebetween, and have a liquid crystal display element 260.

[0310] In addition, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 262 in order to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time of 10 μs to 1 00 μs, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependence.

[0311] Although FIG. 23 is an example of a transmissive liquid crystal display device, one embodiment of the present invention can be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

[0312] In the liquid crystal display device of FIG. 23, a polarizing plate 267 is provided on the outside (viewing side) of the substrate 266, and an example is shown in which a coloring layer 264 and an electrode layer 265 used for a display element are provided in this order on the inside, but the polarizing plate 267 may be provided on the inside of the substrate 266. Also, the laminated structure of the polarizing plate and the coloring layer is also shown in FIG. 23 ​​​​​It is not limited thereto, and it may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the coloring layer. Also, a light-shielding film that functions as a black matrix may be provided.

[0313] In addition, in this embodiment, in order to reduce the surface unevenness of the thin film transistor and improve the reliability of the thin film transistor, the thin film transistor obtained in Embodiment 1 is covered with an insulating layer (insulating layer 211, insulating layer 212, insulating layer 213) that functions as a protective film or a planarization insulating film. Note that the protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the air, and a dense film is preferable. The protective film may be formed by a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film using a sputtering method. In this embodiment, an example of forming the protective film by a sputtering method is shown, but it is not particularly limited and may be formed by various methods. It has a structure of being covered with an insulating layer (insulating layer 211, insulating layer 212, insulating layer 213) that functions as a protective film or a planarization insulating film. Note that the protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the air, and a dense film is preferable. The protective film may be formed by a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film using a sputtering method. In this embodiment, an example of forming the protective film by a sputtering method is shown, but it is not particularly limited and may be formed by various methods. using a sputtering method, a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film, or a laminate thereof. In this embodiment, an example of forming the protective film by a sputtering method is shown, but it is not particularly limited and may be formed by various methods. In this embodiment, an example of forming the protective film by a sputtering method is shown, but it is not particularly limited and may be formed by various methods. The insulating layer 211 is formed as the first layer of the protective film. The insulating layer 211 is effective in preventing hillocks of the aluminum film. Here, a silicon oxide film is formed as the insulating layer 211 using a sputtering method.

[0314] The insulating layer 211 is formed as the first layer of the protective film. The insulating layer 211 is effective in preventing hillocks of the aluminum film. Here, a silicon oxide film is formed as the insulating layer 211 using a sputtering method. The insulating layer 211 is formed as the first layer of the protective film. The insulating layer 211 is effective in preventing hillocks of the aluminum film. Here, a silicon oxide film is formed as the insulating layer 211 using a sputtering method. The insulating layer 211 is formed as the first layer of the protective film. The insulating layer 211 is effective in preventing hillocks of the aluminum film. Here, a silicon oxide film is formed as the insulating layer 211 using a sputtering method.

[0315] Also, the insulating layer 212 is formed as the second layer of the protective film. Here, a silicon nitride film is formed as the insulating layer 212 using a sputtering method. When a silicon nitride film is used as the first layer of the protective film, it is possible to suppress the entry of mobile ions such as sodium into the semiconductor region and the change of the electrical characteristics of the TFT. Also, the insulating layer 212 is formed as the second layer of the protective film. Here, a silicon nitride film is formed as the insulating layer 212 using a sputtering method. When a silicon nitride film is used as the first layer of the protective film, it is possible to suppress the entry of mobile ions such as sodium into the semiconductor region and the change of the electrical characteristics of the TFT. Also, the insulating layer 212 is formed as the second layer of the protective film. Here, a silicon nitride film is formed as the insulating layer 212 using a sputtering method. When a silicon nitride film is used as the first layer of the protective film, it is possible to suppress the entry of mobile ions such as sodium into the semiconductor region and the change of the electrical characteristics of the TFT. the entry of mobile ions such as sodium into the semiconductor region and the change of the electrical characteristics of the TFT.

[0316] After forming the protective film, the IGZO semiconductor layer is annealed (300°C to 400°C). It is also possible.

[0317] In addition, an insulating layer 213 is formed as a planarizing insulating film. The insulating layer 213 is made of acrylic, Heat-resistant organic materials such as polyimide, benzocyclobutene, polyamide, and epoxy In addition to the above organic materials, low-k materials, silicon materials, etc. can be used. Use oxysilane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. Siloxane resins can have hydrogen, fluorine, alkyl groups, or aryl groups as substituents. The insulating film formed of these materials may have at least one of the following groups: The insulating layer 213 may be formed by stacking a plurality of layers.

[0318] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. Siloxane-based resins contain hydrogen, fluorine, alkyl, and aryl groups as substituents. The alkyl group may have at least one of a cyclic group, a cyclic group, or an aromatic hydrocarbon.

[0319] The method for forming the insulating layer 213 is not particularly limited, and may be a sputtering method, a SOG method, or the like, depending on the material. Spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 213 is formed using a material liquid, a baking In the process of forming the IGZO semiconductor layer, annealing (at 300° C. to 400° C.) may be performed at the same time. The annealing process for the IGZO semiconductor layer is also performed during the baking process for the insulating layer 213, so that the semiconductor It becomes possible to fabricate the device.

[0320] The electrode layers 255 and 265 that function as pixel electrode layers are indium containing tungsten oxide oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO .), indium zinc oxide, indium tin oxide added with silicon oxide, and other conductive materials having translucency can be used.

[0321] Further, as the electrode layers 255 and 265, a conductive composition containing a conductive polymer (also referred to as a conductive polymer) can be used for formation. The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. Further, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less.

[0322] As the conductive polymer, so-called π-electron conjugated system conductive polymers can be used. For example polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned.

[0323] Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device .

[0324] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments .

[0325] (Embodiment 8) In this embodiment, an example of an electronic paper is shown as the semiconductor device of the present invention.​​​​

[0326] Figure 30 shows an active matrix type electronic paper as an example of a semiconductor device to which the present invention is applied. As the thin film transistor 581 used in the semiconductor device, it can be manufactured in the same manner as the thin film transistor shown in Embodiment 2, and an oxygen excess oxide semiconductor layer is formed on a gate insulating layer that has been subjected to oxygen radical treatment, and an oxygen deficient oxide semiconductor layer is used as the source region and the drain region, and it is a highly reliable thin film transistor. Also, the thin film transistors shown in Embodiment 1, Embodiment 3, or Embodiment 4 can also be applied as the thin film transistor 581 of the present embodiment.

[0327] The electronic paper in Figure 30 is an example of a display device using the twist ball display method. The twist ball display method is a method of performing display by arranging spherical particles painted white and black between a first electrode layer and a second electrode layer that are used as display elements and are electrode layers, and generating a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

[0328] The thin film transistor 581 is a reverse staggered type thin film transistor with a multi-gate structure, and is in electrical contact with the first electrode layer 587 through a source electrode layer or a drain electrode layer and is in contact with an opening formed in the insulating layer 585. There are a black region 590a and a white region 590b between the first electrode layer 587 and the second electrode layer 588, and spherical particles 589 including a cavity 594 filled with a liquid are provided around them, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin (see Figure 30).

[0329] In addition, it is also possible to use an electrophoretic element instead of the twist ball. A transparent liquid is filled with positively charged white fine particles and negatively charged black fine particles, and microcapsules with a diameter of about 10 μm to 20 0 μm are used. The microcapsules provided between the first electrode layer and the second electrode layer will cause the white fine particles and the black fine particles to move in opposite directions when an electric field is applied by the first electrode layer and the second electrode layer, and can display white or black. The display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than the liquid crystal display element, an auxiliary light is not required, and the power consumption is small, and the display portion can be recognized even in a dim place. Also when the power is not supplied to the display portion, it is possible to hold the image once displayed, so that even when the semiconductor device with a display function (also simply called a display device or a semiconductor device including the display device) is kept away from the radio wave transmission source, the displayed image can be saved. By the above steps, a highly reliable electronic paper can be manufactured as a semiconductor device.

[0330]

[0331] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0332] (Embodiment 9) In this embodiment, an example of a light-emitting display device is shown as the semiconductor device of the present invention. As the display element of the display device, here, a light-emitting element using electroluminescence is used for illustration. The light-emitting element using electroluminescence has an organic compound as the light-emitting material, or They are distinguished according to whether they are inorganic compounds. Generally, the former is an organic EL element and the latter is an inorganic EL element.

[0333] In an organic EL element, when a voltage is applied to the light-emitting element, electrons and holes are respectively injected into a layer containing a light-emitting organic compound, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0334] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element configurations. A dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder and its light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. A thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and its light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL element is used for explanation as the light-emitting element.

[0335] Figs. 26(A) and (B) show an active matrix type light-emitting display device as an example of a semiconductor device to which the present invention is applied. Fig. 26(A) is a plan view of the light-emitting display device, and Fig. 26(B) is a cross-sectional view taken along line Y-Z in Fig. 26(A). Note that Fig. 27 shows an equivalent circuit of the light-emitting display device shown in Fig. 26.

[0336] As the thin-film transistors 301 and 302 used in the semiconductor device, those in Embodiment 1 and Embodiment It can be fabricated in the same manner as the thin-film transistor shown in Embodiment 2, and the gate is subjected to oxygen radical treatment. An oxygen-excessive oxide semiconductor layer is formed on an insulating layer, and oxygen-deficient oxide semiconductor layers are used as source and drain regions. It is a highly reliable thin-film transistor. Also, the thin-film transistors shown in Embodiment 3 or Embodiment 4 can also be applied as the thin-film transistors 301 and 302 of this embodiment.

[0337] The light-emitting display device of this embodiment shown in FIGS. 26(A) and 26(B) includes thin-film transistors 301 having a multi-gate structure, light-emitting elements 303, capacitive elements 304, a source wiring layer 305, a gate wiring layer 306, and a power supply line 307. The thin-film transistors 301 and 302 are n-channel type thin-film transistors.

[0338] Also, in FIG. 26(B), the light-emitting display device of this embodiment includes a thin-film transistor 302, an insulating layer 311, an insulating layer 312, an insulating layer 313, a partition 321, and a first electrode layer 320, an electroluminescent layer 322, and a second electrode layer 323 used for the light-emitting element 303.

[0339] The insulating layer 313 is preferably formed using an organic resin such as acrylic, polyimide, or polyamide, or siloxane.

[0340] In this embodiment, since the thin-film transistor 302 of the pixel is of the n-type, it is desirable to use a cathode as the first electrode layer 320 which is the pixel electrode layer. Specifically, as the cathode, a material with a small work function, for example, Ca, Al, MgAg, AlLi, etc. can be used.

[0341] The partition 321 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. Particularly ​​​​​A photosensitive material is used to form an opening on the first electrode layer 320, and the sidewall of the opening is continuous. It is preferable to form the inclined surface so as to have a continuous curvature.

[0342] The electroluminescent layer 322 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it's

[0343] A second electrode layer 323 using an anode is formed so as to cover the electroluminescent layer 322. The electrode layer 323 is made of a conductive material having light transmission properties as listed in the seventh embodiment for the pixel electrode layer. In addition to the above-mentioned transparent conductive film, a titanium nitride film or A titanium film may be used for the first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 32 3 are overlapped to form the light emitting element 303. The second electrode layer 323 and the partition wall 32 are provided to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the A protective film may be formed on the substrate 1. Examples of the protective film include a silicon nitride film, a silicon oxynitride film, and a DLC film. A film or the like can be formed.

[0344] Furthermore, in practice, once the process is completed up to Figure 26(B), the structure is made airtight to prevent it from being exposed to the outside air. Protective films with high heat resistance and low degassing (laminated films, UV curable resin films, etc.) It is preferable to package (enclose) the container in a container-type container or a cover material.

[0345] Next, the configuration of the light-emitting element will be described with reference to FIG. 28. Here, the driving TFT is The cross-sectional structure of a pixel will be described using the example of the type shown in Figures 28(A), (B), and (C). The driving TFTs used in the semiconductor device, TFTs 7001, 7011, and 7021, are It can be fabricated in the same manner as the thin film transistor shown in Embodiment 1, and has a gate that has been subjected to oxygen radical treatment. An oxygen-rich oxide semiconductor layer is formed on an insulating layer, and oxygen-deficient oxide semiconductor layers are used as source and drain regions, resulting in a highly reliable thin film transistor. Further, the thin film transistors shown in Embodiment 2, Embodiment 3, or Embodiment 4 can also be applied as TFT7001, 7011, 70 21.

[0346] For the light emitting element, at least one of the anode or the cathode needs to be transparent in order to extract light. Thus, a top emission structure that forms a thin film transistor and a light emitting element on a substrate and extracts light from the surface opposite to the substrate, a bottom emission structure that extracts light from the surface on the substrate side, or a double-sided emission structure that extracts light from both the substrate side and the surface opposite to the substrate are available. The pixel configuration of one embodiment of the present invention can be applied to light emitting elements with any of these emission structures. The top emission structure of the light emitting element will be described with reference to Fig. 28(A). Fig. 28(A) shows a cross-sectional view of a pixel when the driving TFT, TFT7001, is of the n-type and light emitted from the light emitting element 7002 escapes toward the anode 7005 side. In Fig. 28(A), the cathode 7003 of the light emitting element 7002 is electrically connected to the driving TFT, TFT7001, and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it has a low work function and reflects light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And

[0347] The light emitting layer 7004 can be composed of a single layer or can be configured such that multiple layers are stacked.

[0348] Fig. 28(A) shows a cross-sectional view of a pixel when the driving TFT, TFT7001, is of the n-type and light emitted from the light emitting element 7002 escapes toward the anode 7005 side. In Fig. 28(A), the cathode 7003 of the light emitting element 7002 is electrically connected to the driving TFT, TFT7001, and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it has a low work function and reflects light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light emitting layer 7004 can be composed of a single layer or can be configured such that multiple layers are stacked. The light emitting layer 7004 can be composed of a single layer or can be configured such that multiple layers are stacked. It doesn't matter which one. When it is composed of multiple layers, an electron injection layer is formed on the cathode 7003 , an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties that transmit light , and for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide , indium oxide containing titanium oxide, indium tin oxide containing titanium oxide , indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide , etc., a light-transmitting conductive film may be used.

[0349] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in Fig. 28(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 as indicated by the arrow .

[0350] Next, the light-emitting element with a bottom emission structure will be described with reference to Fig. 28(B). When the driving TFT7 011 is of the n-type and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side , a cross-sectional view of the pixel is shown. In Fig. 28(B), the cathode 7013 of the light-emitting element 7012 is formed on the light-transmitting conductive film 7017 electrically connected to the driving TFT7011 , and a light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. Note that when the anode 7 015 has light-transmitting properties, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode . The cathode 7013 can be made of various materials as long as it is a conductive material with a small work function, similar to the case of Fig. 28(A). However, its film thickness is 、Set it to a degree of light transmission (preferably about 5 nm to 30 nm). For example, a film with a thickness of 20 nm An aluminum film having a thickness can be used as the cathode 7013. And the light-emitting layer 7 014 may be composed of a single layer or a plurality of layers may be stacked, similar to Fig. 28(A). The anode 7015 does not need to transmit light, but can be formed using a conductive material having light transmittance, similar to Fig. 28(A). And The shielding film 7016 can use, for example, a metal that reflects light, etc., but is not limited to a metal film. For example, a resin added with a black pigment can also be used.

[0351] The region sandwiching the light-emitting layer 7014 between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 7012. In the case of the pixel shown in Fig. 28(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow.

[0352] Next, the light-emitting element with a double-sided emission structure will be described with reference to Fig. 28(C). In Fig. 28(C) On a light-transmissive conductive film 7027 electrically connected to the driving TFT 7021, The cathode 7023 of the light-emitting element 7022 is formed, and the light-emitting layer 7024 and The anode 7025 are sequentially stacked on the cathode 7023. The cathode 7023 can use various materials as long as they are conductive materials with a small work function, similar to the case of Fig. 28(A). However, the film thickness Is set to a degree of light transmission. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 may be composed of a single layer or a plurality of layers may be stacked, similar to Fig. 28(A). The anode 70 25 can be formed using a conductive material having translucency that transmits light, similar to FIG. 28(A). This can be done.

[0353] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 70 22. In the case of the pixel shown in FIG. 28(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0354] Here, although an organic EL element has been described as the light-emitting element, it is also possible to provide an inorganic EL element as the light-emitting element.

[0355] In this embodiment, an example in which a thin-film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically connected has been shown, but a configuration in which a current control TFT is connected between the driving TFT and the light-emitting element may also be used.

[0356] Note that the semiconductor device shown in this embodiment is not limited to the configuration shown in FIG. 28, and various modifications based on the technical idea of the present invention are possible.

[0357] By the above steps, a highly reliable light-emitting display device can be manufactured as a semiconductor device .

[0358] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments .

[0359] (Embodiment 10) Next, the configuration of a display panel, which is one form of the semiconductor device of the present invention, is shown below. In this embodiment a liquid crystal display panel, which is one form of a liquid crystal display device having a liquid crystal element as a display element A panel (also referred to as a liquid crystal panel), which is a form of a semiconductor device having a light-emitting element as a display element will be described. This is a light-emitting display panel (also referred to as a light-emitting panel).

[0360] Next, the appearance and cross-section of a light-emitting display panel corresponding to one form of the semiconductor device of the present invention will be described with reference to FIG. 29. FIG. 29 is a top view of a panel in which a highly reliable thin-film transistor and a light-emitting element including an oxygen-excess oxide semiconductor layer and oxygen-deficient oxide semiconductor layers as source and drain regions are formed on a gate insulating layer subjected to oxygen radical treatment on a first substrate, and FIG. 29(B) corresponds to a cross-sectional view taken along H-I of FIG. 29(A). On the first substrate 4501, there are provided a pixel portion 4502, signal line driver circuits 4503a, 450 3b, and scanning line driver circuits 4504a, 4504b, and a sealing material 4505 is provided so as to surround them. Further, a second substrate 4506 is provided on the pixel portion 4502, signal line driver circuits 4503a, 4503b, and scanning line driver circuits 45 04a, 4504b. Therefore, the pixel portion 4502, signal line driver circuits 4503a, 4503b, and scanning line driver circuits 45 04a, 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506.

[0361] On the first substrate 4501, there are provided a pixel portion 4502, signal line driver circuits 4503a, 4 503b, and scanning line driver circuits 4504a, 4504b, which have a plurality of thin-film transistors. In FIG. 29(B), the thin-film transistor 4510 included in the pixel portion 4502 and the letter are shown. Also, the pixel portion 4502, signal line driver circuits 4503a, 4503b, and scanning line driver circuits 4504a, 4504b have a plurality of thin-film transistors. In FIG. 29(B), the thin-film transistor 4510 included in the pixel portion 4502 and the letter are shown. Thus, the pixel portion 4502, signal line driver circuits 4503a, 4503b, and scanning line driver circuits 45 04a, 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506.

[0362] Also, the pixel portion 4502, signal line driver circuits 4503a, 4 503b, and scanning line driver circuits 4504a, 4504b provided on the first substrate 4501 have a plurality of thin-film transistors. In FIG. 29(B), the thin-film transistor 4510 included in the pixel portion 4502 and the letter are shown. In FIG. 29(B), the thin-film transistor 4510 included in the pixel portion 4502 and the letter illustrates the thin film transistor 4509 included in the gate line driving circuit 4503a.

[0363] The thin film transistors 4509 and 4510 are equivalent to highly reliable thin film transistors including an oxygen radical-treated gate insulating layer, an oxygen-excess oxide semiconductor layer, and oxygen-deficient oxide semiconductor layers as source and drain regions, and the thin film transistors shown in Embodiment 1, Embodiment 2, Embodiment 3, or Embodiment 4 can be applied. In this embodiment, the thin film transistors 4509 and 4510 are n-channel type thin film transistors.

[0364] Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is a pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the configuration of the light-emitting element 4511 is not limited to the configuration shown in this embodiment. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like.

[0365] Also, various signals and potentials supplied to the signal line driving circuits 4503a and 4503b, the scanning line driving circuits 4504a and 4504b, or the pixel portion 4502 are supplied from the FPCs 4518a and 4518b.

[0366] In this embodiment, the connection terminal 4515 is formed of the same conductive film as the second electrode layer 4512, and the wiring 4516 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511.

[0367] The connection terminal 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected.

[0368] The second substrate located in the light extraction direction from the light-emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used. In addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used as the filling material 4507, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filling material.

[0369]

[0370] If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface irregularities and reduces reflection can be performed.

[0371] The signal line driving circuits 4503a and 4503b and the scanning line driving circuits 4504a and 4504b may be mounted on a driving circuit formed of a single-crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line driving circuit, or a part thereof, or only the scanning line driving circuit, or a part thereof may be separately formed and mounted, and this embodiment is not limited to the configuration of FIG. 29.

[0372] ​​​​​​​​​​​​​Next, the appearance and cross-section of a liquid crystal display panel corresponding to one form of the semiconductor device of the present invention will be described with reference to FIG. 24. FIG. 24 shows an oxygen radical treatment performed on a gate insulating layer formed on a first substrate 4001, an oxygen-excess oxide semiconductor layer, and a source region and a drain region including an oxygen-deficient oxide semiconductor layer, highly reliable thin-film transistors 4010 and 4011, and a liquid crystal element 4013, sealed with a sealing material 4005 between the second substrate 4006. FIG. 24(A) is a top view of the panel, and FIG. 24(B) corresponds to a cross-sectional view taken along M-N in FIGS. 24(A1) and (A2). A sealing material 4005 is provided so as to surround a pixel portion 4002 and a scanning line driving circuit 4004 provided on the first substrate 4001. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0373] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 24(A1) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 24(A2) is an example in which the signal line driving circuit 4003 is mounted by the TAB method.

[0374]

[0375] ​​​​​​​Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 have a plurality of thin film transistors. In FIG. 24(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated.

[0376] The thin film transistors 4010 and 4011 are equivalent to highly reliable thin film transistors including an oxygen-rich oxide semiconductor layer on a gate insulating layer subjected to oxygen radical treatment, and an oxygen-deficient oxide semiconductor layer as a source region and a drain region. The thin film transistors shown in Embodiment 1, Embodiment 2, Embodiment 3, or Embodiment 4 can be applied. In this embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors.

[0377] Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are provided with insulating layers 4032 and 4033 that function as alignment films, respectively, and sandwich the liquid crystal layer 4008 via the insulating layers 4032 and 4033.

[0378] Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, PV ​ F (polyvinyl fluoride) film, polyester film, polyester film or an acrylic resin film can be used. Also, an aluminum foil sandwiched between a PVF film or a polyester film can also be used as the sheet having such a structure.

[0379] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used.

[0380] Also, various signals and potentials applied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4 002 are supplied from the FPC 4018.

[0381] In the present embodiment, the connection terminal 4015 is formed of the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013, and the wiring 4016 is formed of the same conductive film as the gate electrode layer of the thin film transistors 4010 and 4011.

[0382] The connection terminal 4015 is electrically connected to the terminal included in the FPC 4018 via the anisotropic conductive film 4019.

[0383] Also, in FIG. 24, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0384] ​​​FIG. 25 shows an example of a liquid crystal display module configured as a semiconductor device using a TFT substrate 2600 manufactured by applying the present invention.

[0385] FIG. 25 is an example of a liquid crystal display module, in which a TFT substrate 2600 and a counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, a coloring layer 2605, and a polarizing plate 2606 are provided therebetween to form a display region. The coloring layer 2605 is necessary when performing color display. In the case of the RGB method, coloring layers corresponding to each of the colors red, green, and blue are provided corresponding to each pixel. Polarizing plates 2606 and 2607 and a diffusion plate 2613 are disposed outside the TFT substrate 2600 and the counter substrate 2601. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible wiring board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Further, it may be laminated in a state having a retardation plate between the polarizing plate and the liquid crystal layer.

[0386] Liquid crystal display modules include TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Bire fringence mode, FLC (Ferroelectric Liquid C rystal) mode, AFLC (AntiFerroelectric Liquid Crystal) can be used.

[0387] Through the above steps, a highly reliable display panel can be manufactured as a semiconductor device.

[0388] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0389] (Embodiment 11) The semiconductor device of the present invention can be used as electronic paper. It can be used in any electronic device that displays information. For example, Electronic paper is used for electronic books, posters, and advertisements inside trains and other vehicles. The present invention can be applied to advertisements, displays on various cards such as credit cards, etc. An example is shown in FIG. 31 and FIG.

[0390] FIG. 31(A) shows a poster 2631 made of electronic paper. In the case of printed matter, the advertisements are exchanged manually, but in the case of electronic matter to which the present invention is applied, By using paper, you can change the display of your advertisement in a short time. Also, the display will not collapse. The poster can also be configured to transmit and receive information wirelessly. good.

[0391] FIG. 31(B) shows an advertisement 2632 on a train or other vehicle. In the case of paper printouts, the advertisements are exchanged manually, but in the case of electronic Using sub-papers, the display of advertisements can be changed in a short time without much manual effort. Moreover, stable images can be obtained without the display being disrupted. Note that the poster may be configured to wirelessly transmit and receive information.

[0392] Also, FIG. 32 shows an example of an e-book 2700. For example, the e-book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can be opened and closed about the shaft portion 2711 as an axis. With such a configuration, it is possible to perform operations similar to those of a paper book.

[0393] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen, or may be configured to display different screens. With a configuration of displaying different screens, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 32), and an image can be displayed on the left display unit (display unit 2707 in FIG. 32).

[0394] Also, in FIG. 32, an example in which the housing 2701 is provided with an operation unit and the like is shown. For example, in the housing 2701, a power supply 2721, operation keys 2723, a speaker 2725, and the like are provided. The page can be advanced by the operation keys 2723. Note that the configuration may be such that a key board, a pointing device, or the like is provided on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion portion, and the like may be provided. ​​​​​​​​​​​ It may be configured as such. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. It may be.

[0395] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is possible to purchase and download desired book data and the like from an electronic book server. It is also possible.

[0396] (Embodiment 12) The semiconductor device according to the present invention can be applied to various electronic devices (including gaming machines). Examples of electronic devices include, for example, television devices (also referred to as TVs or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, and large gaming machines such as pachinko machines.

[0397] FIG. 33(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display an image. Also, here, a configuration in which the housing 9601 is supported by a stand 9605 is shown.

[0398] The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control operation unit 9610. By operation keys 9609 provided in the remote control operation unit 9610, channel and volume operations can be performed, and the image displayed on the display unit 9603 can be operated. Also, on the remote control operation unit 9610, for the remote control operation unit 9610, operations such as channel and volume can be performed, and the image displayed on the display unit 9603 can be operated. Also, on the remote control operation unit 9610, for the remote control operation unit 9610, operations such as channel and volume can be performed, and the image displayed on the display unit 9603 can be operated. Also, on the remote control operation unit 9610, for the remote control operation unit It may be configured to include a display unit 9607 that displays information output from 9610.

[0399] Note that the television device 9600 is configured to include a receiver, a modem, etc. The receiver can receive more general television broadcasts, and can also be connected to a communication network via a modem for priority or wireless to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0400] FIG. 33(B) shows an example of a digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and for example, by displaying image data taken with a digital camera or the like, it can function in the same way as a normal photo stand.

[0401] Note that the digital photo frame 9700 is configured to include an operation unit, external connection terminals (terminals connectable to various cables such as USB terminals, USB cables), a recording medium insertion unit, etc. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface to improve the design. For example, an image memory in which image data taken with a digital camera is stored can be inserted into the recording medium insertion unit of the digital photo frame to import the image data and the imported image data can be displayed on the display unit 9703.

[0402] Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It can also be configured to import and display desired image data wirelessly.

[0403] FIG. 34(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 34(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and at least the present invention is It is sufficient that the device is provided with the semiconductor device, and other auxiliary equipment is provided as appropriate. The portable game machine shown in FIG. 34(A) can be used to play a game using a program recorded on a recording medium. It has the function of reading the program or data and displaying it on the display unit, and wirelessly communicating with other portable gaming machines. The portable gaming machine shown in FIG. 34(A) has the following functions: The function is not limited to this and may have various functions.

[0404] FIG. 34(B) shows an example of a slot machine 9900, which is a large-scale gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. The Machine 9900 also includes other operating means such as a start lever and stop switch, coin The slot machine 9900 is equipped with a slot slot, a speaker, etc. It is not limited to such things, and it may be any configuration including at least the semiconductor device according to the present invention. Other attached equipment can be appropriately provided.

[0405] FIG. 35 shows an example of a mobile phone 1000. The mobile phone 1000 includes, in addition to a display unit 1002 incorporated in a housing 100 1, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like.

[0406] In the mobile phone 1000 shown in FIG. 35, information can be input by touching the display unit 1002 with a finger or the like. Also, operations such as making a phone call or sending an email can be performed by touching the display unit 100

[0407] The screen of the display unit 1002 mainly has three modes. The first is a display mode mainly for displaying images, the second is an input mode mainly for inputting information such as characters. The third is a display + input mode in which the two modes of the display mode and the input mode are mixed. For example, when making a phone call or creating an email, the display unit 1002 may be set to a character input mode mainly for inputting characters, and an input operation on the characters displayed on the screen may be performed. In this case

[0408] it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. For example, when making a phone call or creating an email, the display unit 1002 may be set to a character input mode mainly for inputting characters, and an input operation on the characters displayed on the screen may be performed. In this case it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. Preferably.

[0409] Also, by providing a detection device having sensors for detecting inclination such as a gyro and an acceleration sensor inside the mobile phone 1000, the orientation (vertical or horizontal) of the mobile phone 1000 can be determined, and the screen display of the display unit 1002 can be automatically switched. Preferably.

[0410] Also, the switching of the screen mode can be performed by touching the display unit 1002 or operating the button 1003. It can also be switched according to the type of image displayed on the display unit 1002. For example, if the image signal to be displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0411] Also, in the input mode, the signal detected by the optical sensor of the display unit 1002 is detected, and if there is no input by touch operation on the display unit 1002 for a certain period, the screen mode may be controlled to be switched from the input mode to the display mode.

[0412] The display unit 1002 can also function as an image sensor. For example, by touching the palm or finger on the display unit 10 02, fingerprint, palmprint, etc. can be imaged to perform personal authentication. Also, by using a backlight that emits near-infrared light or a light source for a sensor that emits near-infrared light on the display unit, finger vein, palm vein, etc. can also be imaged.

[0413] (Embodiment 13) This embodiment is an example of a channel protection type thin film transistor in the thin film transistor of the present invention. Therefore, the rest can be performed in the same manner as in Embodiment 1 or Embodiment 2, and the description of the same parts or parts having the same functions as those in Embodiment 1 or Embodiment 2, and the repetition of the processes is omitted.

[0414] In this embodiment, the thin film transistor 175 used in the semiconductor device will be described with reference to FIG. 36.

[0415] ​​​As shown in FIG. 36, a thin film transistor 175 including a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 103, a channel protection layer 108, source regions or drain regions 104a, 104b, and a source electrode layer or a drain electrode layer 105a, 105b is provided on a substrate 100.

[0416] In the thin film transistor 175 of the present embodiment, a channel protection layer 108 is provided on the channel formation of the semiconductor layer 103. The semiconductor layer 103 is not etched because the channel protection layer 108 functions as a channel stopper. The channel protection layer 108 may also be formed by continuously depositing a film without exposing the gate insulating layer 102, the semiconductor layer 103 to the atmosphere. Productivity is improved by continuously depositing the stacked thin films without exposing them to the atmosphere.

[0417] As the channel protection layer 108, an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, etc.) can be used. As a manufacturing method, a sputtering method can be used.

[0418] The semiconductor layer 103 is an oxygen-excess oxide semiconductor layer containing In, Ga, and Zn, and the source regions or drain regions 104a, 104b are oxygen-deficient oxide semiconductor layers containing In, Ga, and Zn.

[0419] The gate insulating layer having an oxygen-excess region and the oxygen-excess oxide semiconductor layer are compatible and can obtain good interface characteristics.

[0420] After the formation of the gate insulating layer 102, an oxygen radical treatment is performed on the surface of the gate insulating layer to form an oxygen-excess region. Let it be so. Also, the gate insulating layer 102 and the semiconductor layer 103 are formed by continuous film formation.

[0421] The oxygen-deficient oxide semiconductor layers of the source region and the drain regions 104a and 104b have crystal grains with a size of 1 nm or more and 10 nm or less, and have a higher carrier concentration than the semiconductor layer 103. The oxygen-deficient oxide semiconductor layers of the source region and the drain regions 104a and 104b have crystal grains with a size of 1 nm or more and 10 nm or less, and have a higher carrier concentration than the semiconductor layer 103.

[0422] In this embodiment, a thin film transistor having a stacked structure of a gate electrode layer, a gate insulating layer, a semiconductor layer (oxygen-excess oxide semiconductor layer), a source region and a drain region (oxygen-deficient oxide semiconductor layer), a source electrode layer, and a drain electrode layer is used. By using a source region and a drain region having a high carrier concentration with crystal grains in the oxygen-deficient oxide semiconductor layer, the film thickness of the semiconductor layer can be kept thin while suppressing the parasitic capacitance. Even if it is a thin film, since the ratio to the gate insulating layer is sufficient, the parasitic capacitance is sufficiently suppressed. In this embodiment, a thin film transistor having a stacked structure of a gate electrode layer, a gate insulating layer, a semiconductor layer (oxygen-excess oxide semiconductor layer), a source region and a drain region (oxygen-deficient oxide semiconductor layer), a source electrode layer, and a drain electrode layer is used. By using a source region and a drain region having a high carrier concentration with crystal grains in the oxygen-deficient oxide semiconductor layer, the film thickness of the semiconductor layer can be kept thin while suppressing the parasitic capacitance. Even if it is a thin film, since the ratio to the gate insulating layer is sufficient, the parasitic capacitance is sufficiently suppressed. In this embodiment, a thin film transistor having a stacked structure of a gate electrode layer, a gate insulating layer, a semiconductor layer (oxygen-excess oxide semiconductor layer), a source region and a drain region (oxygen-deficient oxide semiconductor layer), a source electrode layer, and a drain electrode layer is used. By using a source region and a drain region having a high carrier concentration with crystal grains in the oxygen-deficient oxide semiconductor layer, the film thickness of the semiconductor layer can be kept thin while suppressing the parasitic capacitance. Even if it is a thin film, since the ratio to the gate insulating layer is sufficient, the parasitic capacitance is sufficiently suppressed. In this embodiment, a thin film transistor having a stacked structure of a gate electrode layer, a gate insulating layer, a semiconductor layer (oxygen-excess oxide semiconductor layer), a source region and a drain region (oxygen-deficient oxide semiconductor layer), a source electrode layer, and a drain electrode layer is used. By using a source region and a drain region having a high carrier concentration with crystal grains in the oxygen-deficient oxide semiconductor layer, the film thickness of the semiconductor layer can be kept thin while suppressing the parasitic capacitance. Even if it is a thin film, since the ratio to the gate insulating layer is sufficient, the parasitic capacitance is sufficiently suppressed. In this embodiment, a thin film transistor having a stacked structure of a gate electrode layer, a gate insulating layer, a semiconductor layer (oxygen-excess oxide semiconductor layer), a source region and a drain region (oxygen-deficient oxide semiconductor layer), a source electrode layer, and a drain electrode layer is used. By using a source region and a drain region having a high carrier concentration with crystal grains in the oxygen-deficient oxide semiconductor layer, the film thickness of the semiconductor layer can be kept thin while suppressing the parasitic capacitance. Even if it is a thin film, since the ratio to the gate insulating layer is sufficient, the parasitic capacitance is sufficiently suppressed. In this embodiment, a thin film transistor having a stacked structure of a gate electrode layer, a gate insulating layer, a semiconductor layer (oxygen-excess oxide semiconductor layer), a source region and a drain region (oxygen-deficient oxide semiconductor layer), a source electrode layer, and a drain electrode layer is used. By using a source region and a drain region having a high carrier concentration with crystal grains in the oxygen-deficient oxide semiconductor layer, the film thickness of the semiconductor layer can be kept thin while suppressing the parasitic capacitance. Even if it is a thin film, since the ratio to the gate insulating layer is sufficient, the parasitic capacitance is sufficiently suppressed.

[0423] According to this embodiment, a thin film transistor with a small photocurrent, a small parasitic capacitance, and a high on-off ratio can be obtained, and a thin film transistor having good dynamic characteristics can be manufactured. Therefore, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided. According to this embodiment, a thin film transistor with a small photocurrent, a small parasitic capacitance, and a high on-off ratio can be obtained, and a thin film transistor having good dynamic characteristics can be manufactured. Therefore, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided. According to this embodiment, a thin film transistor with a small photocurrent, a small parasitic capacitance, and a high on-off ratio can be obtained, and a thin film transistor having good dynamic characteristics can be manufactured. Therefore, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided. According to this embodiment, a thin film transistor with a small photocurrent, a small parasitic capacitance, and a high on-off ratio can be obtained, and a thin film transistor having good dynamic characteristics can be manufactured. Therefore, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided.

[0424] This embodiment can be implemented in appropriate combination with other embodiments.

Claims

[Claim 1] a circuit having first to sixth transistors; A pixel electrode; a seventh transistor electrically connected to the pixel electrode; one of a source and a drain of each of the first to fifth transistors is electrically connected to a first wiring; a gate of the first transistor is electrically connected to the other of the source and the drain of the fourth transistor and the other of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the sixth transistor; a gate of the fifth transistor is electrically connected to a gate of the third transistor; a gate of the second transistor and a gate of the sixth transistor are electrically connected to a second wiring; At least one of the first to sixth transistors and each of the seventh transistor are A gate electrode; a gate insulating film on the gate electrode; an oxide layer containing In, Ga, and Zn provided on the gate insulating film; a conductive layer provided over the oxide layer and functioning as one of a source electrode and a drain electrode; the oxide layer has a laminated structure including a first oxide layer on the gate insulating film and a second oxide layer on the first oxide layer; the conductive layer has a laminated structure including a first conductive layer on the second oxide layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer; the oxide layer has a first region in contact with the first conductive layer and a second region in contact with a first insulating layer; When viewed in a cross section in a channel length direction, the first conductive layer has a third region that does not overlap with the second conductive layer and the third conductive layer and is in contact with the first insulating layer, a fourth region that does not overlap with the third conductive layer and is in contact with the second conductive layer, a fifth region that overlaps with the third conductive layer and is in contact with the second conductive layer, a sixth region that does not overlap with the third conductive layer and is in contact with the second conductive layer, and a seventh region that does not overlap with the second conductive layer and the third conductive layer and is in contact with the first insulating layer, In the cross-sectional view, the oxide layer does not have a region in contact with the second conductive layer, a second insulating layer having an organic material on the first insulating layer; the pixel electrode is provided on the second insulating layer and is electrically connected to the conductive layer of the seventh transistor.

Images