Semiconductor device and manufacturing method for the same

Abstract

To improve the connection reliability of a wiring layer.SOLUTION: A semiconductor device has an insulation base material, a wiring layer, a via, and a semiconductor element. The insulation base material is composed of an insulation layer having an adhesive layer on one surface. The wiring layer is formed on one surface of the adhesive layer. The via is made of a conducting sintered material, formed separately from the wiring layer, penetrates the insulating layer and the adhesive layer, and is connected to the wiring layer. The semiconductor element is connected to the other end opposite to the one end connected to the wiring layer of the via on the other surface of the insulating layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device is known in which a semiconductor element is disposed on one surface of an insulating layer constituting an insulating substrate via an adhesive layer, and a wiring layer is formed on the other surface of the insulating layer. In such a semiconductor device, the wiring layer is joined to the semiconductor element via a via penetrating the insulating layer and the adhesive layer.

[0003] The wiring layer and the via are integrally formed by forming via holes in the insulating layer and the adhesive layer and performing electrolytic plating on the other surface of the insulating layer and the inner wall surface of the via holes.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the above-described semiconductor device, there is a problem that the connection reliability of the wiring layer is not sufficient. Specifically, when the wiring layer and the via are integrally formed by electrolytic plating, metal that becomes the wiring layer and the via is deposited along the inner wall surface of the via hole. For this reason, at a position corresponding to the via hole, a recess that is recessed in the depth direction of the via hole is formed in the wiring layer.

[0006] Such a recess in the wiring layer reduces the fluidity of a bonding material such as solder supplied onto the wiring layer when an external component is bonded to the wiring layer. As a result, voids are generated in the bonding material on the wiring layer. When voids are generated in the bonding material on the wiring layer, the electrical connection and mechanical connection between the wiring layer and the external component become unstable. That is, the connection reliability in the wiring layer of the semiconductor device is reduced.

[0007] The disclosed technology has been made in view of the above, and an object thereof is to provide a semiconductor device and a method of manufacturing a semiconductor device capable of improving the connection reliability of a wiring layer.

Means for Solving the Problems

[0008] The semiconductor device disclosed in the present application, in one aspect, includes an insulating substrate, a wiring layer, a via, and a semiconductor element. The insulating substrate is composed of an insulating layer having an adhesive layer on one surface. The wiring layer is formed on one surface of the adhesive layer. The via is made of a conductive sintered material, is formed separately from the wiring layer, penetrates the insulating layer and the adhesive layer, and is connected to the wiring layer. The semiconductor element is connected to the other end of the insulating layer on the side opposite to the one end connected to the wiring layer of the via.

Effects of the Invention

[0009] According to one aspect of the semiconductor device disclosed in the present application, there is an effect that the connection reliability of the wiring layer can be improved.

Brief Description of the Drawings

[0010]

Figure 1

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BEST MODE FOR CARRYING OUT THE INVENTION

[0011] Hereinafter, embodiments of the semiconductor device and the method of manufacturing the semiconductor device disclosed in the present application will be described in detail with reference to the drawings. Note that the technology disclosed by this embodiment is not limited thereto.

[0012] (Embodiment) FIG. 1 is a diagram showing the configuration of a semiconductor device 100 according to the embodiment. In FIG. 1, a cross section of the semiconductor device 100 is schematically shown. The semiconductor device 100 shown in FIG. 1 includes an insulating substrate 110, a wiring layer 120, and a semiconductor element 130.

[0013] In the following description, the surface of the insulating substrate 110 on which the wiring layer 120 is formed is referred to as the "upper surface", the surface opposite to the surface on which the wiring layer 120 is formed is referred to as the "lower surface", and the vertical direction is defined accordingly. However, the semiconductor device 100 may be manufactured and used, for example, upside down, or may be manufactured and used in any posture.

[0014] The insulating base material 110 is a film-shaped member composed of an insulating layer 111 having an adhesive layer 112 on its upper surface 111a, and is the base material of the semiconductor device 100. As the material of the insulating layer 111, for example, insulating resins such as polyimide-based resins, polyethylene-based resins, and epoxy-based resins can be used. The thickness of the insulating layer 111 can be, for example, about 25 μm to 125 μm. As the material of the adhesive layer 112, for example, thermosetting resins such as epoxy-based resins, polyimide-based resins, and silicone-based resins can be used. The thickness of the adhesive layer 112 can be, for example, about 10 μm to 50 μm.

[0015] The wiring layer 120 is formed on the upper surface of the adhesive layer 112. The wiring layer 120 is formed using, for example, copper or a copper alloy. The thickness of the wiring layer 120 can be, for example, about 50 to 500 μm. The wiring layer 120 is electrically connected to the semiconductor element 130 by vias 140.

[0016] The vias 140 are embedded in the insulating layer 111 and the adhesive layer 112 of the insulating base material 110. The vias 140 are formed by filling via holes penetrating the insulating layer 111 and the adhesive layer 112 with a conductive sintered material such as a metal paste, and are connected to the wiring layer 120. That is, one end 141 of the via 140 is connected to the wiring layer 120, and the other end 142 of the via 140 protrudes from the via hole on the lower surface 111b of the insulating layer 111. As the metal paste for forming the vias 140, for example, copper paste or silver paste can be used.

[0017] The semiconductor element 130 is sintered to the other end 142 of the via 140 protruding on the lower surface 111b of the insulating layer 111. As the semiconductor element 130, for example, a semiconductor element using silicon (Si) or silicon carbide (SiC) can be used. Further, the semiconductor element 130 may be a semiconductor element using gallium nitride (GaN), gallium arsenide (GaAs), or the like. For example, as the semiconductor element 130, a semiconductor element as an active element (for example, a silicon chip such as a CPU), an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a diode, or the like can be used.

[0018] In the embodiment, the via 140 is formed separately from the wiring layer 120 by filling a conductive sintered material into a via hole penetrating the insulating layer 111 and the adhesive layer 112. That is, when the via 140 is formed in the via holes of the insulating layer 111 and the adhesive layer 112 by the conductive sintered material, it is not formed integrally with the wiring layer 120, and an interface serving as a bonding surface between the wiring layer 120 and the via 140 exists between the wiring layer 120 and the via 140. By forming the wiring layer 120 and the via 140 separately, a recess recessed in the depth direction of the via hole is not formed in the wiring layer 120, and the surface of the wiring layer 120 becomes a flat surface. As a result, when an external component is bonded to the wiring layer 120, the fluidity of a bonding material such as solder supplied onto the wiring layer 120 is maintained, and the generation of voids in the bonding material can be suppressed. As a result, the connection reliability of the wiring layer 120 to the external component can be improved.

[0019] In addition, in the embodiment, the via 140 has a tapered shape in which the diameter increases as it approaches the semiconductor element 130. That is, in the via 140, the diameter of the other end 142 connected to the semiconductor element 130 is larger than the diameter of the one end 141 connected to the wiring layer 120. Thus, since the via 140 has a tapered shape, the bonding area between the semiconductor element 130 and the via 140 can be increased, and the bonding strength between the semiconductor element 130 and the via 140 can be improved.

[0020] In addition, in the embodiment, the other end 142 of the via 140 protrudes from the lower surface 111b of the insulating layer 111. That is, the other end 142 of the via 140 has an end surface located outside the lower surface 111b of the insulating layer 111. Therefore, the other end 142 can stably contact the semiconductor element 130, and the connection reliability between the semiconductor element 130 and the via 140 can be improved.

[0021] In addition, in the embodiment, the other end 142 of the via 140 has a larger diameter than the diameter of the portion (i.e., the via hole diameter) that penetrates the insulating layer 111 and the adhesive layer 112 of the via 140, and extends around the via hole. That is, the other end 142 extends around the via hole on the lower surface 111b of the insulating layer 111. Therefore, the other end 142 can more stably contact the semiconductor element 130, and the connection reliability between the semiconductor element 130 and the via 140 can be further improved. Note that the other end 142 does not necessarily extend around the via hole on the lower surface 111b of the insulating layer 111. In this case, the end surface of the other end 142 may be located on the same plane as the lower surface 111b of the insulating layer 111.

[0022] Next, a method for manufacturing the semiconductor device 100 configured as described above will be described with reference to FIG. 2 while specifically giving examples. FIG. 2 is a flowchart showing a method for manufacturing the semiconductor device 100 according to the embodiment.

[0023] First, an insulating substrate 110 serving as a base material of the semiconductor device 100 is prepared (step S101). Specifically, for example, as shown in FIG. 3, an insulating substrate 110 composed of an insulating layer 111 having an adhesive layer 112 on the upper surface 111a is prepared. FIG. 3 is a diagram showing a specific example of the insulating substrate 110. As the material of the insulating layer 111, for example, insulating resins such as polyimide-based resins, polyethylene-based resins, and epoxy-based resins can be used. As the material of the adhesive layer 112, for example, thermosetting resins such as epoxy-based resins, polyimide-based resins, and silicone-based resins can be used. At the stage when the insulating substrate 110 is prepared, the adhesive layer 112 is in a semi-cured state. The upper surface of the adhesive layer 112 (the surface opposite to the insulating layer 111) is covered with a protective film 115. As the protective film 115, for example, a polyethylene terephthalate film treated with a silicone-based release agent or a non-silicone-based release agent can be used.

[0024] Subsequently, a metal foil to be the wiring layer 120 is laminated on the upper surface of the adhesive layer 112 (step S102). Specifically, after the protective film 115 is peeled off from the upper surface of the adhesive layer 112, for example, as shown in FIG. 4, a metal foil 120a is laminated on the upper surface of the adhesive layer 112. FIG. 4 is a diagram showing a specific example of the metal foil lamination process. The thickness of the metal foil 120a can be, for example, about 50 to 500 μm, similar to the thickness of the wiring layer 120. At the stage when the metal foil 120a is laminated on the upper surface of the adhesive layer 112, the adhesive layer 112 is thermally cured, and the metal foil 120a adheres closely to the adhesive layer 112. As the material of the metal foil 120a, the metals exemplified as the material of the wiring layer 120 can be used. That is, the metal foil 120a is made of copper or a copper alloy.

[0025] On the upper surface of the adhesive layer 112, a metal foil 120a is laminated, and a wiring layer 120 having a desired wiring pattern is formed from the metal foil 120a (step S103). The wiring layer 120 is formed from the metal foil 120a by, for example, the subtractive method. That is, a resist layer that covers the portions to be left as the wiring pattern is formed on the upper surface of the metal foil 120a. Then, the metal foil 120a that is exposed without being covered by the resist layer is removed by etching, whereby a wiring layer 120 having a desired wiring pattern is formed, for example, as shown in FIG. 5. FIG. 5 is a diagram showing a specific example of the wiring layer forming process.

[0026] When the wiring layer 120 is formed, via holes are formed in the insulating base material 110 (step S104). Specifically, for example, as shown in FIG. 6, via holes 151 that penetrate the insulating layer 111 and the adhesive layer 112 in the thickness direction and reach the wiring layer 120 are formed. FIG. 6 is a diagram showing a specific example of the via hole forming process. The lower surface of the wiring layer 120 is exposed at the bottom surface of the via hole 151. The via hole 151 has a tapered shape in which the diameter becomes smaller as it moves away from the lower surface 111b of the insulating layer 111 (that is, as it approaches the wiring layer 120). The via hole 151 can be formed, for example, by laser processing.

[0027] When the via holes 151 are formed, the via holes 151 are filled with a conductive sintered material such as a metal paste (step S105), and vias 140 are formed. Specifically, for example, as shown in FIG. 7, the via holes 151 are filled with a conductive sintered material such as a semi-cured copper paste or silver paste, and vias 140 are formed. At this time, one end 141 connected to the wiring layer 120 is formed on the bottom surface side of the via hole 151, and the other end 142 protruding from the via hole 151 is formed on the lower surface 111b of the insulating layer 111. That is, on the lower surface 111b of the insulating layer 111, the semi-cured sintered material leaks out from the via hole 151, and the other end 142 having an end surface outside the lower surface 111b of the insulating layer 111 is formed. FIG. 7 is a diagram showing a specific example of the via hole filling process.

[0028] When via 140 is formed, as shown in FIG. 8 for example, semiconductor element 130 is mounted on the lower surface 111b side of insulating layer 111 (step S106), and semiconductor element 130 and the other end 142 of via 140 are temporarily joined. FIG. 8 is a diagram showing a specific example of the semiconductor element mounting process.

[0029] Then, the electrode of semiconductor element 130 is sintered by heating and pressurization at the other end 142 of via 140 (step S107). At this time, on the lower surface 111b of insulating layer 111, the other end 142 having a diameter larger than that of via hole 151 is formed. That is, on the lower surface 111b of insulating layer 111, the semi-cured sintering material is cured in a state of extending to the periphery of via hole 151, and the other end 142 that connects with the electrode of semiconductor element 130 with a wide contact area is formed. Thereby, the connection reliability between semiconductor element 130 and via 140 can be further improved. By sintering semiconductor element 130 to the other end 142 of via 140 on the lower surface 111b of insulating layer 111, semiconductor device 100 is completed.

[0030] (Modification example) Next, a modification example of the embodiment will be described with reference to FIGS. 9 to 11. In each of the various modification examples shown below, the same reference numerals may be given to the same parts as in the embodiment, and redundant descriptions may be omitted.

[0031] FIG. 9 is a diagram showing the configuration of semiconductor device 100 according to a modification example of the embodiment. Semiconductor device 100 according to the modification example is different from the embodiment in that it has wiring substrate 160.

[0032] Specifically, in the modification example, wiring substrate 160 is joined to the surface (lower surface) opposite to the surface (upper surface) to which via 140 of semiconductor element 130 is joined.

[0033] The wiring board 160 has a substrate 161, an upper pad 162, and a lower pad 163. The substrate 161 is an insulating plate-like member and is the base material of the wiring board 160. The substrate 161 is, for example, a ceramic substrate made of ceramics such as oxide-based ceramics or non-oxide-based ceramics. As the oxide-based ceramics, for example, aluminum oxide (Al2O3), zirconia (ZrO2), etc. can be used. As the non-oxide-based ceramics, for example, aluminum nitride (AlN), silicon nitride (Si3N4), etc. can be used.

[0034] Note that the substrate 161 is not limited to a single-layer insulating member, and may be a multilayer substrate in which an insulating layer and a wiring layer are laminated. When the substrate 161 is a multilayer substrate, the wiring layers sandwiching this insulating layer are electrically connected by vias penetrating the insulating layer. As the material of the insulating layer, for example, ceramics such as oxide-based ceramics or non-oxide-based ceramics can be used. Also, as the material of the wiring layer, for example, copper (Cu) or a copper alloy can be used.

[0035] The upper pad 162 is formed in the wiring layer on the upper surface of the substrate 161 and is exposed on the upper surface of the substrate 161 for bonding the semiconductor element 130. When the lower surface of the semiconductor element 130 is bonded to the upper surface of the wiring board 160, the electrode on the lower surface of the semiconductor element 130 is bonded to the upper pad 162 by the sintering material 171. As the material of the upper pad 162, similar to the wiring layer, for example, copper or a copper alloy can be used.

[0036] The lower pad 163 is formed in the wiring layer on the lower surface of the substrate 161. As the material of the lower pad 163, similar to the wiring layer, for example, copper or a copper alloy can be used.

[0037] When such a wiring board 160 is joined to the lower surface of the semiconductor element 130, the semiconductor element 130 will be disposed sandwiched between the wiring board 160 and the insulating base material 110. The semiconductor element 130 sandwiched between the wiring board 160 and the insulating base material 110 is resin-sealed with an insulating resin 172. That is, the space between the wiring board 160 and the insulating base material 110 is filled with the insulating resin 172, covering the semiconductor element 130. As the material of the insulating resin 172, for example, an insulating resin such as a polyimide-based resin or an epoxy-based resin, or a resin material in which fillers such as silica and alumina are mixed into these resins can be used.

[0038] In this way, in the modified example, by joining the wiring board 160 to the lower surface of the semiconductor element 130, the degree of freedom of the wiring layout can be improved.

[0039] Next, a method for manufacturing the semiconductor device 100 configured as described above will be described with reference to FIG. 10 while specifically giving examples. FIG. 10 is a flowchart showing a method for manufacturing the semiconductor device 100 according to a modified example of the embodiment. In FIG. 10, the same parts as those in FIG. 2 are denoted by the same reference numerals.

[0040] When the semiconductor element 130 and the other end 142 of the via 140 are temporarily joined by the process of step S106, the lower surface of the semiconductor element 130 is temporarily joined to the upper surface of the wiring board 160 with a sintering material 171 (step S201). Specifically, for example, as shown in FIG. 11, the electrodes on the lower surface of the semiconductor element 130 are temporarily joined to the upper surface pads 162 with the unsolidified sintering material 171. FIG. 11 is a diagram showing a specific example of the wiring board temporary joining step.

[0041] Then, at the other end 142 of the via 140, the electrodes of the semiconductor element 130 are sintered by heating and pressurization (step S107). Simultaneously with the sintering of the other end 142 of the via 140 and the electrodes of the semiconductor element 130, the electrodes on the lower surface of the semiconductor element 130 are sintered to the upper surface pads 162 by the sintering material 171. That is, the upper surface of the semiconductor element 130 is sintered to the other end 142 of the via 140 on the lower surface 111b of the insulating layer 111, and the wiring substrate 160 is joined to the lower surface of the semiconductor element 130. Thereby, an intermediate structure is obtained in which the semiconductor element 130 is sandwiched between the wiring substrate 160 and the insulating base material 110.

[0042] Then, for example, transfer molding is performed on the intermediate structure, and the semiconductor element 130 sandwiched between the wiring substrate 160 and the insulating base material 110 is resin-sealed with the insulating resin 172 (step S202). In transfer molding, the intermediate structure is housed in a mold, and the liquefied insulating resin 172 is injected into the mold. Then, the insulating resin 172 is heated to a predetermined temperature and cured. As a result, the space between the wiring substrate 160 and the insulating base material 110 is filled with the insulating resin 172 to seal the semiconductor element 130, and the semiconductor device 100 is completed.

[0043] As described above, the semiconductor device (as an example, the semiconductor device 100) according to the embodiment includes an insulating base material (as an example, the insulating base material 110), a wiring layer (as an example, the wiring layer 120), a via (as an example, the via 140), and a semiconductor element (as an example, the semiconductor element 130). The insulating base material is composed of an insulating layer (as an example, the insulating layer 111) having an adhesive layer (as an example, the adhesive layer 112) on one surface (as an example, the upper surface 111a). The wiring layer is formed on one surface (as an example, the upper surface) of the adhesive layer. The via is made of a conductive sintering material, is formed separately from the wiring layer, penetrates the insulating layer and the adhesive layer, and is connected to the wiring layer. The semiconductor element is sintered to the other end (as an example, the other end 142) opposite to one end (as an example, one end 141) connected to the wiring layer of the via on the other surface (as an example, the lower surface 111b) of the insulating layer. Thereby, the connection reliability of the wiring layer can be improved.

Description of Reference Numerals

[0044] 100 Semiconductor device 110 Insulating substrate 111 Insulating layer 111a Upper surface 111b Lower surface 112 Adhesive layer 120 Wiring layer 130 Semiconductor element 140 Via 141 One end 142 The other end 160 Wiring board

Claims

1. An insulating substrate comprising an insulating layer having an adhesive layer on one surface, A wiring layer formed on one surface of the adhesive layer, A via made of a conductive sintered material, formed separately from the wiring layer, penetrating the insulating layer and the adhesive layer, and connecting to the wiring layer, A semiconductor element connected to the other end of the via on the other surface of the insulating layer, which is opposite to the one end connected to the wiring layer of the via A semiconductor device having.

2. The via, Has a tapered shape in which the diameter of the other end is larger than the diameter of the one end The semiconductor device according to claim 1, characterized in that.

3. The other end of the via, Projects from the other surface of the insulating layer The semiconductor device according to claim 1, characterized in that.

4. The other end of the via, Has a larger diameter than the portion penetrating the insulating layer and the adhesive layer of the via The semiconductor device according to claim 3, characterized in that.

5. A wiring board joined to the surface of the semiconductor element opposite to the surface connected to the via The semiconductor device according to claim 1, characterized by having.

6. Prepare an insulating substrate comprising an insulating layer having an adhesive layer on one surface, Laminating a metal foil on one surface of the adhesive layer, Forming a wiring layer from the metal foil, Forming a via hole penetrating the insulating layer and the adhesive layer up to the wiring layer with respect to the insulating substrate, Forming a via connecting to the wiring layer by filling the via hole with a conductive sintered material, Sintering the other end of the via on the other surface of the insulating layer, which is opposite to the one end connected to the wiring layer of the via, and the electrode of the semiconductor element A method for manufacturing a semiconductor device, characterized by having the steps.

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