Semiconductor device and manufacturing method for the same

Abstract

To improve the connection reliability of a wiring layer.SOLUTION: A semiconductor device has an insulation base material, a wiring layer, a via, and a semiconductor element. The insulation base material is composed of an insulation layer having an adhesive layer on one surface. The wiring layer is formed on one surface of the adhesive layer. The via is formed separately from the wiring layer, penetrates the insulation layer and the adhesive layer, and is connected to the wiring layer. The semiconductor element is connected to the other end opposite to the one end connected to the wiring layer of the via on the other surface of the insulation layer, via a sintering material.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device is known in which a semiconductor element is disposed on one surface of an insulating layer constituting an insulating substrate via an adhesive layer, and a wiring layer is formed on the other surface of the insulating layer. In such a semiconductor device, the wiring layer is joined to the semiconductor element via a via that penetrates the insulating layer and the adhesive layer.

[0003] The wiring layer and the via are integrally formed by forming a via hole in the insulating layer and the adhesive layer and performing electrolytic plating on the other surface of the insulating layer and the inner wall surface of the via hole.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the above-described semiconductor device, there is a problem that the connection reliability of the wiring layer is not sufficient. Specifically, when the wiring layer and the via are integrally formed by electrolytic plating, metal that becomes the wiring layer and the via is deposited along the inner wall surface of the via hole. For this reason, a recess that is recessed in the depth direction of the via hole is formed in the wiring layer at a position corresponding to the via hole.

[0006] Such a recess in the wiring layer reduces the fluidity of a bonding material such as solder supplied onto the wiring layer when an external component is bonded to the wiring layer, and as a result, voids are generated in the bonding material on the wiring layer. When voids are generated in the bonding material on the wiring layer, the electrical connection and mechanical connection between the wiring layer and the external component become unstable. That is, the connection reliability in the wiring layer of the semiconductor device is reduced.

[0007] The disclosed technology has been made in view of the above, and an object thereof is to provide a semiconductor device and a method of manufacturing a semiconductor device capable of improving the connection reliability of a wiring layer.

Means for Solving the Problems

[0008] The semiconductor device disclosed in the present application, in one aspect, includes an insulating substrate, a wiring layer, a via, and a semiconductor element. The insulating substrate is composed of an insulating layer having an adhesive layer on one surface. The wiring layer is formed on one surface of the adhesive layer. The via is formed separately from the wiring layer, penetrates the insulating layer and the adhesive layer, and is connected to the wiring layer. The semiconductor element is connected via a sintering material to the other end opposite to one end connected to the wiring layer of the via on the other surface of the insulating layer.

Effects of the Invention

[0009] According to one aspect of the semiconductor device disclosed in the present application, there is an effect that the connection reliability of the wiring layer can be improved.

Brief Description of the Drawings

[0010]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0011] Hereinafter, embodiments of the semiconductor device and the manufacturing method of the semiconductor device disclosed in the present application will be described in detail with reference to the drawings. Note that the disclosed technology is not limited by this embodiment.

[0012] (Embodiment) FIG. 1 is a diagram showing the configuration of a semiconductor device 100 according to the embodiment. In FIG. 1, a cross section of the semiconductor device 100 is schematically shown. The semiconductor device 100 shown in FIG. 1 includes an insulating base material 110, a wiring layer 120, and a semiconductor element 130.

[0013] In the following description, the surface of the insulating substrate 110 on which the wiring layer 120 is formed is referred to as the "upper surface", the surface opposite to the surface on which the wiring layer 120 is formed is referred to as the "lower surface", and the vertical direction is defined accordingly. However, the semiconductor device 100 may be manufactured and used, for example, upside down, or may be manufactured and used in any posture.

[0014] The insulating substrate 110 is a film-like member composed of an insulating layer 111 having an adhesive layer 112 on the upper surface 111a, and is the substrate of the semiconductor device 100. As the material of the insulating layer 111, for example, insulating resins such as polyimide-based resins, polyethylene-based resins, and epoxy-based resins can be used. The thickness of the insulating layer 111 can be, for example, about 25 μm to 125 μm. As the material of the adhesive layer 112, for example, thermosetting resins such as epoxy-based resins, polyimide-based resins, and silicone-based resins can be used. The thickness of the adhesive layer 112 can be, for example, about 10 μm to 50 μm.

[0015] The wiring layer 120 is formed on the upper surface of the adhesive layer 112. The wiring layer 120 is formed using, for example, copper or a copper alloy. The thickness of the wiring layer 120 can be, for example, about 50 to 500 μm. The wiring layer 120 is electrically connected to the semiconductor element 130 by the via 140 and the sintered material 131.

[0016] The via 140 is embedded in the insulating layer 111 and the adhesive layer 112 of the insulating substrate 110. The via 140 penetrates the insulating layer 111 and the adhesive layer 112 and connects to the wiring layer 120. That is, one end 141 of the via 140 is connected to the wiring layer 120, and the other end 142 of the via 140 is exposed on the lower surface 111b of the insulating layer 111.

[0017] The semiconductor element 130 is joined to the other end 142 of the via 140 exposed on the lower surface 111b of the insulating layer 111. As the semiconductor element 130, for example, a semiconductor element using silicon (Si) or silicon carbide (SiC) can be used. Also, the semiconductor element 130 may be a semiconductor element using gallium nitride (GaN), gallium arsenide (GaAs), or the like. For example, as the semiconductor element 130, a semiconductor element as an active element (for example, a silicon chip such as a CPU), an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a diode, or the like can be used.

[0018] In the embodiment, the via 140 is formed separately from the wiring layer 120 by forming via holes in the insulating layer 111 and the adhesive layer 112 and performing electrolytic copper plating. That is, when the via 140 is formed in the via holes of the insulating layer 111 and the adhesive layer 112 by electrolytic copper plating, it is not formed integrally with the wiring layer 120, and an interface serving as a bonding surface between the wiring layer 120 and the via 140 exists between the wiring layer 120 and the via 140. By forming the wiring layer 120 and the via 140 separately, a recess that is recessed in the depth direction of the via hole is not formed in the wiring layer 120, and the surface of the wiring layer 120 becomes a flat surface. As a result, when an external component is joined to the wiring layer 120, the fluidity of a bonding material such as solder supplied onto the wiring layer 120 is maintained, and the generation of voids in the bonding material can be suppressed. As a result, the connection reliability of the wiring layer 120 to the external component can be improved.

[0019] Also, in the embodiment, the semiconductor element 130 is joined to the other end 142 of the via 140 by the sintered material 131. Thereby, the joining strength between the semiconductor element 130 and the via 140 can be improved as compared with the case where the semiconductor element 130 is joined to the other end 142 of the via 140 by another joining material different from the sintered material 131. Note that the semiconductor element 130 may be joined to the other end 142 of the via 140 by another joining material such as solder or the like.

[0020] Also, in the embodiment, the via 140 has a tapered shape in which the diameter increases as it approaches the semiconductor element 130. That is, in the via 140, the diameter of the other end 142 connected to the semiconductor element 130 is larger than the diameter of the one end 141 connected to the wiring layer 120. Since the via 140 has such a tapered shape, the joining area between the semiconductor element 130 and the via 140 increases, and the joining strength between the semiconductor element 130 and the via 140 can be improved.

[0021] Also, in the embodiment, the end face of the other end 142 of the via 140 is located on the same plane as the lower face 111b of the insulating layer 111. Thereby, the area of the end face of the other end 142 serving as the joining face with the semiconductor element 130 increases, and the joining strength between the semiconductor element 130 and the via 140 can be further improved.

[0022] Also, in the embodiment, the end face of the other end 142 of the via 140 is a flat face. Thereby, when the semiconductor element 130 is joined to the other end 142 of the via 140 by the sintered material 131, the flatness of the sintered material 131 is maintained, so that the joining strength between the semiconductor element 130 and the via 140 can be further improved.

[0023] Next, a method for manufacturing the semiconductor device 100 configured as described above will be described with reference to FIG. 2 while specifically giving examples. FIG. 2 is a flowchart showing a method for manufacturing the semiconductor device 100 according to the embodiment.

[0024] First, an insulating substrate 110 serving as a base material of the semiconductor device 100 is prepared (step S101). Specifically, for example, as shown in FIG. 3, an insulating substrate 110 composed of an insulating layer 111 having an adhesive layer 112 on its upper surface 111a is prepared. FIG. 3 is a diagram showing a specific example of the insulating substrate 110. In FIG. 3, the insulating substrate 110 is shown upside down. As the material of the insulating layer 111, for example, insulating resins such as polyimide-based resins, polyethylene-based resins, and epoxy-based resins can be used. As the material of the adhesive layer 112, for example, thermosetting resins such as epoxy-based resins, polyimide-based resins, and silicone-based resins can be used. At the stage when the insulating substrate 110 is prepared, the adhesive layer 112 is in a semi-cured state. The upper surface of the adhesive layer 112 (the surface opposite to the insulating layer 111) is covered with a protective film 115. As the protective film 115, for example, a polyethylene terephthalate film treated with a silicone-based release agent or a non-silicone-based release agent can be used.

[0025] Subsequently, via holes are formed in the insulating substrate 110 (step S102). Specifically, for example, as shown in FIG. 4, via holes 151 penetrating the insulating layer 111, the adhesive layer 112, and the protective film 115 in the thickness direction are formed. FIG. 4 is a diagram showing a specific example of the via hole forming process. The via holes 151 have a tapered shape in which the diameter decreases as they move away from the lower surface 111b of the insulating layer 111. The via holes 151 can be formed, for example, by laser processing or punching. At this time, since the upper surface of the adhesive layer 112 (the surface opposite to the insulating layer 111) is covered with the protective film 115, it is possible to prevent the processing debris of the insulating resin generated by laser processing or punching from adhering to the upper surface of the adhesive layer 112.

[0026] When the via hole 151 is formed, a metal foil that will become the wiring layer 120 is laminated on the upper surface of the adhesive layer 112 (step S103). Specifically, after the protective film 115 is peeled off from the upper surface of the adhesive layer 112, for example, as shown in FIG. 5, the metal foil 120a is laminated on the upper surface of the adhesive layer 112. FIG. 5 is a diagram showing a specific example of the metal foil lamination process. The metal foil 120a is exposed at the bottom surface of the via hole 151. The thickness of the metal foil 120a can be, for example, about 50 to 500 μm, similar to the thickness of the wiring layer 120. When the metal foil 120a is laminated on the upper surface of the adhesive layer 112, the adhesive layer 112 is thermally cured, and the metal foil 120a adheres closely to the adhesive layer 112. As the material of the metal foil 120a, the metals exemplified as the material of the wiring layer 120 can be used. That is, the metal foil 120a is made of copper or a copper alloy.

[0027] When the metal foil 120a is laminated on the upper surface of the adhesive layer 112, electroless copper plating is applied to the lower surface 111b of the insulating layer 111 to form a seed layer (step S104). Specifically, for example, as shown in FIG. 6, a seed layer 152 that continuously covers the lower surface 111b of the insulating layer 111 around the via hole 151, the inner wall surface of the via hole 151, and the surface of the metal foil 120a exposed at the bottom surface of the via hole 151 is formed. FIG. 6 is a diagram showing a specific example of the seed layer formation process.

[0028] When the seed layer 152 is formed on the lower surface 111b of the insulating layer 111, electrolytic copper plating for forming the via 140 is applied using the seed layer 152 as a power supply layer (step S105). As a result, in addition to the via hole 151, electrolytic copper is deposited on the lower surface 111b of the insulating layer 111.

[0029] That is, for example, as shown in FIG. 7, when the via hole 151 is filled with electrolytic copper to form the via 140, an electrolytic copper plating layer 153 is formed on the lower surface 111b of the insulating layer 111. FIG. 7 is a diagram showing a specific example of the electrolytic copper plating process. At a position where the electrolytic copper plating layer 153 overlaps the via hole 151 in plan view, a recess 152a that is recessed in the depth direction of the via hole 151 is formed.

[0030] Then, a wiring layer 120 having a desired wiring pattern is formed from the metal foil 120a (step S106). The wiring layer 120 is formed from the metal foil 120a, for example, by a subtractive method. That is, a resist layer is formed on the upper surface of the metal foil 120a to cover the portions to be left as the wiring pattern. Then, the metal foil 120a that is not covered by the resist layer and is exposed is removed by etching, so that, for example, as shown in FIG. 8, a wiring layer 120 having a desired wiring pattern and to which one end 141 of the via 140 is connected is formed. FIG. 8 is a diagram showing a specific example of the wiring layer forming process.

[0031] When the metal foil 120a is etched, by preventing the surface of the electrolytic copper plating layer 153 from being covered by the resist layer, not only the metal foil 120a that is not covered by the resist layer and is exposed but also the electrolytic copper plating layer 153 is etched. By this etching, the seed layer 152 on the lower surface 111b of the electrolytic copper plating layer 153 and the insulating layer 111 is removed, and the other end 142 of the via 140 is exposed on the lower surface 111b of the insulating layer 111. At this time, etching is performed under etching conditions adjusted so that a recess corresponding to the recess 152a of the electrolytic copper plating layer 153 is not formed on the end face of the other end 142 of the via 140. Thereby, the end face of the other end 142 of the via 140 becomes a flat surface. Further, etching is performed under etching conditions adjusted so that the end face of the other end 142 of the via 140 is positioned on the same plane as the lower surface 111b of the insulating layer 111. Note that the seed layer 152 in contact with the via 140 remains after etching, but is not shown in FIG. 8.

[0032] When the wiring layer 120 is formed, as shown in FIG. 9, for example, a sintering material 131 for joining the semiconductor element 130 and the via 140 is applied to the end face of the other end 142 of the via 140 (step S107). FIG. 9 is a diagram showing a specific example of the sintering material applying process. In FIG. 9, the insulating base material 110 is shown upside down. The application of the sintering material 131 may be performed by printing a sintering material paste, or a dispenser may be used.

[0033] When the sintering material 131 is applied to the end face of the other end 142 of the via 140, as shown in FIG. 10 for example, the semiconductor element 130 is mounted on the lower surface 111b side of the insulating layer 111 (step S108), and the semiconductor element 130 and the other end 142 of the via 140 are temporarily joined by the sintering material 131. FIG. 10 is a diagram showing a specific example of the semiconductor element mounting process.

[0034] Then, the sintering material 131 applied to the end face of the other end 142 of the via 140 is sintered to the electrode of the semiconductor element 130 by heating and pressurization (step S109). As a result, the semiconductor element 130 is joined to the other end 142 of the via 140 on the lower surface 111b of the insulating layer 111, and the semiconductor device 100 is obtained.

[0035] (Modification example) Next, various modification examples of the embodiment will be described with reference to FIGS. 11 to 16. In each of the various modification examples shown below, the same parts as those in the embodiment may be denoted by the same reference numerals, and redundant descriptions may be omitted.

[0036] FIG. 11 is a diagram showing the configuration of the semiconductor device 100 according to Modification Example 1 of the embodiment. In the semiconductor device 100 according to Modification Example 1, the shape of the end face of the other end 142 of the via 140 is different from that in the embodiment.

[0037] Specifically, in Modification Example 1, a recess 143 is formed in the end face of the other end 142 of the via 140. As a result, when the semiconductor element 130 is joined to the other end 142 of the via 140 by the sintering material 131, a part of the sintering material 131 is stored in the recess 143 formed in the other end 142 of the via 140. As a result, since an anchor effect can be exhibited between the via 140 and the sintering material 131, the adhesion of the sintering material 131 to the via 140 can be improved.

[0038] Next, a method for manufacturing the semiconductor device 100 according to Modification 1 will be described. The method for manufacturing the semiconductor device 100 according to Modification 1 is basically the same as the method for manufacturing the semiconductor device 100 shown in FIG. 2. The method for manufacturing the semiconductor device 100 according to Modification 1 differs from the method for manufacturing the semiconductor device 100 shown in FIG. 2 in the contents of the wiring layer formation step (step S106) and the sintering material application step (step S107).

[0039] Specifically, in the wiring layer formation step of step S106, the electrolytic copper plating layer 153 is etched under etching conditions adjusted so that a recess corresponding to the recess 152a of the electrolytic copper plating layer 153 is formed on the end face of the other end 142 of the via 140. As a result, for example, as shown in FIG. 12, a recess 143 is formed on the end face of the other end 142 of the via 140. FIG. 12 is a diagram showing a specific example of the wiring layer formation step. The bottom surface of the recess 143 of the via 140 is curved, and the depth of the deepest part of the recess 143 is smaller than the thicknesses of the insulating layer 111 and the adhesive layer 112.

[0040] Also, in the sintering material application step of step S107, for example, as shown in FIG. 13, a part of the sintering material 131 to be applied is stored in the recess 143 formed in the other end 142 of the via 140. FIG. 13 is a diagram showing a specific example of the sintering material application step. Since an anchor effect can be exhibited between the via 140 and the sintering material 131 by storing a part of the sintering material 131 in the recess 143 of the via 140, the adhesion of the sintering material 131 to the via 140 can be improved.

[0041] FIG. 14 is a diagram showing the configuration of the semiconductor device 100 according to Modification 2 of the embodiment. The semiconductor device 100 according to Modification 2 is different from the embodiment in that it has a wiring substrate 160.

[0042] Specifically, in Modification 2, the wiring substrate 160 is joined to the surface (lower surface) opposite to the surface (upper surface) to which the via 140 of the semiconductor element 130 is joined.

[0043] The wiring board 160 has a substrate 161, upper pads 162, and lower pads 163. The substrate 161 is an insulating plate-like member and is the base material of the wiring board 160. The substrate 161 is, for example, a ceramic substrate made of ceramics such as oxide-based ceramics or non-oxide-based ceramics. As the oxide-based ceramics, for example, aluminum oxide (Al2O3), zirconia (ZrO2), etc. can be used. As the non-oxide-based ceramics, for example, aluminum nitride (AlN), silicon nitride (Si3N4), etc. can be used.

[0044] Note that the substrate 161 is not limited to a single-layer insulating member, and may be a multilayer substrate in which an insulating layer and a wiring layer are laminated. When the substrate 161 is a multilayer substrate, the wiring layers sandwiching this insulating layer are electrically connected by vias penetrating the insulating layer. As the material of the insulating layer, for example, ceramics such as oxide-based ceramics or non-oxide-based ceramics can be used. Also, as the material of the wiring layer, for example, copper (Cu) or a copper alloy can be used.

[0045] The upper pads 162 are formed on the wiring layer on the upper surface of the substrate 161 and are exposed on the upper surface of the substrate 161 for bonding the semiconductor element 130. When the lower surface of the semiconductor element 130 is bonded to the upper surface of the wiring board 160, the electrodes on the lower surface of the semiconductor element 130 are bonded to the upper pads 162 by the sintering material 171. As the material of the upper pads 162, similar to the wiring layer, for example, copper or a copper alloy can be used.

[0046] The lower pads 163 are formed on the wiring layer on the lower surface of the substrate 161. As the material of the lower pads 163, similar to the wiring layer, for example, copper or a copper alloy can be used.

[0047] When such a wiring board 160 is joined to the lower surface of the semiconductor element 130, the semiconductor element 130 will be disposed sandwiched between the wiring board 160 and the insulating base material 110. The semiconductor element 130 sandwiched between the wiring board 160 and the insulating base material 110 is resin-sealed by an insulating resin 172. That is, the space between the wiring board 160 and the insulating base material 110 is filled with the insulating resin 172, covering the semiconductor element 130. As the material of the insulating resin 172, for example, insulating resins such as polyimide-based resins and epoxy-based resins, or resin materials in which fillers such as silica and alumina are mixed into these resins can be used.

[0048] Thus, in Modification 2, by joining the wiring board 160 to the lower surface of the semiconductor element 130, the degree of freedom of the wiring layout can be improved.

[0049] Next, a manufacturing method of the semiconductor device 100 configured as described above will be described with reference to FIG. 15 while specifically giving examples. FIG. 15 is a flowchart showing the manufacturing method of the semiconductor device 100 according to Modification 2 of the embodiment. In FIG. 15, the same reference numerals are given to the same parts as in FIG. 2.

[0050] By the process of Step S108, when the semiconductor element 130 and the other end 142 of the via 140 are temporarily joined by the sintering material 131, the lower surface of the semiconductor element 130 is temporarily joined to the upper surface of the wiring board 160 by the sintering material 171 (Step S201). Specifically, for example, as shown in FIG. 16, the electrodes on the lower surface (the upper surface in FIG. 16) of the semiconductor element 130 are temporarily joined to the upper surface pads 162 by the sintering material 171. FIG. 16 is a diagram showing a specific example of the wiring board temporary joining process.

[0051] Then, the sintered material 131 applied to the end face of the other end 142 of the via 140 is sintered to the electrode of the semiconductor element 130 by heating and pressing (step S109). Simultaneously with the sintering by the sintered material 131, the electrode on the lower surface of the semiconductor element 130 is sintered to the upper surface pad 162 by the sintered material 171. That is, the semiconductor element 130 is joined to the other end 142 of the via 140 on the lower surface 111b of the insulating layer 111, and the wiring substrate 160 is joined to the lower surface of the semiconductor element 130. Thereby, an intermediate structure in which the semiconductor element 130 is sandwiched between the wiring substrate 160 and the insulating base material 110 is obtained.

[0052] Then, for example, transfer molding is performed on the intermediate structure, and the semiconductor element 130 sandwiched between the wiring substrate 160 and the insulating base material 110 is resin-sealed with the insulating resin 172 (step S202). In transfer molding, the intermediate structure is housed in a mold, and the fluidized insulating resin 172 is injected into the mold. Then, the insulating resin 172 is heated to a predetermined temperature and cured. As a result, the space between the wiring substrate 160 and the insulating base material 110 is filled with the insulating resin 172 to seal the semiconductor element 130, and the semiconductor device 100 is completed.

[0053] As described above, the semiconductor device (as an example, the semiconductor device 100) according to the embodiment includes an insulating base material (as an example, the insulating base material 110), a wiring layer (as an example, the wiring layer 120), a via (as an example, the via 140), and a semiconductor element (as an example, the semiconductor element 130). The insulating base material is composed of an insulating layer (as an example, the insulating layer 111) having an adhesive layer (as an example, the adhesive layer 112) on one surface (as an example, the upper surface 111a). The wiring layer is formed on one surface (as an example, the upper surface) of the adhesive layer. The via is formed separately from the wiring layer, penetrates the insulating layer and the adhesive layer, and is connected to the wiring layer. The semiconductor element is connected via a sintered material (as an example, the sintered material 131) to the other end (as an example, the other end 142) opposite to one end (as an example, one end 141) connected to the wiring layer of the via on the other surface (as an example, the lower surface 111b) of the insulating layer. Thereby, the connection reliability of the wiring layer can be improved.

Description of Reference Numerals

[0054] 100 Semiconductor device 110 Insulating substrate 111 Insulating layer 111a Upper surface 111b Lower surface 112 Adhesive layer 120 Wiring layer 130 Semiconductor element 131 Sintered material 140 Via 141 One end 142 The other end 143 Recess 160 Wiring board

Claims

1. An insulating substrate comprising an insulating layer having an adhesive layer on one side, A wiring layer formed on one side of the adhesive layer, A via formed separately from the wiring layer, penetrating the insulating layer and the adhesive layer, and connecting to the wiring layer, A semiconductor element connected via a sintering material to the other end of the via on the other side of the insulating layer, opposite to the one end connected to the wiring layer of the via A semiconductor device having the above components.

2. The via Has a tapered shape with a larger diameter at the other end than at the one end The semiconductor device according to claim 1, characterized in that.

3. The other end of the via Has an end face located on the same plane as the other side of the insulating layer The semiconductor device according to claim 1, characterized in that.

4. The end face Is a flat surface The semiconductor device according to claim 3, characterized in that.

5. The end face Has a recess The semiconductor device according to claim 3, characterized in that.

6. A wiring board joined to the surface of the semiconductor element opposite to the surface joined to the via The semiconductor device according to claim 1, characterized by having the above component.

7. Form a via hole penetrating the insulating layer and the adhesive layer in an insulating substrate composed of an insulating layer having an adhesive layer on one side, Lay a metal foil on one side of the adhesive layer, By metal plating, form a via connecting to the metal foil in the via hole and form a plating layer on the other side of the insulating layer, By etching, form a wiring layer from the metal foil and remove the plating layer from the other side of the insulating layer, Join a semiconductor element to the other end of the via on the other side of the insulating layer, opposite to the one end connected to the wiring layer of the via A method for manufacturing a semiconductor device, characterized by having the above steps.

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