Sequence pattern generation device and sequence synchronization method

Abstract

To provide a sequence pattern generation device with which it is made possible for the evaluation of multiple lanes to be carried out simultaneously by aligning the transmission start timing of a sequence pattern of multiple outputs.SOLUTION: The sequence pattern generation device comprises: a primary module 2 and a secondary module 3, each having two data signal outputs; and a device control unit 16 which, when synchronizing the initiation of output sequences crossing the primary module 2 and the secondary module 3, adjusts the clock phases of the primary module 2 and the secondary module 3 to match, and causes a primary data generation unit 26 of the primary module 2 and a secondary data generation unit 36 of the secondary module 3 to initiate the sequences after the clock phases of the primary data generation unit 26 and the secondary data generation unit 36 are locked.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a sequence pattern generator that generates and outputs an arbitrary sequence pattern set by a user.

Background Art

[0002] In recent years, various digital communication devices have been required to have a larger transmission capacity with the increase in the number of users and the spread of multimedia communication. As an index for evaluating the quality of digital signals in these digital communication devices, the bit error rate (BER), which is defined as the comparison between the number of bit errors occurring in the received data and the total number of received data, is known.

[0003] In the error rate measuring device for measuring the above-described bit error rate, a test signal including fixed data is transmitted to a device under test (DUT) to be tested, and the measured signal input via the DUT and a reference signal serving as a reference are compared bit by bit to measure the error rate of the measured signal.

[0004] In this type of error rate measuring device, a pulse pattern generator that generates a data signal of a predetermined pulse pattern to be input as a test signal to a DUT corresponding to recent high-speed data communication is used.

[0005] Patent Document 1 describes a pulse pattern generator that sets a slave-side phase difference target value using correction data in a storage unit while setting a master-side phase difference target value according to the frequency of a reference clock signal in order to keep the phase states of a plurality of data signals constant.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] In the standards of high-speed serial buses such as USB (Universal Serial Bus) and PCIe (Peripheral Component Interconnect Express), there is a state machine called Link Training & Status State Machine (LTSSM), which manages the initialization of communication between devices and the adjustment of link speed, etc.

[0008] Also, conventional error rate measurement devices have a function (sequence pattern function) to control the LTSSM of PCIe GEN1 to 5 and USB3.1 by quickly switching specific patterns defined by the standard from a pulse pattern generator (PPG: Pulse Pattern Generator) and transitioning to a specific state. Note that the patterns for transitioning the device under test (DUT) are defined by the standard, and the output order of these patterns can be combined and output by the sequence pattern function.

[0009] In the PCIe standard, the number of lanes is defined in variations such as x1, x2, x4, x8, x16, etc. A pattern defined for each lane is transmitted to transition the DUT to a state transition. The number of lanes varies depending on the DUT.

[0010] If there is one lane like x1, there is no need to consider the operation of other lanes. However, for example, in order to simultaneously transition the state of a DUT with multiple lanes such as x2 or x4, since an allowable Skew, which is the allowable value of the phase shift time between lanes of the pattern input to the DUT, is defined, it is necessary to transmit the sequence pattern of each lane to the DUT within the range of the shift corresponding to the allowable Skew.

[0011] When evaluating a DUT with multiple lanes, the current sequence pattern transmitter cannot control the skew of each lane, so it cannot transmit the sequence pattern within the skew range allowed by PCIe.

[0012] Therefore, the operation of each lane is individually checked to confirm the operation of the DUT with multiple lanes.

[0013] Therefore, an object of the present invention is to provide a sequence pattern generator that can simultaneously evaluate multiple lanes by aligning the transmission start timings of sequence patterns of multiple outputs.

Means for Solving the Problems

[0014] The sequence pattern generator of the present invention is a sequence pattern generator in which at least one module having an output of at least one data signal can be mounted, and the total number of outputs of the data signals is two or more. When synchronizing the start of the output sequence across the modules, the phases of the clocks of all the modules having the outputs to be synchronized are aligned, and after the phase of the clock of the data generation unit of the module is locked, a device control unit that starts the sequence is provided.

[0015] With this configuration, when synchronizing the start of the output sequence across the modules, the phases of the clocks of all the modules having the outputs to be synchronized are aligned, and after the phase of the clock of the data generation unit of the module is locked, the sequence is started. Therefore, by aligning the transmission start timings of the sequence patterns of multiple outputs, it is possible to simultaneously evaluate multiple lanes.

[0016] In addition, the sequence synchronization method of the sequence pattern generator of the present invention is a sequence synchronization method of a sequence pattern generator capable of mounting at least one module having an output of at least one data signal, and the total number of outputs of the data signal is two or more. When synchronizing the start of the output sequence across the modules, the method includes the steps of aligning the phases of the clocks of all the modules having the outputs to be synchronized, and starting the sequence after the phase of the clock of the data generation unit of the module is locked.

[0017] With this configuration, when synchronizing the start of the output sequence across the modules, the phases of the clocks of all the modules having the outputs to be synchronized are aligned, and the sequence is started after the phase of the clock of the data generation unit of the module is locked. Therefore, by aligning the transmission start timings of the sequence patterns of the plurality of outputs, it is possible to simultaneously perform the evaluation of the plurality of lanes.

Effect of the Invention

[0018] The present invention can provide a sequence pattern generator capable of simultaneously performing the evaluation of a plurality of lanes by aligning the transmission start timings of the sequence patterns of the plurality of outputs.

Brief Description of the Drawings

[0019]

Figure 1

Figure 2

Embodiments for Carrying Out the Invention

[0020] Hereinafter, with reference to the drawings, the sequence pattern generator according to the embodiment of the present invention will be described in detail.

[0021] In FIG. 1, a sequence pattern generator 1 according to an embodiment of the present invention includes a primary module 2 and a secondary module 3, each of which can output two data signals. The primary module 2 and the secondary module 3 are connected by wiring via a bridge route 4. Note that the primary module 2 and the secondary module 3 may output one data signal or two or more data signals.

[0022] The primary module 2 and the secondary module 3 are detachably provided in a slot (not shown) of the apparatus main body of the measuring apparatus 11. As shown in FIG. 1, in the slot (not shown) of the measuring apparatus 11, in addition to the primary module 2 and the secondary module 3, a plurality of modules such as a clock module 12 and a measurement module 13 are detachably provided.

[0023] As shown in FIG. 1, the measuring apparatus 11 includes an operation unit 14, a display unit 15, and an apparatus control unit 16. A plurality of modules (such as the primary module 2, the secondary module 3, the clock module 12, and the measurement module 13) selected according to the measurement content can be freely added, removed, and recombined with respect to a slot (not shown), and various measurements of a measurement object based on a standard can be performed in various forms.

[0024] The clock module 12 is composed of a clock generator and generates a reference clock signal (1 / 2 half-rate clock or full-rate clock) for input to the primary module 2 and the secondary module 3.

[0025] Note that the clock module 12 is not limited to a configuration that is detachably provided in a slot (not shown) of the measuring apparatus 11, and an external clock generator separate from the measuring apparatus 11 can also be used.

[0026] The measurement module 13 performs various measurements of the measurement object based on the set values of the measurement parameters set by the operation of the operation unit 14.

[0027] The operation unit 14 includes, for example, a pointing device such as a mouse or a touch screen for operating a pointer or an icon on the display screen of the display unit 15, keys, switches, buttons, etc. provided on the apparatus main body of the measuring device 11. The operation unit 14 performs various operations related to measurement, such as an initial value (minimum value or maximum value) of the bit rate that can be generated by the sequence pattern generator 1, an initial division ratio of the primary division unit 21 and the secondary division unit 31 described later of the primary module 2 and the secondary module 3, an initial delay amount of each delay circuit unit 22, 23, 24 of the primary module 2 and each delay circuit unit 32, 33, 34 of the secondary module 3, an allowable range of the phase difference target value of the primary phase comparison unit 25 and the secondary phase comparison unit 35, etc. in addition to initial settings, instructions for starting and stopping measurement, designation of a measurement channel for setting measurement parameters, and setting / change / reference of measurement parameters on the setting screen.

[0028] The display unit 15 is composed of, for example, a liquid crystal display provided on the apparatus main body of the measuring device 11, and displays a setting screen for performing initial settings by the operation unit 14, a setting screen for a predetermined measurement channel, a measurement screen, etc. on the display screen.

[0029] The apparatus control unit 16 is composed of, for example, a microcomputer equipped with a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), etc., and includes setting control of each module based on the operation of the operation unit 14, variable control of the bit rate, output control of the reference clock signal, various measurement controls of the object to be measured based on the measurement signal, display control of the setting screen and the measurement screen, etc., and comprehensively controls the primary module 2, the secondary module 3, the clock module 12, the measurement module 13, the operation unit 14, and the display unit 15.

[0030] Next, the configurations of the primary module 2 and the secondary module 3 that constitute the sequence pattern generator 1 will be described.

[0031] As shown in FIG. 1, the primary module 2 includes a primary frequency divider 21, a primary first delay circuit section 22, a primary second delay circuit section 23, a primary third delay circuit section 24, a primary phase comparator 25, a primary data generator 26, a primary first data multiplexer 27, a primary second data multiplexer 28, and a primary control section 29.

[0032] The primary frequency divider 21 is composed of a 1 / N frequency divider (N: a positive integer of 2 or more), divides a reference clock signal generated by the clock module 12 or an external clock source by 1 / N, and inputs the divided clock signal divided by 1 / N to the primary first delay circuit section 22 and the primary phase comparator 25.

[0033] The reference clock signal is a half-rate clock or a full-rate clock having an operable frequency of the sequence pattern generator 1 (for example, 1.25 GHz to 16 GHz), and is generated by, for example, a clock source prepared by a user, an internal synthesizer incorporated in the measuring device 11 together with the sequence pattern generator 1, an external synthesizer separate from the measuring device 11, and the like. Then, reference clock signals having the same phase are input to the primary module 2 and the secondary module 3.

[0034] The primary first delay circuit section 22 is composed of, for example, an IQ modulator, and the primary control section 29 controls the primary first delay circuit section 22 to vary the phase angle of the divided clock signal from the primary frequency divider 21 and adjust the delay amount so that the data signals (parallel data) input from the primary data generator 26 to the primary first data multiplexer 27 and the primary second data multiplexer 28 and the reference clock signal have an optimal phase relationship. The divided clock signal with the adjusted delay amount is input to the primary phase comparator 25 via the primary second delay circuit section 23, and is also input to the secondary second delay circuit section 33 and the secondary third delay circuit section 34 of the secondary module 3 via the bridge route 4.

[0035] The primary second delay circuit section 23 is composed of, for example, an electronic delay in which delay elements (gate delays) that perform switching in units of several picoseconds electrically are connected in multiple stages to adjust the delay amount of the divided clock signal. The primary second delay circuit section 23 functions as a bypass circuit that allows the divided clock signal whose delay amount has been adjusted by the primary first delay circuit section 22 to pass through as it is and inputs it to the primary phase comparison section 25.

[0036] The primary third delay circuit section 24 is composed of the same electronic delay as the primary second delay circuit section 23 and includes the same number of electronic delays as the number of transmission lanes of the parallel data generated by the primary data generation section 26. For example, if the number of transmission lanes of the parallel data is 8, the primary third delay circuit section 24 is composed of 8 electronic delays. This primary third delay circuit section 24 appropriately adjusts the delay amount for each data under the control of the primary control section 29 in order to perform skew adjustment of each data of the parallel data input from the primary data generation section 26 to the primary first data multiplexing section 27 and the primary second data multiplexing section 28.

[0037] The primary phase comparison section 25 compares the phase of the divided clock signal P1 input from the primary division section 21 with the phase of the divided clock signal P2 input from the primary division section 21, passing through the primary first delay circuit section 22 and input from the primary second delay circuit section 23 via the bridge route 4, treating them as clock and data input to the primary first data multiplexing section 27 and the primary second data multiplexing section 28, and outputs a phase difference signal (voltage signal) P2 - P1 corresponding to the phase difference to the primary control section 29.

[0038] The primary data generation unit 26 is provided on one FPGA (Field Programmable Gate Array) capable of partial configuration, and generates parallel data of a predetermined number of transmission lanes (e.g., 4 Gbps × 8 channels) at the timing of the divided clock signal from the primary third delay circuit unit 24 as a data signal of an arbitrary pulse pattern set by the user, and outputs it to the primary first data multiplexing unit 27 and the primary second data multiplexing unit 28.

[0039] The primary first data multiplexing unit 27 and the primary second data multiplexing unit 28 are composed of, for example, a multiplexer (MUX), a D-type flip-flop circuit, etc., and multiplex and output the parallel data input from the primary data generation unit 26 into serial data at the timing of the reference clock signal.

[0040] The primary control unit 29 comprehensively controls the primary division unit 21, each delay circuit unit 22, 23, 24 of the primary module 2, the primary phase comparison unit 25, the primary data generation unit 26, the primary first data multiplexing unit 27, and the primary second data multiplexing unit 28 so as to synchronize and output the phases of a plurality of data signals according to an arbitrary pulse pattern set by the user.

[0041] The primary control unit 29 stores, as correction data, the primary side phase difference target value targeted by the primary phase comparison unit 25 of the primary module 2 in association with each predetermined step of the frequency (bit rate) of the reference clock signal and tabulates it.

[0042] The primary control unit 29 sets the primary side phase difference target value targeted by the primary phase comparison unit 25 of the primary module 2 according to the frequency (bit rate) of the reference clock signal.

[0043] Note that the primary-side phase difference target value corresponds one-to-one to each frequency (bit rate) of the reference clock signal. For example, if the reference clock signal is a half-rate clock, it consists of a fixed allowable range with the maximum allowable value and the minimum allowable value being the values shifted by ±1 cycle from the center voltage value (for example, ±31.25 psec in the case of 32 Gbit / s, corresponding to the cycle at which the turning of the primary division section 21 changes). Also, if the reference clock signal is a full-rate clock, it consists of a fixed allowable range with the maximum allowable value and the minimum allowable value being the values shifted by ±0.5 cycle from the center voltage value.

[0044] Also, when setting the primary-side phase difference target value at the frequency (bit rate) of the reference clock signal not stored in the primary control unit 29, it is calculated by linear interpolation from the correction data at two points at the frequencies (bit rates) of the reference clock signals before and after the frequency (bit rate) of that reference clock signal.

[0045] The primary control unit 29 adjusts and controls the delay amounts of the respective delay circuit sections 22, 23, and 24 of the primary module 2. Specifically, when initial setting is performed by the operation unit 14, the primary control unit 29 adjusts and controls the respective delay circuit sections 22, 23, and 24 of the primary module 2 to the initial delay amounts.

[0046] Also, when the primary control unit 29 outputs while keeping the pattern generation timings of the four data signals constant, it adjusts and controls the delay amount of the primary second delay circuit section 23 so that the voltage read value (voltage value corresponding to the phase difference signal P2 - P1) of the primary phase comparison section 25 becomes approximately equal to the center voltage value.

[0047] Similar to the primary module 2, the secondary module 3 is configured to include a secondary division section 31, a secondary first delay circuit section 32, a secondary second delay circuit section 33, a secondary third delay circuit section 34, a secondary phase comparison section 35, a secondary data generation section 36, a secondary first data multiplexing section 37, a secondary second data multiplexing section 38, and a secondary control unit 39.

[0048] Similar to the primary frequency division section 21 of the primary module 2, the secondary frequency division section 31 is composed of a 1 / N frequency divider (N: a positive integer of 2 or more), divides a reference clock signal having the same phase as the reference clock signal input to the primary frequency division section 21 of the primary module 2 by 1 / N, and inputs this 1 / N-divided frequency division clock signal to the secondary first delay circuit section 32 and the secondary phase comparison section 35.

[0049] The secondary first delay circuit section 32 is composed of an IQ modulator, similar to the primary first delay circuit section 22 of the primary module 2. Although this secondary first delay circuit section 32 is an originally unnecessary configuration, it is provided to achieve commonality between the primary module 2 and the secondary module 3. Here, the output of the secondary first delay circuit section 32 is open so that no output is generated anywhere even when a frequency division clock signal is input from the secondary frequency division section 31.

[0050] Similar to the primary second delay circuit section 23 of the primary module 2, the secondary second delay circuit section 33 is composed of an electronic delay in which delay elements (gate delays) that adjust the delay amount of the frequency division clock signal by performing switching in units of several picoseconds electrically are connected in multiple stages. The secondary second delay circuit section 33 adjusts the delay amount of the frequency division clock signal received from the primary module 2 under the control of the secondary control section 39 so that the phase relationship between the data signal (parallel data) input from the secondary data generation section 36 to the secondary first data multiplexing section 37 and the secondary second data multiplexing section 38 and the reference clock signal is the same as the phase relationship between the data signal (parallel data) input to the primary first data multiplexing section 27 and the primary second data multiplexing section 28 of the primary module 2 and the reference clock signal.

[0051] Similar to the primary third delay circuit section 24 of the primary module 2, the secondary third delay circuit section 34 is composed of electronic delays and has the same number of electronic delays as the number of transmission lanes of the parallel data generated by the secondary data generation section 36. This secondary third delay circuit section 34 appropriately adjusts the delay amount for each data under the control of the secondary control section 39 in order to perform skew adjustment of each data of the parallel data input from the secondary data generation section 36 to the secondary first data multiplexing section 37 and the secondary second data multiplexing section 38.

[0052] The secondary phase comparison section 35 compares the divided clock signal S1 from the secondary frequency division section 31 with the divided clock signal S2 input from the secondary second delay circuit section 33 via the bridge root 4 from the primary first delay circuit section 22 of the primary module 2, and outputs a phase difference signal (voltage signal) corresponding to the phase difference S2 - S1 to the secondary control section 39.

[0053] Similar to the primary data generation section 26 of the primary module 2, the secondary data generation section 36 is provided on one FPGA capable of partial configuration, and generates parallel data (for example, 4 Gbps × 8 channels) of a predetermined number of transmission lanes at the timing of the divided clock signal from the secondary third delay circuit section 34 as a data signal of an arbitrary pulse pattern set by the user, and outputs it to the secondary first data multiplexing section 37 and the secondary second data multiplexing section 38.

[0054] Similar to the primary first data multiplexing section 27 and the primary second data multiplexing section 28 of the primary module 2, the secondary first data multiplexing section 37 and the secondary second data multiplexing section 38 are composed of, for example, a multiplexer (MUX), a D-type flip-flop circuit, etc., and multiplex the parallel data input from the secondary data generation section 36 into serial data at the timing of the reference clock signal and output it.

[0055] The secondary control unit 39 comprehensively controls the secondary frequency division unit 31, the delay circuit units 32, 33, 34 of the secondary module 3, the secondary phase comparison unit 35, the secondary data generation unit 36, the secondary first data multiplexing unit 37, and the secondary second data multiplexing unit 38 so as to synchronize and output the phases of a plurality of data signals according to an arbitrary pulse pattern set by the user.

[0056] The secondary control unit 39 stores, as correction data tabulated by associating, for each predetermined step of the frequency (bit rate) of the reference clock signal, the secondary side phase difference target value targeted by the secondary phase comparison unit 35 of the secondary module 3 and the error of the delay amount caused by the characteristics and wiring variations of the delay circuit units 22, 23, 24 of the primary module 2 and the delay circuit units 32, 33, 34 of the secondary module 3, and the phase shift associated with the deterioration of the duty ratios of the primary frequency division unit 21 and the secondary frequency division unit 31.

[0057] Note that the correction value is a value obtained by subtracting the primary side phase difference target value (voltage reading value) from the secondary side phase difference target value (voltage reading value).

[0058] The secondary control unit 39 sets the secondary side phase difference target value targeted by the secondary phase comparison unit 35 of the secondary module 3 according to the frequency (bit rate) of the reference clock signal.

[0059] Note that the secondary side phase difference target value corresponds one-to-one to each frequency (bit rate) of the reference clock signal. For example, if the reference clock signal is a half-rate clock, it consists of a fixed allowable range with the maximum allowable value and the minimum allowable value being values shifted by ±1 cycle (for example, ±31.25 psec in the case of 32 Gbit / s: corresponding to the cycle in which the roll of the secondary frequency division unit 31 changes) from the center voltage value. Also, if the reference clock signal is a full-rate clock, it consists of a fixed allowable range with the maximum allowable value and the minimum allowable value being values shifted by ±0.5 cycle from the center voltage value.

[0060] Also, when setting the secondary-side phase difference target value at the frequency (bit rate) of the reference clock signal not stored in the secondary control unit 39, it is calculated by linear interpolation from two-point correction data at the frequencies (bit rates) of the reference clock signals before and after the frequency (bit rate) of the reference clock signal.

[0061] Note that correction data can also be stored in advance, where the values obtained by adding correction values to the center voltage value, maximum value, and minimum value of the primary-side phase difference target value for each predetermined step of the frequency (bit rate) of the reference clock signal are used as the center voltage value, maximum value, and minimum value of the secondary-side phase difference target value.

[0062] The secondary control unit 39 adjusts and controls the delay amounts of the delay circuit sections 32, 33, and 34 of the secondary module 3. Specifically, when initial settings are made by the operation unit 14, the secondary control unit 39 adjusts and controls the delay circuit sections 32, 33, and 34 of the secondary module 3 to their initial delay amounts.

[0063] Also, when the secondary control unit 39 outputs while keeping the pattern generation timings of the four data signals constant, it adjusts and controls the delay amount of the secondary second delay circuit section 33 so that the voltage reading value (voltage value corresponding to the phase difference S2 - S1) of the secondary phase comparison unit 35 becomes approximately equal to the center voltage value.

[0064] Furthermore, when the secondary control unit 39 determines that the voltage reading value (voltage value corresponding to the phase difference signal P2 - P1) of the primary phase comparison unit 25 of the primary module 2 is not equal to the voltage reading value (voltage value corresponding to the phase difference signal S2 - S1) of the secondary phase comparison unit 35 of the secondary module 3, it adjusts and controls the delay amount of the secondary second delay circuit section 33 so that the phase advances or delays by the reciprocal multiple of the reference clock signal according to the change state of the voltage reading value of the secondary phase comparison unit 35 of the secondary module 3.

[0065] For example, when the reference clock signal is a half-rate clock, if the change state of the voltage reading value of the secondary phase comparison unit 35 is rising on the right shoulder, the delay amount of the secondary second delay circuit unit 33 is adjusted and controlled so that the phase advances by 2UI. On the contrary, if the change state of the voltage reading value of the secondary phase comparison unit 35 is falling on the right shoulder, the delay amount of the secondary second delay circuit unit 33 is adjusted and controlled so that the phase is delayed by 2UI.

[0066] When the secondary control unit 39 outputs while keeping the pattern generation timing of the four data signals constant after the initial setting, when the bit rate is variably changed by a predetermined amount, the secondary frequency division unit 31 is inhibited from operating.

[0067] When the secondary control unit 39 variably changes the bit rate from the initial value (the minimum value or the maximum value of the bit rate range) by a predetermined amount and inhibits the secondary frequency division unit 31, the voltage reading value (the voltage value corresponding to the phase difference signal P2 - P1) of the primary phase comparison unit 25 of the primary module 2 and the voltage reading value (the voltage value corresponding to the phase difference signal S2 - S1) of the secondary phase comparison unit 35 of the secondary module 3 are compared, and it is determined whether the voltage reading values of both are equal (whether P2 - P1 = S2 - S1).

[0068] By the way, in the configuration of FIG. 1 described above, in order to make the primary module 2 and the secondary module 3 common, the internal configurations of both modules 2 and 3 are made the same, but the secondary first delay circuit unit 32 of the secondary module 3 may be omitted.

[0069] In the sequence pattern generator 1 of the present embodiment, each of the primary module 2 and the secondary module 3 has two outputs (referred to as Data1 and Data2), and a maximum of four data signals can be output. If a module is added, the number of outputs is not limited to this number and can be increased.

[0070] The sequence pattern generator 1 of the present embodiment can output a plurality of data signals in synchronization.

[0071] The operations are different when synchronizing two outputs within Modules 2 and 3 and when synchronizing outputs across Modules 2 and 3. The settings of the outputs to be synchronized are input by operations on the operation unit 14 and stored in the device control unit 16.

[0072] When synchronizing two outputs within Modules 2 and 3, when transmission start is selected for any one of the outputs by input to the operation unit 14, the device control unit 16 sends a reset request for the sequence internal circuit to the control units 29 and 39 of Modules 2 and 3.

[0073] When the control units 29 and 39 receive a reset request for the sequence internal circuit, they reset the data generation units 26 and 36. When the reset of the data generation units 26 and 36 is completed, the control units 29 and 39 send the completion of the reset to the device control unit 16. Note that the data generation units 26 and 36 enter a reset state when the reset is completed.

[0074] When the device control unit 16 receives the completion of the reset from the control units 29 and 39, it sends a reset release to the control units 29 and 39.

[0075] When the control units 29 and 39 receive the reset release, they release the reset state of the data generation units 26 and 36. When the reset state of the data generation units 26 and 36 is released, the data generation units 26 and 36 start generating sequence data and output it to the first data multiplexing units 27 and 37 and the second data multiplexing units 28 and 38.

[0076] In this way, when synchronizing two outputs within Modules 2 and 3, since clock synchronization is established within Modules 2 and 3, by releasing the reset after resetting the data generation units 26 and 36, the sequence can be started and the sequence outputs can be synchronized.

[0077] When synchronizing the outputs across Modules 2 and 3, when transmission start is selected for any one of the outputs to be synchronized by an input to the operation unit 14, the device control unit 16 sets all the outputs to be synchronized to the state where transmission start is selected.

[0078] The device control unit 16 causes the control units 29 and 39 to perform clock phase control so that the clocks of all the modules having the outputs to be synchronized match.

[0079] After the clock phase control is completed, the device control unit 16 waits for the clock phases of the data generation units 26 and 36 of all the modules having the outputs to be synchronized to lock.

[0080] The data generation units 26 and 36 are configured by FPGAs, and clocks are input to the transceivers of the FPGAs. The transceivers of the FPGAs perform clock division and multiplication internally, and here a PLL (phase locked loop) is used. When the frequency and phase of the input clock change significantly, the phase lock is lost.

[0081] Therefore, the device control unit 16 waits from the state where the phase lock of the data generation units 26 and 36 is lost until the phase is locked. Until the phase is locked, the clock output from the PLL is unstable, and a stable clock can be obtained after the phase lock.

[0082] When the clock phases of the data generation units 26 and 36 of all the modules having the outputs to be synchronized are locked, the device control unit 16 sends a reset request for the sequence internal circuit to the control units 29 and 39 of all the modules having the outputs to be synchronized.

[0083] When the control units 29 and 39 receive a reset request from the internal circuit of the sequence, they reset the data generation units 26 and 36. When the reset of the data generation units 26 and 36 is completed, the control units 29 and 39 send a reset completion signal to the device control unit 16. Note that when the reset is completed, the data generation units 26 and 36 enter a reset state.

[0084] When the device control unit 16 receives a reset completion signal from the control units 29 and 39, it sends a reset release signal to the control units 29 and 39.

[0085] When the control units 29 and 39 receive a reset release signal, they release the reset state of the data generation units 26 and 36. When the reset state of the data generation units 26 and 36 is released, they start generating sequence data and output it to the first data multiplexing units 27 and 37 and the second data multiplexing units 28 and 38.

[0086] In this way, when synchronizing the outputs across modules 2 and 3, the phases of the clocks of all the modules having the outputs to be synchronized are aligned. After the phases of the clocks of the data generation units 26 and 36 are locked, the sequence is started, so that the transmission start timings of the sequence patterns of the multiple outputs can be made consistent.

[0087] The sequence start process by the sequence pattern generation device 1 according to the present embodiment configured as described above will be described with reference to FIG. 2. Note that the sequence start process described below starts when, based on an input to the operation unit 14, transmission start is selected for any one of the outputs to be synchronized.

[0088] In step S1, the device control unit 16 determines whether the synchronization setting is inter-module synchronization.

[0089] If it is determined that it is inter-module synchronization, the device control unit 16 executes the process of step S2. If it is determined that it is not inter-module synchronization, the control unit 6 executes the process of step S5.

[0090] In step S2, the device control unit 16 sets all the outputs to be synchronized to the state where transmission start is selected. After executing the process of step S2, the device control unit 16 executes the process of step S3.

[0091] In step S3, the device control unit 16 causes the control units 29 and 39 to perform clock phase control so that the clocks of all the modules having the outputs to be synchronized match. After executing the process of step S3, the device control unit 16 executes the process of step S4.

[0092] In step S4, the device control unit 16 waits for the clock phases of the data generation units 26 and 36 of all the modules having the outputs to be synchronized to lock. After executing the process of step S4, the device control unit 16 executes the process of step S5.

[0093] In step S5, the device control unit 16 causes the control units 29 and 39 of all the modules having the outputs to be synchronized to reset the data generation units 26 and 36. After executing the process of step S5, the device control unit 16 executes the process of step S6.

[0094] In step S6, the device control unit 16 determines whether or not the reset of the data generation units 26 and 36 has been completed.

[0095] If it is determined that the reset of the data generation units 26 and 36 has been completed, the device control unit 16 executes the process of step S7. If it is determined that the reset of the data generation units 26 and 36 has not been completed, the device control unit 16 executes the process of step S6.

[0096] In step S7, the device control unit 16 causes the control units 29 and 39 of all the modules having the outputs to be synchronized to release the reset state of the data generation units 26 and 36. After executing the process of step S7, the data generation units 26 and 36 execute the process of step S8.

[0097] In step S8, the data generation units 26 and 36 start transmitting the sequence pattern. After executing the process of step S8, the device control unit 16 ends the sequence start process.

[0098] As described above, in the above embodiment, when the device control unit 16 synchronizes the outputs across the modules 2 and 3, it aligns the phases of the clocks of all the modules having the outputs to be synchronized, and after the phases of the clocks of the data generation units 26 and 36 are locked, it starts the sequence.

[0099] Thereby, it is possible to align the transmission start timings of the sequence patterns of the plurality of outputs, and it is possible to simultaneously perform the evaluation of the plurality of lanes.

[0100] Note that, in the present embodiment, the measurement device 11 is shown having the operation unit 14, the display unit 15, and the device control unit 16, but a personal computer connected to the measurement device 11 may substitute for the functions of the operation unit 14, the display unit 15, and the device control unit 16.

[0101] Although embodiments of the present invention have been disclosed, it is obvious that changes can be made by those skilled in the art without departing from the scope of the present invention. It is intended that all such modifications and equivalents be included in the following claims.

Explanation of Reference Numerals

[0102] 1 Sequence Pattern Generator 2 Primary Module 3 Secondary Module 14 Operation Unit 15 Display Unit 16 Device Control Unit 26 Primary Data Generation Unit 29 Primary Control Unit 36 Secondary Data Generation Unit 39 Secondary Control Unit

Claims

1. A sequence pattern generator (1) capable of mounting at least one module (2, 3) having an output of at least one data signal, wherein the total number of outputs of the data signals is two or more, When synchronizing the start of the output sequence across the modules, the phase of the clocks of all the modules having the outputs to be synchronized is adjusted, and a device control unit (16) that starts the sequence after the phase of the clock of the data generation units (26, 36) of the modules is locked. A sequence pattern generator comprising.

2. A sequence synchronization method for a sequence pattern generator (1) capable of mounting at least one module (2, 3) having an output of at least one data signal, wherein the total number of outputs of the data signals is two or more, When synchronizing the start of the output sequence across the modules, the step of adjusting the phase of the clocks of all the modules having the outputs to be synchronized; And a step of starting the sequence after the phase of the clock of the data generation units (26, 36) of the modules is locked. A sequence synchronization method comprising.

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