Power conversion circuit, power module, converter, and inverter

Abstract

To prevent a short circuit between a switching element and a synchronous rectifier element and reduce power loss thereof.SOLUTION: Provided is a power conversion circuit in which a switching transistor and a synchronous rectifier transistor are connected in series, and a source inductance of the switching transistor is smaller than a source inductance of the synchronous rectifier transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This embodiment relates to a power conversion circuit, a power module, a converter, and an inverter.

Background Art

[0002] In a half-bridge circuit or a full-bridge circuit in which two elements (a switching element and a synchronous rectifier element) are connected in series, if the two elements are turned on simultaneously, a short circuit occurs between the power supply and the ground, and a large through-current flows. The large through-current causes losses in the switching element or may even destroy the switching element itself.

[0003] To suppress the through-current, a dead time (a pause period) is required during which all elements are turned off during the transition period of the on / off state of the elements. However, when turning on one element from the dead time state in which all elements are turned off, a phenomenon (false turn-on or false conduction) may occur in which the gate of the other element turns on due to a change in the drain voltage. This is a problem that can occur, for example, in a three-phase inverter for motor drive or a DC / DC converter for synchronous rectification.

[0004] In recent years, many research institutions have been conducting research and development on silicon carbide (SiC) devices. Characteristics of SiC power devices include lower on-resistance, faster switching, and higher temperature operation compared to conventional Si power devices.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] Generally, when using a high-speed switching element, a source sense signal wiring is connected to the switching element. Since the electromotive force of the inductance of the source of the switching element does not affect the gate circuit and a potential difference sufficient for charging the gate oxide film of the switching element can be ensured, the current change rate can be increased. As a result, the loss (switching loss) generated when the switching element is turned on / off is reduced.

[0007] On the other hand, in the voltage change region, since only the charge / discharge current contributes to the current change, the contribution is relatively small, and the difference in the voltage change of the switching element due to the presence or absence of the source sense signal wiring connection is small and almost the same.

[0008] Also, the switching characteristics of the synchronous rectifier element are determined by the operation of the switching element. In a half-bridge circuit, a short circuit of the switching element and the synchronous rectifier element connected in series due to mis-turn-on of the synchronous rectifier element has been a problem.

[0009] The short circuit occurs in the voltage change region, but the electromotive force of the inductance of the source on the reflux side in the current change region that occurs before the voltage change region greatly affects the short circuit. The direction of the electromotive force of the inductance of the source of the synchronous rectifier element in the current change region is the same as the direction of the electromotive force of the inductance of the source of the switching element, and the voltage of the gate oxide film of each element in the voltage change region rises in the positive direction.

[0010] In the synchronous rectifier element not connected to the source sense signal wiring, since the inductance of the source is shared with the gate circuit, the electromotive force charges the gate oxide film negatively. For this reason, the starting point of the voltage rise in the voltage change region becomes low and a short circuit is less likely to occur.

[0011] In the element connected to the source sense signal wiring, since the source signal wiring is separated, the electromotive force of the inductance of the source does not affect the voltage of the gate oxide film. For this reason, it is easily affected by the voltage rise in the voltage change region and a short circuit is likely to occur.

[0012] The short circuit increases the power loss of the element. A half-bridge circuit composed of elements connected to the source sense signal wiring may lose the advantage of low power loss obtained by improving the switching characteristics of the elements connected to the source sense signal wiring due to the short circuit.

[0013] In order to suppress the short circuit, it is necessary to suppress the mis-turn-on of the synchronous rectifier element. However, the switching characteristics including the synchronous rectifier element are determined by the switching element.

[0014] One aspect of the present embodiment provides a power conversion circuit that suppresses short circuits of the switching element and the synchronous rectifier element and reduces power loss. Another aspect of the present embodiment provides a power module including the power conversion circuit. Another aspect of the present embodiment provides a converter and an inverter including the power module.

Means for Solving the Problems

[0015] In the present embodiment, in the power conversion circuit, by using in combination a switching element connected to the source sense signal wiring and a synchronous rectifier element not connected to the source sense signal wiring, while taking advantage of the switching characteristics of the switching element connected to the source sense signal wiring, the short circuit of the synchronous rectifier element is suppressed.

[0016] One aspect of the present embodiment is a power conversion circuit in which a switching transistor and a synchronous rectifier transistor are connected in series, and the inductance of the source of the switching transistor is smaller than the inductance of the source of the synchronous rectifier transistor.

[0017] Another aspect of the present embodiment is a power module including the power conversion circuit.

[0018] Another aspect of the present embodiment has a function of exciting a first inductor, a first transistor connected to a first source sense signal wiring, and a second transistor having a function of releasing the power stored in the first inductor. The first gate signal wiring and the first source sense signal wiring are electrically connected to the gate of the first transistor, and the second gate signal wiring and the first source signal wiring are electrically connected to the gate of the second transistor. The first transistor is connected in series with the second transistor, and the first inductor is a power module connected to a connection point between the first transistor and the second transistor.

[0019] Another aspect of the present embodiment is a converter or an inverter including the power module.

Advantages of the Invention

[0020] According to the present embodiment, it is possible to provide a power conversion circuit that suppresses short circuits of switching elements and synchronous rectifying elements and reduces power loss. Further, another embodiment can provide a power module including the power conversion circuit. Further, another embodiment can provide a converter and an inverter including the power module.

Brief Description of the Drawings

[0021]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

DETAILED DESCRIPTION OF THE INVENTION

[0022] Next, with reference to the drawings, this embodiment will be described. In the description of the drawings below, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions of each component is different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Also, it goes without saying that there are portions where the dimensional relationships and ratios are different between the drawings.

[0023] Also, the embodiments shown below are examples of devices and methods for embodying the technical idea, and do not specify the materials, shapes, structures, arrangements, etc. of each component. Various modifications can be made to this embodiment within the scope of the claims.

[0024] One aspect of this embodiment is as follows.

[0025] [1] A power conversion circuit in which a switching transistor and a synchronous rectifier transistor are connected in series, and the inductance of the source of the switching transistor is smaller than the inductance of the source of the synchronous rectifier transistor.

[0026] [2] The power conversion circuit according to [1], further comprising a capacitor electrically connected to the switching transistor and the synchronous rectifier transistor.

[0027] [3] The power conversion circuit according to [2], further comprising an output terminal electrically connected to the capacitor.

[0028] [4] The power conversion circuit according to any one of [1] to [3], further comprising a power terminal electrically connected to the drain of the switching transistor.

[0029] [5] A power module including the power conversion circuit according to any one of [1] to [4].

[0030] [6] A power module having a function of exciting a first inductor, a first transistor connected to a first source sense signal wiring, a second transistor having a function of discharging power accumulated in the first inductor, a first gate signal wiring and the first source sense signal wiring electrically connected to the gate of the first transistor, and a second gate signal wiring and a first source signal wiring electrically connected to the gate of the second transistor, wherein the first transistor is connected in series with the second transistor, and the first inductor is connected to a connection point between the first transistor and the second transistor.

[0031] [7] The power module according to [6], wherein the inductance of the source of the first transistor is smaller than the inductance of the source of the second transistor.

[0032] [8] The power module according to [6] or [7], further comprising a capacitor electrically connected to the first transistor and the second transistor.

[0033] [9] The power module according to [8], further comprising an output terminal electrically connected to the capacitor.

[0034]

[10] The power module according to any one of [6] to [9], further comprising a power terminal electrically connected to the drain of the first transistor.

[0035]

[11] In the power module according to any one of [6] to

[10] , the first transistor functions as a switching element, and the second transistor functions as a synchronous rectification element.

[0036]

[12] In the power module according to any one of [6] to

[11] , the second transistor outputs a signal to the first source signal wiring via the drain of the first transistor.

[0037]

[13] In the power module according to any one of [6] to

[11] , the second transistor outputs a signal to the first source signal wiring via the source of the second transistor.

[0038]

[14] Further comprising a second source signal wiring electrically connected to the first transistor and a second source sense signal wiring electrically connected to the second transistor, and in the power module according to

[13] , the first transistor outputs a signal to the second source signal wiring via the drain of the second transistor.

[0039]

[15] The second transistor and the drain of the first transistor are connected by a first wiring, and when a signal is output from the gate of the second transistor to the first source signal wiring, the current tolerance value of the first wiring is larger than the current tolerance value of the wiring directly connected to the second gate signal wiring.

[0040]

[16] When outputting a signal from the gate of the second transistor to the first source signal wiring, the current tolerance of the second wiring via the source of the second transistor is larger than the current tolerance of the wiring directly connected to the second gate signal wiring. The power module according to

[13] .

[0041]

[17] A converter including the power module according to any one of [5] to

[16] .

[0042]

[18] An inverter including the power module according to any one of [5] to

[16] .

[0043] (Power conversion circuit) The power conversion circuit according to the present embodiment will be described.

[0044] FIG. 1 is a power conversion circuit according to an aspect of the present embodiment, and includes a transistor U1 which is a synchronous rectifier element, a transistor U4 which is a switching element, gate resistors R g1 , R g4 , and gate drive circuits V G1 , V G4 . The power conversion circuit has a plurality of metal-insulator-semiconductor field effect transistors (MISFETs). The transistor U1 includes a MISFET chip Q1 that functions as a synchronous rectifier element, and the wiring of the transistor U1 has an inductance L1. The transistor U4 includes a MISFET chip Q4 that functions as a switching element and a source sense signal wiring SS4, and the wiring of the transistor U4 has an inductance L4.

[0045] Note that a first inductor (not shown) can be connected to the connection point (● in FIG. 1) between the transistor U1 and the transistor U4. Also, the gate drive circuit V G1monitors the source of the MISFET chip Q1 via the inductance L1 of the wiring, and supplies a drive signal to the gate of the MISFET chip Q1 via the gate resistor R according to the monitoring result. Note that the inductance L1 forms the current path through which the current flowing between the source and drain of the MISFET chip Q1 flows. Also, the gate drive circuit V g1 monitors the source of the MISFET chip Q4 via the source sense signal wiring SS4, and supplies a drive signal to the gate of the MISFET chip Q4 via the gate resistor R G4 according to the monitoring result. Note that the inductance L4 forms the current path through which the current flowing between the source and drain of the MISFET chip Q4 flows, and the source sense signal wiring SS4 is a signal path provided separately from that current path. g4 Note that the MISFET chip Q4 has a function of exciting a first inductor (not shown), and the MISFET chip Q1 has a function of discharging the power stored in the first inductor. The smaller the source inductance, the more capable of high-speed switching operation. Also, the larger the source inductance, the less likely a short circuit will occur during high-speed switching operation. Therefore, a transistor with a small source inductance and provided with a source signal wiring is used as the switching element for exciting the first inductor that determines the switching characteristics, and a transistor with a large source inductance and not provided with a source signal wiring is used as the switch (synchronous rectifier element) for discharging the power stored in the inductor that determines the degree of short circuit occurrence, making it possible to configure a power conversion circuit that is high-speed, low-loss, and less likely to cause a short circuit.

[0046] The power conversion circuit shown in FIG. 1 will be described in more detail with reference to FIGS. 2 and 3. The circuits shown in FIGS. 2 and 3 are the power conversion circuit 1, which is an example of the schematic circuit configuration of a half-bridge circuit. Note that the power conversion circuit 1 according to the present embodiment is not limited to a half-bridge circuit and can also be applied to a full-bridge circuit, a three-phase bridge circuit, or the like.

[0047]

[0048] ​The power conversion circuit 1 includes the transistor U4 which is a switching element including the transistor U1 which is a synchronous rectification element and the source sense signal wiring SS4 as described above. Here, the characteristics of the element (transistor) depending on the presence or absence of connection to the source sense signal wiring will be described.

[0049] Figure 12(a) shows Circuit A including the MISFET chip Q not connected to the source sense signal wiring, and Figure 12(b) shows Circuit B including the MISFET chip Q connected to the source sense signal wiring SS.

[0050] Figure 13 shows the voltage change of the gate in the non-driven side element which is one of the switching element or the synchronous rectification element and is not performing the switching operation.

[0051] In the current change region (current change period) in the figure, in Circuit A, since the source inductance is shared with the gate circuit, the electromotive force charges the gate oxide film negatively, while in Circuit B, since the element is connected to the source sense signal wiring and the source signal wiring is separated, the electromotive force of the source inductance does not affect the voltage of the gate oxide film.

[0052] In the voltage change region (voltage change period) in the figure, in Circuit A, the starting point of the voltage rise is low, while in Circuit B, the starting point of the voltage rise is high. Circuit B is likely to exceed the threshold voltage of the element and is likely to turn on erroneously, while Circuit A is less likely to exceed the threshold voltage of the element because the starting point of the voltage rise is low and is likely to operate normally.

[0053] Therefore, in order to operate the power conversion circuit at high speed and normally, it is effective to use both a switching element connected to the source sense signal wiring and a synchronous rectifier element not connected to the source sense signal wiring. By adopting such a configuration, while taking advantage of the switching characteristics of the switching element connected to the source sense signal wiring, the starting point of the voltage rise of the synchronous rectifier element not connected to the source sense signal wiring is low, so false turn-on can be suppressed and operation stability can be ensured.

[0054] Furthermore, in the power conversion circuit of the present embodiment and the conventional power conversion circuit, the operation waveforms and losses of the transistors in the double pulse test are compared. Fig. 16 shows the circuit (DPT (Double Pulse Test) circuit) used in the double pulse test. Here, although the configurations of circuit A' and circuit B' illustrate the power conversion circuit of the present embodiment, the operation waveforms and losses of the transistors due to the differences in the configurations of circuit A' and circuit B' are compared.

[0055] As shown in Fig. 16, in the configurations of the transistors included in circuit A' and the transistors included in circuit B', the power supply E, capacitor C, inductor L, and constant current source I are connected to circuit A' and circuit B'. The transistor included in circuit A' functions as a synchronous rectifier element, and the transistor included in circuit B' functions as a switching element.

[0056] Here, the power supply E of the DPT circuit is set to 800 V, and the constant current source I is set to 16 A. Also, FIG. 17 shows a circuit diagram showing the combination of circuit A' and circuit B' of the DPT circuit. FIG. 17(a) is a circuit including a transistor (SiC MOSFET S4108 manufactured by Rohm Co., Ltd.) in which circuit A' is not connected to the source sense signal wiring, and circuit B' is a circuit including a transistor (SiC MOSFET S4108 manufactured by Rohm Co., Ltd.) connected to the source sense signal wiring. FIG. 17(b) is a combination of circuits including transistors (SCT3080KL manufactured by Rohm Co., Ltd.) in which neither circuit A' nor circuit B' is connected to the source sense signal wiring. FIG. 17(c) is a combination of circuits including transistors (SiC MOSFET S4108 manufactured by Rohm Co., Ltd.) in which both circuit A' and circuit B' are connected to the source sense signal wiring.

[0057] In the above DPT circuit, the circuit shown in FIG. 17(a) is the configuration of Example 1 including the power conversion circuit of the present embodiment, the circuit shown in FIG. 17(b) is the configuration of Comparative Example 1 including the conventional power conversion circuit, and the circuit shown in FIG. 17(c) is the configuration of Comparative Example 2 including the conventional power conversion circuit. Note that the circuit symbols and the like shown in FIGS. 17(a) to 17(c) can be the same as those shown in FIGS. 12(a) and 12(b), so they are omitted.

[0058] In the above power conversion circuit, the operation waveforms and losses of the transistors by the double pulse test are shown in FIGS. 18 and 19. FIG. 18(a) is a diagram showing the operation waveform of the gate voltage (V ox,L ) of the transistor included in circuit B'. FIG. 18(b) is a diagram showing the operation waveform of the drain current (I d,L ) of the transistor included in circuit B'. FIG. 18(c) is the operation waveform of the drain voltage (V ds,L ) of the transistor included in circuit B'. FIG. 19(a) is a diagram showing the synchronous rectifier element loss (P H (W)) of the transistor included in circuit A'. FIG. 19(b) is a diagram showing the switching element loss (P L (W)) of the transistor included in circuit B'.

[0059] As shown in Fig. 18(a), there is little difference in the operating waveform of the gate voltage among Example 1, Comparative Example 1, and Comparative Example 2. On the other hand, as shown in Fig. 18(b), regarding the operating waveform of the drain current, the change in Comparative Example 2 is large and it is in a state where it is likely to turn on erroneously, while in Example 1, the current changes gently as in Comparative Example 1. Also, as shown in Fig. 18(c), regarding the operating waveform of the drain voltage, the starting point of the voltage change in Comparative Example 1 is later than that in Comparative Example 2, while in Example 1, the starting point of the voltage change is the same as that in Comparative Example 2 and faster than that in Comparative Example 1. For this reason, as shown in Fig. 19(a), the synchronous rectifier element loss of the transistor in Example 1 is smaller than that in Comparative Example 1 and Comparative Example 2, and as shown in Fig. 19(b), the switching element loss of the transistor in Example 1 is smaller than that in Comparative Example 1 and Comparative Example 2.

[0060] As described above, by using in combination a transistor that functions as a switching element connected to the source sense signal wiring and a transistor that functions as a synchronous rectifier element not connected to the source sense signal wiring, the synchronous rectifier element loss and the switching element loss can be made smaller than those of a conventional power conversion circuit, and a power conversion circuit that operates at high speed and normally can be obtained.

[0061] Note that the power conversion circuit 1 may include a control circuit described later, and for example, may include a gate diode as shown in Fig. 3.

[0062] As shown in Fig. 3, between the externally extracted gate terminal GT1 and source terminal ST1 and the gate G1 and source S1 of the MISFET chip Q1, there are parasitic inductances L GP1 and L SP1exists, and between the gate terminal GT4 and source sense terminal SST4 for external extraction and the gate G4 of the MISFET chip Q4 and the source sense signal wiring SS4, there are parasitic inductances L GP4 and L SP4 existing. Since such inductance components exist in the gate closed circuit of the MISFET chip, they cause an increase in the operation delay in the gate drive of the MISFET chip and the voltage fluctuation between the gate and source sense during the voltage change between the drain and source.

[0063] To suppress the parasitic effects caused by such inductance components, the shorter the distance from the cathode and anode of the diode to the gate pad electrode and source pad electrode, the higher the effect. The gate pad electrode and source pad electrode of the MISFET are formed on the surface of the MISFET. Therefore, even if the gate diode is fabricated within the same chip as the MISFET, it may be configured to directly solder the anode of the gate diode chip onto the source pad electrode of the MISFET.

[0064] Also, the gate diodes may be collectively arranged for each MISFET arranged in parallel, but it is more effective to connect them individually for each of the plurality of MISFETs.

[0065] Also, the MISFET can be composed of a SiC MISFET. Here, FIG. 4 shows a schematic cross-sectional structure of a SiC DI (Double Implanted) MISFET, which is an example of the semiconductor device 100 applicable to the power conversion circuit 1.

[0066] As shown in FIG. 4, the SiC DIMISFET includes a semiconductor substrate 26 made of an n - high-resistance layer, a p-body region 28 formed on the surface side of the semiconductor substrate 26, and an n +A gate insulating film 32 disposed on the surface of the semiconductor substrate 26 between the source region 30 and the p-body region 28, a gate electrode 38 disposed on the gate insulating film 32, a source electrode 34 connected to the source region 30 and the p-body region 28, and an n disposed on the back surface opposite to the surface of the semiconductor substrate 26 + drain region 24, and an n + drain electrode 36 connected to the drain region 24.

[0067] In FIG. 4, the semiconductor device 100 includes a p-body region 28 and an n formed on the surface of the p-body region 28 + The source region 30 is formed by double ion implantation (DI), and the source pad electrode SP is connected to the source electrode 34 connected to the source region 30 and the p-body region 28. The gate pad electrode (not shown) is connected to the gate electrode 38 disposed on the gate insulating film 32. Further, the source pad electrode SP and the gate pad electrode (not shown) are disposed on an interlayer insulating film 44 for passivation covering the surface of the semiconductor device 100 as shown in FIG. 4.

[0068] As shown in FIG. 4, the SiC DIMISFET has an n sandwiched between p-body regions 28 - Since a depletion layer as indicated by a broken line is formed in the semiconductor substrate 26 made of a high-resistance layer, a channel resistance R due to the junction FET (JFET) effect JFET is formed. Also, a body diode BD is formed between the p-body region 28 and the semiconductor substrate 26.

[0069] Also, the MISFET can be composed of a SiC trench (T: Trench) MISFET. Here, FIG. 5 shows a schematic cross-sectional structure of a SiC TMISFET which is an example of the semiconductor device 100 applicable to the power conversion circuit 1.

[0070] As shown in FIG. 5, the SiC TMISFET includes a semiconductor substrate 26N made of an n layer, a p-body region 28 formed on the surface side of the semiconductor substrate 26N, and an n formed on the surface of the p-body region 28 +The source region 30, the trench gate electrode 38TG formed through the p-body region 28 and within a trench formed down to the semiconductor substrate 26N via a gate insulating film 32 and interlayer insulating films 44U and 44B, and n + The source electrode 34 connected to the source region 30 and the p-body region 28, and n + The drain region 24, and n + The drain electrode 36 connected to the drain region 24.

[0071] In FIG. 5, in the semiconductor device 100, a trench gate electrode 38TG is formed through the p-body region 28 and within a trench formed down to the semiconductor substrate 26N via a gate insulating film 32 and interlayer insulating films 44U and 44B. The source pad electrode SP is connected to the source electrode 34 connected to the source region 30 and the p-body region 28. The gate pad electrode (not shown) is connected to the gate electrode 38 disposed on the gate insulating film 32. Also, as shown in FIG. 5, the source pad electrode SP and the gate pad electrode (not shown) are disposed on the interlayer insulating film 44U for passivation covering the surface of the semiconductor device 100.

[0072] In the SiC TMISFET, the channel resistance R associated with the junction FET (JFET) effect like that of the SiC DIMISFET is not formed. Also, a body diode BD is formed between the p-body region 28, the semiconductor substrate 26, and the n JFET drain region 24. + Moreover, for the semiconductor device 100 (MISFET chips Q1 and Q4) applicable to the power conversion circuit 1, instead of the SiC-based MISFET, a GaN-based FET or the like can also be applied.

[0073] Furthermore, for the semiconductor device 100 (MISFET chips Q1 and Q4) applicable to the power conversion circuit 1, a semiconductor having a bandgap energy of, for example, 1.1 eV to 8 eV can be used.

[0074] ​

[0075] (Modification example) Also, as shown in FIG. 6, the connection relationship between the switching element and the synchronous rectifying element of the power conversion circuit 1 may be such that the source S4 of the MISFET chip Q4 operating as a switching element is electrically connected to the drain D1 of the MISFET chip Q1 operating as a synchronous rectifying element via the inductance L4. Further, as shown in FIGS. 7 and 8, the power conversion circuit shown in FIGS. 1 and 6 may be further provided with a power supply E, a capacitor C, and an inductor L.

[0076] (Power module) As described above, the power module equipped with the power conversion circuit 1 can have a half-bridge built-in module configuration. In the power module, the MISFET chip Q1 and the MISFET chip Q4 are built in one module. In FIG. 3, an example is shown in which the MISFET chip Q1 and the MISFET chip Q4 are each arranged in parallel with four chips.

[0077] In the power module, an example of a simplified schematic planar pattern configuration is shown in FIGS. 9 to 11.

[0078] As shown in FIG. 9, the transistor including the MISFET chip Q1 includes a source signal wiring pattern SL1 and a gate signal wiring pattern GL1, and the transistor including the MISFET chip Q4 includes a source sense signal wiring pattern SSL4 and a gate signal wiring pattern GL4. The gate of the MISFET chip Q1 is directly connected to the gate signal wiring pattern GL1 via the wiring W11. Also, the gate of the MISFET chip Q1 is electrically connected to the source signal wiring pattern SL1 via the wirings W1 and W2 and the transistor including the MISFET chip Q4 (specifically, the drain D4). Since the current path through the wirings W1 and W2 and the transistor including the MISFET chip Q4 has a larger current tolerance than the current path through the wiring W11, a large current can flow. Further, the gate of the MISFET chip Q4 is directly connected to the gate signal wiring pattern GL4 and the source sense signal wiring pattern SSL4 via a wiring.

[0079] Also, as shown in FIG. 10, the transistor including the MISFET chip Q1 includes a source signal wiring pattern SL1 and a gate signal wiring pattern GL1, and the transistor including the MISFET chip Q4 includes a source sense signal wiring pattern SSL4 and a gate signal wiring pattern GL4. The gate of the MISFET chip Q1 is directly connected to the gate signal wiring pattern GL1 via the wiring W12. Also, the gate of the MISFET chip Q1 is electrically connected to the source signal wiring pattern SL1 via the wirings W3 and W4 and the source S1 of the MISFET chip Q1. Since the current path through the wirings W3 and W4 and the source S1 of the MISFET chip Q1 has a larger current tolerance than the current path through the wiring W12, a large current can flow. Further, the gate of the MISFET chip Q4 is directly connected to the gate signal wiring pattern GL4 and the source sense signal wiring pattern SSL4 via a wiring.

[0080] Also, as shown in FIG. 11, the transistor including the MISFET chip Q1 includes a source sense signal wiring pattern SSL1, a source signal wiring pattern SL1, and a gate signal wiring pattern GL1, and the transistor including the MISFET chip Q4 includes a source sense signal wiring pattern SSL4, a source signal wiring pattern SL4, and a gate signal wiring pattern GL4. The gate of the MISFET chip Q1 is directly connected to the gate signal wiring pattern GL1 via the wiring W12. Also, the gate of the MISFET chip Q1 is electrically connected to the source signal wiring pattern SL1 via the wirings W3 and W4 and the source S1 of the MISFET chip Q1. Since the current path through the wirings W3 and W4 and the source S1 of the MISFET chip Q1 has a larger current tolerance than the current path through the wiring W12, a large current can flow. Further, the gate of the MISFET chip Q4 is directly connected to the gate signal wiring pattern GL4 and the source sense signal wiring pattern SSL4 via a wiring. Also, the gate of the MISFET chip Q4 is electrically connected to the source signal wiring pattern SL4 via the wirings W1 and W2 and the transistor including the MISFET chip Q1 (specifically, the drain D1). Since the current path through the wirings W1 and W2 and the transistor including the MISFET chip Q1 has a larger current tolerance than the current path through the wiring W11, a large current can flow.

[0081] Note that in the power module shown in FIG. 11, either the MISFET chip Q1 or the MISFET chip Q4 functions as a switching element. Control may be performed such that the source sense signal wiring of the transistor including the MISFET functioning as the switching element is connected to the MISFET.

[0082] Note that each signal wiring of the power modules shown in FIGS. 9 to 11 is connected to an external extraction terminal (reference numerals omitted).

[0083] (Converter) FIG. 14 is a circuit diagram showing a current-mode synchronous rectification step-down DC / DC converter including the power module according to the present embodiment. The DC / DC converter 51 steps down an input voltage Vin supplied to an input terminal VIN and generates a desired output voltage Vout at an output terminal VOUT.

[0084] The DC / DC converter 51 includes a switching element T11, a rectifying element T12, a drive circuit 53, a feedback voltage generation circuit 56, an error amplifier 57, a phase compensation circuit 58, a PWM comparator 60, a slope voltage generation circuit 61, an inductor L11, and a smoothing capacitor C1.

[0085] The switching element T11 is an N-channel MOS (Metal Oxide Semiconductor) field effect transistor connected to the drive circuit 53, an output current detection unit 54, and the rectifying element T12, and functions as a switching transistor that repeatedly turns on and off to control the current flowing through the inductor L11. The drain D of the switching element T11 is connected to the input terminal VIN. The source S of the switching element T11 is connected to the drain D of the rectifying element T12. A gate signal GH is applied to the gate G of the switching element T11 from the drive circuit 53. Also, the source voltage of the switching element T11 is fed back to the drive circuit 53 via a source sense signal wiring SS. The switching element T11 turns off when the gate signal GH is at a low level and turns on when the gate signal GH is at a high level. The rectifying element T12 supplies current toward the inductor L11 when the switching element T11 is off.

[0086] The rectifying element T12 is an N-channel MOS field-effect transistor connected to the switching element T11 and the drive circuit 53, and operates complementarily in synchronization with the switching element T11 as a synchronous rectifying transistor. The drain D of the rectifying element T12 is connected to the source S of the switching element T11. The common connection point of the rectifying element T12 and the switching element T11 is shown as node N1. The rectifying element T12 turns on when the switching element T11 is off and is turned off when the switching element T11 is on. The source S of the rectifying element T12 is connected to the ground potential GND. A gate signal GL is applied to the gate G of the rectifying element T12 from the drive circuit 53. The rectifying element T12 turns on when the gate signal GL is at a high level and turns off when the gate signal GL is at a low level.

[0087] By turning on and off the switching element T11 and the rectifying element T12 complementarily, a rectangular-wave switching voltage Vsw appears at node N1. By smoothing this switching voltage Vsw with the inductor L11 and the smoothing capacitor C1, the output voltage Vout is taken out at the output terminal VOUT. The inductor L11 and the smoothing capacitor C1 are connected in series between node N1 and the ground potential GND, and their common connection point is shown as node N2. The voltage generated in the smoothing capacitor C1, that is, the output voltage Vout, is generated at node N2.

[0088] In the DC / DC converter 51, by using the switching element T11, the rectifying element T12, the inductor L11, and the smoothing capacitor C1, a step-down type switch output stage is formed that steps down the input voltage Vin supplied to the input terminal VIN and generates the desired output voltage Vout at the output terminal VOUT.

[0089] When integrating the components of the DC / DC converter 51 into an IC, the switching element T11 and the rectifying element T12 may be incorporated into the IC or externally attached to the IC. When externally attaching to the IC, external terminals for externally outputting the gate signal GH and the gate signal GL are required. Also, an N-channel type MOS field effect transistor can be used as the switching element T11. Further, an IGBT or the like can be used as the switching element T11 or the rectifying element T12. Also, the switching element T11 and the rectifying element T12 may be composed of bipolar transistors.

[0090] In the drive circuit 53, in order to prevent an excessive through current flowing from the switching element T11 toward the rectifying element T12, a section (so-called dead time) is provided in which the gate signal GH is at a low level and the gate signal GL is at a low level so that the gate signal GH is not at a high level and the gate signal GL is not at a high level.

[0091] Furthermore, the drive circuit 53 also has a function (a function of setting the gate signal GH output to the switching element T11 to a low level and the gate signal GL output to the rectifying element T12 to a low level) of forcibly stopping the switching operation of the switch output stage in response to an abnormality protection signal (not shown).

[0092] The feedback voltage generation circuit 56 is composed of resistors R1 and R2 connected in series between the output terminal VOUT and the ground potential GND, and outputs a feedback voltage Vfb from a node N3 which is a common connection point of the two. The feedback voltage Vfb is a voltage proportional to the voltage generated in the smoothing capacitor C1 and is also a DC voltage proportional to the output voltage Vout generated at the output terminal VOUT.

[0093] The error amplifier 57 generates an error voltage Verr in accordance with the difference between the reference voltage Vref input to the non-inverting input terminal (+) and the feedback voltage Vfb input to the inverting input terminal (-). The error voltage Verr rises when the feedback voltage Vfb is lower than the reference voltage Vref, and falls when the feedback voltage Vfb is higher than the reference voltage Vref. The error voltage Verr is output from the output side of the error amplifier 57. Note that it is also possible to convert the output from the output side of the error amplifier 57 into a current and output it instead of a voltage. An error amplifier with such a configuration is known as a transconductance error amplifier.

[0094] The phase compensation circuit 58 is composed of a series circuit of a resistor R3 and a capacitor C3 connected in series between the output terminal of the error amplifier 57 and the ground potential GND. It is well known to use such a phase compensation circuit in a DC / DC converter. The phase compensation circuit 58 is used to increase the phase margin, which is the difference with respect to a 180-degree phase delay in the DC / DC converter 51. For example, assuming that the phase when the loop gain of the DC / DC converter 51 is 0 dB (gain x1) is 120 degrees, the phase margin is 180 degrees - 120 degrees = 60 degrees. It is also said that this phase margin is sufficient if it is, for example, 45 degrees or more.

[0095] The PWM comparator 60 compares the error voltage Verr applied to the inverting input terminal (-) with the slope signal Vsl applied to the non-inverting input terminal (+) to generate a pulse width modulation signal pwm. Based on the pulse width modulation signal pwm, PWM control is performed in the DC / DC converter 51.

[0096] The pulse width modulation signal pwm output from the PWM comparator 60 is applied to the subsequent drive circuit 53 to complementarily turn on and off the switching element T11 and the rectifying element T12. Inside the drive circuit 53, a sequential circuit (for example, an RS flip-flop) (not shown) is provided. A clock signal is applied to the set terminal of this RS flip-flop, and the pulse width modulation signal pwm is applied to the reset terminal. In this case, the clock signal corresponds to the set signal of the RS flip-flop, and the pulse width modulation signal pwm corresponds to the reset signal of the RS flip-flop.

[0097] The slope voltage generation circuit 61 generates a slope signal Vsl to operate the PWM comparator 60 in pulse width modulation. The slope signal Vsl is a triangular wave signal generated based on the clock signal.

[0098] The converter including the power module according to this embodiment applies a power conversion circuit including a switching element connected to the source sense signal wiring and a rectifying element not connected to the source sense signal wiring, thereby taking advantage of the switching characteristics of the switching element connected to the source sense signal wiring and suppressing false turn-on by utilizing the fact that the starting point of the voltage rise of the rectifying element not connected to the source sense signal wiring is low, and ensuring operation stability.

[0099] FIG. 15 is a circuit diagram showing a current mode synchronous rectification boost type DC / DC converter including the power module according to this embodiment. The DC / DC converter 72 boosts the input voltage Vin supplied to the input terminal VIN and generates a desired output voltage Vout at the output terminal VOUT.

[0100] The DC / DC converter 72 includes a switching element T21, a rectifying element T22, a drive circuit 53, a feedback voltage generation circuit 56, an error amplifier 57, a phase compensation circuit 58, a PWM comparator 60, a slope voltage generation circuit 61, an inductor L12, and a smoothing capacitor C2.

[0101] The DC / DC converter 72 differs from the step-down type shown in FIG. 14 in that the circuit section after the drive circuit 53 is different. The other circuit sections are the same. Here, the different circuit sections of both will be described.

[0102] The switching element T21 is an N-channel MOS field-effect transistor connected to the rectifying element T22, the drive circuit 53, and the inductor L12, and functions as a switching transistor that repeatedly turns on and off to control the current flowing through the inductor L12. The switching element T21 operates complementarily in synchronization with the rectifying element T22. The source S of the switching element T21 is connected to the ground potential GND. The drain D of the switching element T21 is commonly connected to the source S of the rectifying element T22 and one end of the inductor L12. This common connection point is indicated by node N1. A gate signal GL is applied to the gate G of the switching element T21 from the drive circuit 53. Also, the source voltage of the switching element T21 is fed back to the drive circuit 53 via the source sense signal wiring SS. The switching element T21 turns on when the gate signal GL is at a high level and turns off when the gate signal GL is at a low level.

[0103] The other end of the inductor L12 is connected to the input terminal VIN to which the input voltage Vin is supplied. That is, the switching element T21 is coupled to the input voltage Vin via the inductor L12. The current flowing through the inductor L12 is controlled by the switching element T21.

[0104] The source S of the rectifying element T22 is connected to the drain D of the switching element T21 and one end of the inductor L12. The drain D of the rectifying element T22 is connected to node N2, that is, the output terminal VOUT. A gate signal GH is applied to the gate G of the rectifying element T22 from the drive circuit 53. The rectifying element T22 turns off when the gate signal GH is at a low level and turns on when the gate signal GH is at a high level.

[0105] A smoothing capacitor C2 is connected between the node N2, i.e., the output terminal VOUT, and the ground potential GND. The smoothing capacitor C2 performs a rectifying and smoothing operation together with the inductor L12 and the rectifying element T22.

[0106] The synchronous rectification boost type DC / DC converter 72 was described as being different from the synchronous rectification buck type DC / DC converter 51 shown in FIG. 14. Since the other circuit parts are the same as those in FIG. 14, the description thereof will be omitted. Also in the DC / DC converter 72, a switching element connected to the source sense signal wiring and a rectifying element not connected to the source sense signal wiring will be applied. Note that the DC / DC converter shown in FIG. 14 is an example of a buck type, and the DC / DC converter shown in FIG. 15 is an example of a boost type. Needless to say, the present invention can be applied to a so-called buck-boost type DC / DC converter that can switch between a buck type and a boost type.

[0107] Although not shown, it is also possible to configure an inverter including the power conversion circuit of the present embodiment. In order to function as an inverter, when making the elements in the inverter function as switching elements, control may be performed so as to use the elements connected to the source sense signal wiring.

[0108] [Other Embodiments] As described above, several embodiments have been described. However, the discussions and drawings that form part of the disclosure are exemplary and should not be construed as limiting. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure. Thus, the present embodiment includes various embodiments not described herein.

Description of Reference Numerals

[0109] 10... Substrate 24... n + Drain region 26, 26N... Semiconductor substrate (drift layer) 28... p-body region 30... Source region 32... Gate insulating film 34…Source electrode 36…Drain electrode 38…Gate electrode 38TG…Trench gate electrode 44, 44U, 44B…Interlayer insulating film 51, 72…DC / DC converter 53…Drive circuit 56…Feedback voltage generation circuit 57…Error amplifier 58…Phase compensation circuit 60…PWM comparator 61…Slope voltage generation circuit 100…Semiconductor device BD…Body diode C, C3…Capacitor C1, C2…Smoothing capacitor D, D1, D4…Drain D G1 , D G4 …Gate diode E…Power supply G, G1, G4…Gate GH, GL…Gate signal GL1, GL4…Gate signal wiring pattern GND…Ground potential GT1, GT4…Gate terminal I…Constant current source IL…Load current L, L11, L12…Inductor L1, L2, L4, L GP1 , L SP1 , L GP4 , L SP4 …Inductance N…Negative power terminal N1, N2, N3…Node O, VOUT…Output terminal P…Positive power terminal pwm…Pulse width modulation signal Q, Q1, Q4…MISFET chip R1, R2, R3…Resistor R g1 , R g4 …Gate resistor RJFET …Channel resistance Ron…On-resistance value S, S1, S4…Source SL1, SL4…Signal wiring pattern for source ST1…Source terminal SP…Source pad electrode SS, SS1, SS4…Signal wiring for source sense SSL1, SSL4…Signal wiring pattern for source sense SST4…Source sense terminal SSW4…Wire for source sense T11, T21…Switching element T12, T22…Rectifying element U1, U4…Transistor Verr…Error voltage Vfb…Feedback voltage V G1 , V G4 …Gate drive circuit Vin…Input voltage VIN…Input terminal Vout…Output voltage Vref…Reference voltage Vsl…Slope signal W1, W2, W3, W4, W11, W12…Wiring

Claims

1. A power conversion circuit in which a switching transistor and a synchronous rectifier transistor are connected in series, and an inductance of a source of the switching transistor is smaller than an inductance of a source of the synchronous rectifier transistor.

2. The power conversion circuit according to claim 1, further comprising a capacitor electrically connected to the switching transistor and the synchronous rectifier transistor.

3. The power conversion circuit according to claim 2, further comprising an output terminal electrically connected to the capacitor.

4. The power conversion circuit according to any one of claims 1 to 3, further comprising a power terminal electrically connected to a drain of the switching transistor.

5. A power module including the power conversion circuit according to any one of claims 1 to 4.

6. A first transistor having a function of exciting a first inductor and connected to a first source sense signal wiring, a second transistor having a function of discharging power stored in the first inductor, a first gate signal wiring and the first source sense signal wiring electrically connected to a gate of the first transistor, a second gate signal wiring and a first source signal wiring electrically connected to a gate of the second transistor, wherein the first transistor is connected in series with the second transistor, and the first inductor is connected to a connection point between the first transistor and the second transistor.

7. The power module according to claim 6, wherein an inductance of a source of the first transistor is smaller than an inductance of a source of the second transistor.

8. The power module according to claim 6 or 7, further comprising a capacitor electrically connected to the first transistor and the second transistor.

9. The power module according to claim 8, further comprising an output terminal electrically connected to the capacitor.

10. The power module according to any one of claims 6 to 9, further comprising a power terminal electrically connected to a drain of the first transistor.

11. The first transistor functions as a switching element, and the second transistor functions as a synchronous rectifier element.

12. The power module according to any one of claims 6 to 11, wherein the second transistor outputs a signal to the first source signal wiring via the drain of the first transistor.

13. The power module according to any one of claims 6 to 11, wherein the second transistor outputs a signal to the first source signal wiring via the source of the second transistor.

14. Furthermore, a second source signal wiring electrically connected to the first transistor, and a second source sense signal wiring electrically connected to the second transistor, The power module according to claim 13, wherein the first transistor outputs a signal to the second source signal wiring via the drain of the second transistor.

15. The second transistor and the drain of the first transistor are connected by a first wiring, When a signal is output from the gate of the second transistor to the first source signal wiring, the current tolerance of the first wiring is greater than the current tolerance of the wiring directly connected to the second gate signal wiring. The power module according to claim 12.

16. When a signal is output from the gate of the second transistor to the first source signal wiring, the current tolerance of the second wiring via the source of the second transistor is greater than the current tolerance of the wiring directly connected to the second gate signal wiring. The power module according to claim 13.

17. A converter comprising the power module according to any one of claims 5 to 16.

18. An inverter comprising the power module according to any one of claims 5 to 16.

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