Silicon carbide semiconductor device

Abstract

To provide an SiC semiconductor device with which contact resistance is suppressed.SOLUTION: The SiC semiconductor device comprises: a drift layer containing first conductive type of SiC; main regions 8a, 8b containing a first conductive type of SiC and provided on the upper side of the drift layer; base regions 6a, 6b being in contact with a main region, containing a second conductive type of SiC, and provided on the upper side of the drift layer; a gate electrode being in contact with the base regions via a gate insulating film; and a main electrode being in contact with the main region. The main region has a contact region on the upper side that is in contact with the main electrode, and the contact region contains a plurality of SiC microcrystals of 3C structure. The plurality of SiC microcrystals in the contact region includes a first microcrystal in grain sizes larger than or equal to a threshold and a second microcrystal in grain sizes smaller than the threshold. The percentage that the first microcrystal in the contact region occupies the upper side of the contact region is 10% or greater.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a SiC semiconductor device using silicon carbide (SiC).

Background Art

[0002] Patent Document 1 discloses a semiconductor device in which an amorphous layer is formed by ion-implanting phosphorus into a hexagonal single-crystalline silicon carbide substrate, the amorphous layer is recrystallized into cubic single-crystalline n-type silicon carbide by heat treatment, and an electrode is formed by depositing nickel on the upper surface of the n-type silicon carbide.

[0003] Patent Document 2 discloses an n-type epitaxial growth layer formed on a first main surface of n-type SiC made of 4H-SiC, which has an n-type source region, an n-type 3C-SiC region formed in the n-type source region, and a p-type potential fixing region. A barrier metal film is formed in contact with the n-type 3C-SiC region and the p-type potential fixing region, and a source wiring electrode is formed on the barrier metal film. + type SiC's first main surface, and in the n - type epitaxial growth layer, an n + type source region, and an n + type source region formed within the n + type 3C-SiC region and a p + type potential fixing region, and an n + type 3C-SiC region and a p + type potential fixing region, and a barrier metal film is formed in contact with the n-type 3C-SiC region and the p-type potential fixing region, and a source wiring electrode is formed on the barrier metal film.

[0004] Patent Document 3 describes that a 3C-SiC layer is provided on a hexagonal SiC layer.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0006] By providing nickel silicide, contact resistance can be suppressed. However, in order to provide nickel silicide, a number of manufacturing steps are required, such as Ni film formation, etching, high-temperature annealing, and etching and removal of unreacted substances, making it difficult to suppress manufacturing costs.

[0007] Therefore, it has been studied to locally form 3C-SiC (bandgap: 2.23 eV) only in the contact portion by breaking the crystal of 4H-SiC (bandgap: 3.26 eV) by ion implantation of impurities and further performing an annealing process. As a result, it has become possible to form a contact structure between the source electrode and the SiC substrate only by the ion implantation of impurities and the annealing process.

[0008] However, even when 3C-SiC is provided, it is desirable to further suppress contact resistance.

[0009] In view of the above problems, an object of the present disclosure is to provide a SiC semiconductor device with suppressed contact resistance.

Means for Solving the Problems

[0010] To achieve the above object, one aspect of the present disclosure includes a drift layer containing silicon carbide of a first conductivity type, a main region provided on the upper surface side of the drift layer and containing silicon carbide of the first conductivity type, a base region provided on the upper surface side of the drift layer, in contact with the main region, and containing silicon carbide of a second conductivity type, a gate electrode in contact with the base region via a gate insulating film, and a main electrode in contact with the main region. The main region has a contact region in contact with the main electrode on the upper surface side. The contact region includes a plurality of silicon carbide microcrystals having a 3C structure. The plurality of silicon carbide microcrystals in the contact region include first microcrystals having a particle size equal to or greater than a threshold value and second microcrystals having a particle size smaller than the threshold value. The ratio of the first microcrystals in the contact region occupying the upper surface of the contact region is 10% or more. The gist is a SiC semiconductor device.

Effect of the Invention

[0011] According to the present disclosure, a SiC semiconductor device with suppressed contact resistance can be provided.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Mode for Carrying Out the Invention

[0013] Hereinafter, the first embodiment of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicate explanations are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be parts where the dimensional relationships and ratios are different even between the drawings. Further, the first embodiment shown below is an example of an apparatus and a method for embodying the technical idea of the present disclosure, and the technical idea of the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of the constituent parts as the following.

[0014] In this specification, the source region of a metal-oxide-semiconductor field-effect transistor (MOSFET) is "one main region (first main region)" that can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). Also, in a thyristor such as a MOS-controlled static induction thyristor (SI thyristor), the "one main region" can be selected as the cathode region. The drain region of the MOSFET is the "other main region (second main region)" of a semiconductor device that can be selected as the collector region in the IGBT and as the anode region in the thyristor. When simply referred to as the "main region" in this specification, it means either the appropriate first main region or second main region based on the common general knowledge of those skilled in the art.

[0015] Also, the definitions of directions such as up and down in the following description are merely for convenience of explanation and do not limit the technical idea of the present disclosure. For example, if the object is rotated by 90° and observed, up and down are read as left and right, and it goes without saying that if it is rotated by 180° and observed, up and down are read in reverse. Also, "upper surface" may be read as "front surface", and "lower surface" may be read as "back surface".

[0016] Also, in the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type will be exemplified. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Also, + and - attached to n and p mean semiconductor regions with relatively higher or lower impurity concentrations, respectively, compared to semiconductor regions without + and - attached. However, even for semiconductor regions with the same n attached, it does not mean that the impurity concentrations of the respective semiconductor regions are exactly the same.

[0017] Also, there are crystal polymorphs in SiC crystals, and the main ones are cubic 3C, and hexagonal 4H and 6H. The reported values of the bandgap at room temperature are 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In the following description, the cases mainly using 4H-SiC and 3C-SiC will be exemplified.

[0018] (First Embodiment) <Structure of SiC Semiconductor Device> As shown in FIG. 1, the SiC (silicon carbide) semiconductor device (semiconductor chip) 100 according to the first embodiment includes, in a plan view, for example, an active portion 101 having a rectangular planar shape, and a breakdown voltage structure portion 102 provided so as to surround the periphery of the active portion 101. Further, in a plan view, the SiC semiconductor device 100 includes a region 103 provided so as to surround the active portion 101 between the active portion 101 and the breakdown voltage structure portion 102.

[0019] FIG. 2 is a cross-sectional view taken along the line A-A of FIG. 1. In FIG. 2, a part of the active portion 101 is not shown. As shown in FIG. 2, the active portion 101 includes active elements, the region 103 includes a ring region 9b, and the breakdown voltage structure portion 102 includes a plurality of electric field relaxation regions 9a, which will be described later, as a termination structure.

[0020] As shown in FIG. 2, the SiC semiconductor device 100 is exemplified as including a trench gate type MOSFET as an active element. In FIG. 2, a unit cell including an insulated gate electrode structure (7b, 7c) embedded in one trench 7a is exemplified, but actually, a large number of these unit cells are periodically arranged.

[0021] The SiC semiconductor device 100 includes a drift layer 2 of a first conductivity type (n - type) provided across the active portion 101, the breakdown voltage structure portion 102, and the region 103. The drift layer 2 is composed of, for example, an epitaxial growth layer made of SiC such as 4H-SiC. The impurity concentration of the drift layer 2 is, for example, 1×10 15 cm -3 or more and 5×10 16 cm -3 or less. The thickness of the drift layer 2 is, for example, in the range of 1 μm or more and 100 μm or less. The impurity concentration and thickness of the drift layer 2 can be appropriately adjusted according to the breakdown voltage specification and the like.

[0022] Over the active part 101 and the region 103, on the upper surface side of the drift layer 2, a current spreading layer (CSL) 3 of the first conductivity type (n-type) with a higher impurity concentration than the drift layer 2 is selectively provided. The lower surface of the current spreading layer 3 is in contact with the upper surface of the drift layer 2. The current spreading layer 3 is formed, for example, by N ion implantation. The impurity concentration of the current spreading layer 3 is, for example, 5×10 16 cm -3 or more and within the range of about 5×10 17 cm -3 or less. Note that the current spreading layer 3 does not necessarily need to be provided. When the current spreading layer 3 is not provided, the drift layer 2 may be provided up to the region of the current spreading layer 3.

[0023] In the active part 101, base regions 5a, 5b of the second conductivity type (p-type) are selectively provided on the upper surface side of the current spreading layer 3. The lower surfaces of the base regions 5a, 5b are in contact with the upper surface of the current spreading layer 3. Note that when the current spreading layer 3 is not provided, the lower surfaces of the base regions 5a, 5b are in contact with the upper surface of the drift layer 2. The base regions 5a, 5b are, for example, regions made of SiC obtained by ion implanting a p-type impurity such as aluminum into the current spreading layer 3. The base regions 5a, 5b may be composed of an epitaxial growth layer made of SiC such as 4H-SiC. The impurity concentration of the base regions 5a, 5b is, for example, 1×10 16 cm -3 or more and within the range of about 1×10 18 cm -3 or less.

[0024] On the upper surface side of the current spreading layer 3, a first conductivity type (n +The first main regions (source regions) 6a and 6b of the 19 cm -3 type are selectively provided. More specifically, the source regions 6a and 6b are selectively provided on the upper surface side of the base regions 5a and 5b. The source regions 6a and 6b are in contact with the base regions 5a and 5b. More specifically, the lower surface of the source region 6a is in contact with the upper surface of the base region 5a, and the lower surface of the source region 6b is in contact with the upper surface of the base region 5b. The source regions 6a and 6b are regions made of, for example, SiC obtained by ion-implanting n-type impurities into the current diffusion layer 3. The impurity concentration of the source regions 6a and 6b is, for example, 1×10 21 cm -3 or more and within the range of about 3×10

[0025] The source region 6a has a two-layer stacked structure of a lower n + -type source extension region 61a and an upper n + -type source contact region 62a. The lower surface of the source extension region 61a is in contact with the upper surface of the base region 5a. The upper surface of the source extension region 61a is in contact with the lower surface of the source contact region 62a. The source region 6b has a two-layer stacked structure of a lower n + -type source extension region 61b and an upper n + -type source contact region 62b. The lower surface of the source extension region 61b is in contact with the upper surface of the base region 5b. The upper surface of the source extension region 61b is in contact with the lower surface of the source contact region 62b. Thus, the source regions 6a and 6b have the source contact regions 62a and 62b on the upper surface side. The source contact regions 62a and 62b are contact regions that are in contact with the source electrodes described later. The impurity concentration of the source contact regions 62a and 62b is, for example, 5×10 19 cm -3 or more and within the range of about 3×10 21 cm -3 or less.

[0026] The source regions 6a and 6b contain 3C-SiC and 4H-SiC. More specifically, the source extension regions 61a and 61b are made of 4H-SiC. The source contact regions 62a and 62b contain 3C-SiC. The proportion of 3C-SiC contained in the source contact regions 62a and 62b is within a range of, for example, 10 percent or more and 100 percent or less. When the proportion of 3C-SiC is less than 100 percent, the source contact regions 62a and 62b may contain 4H-SiC. Note that "the source extension regions 61a and 61b are made of 4H-SiC" may mean "the source extension regions 61a and 61b are mainly made of 4H-SiC". Even if the source extension regions 61a and 61b contain something other than 4H-SiC such as 3C-SiC, it is only a very small amount. Hereinafter, the 3C-SiC in the source contact regions 62a and 62b may be referred to as the 3C structure, and the 4H-SiC may be referred to as the 4H structure.

[0027] Hereinafter, how the 3C-SiC in the source contact regions 62a and 62b is formed will be described. First, for the 3C-SiC, an n-type impurity (an impurity of the first conductivity type) such as phosphorus (P) or nitrogen (N) is ion-implanted into the 4H-SiC to break the structure of the 4H-SiC and form an amorphous structure. The temperature during ion implantation is set low to break the structure of the 4H-SiC. By performing ion implantation of a high-concentration impurity at a low temperature, the structure of the 4H-SiC can be broken. The temperature during ion implantation is set within a range of, for example, room temperature (for example, 20 °C) or more and 200 °C or less. And the dose amount during ion implantation is, for example, 5×10 14 cm -2 or more and 1×10 16 cm -2Set it within the following range. By adjusting the temperature and concentration conditions for ion implantation of high-concentration impurities at a low temperature, increase the number of large-sized microcrystals and reduce grain boundaries. Then, perform heat treatment to activate the ion-implanted impurities and simultaneously recrystallize the amorphous structure to obtain 3C-SiC. Note that the heat treatment temperature is set within a range of, for example, 1600 °C or higher and 1900 °C or lower. The heat treatment temperature may be set to, for example, 1750 °C. Also, the heat treatment is performed for about 30 minutes. This heat treatment may also serve as an activation anneal to activate the impurities ion-implanted into SiC. Note that, in order to break the structure of 4H-SiC, an inert gas element such as argon, silicon, carbon, etc. may be ion-implanted. By forming 3C-SiC in this way, an increase in the manufacturing cost of the SiC semiconductor device 100 can be suppressed.

[0028] The dimensions in the depth direction of the source contact regions 62a and 62b are, for example, in the range of 50 nm or more and 100 nm or less. Considering the bandgap with the source extension regions 61a and 61b, it is desirable to provide the dimensions in the depth direction of the source contact regions 62a and 62b to be about 100 nm. The source contact regions 62a and 62b are of the first conductivity type (n + type) and contain a plurality of microcrystals of 3C-SiC. More specifically, the source contact regions 62a and 62b each contain a plurality of first microcrystals with a particle size equal to or greater than the threshold value and second microcrystals with a particle size smaller than the threshold value as microcrystals of 3C-SiC. For example, the threshold value is 30 nm, the first microcrystals are microcrystals with a particle size of 30 nm or more, and the second microcrystals are microcrystals with a particle size smaller than 30 nm.

[0029] FIG. 3 is a diagram showing the result (phase map) of analyzing the upper surface (the surface on the source electrode side) S of the source contact regions 62a and 62b using the EBSD (Electron Back Scattered Diffraction Pattern) method. The following apparatus was used as the measuring apparatus. Thermionic field emission scanning electron microscope (TFE-SEM) JSM-6500F manufactured by JEOL Ltd. TSL's DigiViewIV Slow-Scan CCD Camera, Analysis Software OIM Data Collection ver.7.x and OIM Analysis ver.7.x Also, regarding the crystal grain size, it was determined from a grain size distribution chart (Grain Size Distribution Chart Diameter) for which illustration is omitted. The grain size distribution chart is a diagram in which, for each individual crystal grain identified in the crystal grain map, the equivalent circle diameter (the diameter of a circle with the same area) is calculated and displayed as a histogram. The crystal grain map is a diagram in which crystal grains are identified as the same grain when there are two or more continuous measurement points within a specified azimuth difference (5°), and it is displayed in pseudo-color. The average value of the crystal grain size was taken as the average value of the equivalent circle diameters. More specifically, the average value dave of the crystal grain sizes of n microcrystals from microcrystal a1 to microcrystal an is the value obtained by adding up the n grain sizes from the grain size d1 which is the equivalent circle diameter of microcrystal a1 to the grain size dn which is the equivalent circle diameter of microcrystal an, and then dividing by the number n of microcrystals (dave = (d1 + d2 +... + dn) / n). In the EBSD method, generally, a region up to a depth of about 50 nm from the upper surface of the object to be inspected can be analyzed. Therefore, "upper surface" may mean not only a two-dimensional surface but also a three-dimensional region up to a depth of about 50 nm from the upper surface. Also, in a region deeper than 50 nm in the source contact regions 62a and 62b, microcrystals of 3C-SiC may be formed. In region 14 of FIG. 3, first microcrystals with a grain size of 30 nm or more are provided. A plurality of regions 14 are provided on the upper surface S, and one region 14 is occupied by one first microcrystal. That is, the boundary between region 14 and regions 15 and 16 described later is the grain boundary of the first microcrystal. In region 15, a plurality of second microcrystals with a grain size smaller than 30 nm are provided. Since the second microcrystals are fine, illustration of their grain boundaries is omitted. Region 15 is a region occupied by a large number of second microcrystals. In region 16, microcrystals of 4H-SiC are provided.

[0030] The influence of microcrystals on electrical characteristics will be described below. FIG. 4 shows two microcrystals A made of SiC and a grain boundary B between the microcrystals A. FIG. 5 shows a comparative example in which a large number of microcrystals below the threshold exist in the SiC semiconductor. As shown in FIG. 4, electrons flowing in the SiC are scattered by the grain boundary B. Therefore, as shown in FIG. 5, when there are a large number of grain boundaries, electrons may be scattered. As a result, the mobility of the electrons decreases, and the electrical resistance of the source contact regions 62a and 62b may increase. On the other hand, the SiC semiconductor shown in FIG. 6 contains microcrystals with a relatively large particle size. In this way, by including many microcrystals with a relatively large particle size, the grain boundary B can be reduced. Therefore, in the present embodiment, the electrical resistance as a bulk is reduced by reducing the grain boundary of the 3C-SiC microcrystals included in the source contact regions 62a and 62b, and the electrical resistance between the source contact regions 62a and 62b and the source electrode described later is reduced.

[0031] In the present embodiment, the ratio of the first microcrystals occupying the upper surface S is 10% or more. Thereby, the grain boundary can be reduced, and the electrical resistance of SiC can be improved. Note that the more the ratio of the first microcrystals occupying the upper surface S is increased, the more the grain boundary of the 3C-SiC microcrystals can be reduced. Therefore, the ratio of the first microcrystals occupying the upper surface S may be 15% or more, or may be 20% or more. Also, the upper limit value of the ratio of the first microcrystals occupying the upper surface S is preferably as high as possible if possible. The upper limit value of the ratio of the first microcrystals occupying the upper surface S is, for example, about 50%.

[0032] In addition, the dimension along the depth direction of the microcrystal has a size according to the dimension along the horizontal direction. That is, the larger the dimension along the horizontal direction of the first microcrystal, the larger the dimension along the depth direction. When the dimension along the depth direction of the first microcrystal increases, as shown in the comparative example of FIG. 6, the presence of a large number of grain boundaries along the depth direction can be suppressed. And when electrons travel from the upper surface S along the depth direction, the number of grain boundaries is suppressed, so it is difficult to be scattered. The maximum value of the particle size of the first microcrystal is, for example, about 1000 nm.

[0033] Also, the average value of the grain size of the first microcrystals included in the source contact regions 62a and 62b is in the range of about 60 nm or more and 400 nm or less, and may be, for example, 70 nm. The average value of the grain size of the first microcrystals may be 60 nm or more and 80 nm or less.

[0034] As shown in FIG. 2, a trench 7a penetrating the source regions 6a and 6b and the base regions 5a and 5b is provided in the normal direction (depth direction) of the upper surfaces of the source regions 6a and 6b from the upper surfaces of the source regions 6a and 6b. The lower surface of the trench 7a reaches the current diffusion layer 3. The width of the trench 7a is, for example, about 1 μm or less. The source region 6a and the base region 5a are in contact with the left side surface of the trench 7a. The source region 6b and the base region 5b are in contact with the right side surface of the trench 7a. The trench 7a may have a planar pattern extending in a stripe shape in the depth direction and the front direction of the paper surface of FIG. 2, or may have a dot-shaped planar pattern.

[0035] A gate insulating film 7b is provided along the lower surface and both side surfaces of the trench 7a. A gate electrode 7c is embedded inside the trench 7a with the gate insulating film 7b interposed therebetween. As shown in FIG. 2, the upper surface of the gate electrode 7c is at a position deeper than the boundary between the source contact regions 62a and 62b and the source extension regions 61a and 61b, but is not limited thereto. The upper surface of the gate electrode 7c may be at the same depth position as the upper surface S of the source contact regions 62a and 62b. The gate insulating film 7b and the gate electrode 7c constitute a trench gate type insulated gate electrode structure (7b, 7c).

[0036] As the gate insulating film 7b, in addition to a silicon oxide film (SiO2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, a yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, a bismuth oxide (Bi2O3) film, any one single-layer film or a composite film formed by laminating a plurality of these can be adopted. As the material of the gate electrode 7c, for example, a polysilicon layer (doped polysilicon layer) with a p-type impurity or an n-type impurity added at a high impurity concentration, or a refractory metal such as titanium (Ti), tungsten (W), or nickel (Ni) can be used.

[0037] Inside the current diffusion layer 3 and at the bottom of the trench 7a, a gate bottom protection region 4 of the second conductivity type (p + -type) is provided. The upper surface of the gate bottom protection region 4 is in contact with the lower surface of the trench 7a. The upper surface of the gate bottom protection region 4 does not necessarily have to be in contact with the lower surface of the trench 7a. The impurity concentration of the gate bottom protection region 4 is, for example, 1×10 17 cm -3 or more and 1×10 19 cm -3 or less. The gate bottom protection region 4 is, for example, a region made of SiC obtained by ion-implanting a p-type impurity into the current diffusion layer 3. The gate bottom protection region 4 is electrically connected to the source wiring electrode 12 at a portion not shown in the figure and has a function of depleting during the OFF state of the MOSFET to relax the electric field applied to the lower surface of the trench 7a.

[0038] On the upper surface side of the current diffusion layer 3, p-type embedded regions 81a and 81b of the second conductivity type are selectively provided in contact with the base regions 5a and 5b. The lower surfaces of the embedded regions 81a and 81b are in contact with the current diffusion layer 3. The side surfaces of the embedded region 81a are in contact with the current diffusion layer 3 and the base region 5a, and the side surfaces of the embedded region 81b are in contact with the current diffusion layer 3 and the base region 5b. The embedded regions 81a and 81b are regions made of, for example, SiC obtained by ion-implanting p-type impurities such as aluminum into the current diffusion layer 3. The impurity concentration of the embedded regions 81a and 81b is, for example, 5×10 17 cm -3 or more and 1×10 19 cm -3 or less. The embedded regions 81a and 81b are mainly made of 4H-SiC and, even if they contain 3C-SiC, the amount is small.

[0039] On the upper surface side of the embedded regions 81a and 81b (current diffusion layer 3), base contact regions 82a and 82b made of SiC of the second conductivity type (p + type) with a higher impurity concentration than that of the embedded region 81a are selectively provided. The base contact regions 82a and 82b contain p + type SiC. The base contact regions 82a and 82b are contact regions that contact a source electrode described later. The lower surface of the base contact region 82a is in contact with the upper surface of the embedded region 81a, and the side surface of the base contact region 82a is in contact with the source region 6a. The base contact region 82a is electrically connected to the base region 5a. The lower surface of the base contact region 82b is in contact with the upper surface of the embedded region 81b, and the side surface of the base contact region 82b is in contact with the source region 6b. The base contact region 82b is electrically connected to the base region 5b. The base contact regions 82a and 82b are regions made of, for example, SiC obtained by ion-implanting p-type impurities such as aluminum into the current diffusion layer 3. The impurity concentration of the base contact regions 82a and 82b is higher than that of the embedded regions 81a and 81b and is, for example, within the range of 5×10 19 cm -3 or more and 3×10 21 cm -3 or less.

[0040] The base contact regions 82a and 82b may or may not contain 3C-SiC. When the base contact regions 82a and 82b contain 3C-SiC, the configurations of the base contact regions 82a and 82b other than the above are the same as those of the source contact regions 62a and 62b. Hereinafter, the case where the base contact regions 82a and 82b contain 3C-SiC will be described in more detail.

[0041] The depthwise dimension of the base contact regions 82a and 82b is, for example, in the range of about 50 nm or more and 100 nm or less. The base contact regions 82a and 82b contain a plurality of microcrystals of 3C-SiC. Considering the band gap with the embedded regions 81a and 81b, it is desirable to provide the depthwise dimension of the base contact regions 82a and 82b at about 100 nm. The base contact regions 82a and 82b are of the second conductivity type (p + -type) and contain a plurality of microcrystals of 3C-SiC. More specifically, the base contact regions 82a and 82b each contain a plurality of first microcrystals having a particle size equal to or greater than a threshold value and second microcrystals having a particle size smaller than the threshold value as microcrystals of 3C-SiC. For example, the threshold value is 30 nm, the first microcrystals are microcrystals having a particle size of 30 nm or more, and the second microcrystals are microcrystals having a particle size smaller than 30 nm.

[0042] Since the result of analyzing the upper surface (the surface on the source electrode side) S1 of the base contact regions 82a and 82b by EBSD is the same as that in FIG. 3, the illustration and detailed description are omitted. In the present embodiment, the ratio of the first microcrystals occupying the upper surface S1 of the base contact regions 82a and 82b is 10% or more. Thereby, the grain boundaries can be reduced and the electrical resistance can be improved. Note that the more the ratio of the first microcrystals occupying the upper surface S1 is increased, the more the grain boundaries of the 3C-SiC microcrystals can be reduced. Therefore, the ratio of the first microcrystals occupying the upper surface S1 may be 15% or more, or may be 20% or more. Also, the upper limit value of the ratio of the first microcrystals occupying the upper surface S1 is preferably as high as possible if possible. The upper limit value of the ratio of the first microcrystals occupying the upper surface S1 is, for example, about 50%.

[0043] The maximum value of the grain size of the first microcrystals included in the base contact regions 82a and 82b is, for example, about 1000 nm. Further, the average value of the grain size of the first microcrystals included in the base contact regions 82a and 82b is within a range of 60 nm or more and 400 nm or less, and may be, for example, 70 nm. The average value of the grain size of the first microcrystals may be 60 nm or more and 80 nm or less.

[0044] When the base contact regions 82a and 82b do not contain 3C-SiC, the base contact regions 82a and 82b mainly consist of 4H-SiC, and even if they contain 3C-SiC, it is only a small amount.

[0045] In the breakdown voltage structure portion 102, a plurality of second conductivity type (p-type) electric field relaxation regions 9a are selectively provided on the upper surface side of the drift layer 2. In the example shown in FIG. 2, three electric field relaxation regions 9a are provided on the upper surface side of the drift layer 2. The electric field relaxation regions 9a are concentric ring-shaped guard rings (field limiting rings) in plan view, although not shown. The electric field relaxation regions 9a are separated from each other by the drift layer 2. The lower surface of the electric field relaxation region 9a is in contact with the upper surface of the drift layer 2. The electric field relaxation region 9a is, for example, a region made of SiC in which a p-type impurity such as aluminum is ion-implanted into the drift layer 2. More specifically, the electric field relaxation region 9a is a region made of 4H-SiC. The electric field relaxation region 9a has a p-type first portion 91a and a p + type second portion 92a. The second portion 92a is at a shallower position in the depth direction than the first portion 91a, and the lower surface of the second portion 92a is in contact with the upper surface of the first portion 91a.

[0046] Also, in the breakdown voltage structure portion 102, a first conductivity type (n + type) channel stopper region 6c is provided on the outermost periphery on the upper surface side of the drift layer 2. The lower surface of the channel stopper region 6c is in contact with the upper surface of the drift layer 2. The channel stopper region 6c is, for example, a region made of 3C-SiC in which an n-type impurity is ion-implanted into the drift layer 2.

[0047] In region 103, a ring region 9b of the second conductivity type (p-type) is selectively provided on the upper surface side of the drift layer 2. The lower surface of the ring region 9b is in contact with the upper surface of the drift layer 2. The ring region 9b is, for example, a region made of SiC in which p-type impurities are ion-implanted into the drift layer 2. More specifically, the ring region 9b is a region made of 4H-SiC. The ring region 9b is a ring-shaped portion surrounding the edge of the active portion 101 in a plan view, although not shown in the figure. The ring region 9b has a first portion 91b and a second portion 92b. The second portion 92b is at a shallower position in the depth direction than the first portion 91b, and the lower surface of the second portion 92b is in contact with the upper surface of the first portion 91b.

[0048] An insulating film 10 is selectively provided on the upper surface side of the gate electrode 7c, the upper surface side of the region 103, and the upper surface side of the breakdown voltage structure portion 102. In the breakdown voltage structure portion 102, the insulating film 10 is provided on the upper surface of the electric field relaxation region 9a. More specifically, the insulating film 10 is provided at a position covering the second portion 92a of the electric field relaxation region 9a. The insulating film 10 is composed of, for example, a single-layer film such as a silicon oxide film added with boron (B) and phosphorus (P) (BPSG film), a silicon oxide film added with phosphorus (P) (PSG film), a non-doped silicon oxide film called "NSG" that does not contain phosphorus (P) or boron (B), a silicon oxide film added with boron (B) (BSG film), a silicon nitride film (Si3N4 film), or a laminated film of these. Openings 10a and 10b are provided in the insulating film 10 so as to expose the upper surfaces of the source regions 6a and 6b and the base contact regions 82a and 82b. Further, an opening 10c is provided in the insulating film 10 so as to expose the upper surface of the ring region 9b, more specifically, the upper surface of the second portion 92b.

[0049] The first main electrode (source electrode) (11, 12) is provided so as to cover the insulating film 10, the upper surfaces of the source regions 6a, 6b and the base contact regions 82a, 82b exposed from the openings 10a, 10b, and the upper surface of the ring region 9b exposed from the opening 10c. The source electrodes (11, 12) include a lower barrier metal layer 11 and an upper source wiring electrode 12. For example, the barrier metal layer 11 is made of a metal such as titanium nitride (TiN), titanium (Ti), or a stacked structure of TiN / Ti with Ti as the lower layer. The barrier metal layer 11 is in direct contact with the source regions 6a, 6b and the base contact regions 82a, 82b, and makes an ohmic contact with the source regions 6a, 6b and the base contact regions 82a, 82b with low resistance. Further, the barrier metal layer 11 is in direct contact with the second portion 92b of the ring region 9b.

[0050] The source wiring electrode 12 is electrically connected to the source regions 6a, 6b, the base contact regions 82a, 82b, and the ring region 9b via the barrier metal layer 11. The source wiring electrode 12 is provided separately from a gate wiring electrode (not shown) that is electrically connected to the gate electrode 7c. The source wiring electrode 12 is made of a metal such as aluminum (Al), aluminum-silicon (Al-Si), aluminum-copper (Al-Cu), copper (Cu), or the like.

[0051] On the lower surface side of the drift layer 2, a second main region (drain region) 1 of the first conductivity type (n + type) with a higher impurity concentration than the drift layer 2 is provided. The drain region 1 is made of, for example, a semiconductor substrate (SiC substrate) made of 4H-SiC. The impurity concentration of the drain region 1 is, for example, 1×10 18 cm -3 or more and 3×10 20 cm -3 or less. The thickness of the drain region 1 is, for example, about 30 μm or more and 500 μm or less. Note that a dislocation conversion layer or a recombination promotion layer, which is an n-type buffer layer having a higher impurity concentration than the drift layer 2 and a lower impurity concentration than the drain region 1, may be provided between the drift layer 2 and the drain region 1.

[0052] On the lower surface side of the drain region 1, a second main electrode (drain electrode) 13 is provided. As the drain electrode 13, for example, a single-layer film made of gold (Au) or a metal film laminated in the order of titanium (Ti), nickel (Ni), and Au from the drain region 1 side can be used. Further, a metal film such as molybdenum (Mo) or tungsten (W) may be laminated on the lowermost layer thereof. Also, a drain contact layer such as a nickel silicide (NiSi x ) film or the like may be provided between the drain region 1 and the drain electrode 13 for ohmic contact.

[0053] During the operation of the SiC semiconductor device 100 according to the first embodiment, when a positive voltage is applied to the drain electrode 13 with the source electrodes (11, 12) at the ground potential and a positive voltage equal to or higher than the threshold value is applied to the gate electrode 7c, an inversion layer (channel) is formed on the side surface of the trench 7a in the base regions 5a and 5b, and the device is turned on. In the on state, current flows from the drain electrode 13 through the drain region 1, the drift layer 2, the current diffusion layer 3, the inversion layers in the base regions 5a and 5b, and the source regions 6a and 6b to the source electrodes (11, 12). On the other hand, when the voltage applied to the gate electrode 7c is less than the threshold value, no inversion layer is formed in the base regions 5a and 5b, so the device is turned off and no current flows from the drain electrode 13 to the source electrodes (11, 12).

[0054] According to the SiC semiconductor device 100 according to the first embodiment, at least the source contact regions 62a and 62b among the source contact regions 62a, 62b and the base contact regions 82a, 82b include a plurality of silicon carbide microcrystals having a 3C structure. The silicon carbide microcrystals include first microcrystals having a particle size equal to or greater than a threshold value (30 nm) and second microcrystals having a particle size smaller than the threshold value. The ratio of the first microcrystals occupying the upper surface of the source contact regions 62a, 62b or the base contact regions 82a, 82b is 10% or more. By setting the ratio of the first microcrystals occupying the upper surface of SiC to 10% or more, a relatively large number of microcrystals with a large particle size are included, and grain boundaries existing in the paths of electrons or holes can be reduced. As a result, the electrical resistance of SiC as a bulk can be reduced, and the electrical resistance between the source contact regions 62a, 62b and the base contact regions 82a, 82b and the source electrodes (11, 12) can be reduced. Thereby, a SiC semiconductor device 100 with low cost and low contact resistance can be obtained.

[0055] (Other Embodiments) As described above, although the first embodiment of the present disclosure has been described, the discussions and drawings forming a part of this disclosure should not be understood as limiting the present disclosure. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0056] For example, although a MOSFET is exemplified as the semiconductor device according to the first embodiment, an insulated gate bipolar transistor (IGBT) having a configuration in which a p + type collector region is provided instead of the n + type drain region 1 is also applicable. In addition to the IGBT alone, it is also applicable to a reverse conducting IGBT (RC-IGBT) and a reverse blocking insulated gate bipolar transistor (RB-IGBT).

[0057] Also, in the first embodiment, although the electric field relaxation region 9a has been described as a guard ring, it may have a JTE structure.

[0058] In addition, the transistor included in the SiC semiconductor device 100 may be a vertical type in which the channel is formed in the depth direction, or a horizontal type in which the channel is formed in the horizontal direction. The transistor included in the SiC semiconductor device 100 may be a planar type transistor or a trench gate type transistor.

[0059] Also, the configurations disclosed in the first embodiment can be appropriately combined and modified within a range where no contradiction occurs. Thus, it goes without saying that the present disclosure includes various embodiments and the like not described herein. Therefore, the technical scope of the present disclosure is defined only by the invention specifying matters according to the proper claims from the above description.

Description of Reference Numerals

[0060] 1… Drain region (SiC substrate) 2… Drift layer 3… Current diffusion layer 4… Gate bottom protection region 6a, 6b… Source region 61a, 61b… Source extension region 62a, 62b… Source contact region (contact region) 6c… Channel stopper region 7a… Trench 7b… Gate insulating film 7c… Gate electrode 81a, 81b… Embedded region 82a, 82b… Base contact region 9a… Electric field relaxation region 9b… Ring region 10… Insulating film 11… Barrier metal layer 12… Source wiring electrode 13… Drain electrode

Claims

1. A drift layer containing silicon carbide of a first conductivity type, a main region provided on the upper surface side of the drift layer and containing silicon carbide of a first conductivity type, a base region provided on the upper surface side of the drift layer, in contact with the main region, and containing silicon carbide of a second conductivity type, a gate electrode in contact with the base region via a gate insulating film, a main electrode in contact with the main region, comprising, the main region has a contact region in contact with the main electrode on the upper surface side, the contact region contains a plurality of silicon carbide microcrystals having a 3C structure, the plurality of silicon carbide microcrystals in the contact region include first microcrystals having a particle size equal to or greater than a threshold value and second microcrystals having a particle size smaller than the threshold value, the ratio of the first microcrystals in the contact region occupying the upper surface of the contact region is 10% or more, a silicon carbide semiconductor device.

2. A base contact region provided on the upper surface side of the drift layer, electrically connected to the base region, and containing silicon carbide of a second conductivity type, the base contact region contains a plurality of silicon carbide microcrystals having a 3C structure, the plurality of silicon carbide microcrystals in the base contact region include first microcrystals having a particle size equal to or greater than the threshold value and second microcrystals having a particle size smaller than the threshold value, the ratio of the first microcrystals in the base contact region occupying the upper surface of the base contact region is 10% or more, the silicon carbide semiconductor device according to Claim 1.

3. the threshold value is 30 nm, the silicon carbide semiconductor device according to Claim 1 or 2.

4. the ratio of the first microcrystals in the contact region occupying the upper surface of the contact region is 50% or less, the silicon carbide semiconductor device according to Claim 1.

5. the average value of the particle sizes of the first microcrystals in the contact region is in the range of 60 nm or more and 400 nm or less, the silicon carbide semiconductor device according to Claim 1.

6. the dimension in the depth direction of the contact region is in the range of 50 nm or more and 100 nm or less, the silicon carbide semiconductor device according to Claim 1.

7. The contact region is formed by ion implantation with an impurity of a first conductivity type in a dose amount within a range of 5×10 １４ cm －２ or more and 1×10 １６ cm －２ or less in a temperature range of 20°C or higher and 200°C or lower. the silicon carbide semiconductor device according to Claim 1.

8. the main region is provided on the upper surface side of the base region, the gate electrode is provided inside a trench penetrating the main region and the base region via the gate insulating film, the silicon carbide semiconductor device according to Claim 1 or 2.

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