Semiconductor device and manufacturing method for the same

Abstract

To provide a semiconductor device that does not interrupt a path of on-state current of a transistor, and a manufacturing method for the same.SOLUTION: A semiconductor device 100 includes a drift region 2 of a first conductivity type formed in contact with a main surface 1a of a semiconductor substrate 1, a well region 3 of a second conductivity type, a drain region 5 of the first conductivity type, a source region 4 of the first conductivity type, an anode region 9 of the second conductivity type formed in contact with a bottom part 8a of a groove 8 formed in contact with the source region 4, the well region 3, and the drift region 2 and in contact with a first side surface of the groove 8 that is perpendicular to a direction of current flowing from the drain region 5 to the source region 4, an interlayer insulating film 6 formed in contact with a second side surface 8c of the groove 8 that is parallel to the direction of current flowing from the drain region 5 to the source region 4 and in contact with the anode region 9, and a gate electrode 7 disposed inside the groove 8 through the interlayer insulating film 6. The anode region 9 is in contact with the well region 3 at least in the bottom part 8a of the groove 8. The anode region 9 and the drift region 2 are in hetero-junction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] Patent Document 1 describes a transistor in which a groove is provided in a semiconductor substrate, and a gate electrode and a gate insulating film are disposed in the groove. A protection region having a conductivity type different from that of the drift region is formed on a surface of the gate insulating film facing the drain region to alleviate electric field concentration between the gate electrode and the drift region.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In FIG. 1 of Patent Document 1, a connection region for connecting the protection region to the well region is formed on a side surface of the groove. For this reason, the connection region inhibits a path through which the on-current of the transistor flows and increases the on-resistance of the transistor.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device that does not inhibit a path of the on-current of a transistor and a method for manufacturing the same.

Means for Solving the Problems

[0006] A semiconductor device according to one aspect of the present invention includes a drift region of a first conductivity type formed in contact with one main surface of a semiconductor substrate, a well region of a second conductivity type formed in contact with the drift region, a drain region of the first conductivity type formed in the drift region separated from the well region, a first electrode electrically connected to the drain region, a source region of the first conductivity type formed in the well region, a bottom of a groove formed in contact with the source region, the well region, and the drift region, and a second conductivity type anode region formed in contact with a first side surface of the groove perpendicular to the direction of current flowing from the drain region to the source region, an interlayer insulating film formed in contact with a second side surface of the groove parallel to the direction of current flowing from the drain region to the source region and the anode region, a gate electrode disposed inside the groove through the interlayer insulating film, and a second electrode electrically connected to the anode region and the source region. The anode region is in contact with the well region at least at the bottom of the groove. The anode region and the drift region are hetero-junctioned.

Advantages of the Invention

[0007] According to one aspect of the present invention, a semiconductor device that does not inhibit the on-current path of a transistor can be provided.

Brief Description of the Drawings

[0008]

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DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to the embodiment will be described in detail with reference to the drawings. Note that the embodiments described below show general or specific examples. The numerical values, shapes, materials, installation positions, and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, the dimensional ratios in the drawings are exaggerated for the convenience of explanation and may differ from the actual ratios. In addition, the following embodiments and their modifications may include the same components. The same components are given the same reference numerals, and redundant descriptions are omitted.

[0010] (First Embodiment) [Structure of Semiconductor Device] The semiconductor device 100 according to the first embodiment is a MOS (Metal-Oxide-Semiconductor) field effect transistor (MOSFET) having a trench gate structure and a lateral structure. FIG. 1 is a cross-sectional perspective view showing the structure of the semiconductor device 100 according to the first embodiment.

[0011] The semiconductor device 100 includes a semiconductor substrate 1, a drift region 2 of the first conductivity type, a well region 3 of the second conductivity type, a drain region 5 of the first conductivity type, a first electrode 12, a source region 4 of the first conductivity type, an anode region 9 of the second conductivity type, an interlayer insulating film 6, a gate electrode 7, and a second electrode 11.

[0012] The direction from the first electrode 12 to the second electrode 11 is defined as the X-axis direction. One direction perpendicular to the X-axis direction is defined as the Y-axis direction. The direction perpendicular to the X-axis direction and the Y-axis direction is defined as the Z-axis direction. The X-axis, Y-axis, and Z-axis are common to all the figures illustrated in the following description.

[0013] FIG. 2 is a cross-sectional view of the semiconductor device 100 in the XZ plane including the II-II cut line of FIG. 1. FIG. 3 is a cross-sectional view of the semiconductor device 100 in the YZ plane including the III-III cut line of FIG. 1.

[0014] FIG. 1 shows the unit cell structure of the MOSFET. In an actual device, the unit cell structure is repeated in the Y direction, and in the X direction, a structure planar with respect to the side surface parallel to the YZ plane of the unit cell structure is repeated.

[0015] The first conductivity type and the second conductivity type are different conductivity types. That is, if the first conductivity type is P-type, the second conductivity type is N-type, and if the first conductivity type is N-type, the second conductivity type is P-type. In the present embodiment, the case where the first conductivity type is N-type and the second conductivity type is P-type will be described.

[0016] For the semiconductor substrate 1, for example, a semi-insulating silicon carbide substrate (SiC substrate) can be used. Since SiC is a wide-bandgap semiconductor and has a small number of intrinsic carriers, high insulation can be obtained, and a semiconductor device 100 with a high breakdown voltage can be realized. There are several polytypes (crystal polymorphs) in SiC, and a typical 4H SiC substrate in the hexagonal system can be used as the semiconductor substrate 1. By using a SiC substrate for the semiconductor substrate 1, the breakdown voltage of the semiconductor substrate 1 can be increased. In addition, the thermal conductivity of silicon carbide is large, and heat generated by the on-current of the semiconductor device 100 can be efficiently dissipated. A semiconductor device 100 with high cooling performance can be provided.

[0017] Further, the semiconductor substrate 1 is not limited to the SiC substrate, and other semiconductor materials with a wide bandgap may be used. Examples of semiconductor materials with a wide bandgap include III-V compound semiconductors using nitrogen as a Group V element such as GaN (gallium nitride), AlN (aluminum nitride), AlGaN (aluminum gallium nitride), InN (indium nitride), diamond, ZnO (zinc oxide), and the like.

[0018] The N-type drift region 2 is formed in contact with one main surface 1a of the semiconductor substrate 1. One main surface 1a is the surface facing the positive direction of the Z-axis of the semiconductor substrate 1, that is, the top surface. In the Z direction, the direction in which the drift region 2 is located as viewed from the semiconductor substrate 1 is also referred to as the upward direction, and the direction in which the semiconductor substrate 1 is located as viewed from the drift region 2 is also referred to as the downward direction. The surface facing upward of each member is referred to as the top surface, the surface facing downward is referred to as the bottom surface, and the surface connecting the top surface and the side surface is referred to as the side surface. For example, the N-type drift region 2 is a region formed in the upper part of the semiconductor substrate 1 including the top surface (one main surface 1a) of the semiconductor substrate 1.

[0019] The N-type drift region 2 is a region through which current flows in the semiconductor device 100 when the transistor (semiconductor device 100) is in the on state. The current flows from the drain region 5 to the source region 4 (in the positive X-axis direction) in the drift region 2. The drift region 2 is in contact with the P-type well region 3 in the positive X-axis direction (arrow direction) and is in contact with the N-type drain region 5 in the negative X-axis direction (opposite to the arrow direction). The well region 3 and the drain region 5 are not in direct contact but are electrically connected via the drift region 2.

[0020] The drift region 2 may be formed of a wide bandgap semiconductor. Thereby, it is possible to achieve both low on-resistance and high breakdown voltage. The semiconductor substrate 1, the well region 3, and the drift region 2 may be formed of the same material. Thereby, it is possible to prevent performance degradation such as lattice mismatch that occurs when different materials are used.

[0021] The P-type well region 3 is formed in contact with the N-type drift region 2. The interface between the well region 3 and the drift region 2 forms a PN junction. The P-type impurity concentration in the well region 3 is, for example, 1E15 cm -3 or more and 1E19 cm -3 or less. Similar to the drift region 2, the well region 3 is preferably formed of a wide-bandgap semiconductor. It is possible to achieve both low on-resistance and high breakdown electric field.

[0022] The N-type source region 4 is formed within the well region 3. The interface between the source region 4 and the well region 3 forms a PN junction. The N-type impurity concentration in the source region 4 is higher than that in the drift region 2, for example, 1E18 cm -3 or more and 1E21 cm -3 or less. The source region 4 is joined to the second electrode 11 on its upper surface. The source region 4 and the second electrode 11 form an ohmic contact.

[0023] In the manufacturing process of the semiconductor device 100, a groove 8 is formed in the semiconductor substrate 1. The groove 8 is in contact with the source region 4, the well region 3, and the drift region 2. The groove 8 is defined by a bottom 8a, a first side surface 8b perpendicular to the direction of the current flowing from the drain region 5 to the source region 4, i.e., the positive direction of the X-axis, and a second side surface 8c of the groove 8 parallel to the direction of the current flowing from the drain region 5 to the source region 4. The groove 8 is in contact with the source region 4, the well region 3, and the drift region 2 at least at the second side surface 8c. The groove 8 penetrates the source region 4, the well region 3, and the drift region 2 when viewed in the negative direction of the Z-axis. The bottom 8a of the groove 8 reaches the semiconductor substrate 1.

[0024] As shown in FIGS. 1 and 2, the P-type anode region 9 is formed in contact with the bottom 8a of the groove 8 and the first side surface 8b of the groove 8. On the other hand, as shown in FIG. 3, the anode region 9 is not formed on the second side surface 8c of the groove 8. The anode region 9 formed on the bottom 8a of the groove 8 is in contact with the well region 3 at the second side surface 8c of the groove 8. As shown in FIGS. 2 and 3, the anode region 9 formed in contact with the first side surface 8b on the drain region 5 side (negative X-axis side) of the groove 8 is in contact with the drift region 2 at the first side surface 8b and the second side surface 8c. The upper end portion of the anode region 9 formed on the first side surface 8b on the source region 4 side of the groove 8 is in contact with the second electrode 11. The anode region 9 and the second electrode 11 form an ohmic contact.

[0025] The anode region 9 is made of a material different from that of the drift region 2. For example, the anode region 9 is made of silicon (Si) instead of silicon carbide (SiC). The anode region 9 may be P-type polysilicon. The impurity level of P-type polysilicon is close to that of P-type silicon carbide. Therefore, the well region 3 made of P-type silicon carbide and the anode region 9 are connected with low resistance. Thus, it becomes easier to fix the potential of the well region 3, and a semiconductor device 100 that is resistant to noise can be provided. When the anode region 9 is made of polysilicon, contamination to the gate electrode 7 is less than that of a metal material, and a highly reliable semiconductor device 100 can be provided.

[0026] The anode region 9 and the drift region 2 are hetero-junctioned. A heterojunction diode (HJD) is formed at the junction interface where the P-type polysilicon anode region 9 and the N-type silicon carbide drift region 2 are in contact. In contrast, the well region 3 and the drift region 2 are PN-junctioned. The heterojunction diode has a lower turn-on voltage and lower resistance than a PN diode made of silicon carbide, so diode loss can be reduced.

[0027] The interlayer insulating film 6 is disposed inside the groove 8 and formed in contact with the second side surface 8c of the groove 8 and the anode region 9. The interlayer insulating film 6 includes a first interlayer insulating film 6a formed in contact with the anode region 9 and a second interlayer insulating film 6b formed in contact with the second side surface 8c of the groove. The film thickness of the first interlayer insulating film 6a is thicker than that of the second interlayer insulating film 6b. For example, the film thickness of the first interlayer insulating film 6a is about several hundreds of nm, and the film thickness of the second interlayer insulating film 6b is about several tens of nm.

[0028] The gate electrode 7 is disposed inside the groove 8 via the interlayer insulating film 6. As the material of the gate electrode 7, for example, polycrystalline silicon doped with a high concentration of N-type or P-type impurities can be used. Instead of polycrystalline silicon, other semiconductor materials such as silicon carbide (SiC) and silicon germanium (SiGe), or metal materials such as aluminum (Al) may be used.

[0029] The impurity concentration of the semiconductor substrate 1 may be lower than that of the drift region 2. Alternatively, the semiconductor substrate 1 may be a semi-insulating semiconductor substrate. Thereby, when cooling the semiconductor device 100, an insulating material between the semiconductor device 100 and the cooler becomes unnecessary. The cooling performance is improved and the attachment to the cooler can be facilitated. Also, when the semiconductor device 100 is off, the semiconductor substrate 1 and the first electrode 12 are not at the same potential. Therefore, a high electric field is not applied to the well region 3 or the anode region 9 in contact with the semiconductor substrate 1 as compared with a conductive substrate. Thus, the breakdown voltage of the semiconductor device 100 is improved.

[0030] Next, the basic operation of the semiconductor device 100 shown in FIGS. 1 to 3 will be described.

[0031] The semiconductor device 100 operates as a transistor by controlling the potential of the gate electrode 7 while applying a positive potential to the first electrode 12 with reference to the potential of the second electrode 11. At this time, the potential of the P-type anode region 9 is fixed by the second electrode 11, and the potential of the well region 3 is fixed by the P-type anode region 9. When the potential difference between the gate electrode 7 and the second electrode 11 becomes equal to or greater than a predetermined threshold voltage, an inversion layer is formed at the interface between the P-type well region 3 in contact with the second side surface 8c of the groove 8 and the second interlayer insulating film 6b (gate insulating film), the transistor becomes in an on state, and a current flows from the first electrode 12 to the second electrode 11. Specifically, electrons supplied from the second electrode 11 flow into the drift region 2 from the source region 4 through the inversion layer, and flow from the drift region 2 to the first electrode 12 through the drain region 5.

[0032] Since the potential of the well region 3 can be fixed by using the anode region 9 made of P-type polysilicon, a P+ region made of silicon carbide doped with a high concentration of P-type impurities becomes unnecessary. Since the anode region 9 is formed inside the groove 8, it does not affect the size of the semiconductor device 100. Therefore, the size of the semiconductor device 100 can be reduced as compared with the potential fixing of the well region 3 by the P+ region made of silicon carbide.

[0033] On the other hand, when the potential difference between the gate electrode 7 and the second electrode 11 becomes less than a predetermined threshold voltage, the inversion layer disappears, the transistor becomes in an off state, and the current is cut off. In the off state, a high voltage is applied between the first electrode 12 and the first electrode 11. As a result, a depletion layer spreads into the drift region 2 from the surface where the well region 3 and the drift region 2 are in contact and the surface where the anode region 9 and the drift region 2 are in contact. The wider the voltage between the first electrode 12 and the second electrode 11 becomes, the wider the depletion layer spreads. When the voltage between the first electrode 12 and the second electrode 11 reaches a predetermined maximum voltage, the spread of the depletion layer stops. At this time, the distances between the drain region 5 and the anode region 9 and between the drain region 5 and the well region 3 are designed so that the electric field applied inside the semiconductor device 100 is below the breakdown electric field of each material.

[0034] Next, the turn-on operation of the transistor will be described. Generally, when the transistor switches from the off state to the on state, it is preferable that the potential of the gate electrode 7 changes immediately to a predetermined potential. However, since the capacitance Cgs exists between the gate electrode 7 and the second electrode 11, the rise of the gate potential starts after the capacitance Cgs is charged. The power generated during this period becomes switching loss. To increase the potential of the gate electrode 7 quickly, it is preferable that the capacitance Cgs is small. Therefore, the thickness of the first interlayer insulating film 6a in contact with the anode region 9 is made thicker than the thickness of the second interlayer insulating film 6b in contact with the well region 3 exposed on the second side surface 8c of the groove 8. Thereby, the capacitance Cgs formed between the gate electrode 7 and the anode region 9 can be reduced. Since the capacitance Cgs can be lowered, the gate potential is applied earlier, and the turn-on loss can be reduced.

[0035] When the semiconductor device 100 (transistor) is used in an inverter circuit for driving a motor, even when the transistor is in the off state, the motor rotates due to inertia, so a regenerative current may flow through the body diode built into the transistor. In the present embodiment, a heterojunction diode is formed between the anode region 9 made of P-type polysilicon and the drift region 2 made of N-type silicon carbide. The turn-on voltage of this heterojunction diode is affected by the band gaps of P-type polysilicon and N-type silicon carbide, and is approximately 1.5 V or less, which is 50% or more lower than the turn-on voltage of a PN diode of silicon carbide. When the current returns from the motor to the battery, the second electrode becomes a positive potential with the first electrode 12 as the reference potential. In the semiconductor device 100, when the potential of the second electrode 11 exceeds the turn-on voltage of the heterojunction diode, a regenerative current starts to flow between the second electrode 11 and the first electrode 12. The regenerative current at this time flows from the second electrode 11, through the anode region 9 to the drift region 2, from the drift region 2 to the drain region 5, and finally to the first electrode 12. In this way, the transistor enters the regenerative state, and a regenerative current flows through the heterojunction diode provided in the semiconductor device 100. The loss in the transistor at this time is the product of the current value of the heterojunction diode and the potential difference between the second electrode 11 and the first electrode 12 at that time. Since the turn-on voltage of the heterojunction diode is lower than that of a silicon carbide PN diode, the diode loss can be reduced.

[0036] [Method for manufacturing a semiconductor device] Next, with reference to FIGS. 4A to 11B, an example of a method for manufacturing the semiconductor device 100 according to the present embodiment will be described.

[0037] First, a semiconductor substrate 1 without impurities added is prepared. As shown in FIGS. 4A and 4B, a drift region 2 is formed in the semiconductor substrate 1 by an ion implantation method. Specifically, N-type impurities are ion-implanted into the semiconductor substrate 1 to form a drift region 2 made of N-type silicon carbide. The implantation concentration is 1E14 cm -3 ~1E18 cm -3It is sufficient to adjust the thickness of the drift region 2 according to the acceleration energy during ion implantation. The thickness of the drift region 2 is preferably several μm or less.

[0038] Note that the region to be ion-implanted may be patterned. In this case, ion implantation is performed using a mask material made of a silicon oxide film as a mask. Specifically, as the method for depositing the silicon oxide film, a thermal CVD method or a plasma CVD method can be used. A resist is patterned on the silicon oxide film (not shown). As the patterning method, a general photolithography method can be used. Using the patterned resist as a mask, the mask material is etched. As the etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used. After etching the mask material, the resist is removed with oxygen plasma or sulfuric acid or the like. Using the mask material as a mask, N-type impurities such as nitrogen (N) are ion-implanted. By performing ion implantation while heating the semiconductor substrate 1 to about 600°C, the generation of crystal defects in the implanted region can be suppressed. After ion implantation, the mask material is removed by etching using, for example, hydrofluoric acid. The cross section after forming the drift region 2 is shown in FIGS. 4A and 4B.

[0039] Next, a P-type well region 3, an N-type source region 4, and an N-type drain region 5 are formed using an ion implantation method. As the formation order, it is preferable to first form the well region 3. Thereafter, the source region 4 and the drain region 5 may be formed simultaneously. The method for patterning the region to be ion-implanted can be the same method as that for the drift region 2 described above. As the P-type impurity, aluminum (Al) or boron (B) can be used. As the N-type impurity, nitrogen (N) can be used. The impurity concentration of the source region 4 and the drain region 5 is preferably 1E18 cm -3 ~1E21 cm -3 is suitable. Also, the concentration of the well region 3 is preferably 1E15 cm -3 ~1E19 cm -3 is suitable.

[0040] Thereafter, the heat treatment process is used to activate the ion-implanted impurities. A temperature of about 1700°C can be used as the heat treatment temperature. As the atmosphere during heat treatment, argon (Ar) or nitrogen (N) can be preferably used. As a result, as shown in FIGS. 5A and 5B, a drift region 2, a well region 3, a source region 4, and a drain region 5 are formed on the upper part including one main surface 1a of the semiconductor substrate 1.

[0041] Next, as shown in FIGS. 6A and 6B, a part of the semiconductor substrate 1 is etched to form a groove 8. Specifically, a mask material made of a silicon oxide film is formed and patterned. Using the patterned mask material as a mask, a part of the drift region 2, the well region 3, the source region 4, and the drain region 5 is etched by dry etching to form the groove 8. Thereafter, the mask material is removed by hydrofluoric acid cleaning.

[0042] Next, an anode film 9a serving as an anode region 9 is formed inside the groove 8. Specifically, the anode film 9a is formed on the semiconductor substrate 1. The thickness of the anode film 9a is not less than 1 / 2 of the width of the groove 8 in FIG. 7B. That is, a polysilicon film having a film thickness not less than 1 / 2 of the length of the groove 8 in the Y direction is deposited on the entire surface of the semiconductor substrate 1. As a result, as shown in FIGS. 7A and 7B, the anode film 9a is formed inside the groove 8. By setting the film thickness of the polysilicon film to not less than 1 / 2 of the length of the groove 8 in the Y direction, the inside of the groove 8 can be filled back with the anode film 9a. After the polysilicon deposition, annealing is performed in an atmosphere of boron trichloride (BCl3) at 950°C to form the anode film 9a made of conductive P-type polysilicon.

[0043] Next, as shown in FIGS. 8A and 8B, the surface of the anode film 9a is etched. Any etching method may be used, either isotropic etching or anisotropic selective etching. This etching is preferably a full-surface etching without using a mask. The anode film 9a is etched until the film thickness of the anode film 9a formed on the drift region 2, well region 3, and drain region 5 other than the groove 8 becomes a thickness that can be completely oxidized by the thermal oxidation treatment of the anode film 9a described later.

[0044] Next, by etching a part of the anode film 9a embedded inside the groove 8, an anode region 9 is formed inside the groove 8 as shown in FIGS. 9A and 9B. Specifically, the resist is patterned by lithography, and a part of the anode film 9a may be etched using the patterned resist as a mask. At this time, as shown in FIG. 9A, the anode region 9 is formed on the bottom 8a and the first side surface 8b of the groove 8. As shown in FIG. 9B, the anode film 9a on the second side surface 8c of the groove 8 is removed, and the well region 3 is exposed on the second side surface 8c. Inside the groove 8, a recess 10 surrounded by the anode region 9 and the second side surface 8c of the groove 8 is formed. Although not shown, not only the well region 3 but also the drift region 2 and the source region 4 are exposed on the second side surface 8c.

[0045] By thermally oxidizing the exposed portions of the anode film 9a, anode region 9, well region 3, drift region 2, and source region 4, an interlayer insulating film 6 is formed as shown in FIGS. 10A and 10B. Specifically, it is heated at a temperature of about 1100°C in an oxygen atmosphere. A thermal oxide film is formed on the exposed surface where oxygen touches. Here, the thermal oxidation rate of the anode film 9a and anode region 9 made of polysilicon film is faster than that of the well region 3, drift region 2, and source region 4 made of silicon carbide. When a silicon oxide film with a thickness of several tens of nm is formed on the exposed surface of silicon carbide (2, 3, 4), a silicon oxide film with a thickness of several hundreds of nm is formed on the exposed surface of polysilicon (9, 9a). Therefore, a first interlayer insulating film 6a is formed on the anode region 9 disposed at the bottom 8a and the first side surface 8b of the groove 8, and a second interlayer insulating film 6b is formed on the second side surface 8c of the groove 8. Note that all the anode films 9a formed on the drift region 2, well region 3, and drain region 5 other than the groove 8 are oxidized to become the interlayer insulating film 6.

[0046] After forming the interlayer insulating film 6, in order to reduce the interface states at the interface between the well region 3 and the second interlayer insulating film 6b, annealing may be performed at about 1000°C in an atmosphere such as nitrogen, argon, or N2O (nitrous oxide). Also, direct thermal oxidation in a NO (nitric oxide) or N2O atmosphere is also possible. In that case, a temperature of 1100°C to 1400°C is suitable.

[0047] Next, a gate electrode 7 is formed inside the recess 10 surrounded by the interlayer insulating films (6a, 6b). Specifically, a polysilicon film is deposited to a thickness such that the recess 10 is filled back. As a method for depositing the polysilicon film, a low-pressure CVD method may be used. The deposition thickness of the polysilicon film is not limited, but it may be about 1 μm. Also, after depositing the polysilicon film, annealing in phosphoryl chloride (POCl3) forms a conductive N-type polysilicon film. The annealing temperature is preferably 950°C. By leaving the polysilicon film inside the recess 10 and etching the other polysilicon films, a gate electrode 7 is formed inside the recess 10 as shown in FIGS. 11A and 11B.

[0048] Next, contact holes for forming the first electrode 12 and the second electrode 11 are formed in the interlayer insulating film 6. The drain region 5 is exposed at the bottom of the contact hole for the first electrode 12. The anode region 9 and the source region 4 are exposed in the contact hole for the second electrode 11. Then, the first electrode 12 and the second electrode 11 are formed. As the electrode material, titanium (Ti), nickel (Ni), molybdenum (Mo), or a laminated film such as Ni / Ti / Al can be used. The deposition method of the electrode film can use the sputtering method. After depositing the electrode film, the electrode film is patterned using a mask material. Through the above manufacturing process, the semiconductor device 100 shown in FIGS. 1 to 3 is completed. In FIGS. 1 to 3, the interlayer insulating film 6 formed on one main surface 1a of the semiconductor substrate 1 is not shown.

[0049] According to the manufacturing method of the semiconductor device 100 described above, the following effects can be obtained.

[0050] An anode film 9a that becomes the anode region 9 is formed inside the groove 8. The thickness of the anode film 9a is set to be 1 / 2 or more of the width of the groove 8. Thereby, the anode region 9 can be formed by a film formation method. Also, by setting the film thickness of the anode film 9a to 1 / 2 or more of the groove width, the groove 8 can be filled with the anode film 9a in a single film formation, the surface of the semiconductor substrate 1 can be made flat thereafter, the next process can be easily executed, and a highly reliable manufacturing method can be provided.

[0051] As shown in FIG. 9B, the well region 3 is exposed on the second side surface 8c of the groove, and the anode film 9a is selectively etched so that a part of the anode film 9a remains at the bottom of the groove 8. The anisotropic etching of the anode film 9a etches the anode film 9a by causing plasma to collide with the anode film 9a from the surface of the semiconductor substrate 1. At this time, if the anode film 9a at the bottom 8a of the groove 8 is completely etched, the plasma also collides with the bottom 8a of the groove 8, so the semiconductor substrate 1 at the bottom 8a of the groove 8 becomes rough. Therefore, by leaving the anode film 9a at the bottom 8a of the groove 8, a highly reliable semiconductor device 100 can be provided because the semiconductor substrate 1 does not become rough.

[0052] (Second Embodiment) [Structure of Semiconductor Device] FIG. 12 is a cross-sectional perspective view showing the structure of a semiconductor device 101 according to the second embodiment. FIG. 13 is a cross-sectional view of the semiconductor device 101 in the XZ plane including the XIII-XIII cut line of FIG. 12. The cross-sectional view of the semiconductor device 101 in the YZ plane including the III-III cut line of FIG. 12 is the same as FIG. 3. The semiconductor device 101 according to the second embodiment is different in that it further has a P-type electric field protection region 13A compared to the semiconductor device 100. The other configurations of the semiconductor device 101 are the same as those of the semiconductor device 100, and the same reference numerals are given in FIGS. 12 and 13, and the repeated description is omitted.

[0053] The electric field protection region 13A is in contact with the anode region 9 on the first side surface 8b of the groove 8 facing the drain region 5. The length of the electric field protection region 13A in the Y-axis direction is substantially the same as that of the groove 8, and the side surface of the electric field protection region 13A parallel to the XZ plane and the side surface of the groove 8 may be flush. The length of the electric field protection region 13A in the Z-axis direction may be formed to reach deeper into the semiconductor substrate 1 than the drift region 2 from the main surface 1a of the semiconductor substrate 1. The electric field protection region 13A is made of a wide-gap semiconductor such as silicon carbide, the same as the drift region, and the electric field protection region 13A and the drift region 2 form a PN junction. The electric field protection region 13A is electrically connected to the anode region 9 with low resistance, and the potential of the electric field protection region 13A is fixed by the anode region 9.

[0054] When the voltage between the gate electrode 7 and the second electrode 11 is made equal to or lower than a predetermined threshold voltage, the transistor turns off. At this time, a high voltage is applied between the first electrode 12 and the second electrode 11. At this time, depletion layers respectively spread into the drift region from the interfaces where the well region 3 contacts the drift region 2 and where the anode region 9 contacts the drift region 2. The higher the voltage between the first electrode 12 and the second electrode 11, the wider the width of the depletion layer, and the electric field concentrates on each of the above-described interfaces. Since the anode region 9 is made of silicon, its breakdown voltage is lower than that of silicon carbide. Thus, when the breakdown voltage of the material used for the anode region 9 is lower than the breakdown voltage of the material of the semiconductor substrate 1, breakdown of the anode region 9 is likely to occur on the first side surface 8b of the groove 8 facing the drain region 5. Therefore, an electric field protection region 13A made of P-type silicon carbide that contacts the anode region 9 is disposed on the first side surface 8b of the groove 8 facing the drain region 5. Thereby, the electric field concentration on the first side surface 8b of the groove 8 facing the drain region 5 can be alleviated, so that a semiconductor device 101 with a high breakdown voltage can be provided.

[0055] The basic operation of the semiconductor device 100 and the turn-on operation of the transistor are the same as those in the first embodiment, and thus the description thereof is omitted.

[0056] According to the semiconductor device 101, the same operational effects as those of the semiconductor device 100 can be obtained.

[0057] [Manufacturing Method of Semiconductor Device] Next, an example of a manufacturing method of the semiconductor device 101 according to the present embodiment will be described.

[0058] As shown in FIGS. 4A and 4B, the process of forming the N-type drift region 2 in the semiconductor substrate 1 is the same as that in the first embodiment. Next, in the process of forming the P-type well region 3, the N-type source region 4, and the N-type drain region 5 shown in FIGS. 5A and 5B, a P-type electric field protection region 13A is formed. Specifically, as shown in FIG. 14, the P-type well region 3 can be formed first, and then the P-type electric field protection region 13A can be formed. Thereafter, the source region 4 and the drain region 5 may be formed simultaneously. The impurity concentration of the electric field protection region 13A is different from that of the well region 3 and may be 1E18 cm -3 or more and 1E19 cm -3 or less. The implantation depth may be deeper than the drift region 2 and reach the semiconductor substrate 1. The activation process of the impurities after ion implantation is the same as that in the first embodiment.

[0059] As shown in FIG. 15, the groove 8 is formed such that the electric field protection region 13A appears on the first side surface on the drift region 2 side. The cross-sectional structure in the YZ cross-sectional plane including the III-III cutting line in FIG. 12 is the same as that in FIG. 6B, and the illustration is omitted.

[0060] The subsequent manufacturing process of the semiconductor device 101 is the same as the manufacturing process of the semiconductor device 100 described with reference to FIGS. 7A to 11B, and the illustration and repeated description are omitted.

[0061] According to the manufacturing method of the semiconductor device 101 described above, the same operational effects as those of the manufacturing method of the semiconductor device 100 can be obtained.

[0062] (Third Embodiment) [Structure of Semiconductor Device] FIG. 16 is a cross-sectional perspective view showing the structure of the semiconductor device 102 according to the third embodiment. FIG. 17 is a cross-sectional view of the semiconductor device 102 in the XZ plane including the XVII-XVII cutting line of FIG. 16. The cross-sectional view of the semiconductor device 102 in the YZ plane including the III-III cutting line of FIG. 16 is the same as FIG. 3. The semiconductor device 102 according to the third embodiment is different from the semiconductor device 100 in that it further has a P-type electric field protection region 13B. The electric field protection region 13B is in contact with the anode region 9 on the first side surface 8b of the groove 8 facing the drain region 5. The length of the electric field protection region 13B in the X direction is longer than that of the electric field protection region 13A in FIGS. 12 and 13. The end portion of the electric field protection region 13B on the side of the first electrode 12 is located near the drain region 5. The lengths of the electric field protection region 13B in the Y-axis direction and the Z-axis direction are the same as those of the electric field protection region 13A.

[0063] When the voltage between the gate electrode 7 and the second electrode 11 is made equal to or lower than a predetermined threshold voltage, the transistor is turned off. At this time, a high voltage is applied between the first electrode 12 and the second electrode 11. At this time, depletion layers respectively spread into the drift region 2 from the interfaces where the well region 3 and the drift region 2 are in contact and where the anode region 9 and the drift region 2 are in contact. Further, depletion layers respectively spread into the drift region 2 and the electric field protection region 13B from the interface where the electric field protection region 13B and the drift region 2 are in contact. The higher the voltage between the first electrode 12 and the second electrode 11, the wider the width of the depletion layer becomes, and the drift region 2 and the electric field protection region 13B enter a completely depleted state (pinch-off state). By entering the pinch-off state, the electric field distribution in the drift region 2 and the electric field protection region 13B becomes a uniform rectangular distribution, and the maximum electric field applied to the semiconductor device 102 is greatly reduced. Thereby, the breakdown voltage of the semiconductor device 102 is improved.

[0064] When the breakdown voltage of the material used for the anode region 9 is lower than that of the material of the semiconductor substrate 1, breakdown of the anode region 9 is likely to occur on the first side surface 8b of the groove 8 facing the drift region 2. Therefore, an electric field protection region 13B made of P-type silicon carbide in contact with the anode region 9 is disposed on the first side surface 8b of the groove 8 facing the drain region 5. Thereby, since the electric field concentration on the first side surface 8b of the groove 8 facing the drain region 5 can be alleviated, a semiconductor device 102 with a high breakdown voltage can be provided.

[0065] Other configurations, operations, and technical effects are the same as those of the semiconductor device 101, and the same reference numerals are given in FIGS. 16 and 17, and repeated descriptions are omitted.

[0066] [Method for manufacturing a semiconductor device] Next, an example of a method for manufacturing the semiconductor device 102 according to the present embodiment will be described.

[0067] As shown in FIGS. 4A and 4B, the step of forming the N-type drift region 2 in the semiconductor substrate 1 is the same as that in the first embodiment. Next, in the steps of forming the P-type well region 3, the N-type source region 4, and the N-type drain region 5 shown in FIGS. 5A and 5B, a P-type electric field protection region 13B is formed. Specifically, as shown in FIG. 18, the P-type well region 3 may be formed first, and then the P-type electric field protection region 13B may be formed. Thereafter, the source region 4 and the drain region 5 may be formed simultaneously. The impurity concentration of the electric field protection region 13B is different from that of the well region 3, and is 1E17 cm -3 Above 1E18 cm -3 The following may be used. The implantation depth may be deeper than the drift region 2 and reach the semiconductor substrate 1. The impurity activation process after ion implantation is the same as that in the first embodiment.

[0068] As shown in FIG. 19, the groove 8 is formed such that the electric field protection region 13B appears on the first side surface on the drift region 2 side. The cross-sectional structure in the YZ cross-section including the III-III cutting line in FIG. 16 is the same as that in FIG. 6B, and the illustration is omitted.

[0069] The subsequent manufacturing process of the semiconductor device 102 is the same as that of the semiconductor device 100 described with reference to FIGS. 7A to 11B, and the illustration and description thereof are omitted.

[0070] According to the manufacturing method of the semiconductor device 102 described above, the same operational effects as those of the manufacturing method of the semiconductor device 100 can be obtained.

[0071] (Fourth Embodiment) [Structure of Semiconductor Device] FIG. 20 is a cross-sectional perspective view showing the structure of a semiconductor device 103 according to the fourth embodiment. FIG. 21 is a cross-sectional view of the semiconductor device 103 in the XZ plane including the cutting line XXI-XXI of FIG. 20. FIG. 22 is a cross-sectional view of the semiconductor device 103 in the YZ plane including the cutting line XXII-XXII of FIG. 20. The semiconductor device 103 according to the third embodiment further includes a protective film 14 disposed on one main surface 1a of the semiconductor substrate 1, and a plate electrode 15 disposed so as to cover the interface where the anode region 9 and the drift region 2 are in contact with each other on the protective film 14. The protective film 14 is disposed on one main surface 1a of the semiconductor substrate 1 where the first electrode 12 and the second electrode 11 are not formed. One end of the plate electrode 15 in the X-axis direction is in contact with the second electrode 11 and is electrically connected to the second electrode 11 with low resistance. When viewed in the negative direction of the Z-axis, the other end of the plate electrode 15 in the X-axis direction is located on the drain region 5 side with respect to the interface where the anode region 9 and the drift region 2 are in contact with each other. The plate electrode 15 covers the interface where the anode region 9 and the drift region 2 are in contact with each other when viewed in the negative direction of the Z-axis.

[0072] By providing the plate electrode 15, the electric field applied to the interface between the anode region 9 and the drift region 2 is dispersed by the plate electrode 15. In other words, when the transistor is in the off state, a part of the electric field applied to the interface between the anode region 9 and the drift region 2 is shared by the plate electrode 15. Therefore, the electric field concentration at the interface between the anode region 9 and the drift region 2 can be alleviated. Thus, a semiconductor device 103 having a higher breakdown voltage than the semiconductor device 102 of the third embodiment can be provided.

[0073] Other configurations, operations, and technical effects are the same as those of the semiconductor device 102, and the same reference numerals are used in FIGS. 20 to 22, and the repeated description is omitted.

[0074] [Method for manufacturing a semiconductor device] Next, an example of a method for manufacturing the semiconductor device 103 according to the present embodiment will be described. From the formation of the drift region 2 in FIGS. 4A and 4B to the formation of the gate electrode 7 in FIGS. 11A and 11B, it is the same as the method for manufacturing the semiconductor device 102 of the third embodiment, and the repeated description is omitted.

[0075] Thereafter, for example, by chemical mechanical polishing (CMP), a part (upper part) of the interlayer insulating film 6 and the gate electrode 7 formed on the main surface 1a of the semiconductor substrate 1 shown in FIGS. 11A and 11B is ground to expose the main surface 1a of the semiconductor substrate 1.

[0076] Thereafter, as shown in FIGS. 23A and 23B, a protective film 14 made of a silicon oxide film is formed. As a film formation method, a thermal CVD method or a plasma CVD method can be used.

[0077] Next, as shown in FIG. 24, the protective film 14 is selectively etched to form contact holes for forming the second electrode 11 and the first electrode 12. The drain region 5, the anode region 9, and the source region 4 (not shown) are exposed at the bottom of the contact hole. Thereafter, the second electrode 11 and the first electrode 12 are formed in the same manner as in the first embodiment. When patterning the electrode film, by changing the shape of the mask material, not only the second electrode 11 and the first electrode 12 but also the plate electrode 15 can be formed simultaneously. Through the above manufacturing process, the semiconductor device 103 shown in FIGS. 20 to 22 is completed.

[0078] According to the method for manufacturing the semiconductor device 103 described above, the same operational effects as those of the method for manufacturing the semiconductor device 100 can be obtained.

[0079] As described above, embodiments of the present invention have been described, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0080] As a method for forming the drift region 2, a method of ion implanting into the semiconductor substrate 1 has been described, but a drift region 2 made of single-crystalline SiC may be grown on the main surface of the semiconductor substrate 1 using an epitaxial growth method.

[0081] In the fourth embodiment (FIG. 21), a semiconductor device 103 further including a protective film 14 and a plate electrode 15 was exemplified with respect to the semiconductor device 102 according to the third embodiment. Not limited to this, a semiconductor device according to a modification of the fourth embodiment may further include a protective film 14 and a plate electrode 15 with respect to the semiconductor device 100 according to the first embodiment or the semiconductor device 101 according to the second embodiment.

Description of Reference Numerals

[0082] 1 Semiconductor substrate 1a Main surface 2 Drift region 3 Well region 4 Source region 5 Drain region 6 Interlayer insulating film 6a First interlayer insulating film 6b Second interlayer insulating film 7 Gate electrode 8 Groove 8a Bottom 8b First side surface 8c Second side surface 9 Anode region 9a Anode film 10 Recess 11 Second electrode 12 First electrode 13A, 13B Electric field protection regions 14 Protective film 15 Plate electrode 100 - 103 Semiconductor devices

Claims

1. A semiconductor substrate, A drift region of a first conductivity type formed in contact with one main surface of the semiconductor substrate, A well region of a second conductivity type formed in contact with the drift region, A drain region of a first conductivity type formed in the drift region separated from the well region, A first electrode electrically connected to the drain region, A source region of a first conductivity type formed in the well region, A second conductivity type anode region formed in contact with the bottom of a groove formed in contact with the source region, the well region, and the drift region, and a first side surface of the groove perpendicular to the direction of current flowing from the drain region to the source region, A second side surface of the groove parallel to the direction of current flowing from the drain region to the source region, and an interlayer insulating film formed in contact with the anode region, A gate electrode disposed inside the groove through the interlayer insulating film, A second electrode electrically connected to the anode region and the source region, and having, The anode region is in contact with the well region at least at the bottom of the groove, A semiconductor device in which the anode region and the drift region are hetero-junctioned.

2. The semiconductor device according to claim 1, further comprising a second conductivity type field protection region in contact with the anode region on the first side surface of the groove facing the drain region.

3. The semiconductor device according to claim 1, wherein the anode region is made of silicon.

4. The interlayer insulating film, A first interlayer insulating film formed in contact with the anode region, A second interlayer insulating film formed in contact with the second side surface of the groove, and comprising, The semiconductor device according to claim 1, wherein the film thickness of the first interlayer insulating film is thicker than the film thickness of the second interlayer insulating film.

5. A protective film disposed on the main surface of the semiconductor substrate, On the protective film, a plate electrode disposed so as to cover a surface where the anode region and the drift region are in contact and electrically connected to the second electrode, and further comprising the semiconductor device according to claim 1.

6. The semiconductor device according to claim 1, wherein the impurity concentration of the semiconductor substrate is lower than the impurity concentration of the drift region, or the semiconductor substrate is a semi-insulating semiconductor substrate.

7. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of a wide bandgap semiconductor.

8. A method for manufacturing the semiconductor device according to any one of claims 1 to 7, A step of forming an anode film serving as the anode region inside the groove is included, A method for manufacturing a semiconductor device, wherein the thickness of the anode film is equal to or greater than 1 / 2 of the width of the groove. **Claim 9** A method for manufacturing a semiconductor device according to any one of Claims 1 to 7, A step of forming an anode film serving as the anode region inside the groove, and A step of selectively etching the anode film such that the well region is exposed on a second side surface of the groove and a part of the anode region remains at the bottom of the groove. A method for manufacturing a semiconductor device having these steps.

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