Semiconductor device and power conversion device using the same

Abstract

To provide a semiconductor device with which it is possible to both reduce switching losses and improve resistance to power cycles.SOLUTION: Provided is a semiconductor device including one or more of a half bridge circuit 100. The semiconductor device comprises: an insulating substrate 10; a conductor layer patterns 11-20; a plurality of power semiconductor elements 21-24; lead frames 25, 26 for connecting each of the power semiconductor elements 21-24 to the conductor patterns 11-20; individual gate wirings 31-34, 51-54; and main terminals 1, 3. The lead frames include a first connection face part connecting to each of electrode faces of the plurality of power semiconductor elements 21-24, a lead frame branch part branched into many, and a second connecting face part connecting to a second conductive layer pattern and provided at end of the lead frame branch part. In a top view of the insulating substrate, the gate electrodes and the individual gate wirings are held between two lead frame branch parts.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to the configuration of a semiconductor device, and more particularly to a technique effective when applied to a power semiconductor module configured by connecting a plurality of power semiconductor elements in parallel.

Background Art

[0002] In power control and motor control of industrial equipment, electric railway vehicles, automobiles, home appliances, etc., a power semiconductor module in which a plurality of semiconductor elements such as switching elements such as power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), and freewheel diodes are mounted on one module is used.

[0003] In recent years, GaN (gallium nitride) and SiC (silicon carbide) have been used as materials for power semiconductor chips, and advantages such as high switching speed and high operating temperature compared to semiconductor elements using Si (silicon) are being utilized. Currently, since GaN and SiC elements have a small element size, in order to configure a power semiconductor module that satisfies a predetermined current capacity, it is necessary to connect a plurality of power semiconductor chips in parallel and mount them on an insulating substrate in the module.

[0004] In applications such as automotive inverters where power loss in the inverter affects the cruising range of electric vehicles and fuel cell vehicles, it is necessary to minimize the power loss generated in the power semiconductor module. Therefore, in the power semiconductor module, it is important to suppress both the resistive loss during conduction and the transient switching loss during switching to a small value. In order to reduce the switching loss, it is essential to perform switching in a short time, that is, high-speed switching.

[0005] In addition, high reliability is required for the power semiconductor module used in the inverter. The power cycle tolerance indicating the reliability of the power semiconductor module is determined by the deterioration of the solder used for the junction between the electrodes of the power semiconductor chip built in the module and the wiring material. In order to suppress the deterioration of the solder and improve the power cycle tolerance, it is necessary to reduce the thermal stress applied to the solder and to make the thermal stress uniform for each power semiconductor chip.

[0006] When the thermal stress is non-uniform among the power semiconductor chips, one power semiconductor chip will deteriorate earlier, resulting in a problem that the reliability is quickly impaired. Since this thermal stress is proportional to the power loss generated in the power semiconductor chip, in order to improve the reliability of the power module, it is necessary to equalize the power losses generated between the power semiconductor chips.

[0007] From the above, in an inverter for an automobile that utilizes power semiconductor chips such as GaN and SiC, in order to extend the cruising range of the automobile, it is necessary to suppress both the resistive loss during conduction and the transient switching loss during switching of the built-in power semiconductor module to a small value. In addition, in order to improve the reliability of the power semiconductor module and extend the life of the inverter, it is necessary to make the power losses of each of the plurality of power semiconductor chips used in the power semiconductor module as uniform as possible. In particular, regarding the power loss, reducing the variation between the plurality of power semiconductor chips is more important for the dynamic switching loss than for the so-called static resistive loss.

[0008] As a background art in this technical field, for example, there is a technology such as Patent Document 1. Patent Document 1 discloses a semiconductor module capable of reducing the variation in inductance between the gate and the source.

[0009] In Patent Document 1, for the purpose of achieving further high-speed switching, it is an issue to reduce the inductance and variation of the main current path of the power semiconductor module, and further suppress the variation of the inductance of the gate-source wiring between the power semiconductor chips as much as possible.

[0010] In addition, Patent Document 2 discloses a power semiconductor module configured by multi-parallel connecting a plurality of power semiconductor chips arranged on the same substrate, which can reduce the wiring inductance in the module while reducing the chip arrangement area on the substrate.

[0011] In Patent Document 2, as a technical problem, in the internal structure of the power semiconductor module, when semiconductor chips are connected in parallel, the area of the substrate on which the semiconductor chips are mounted increases in order to ensure the insulation distance. In particular, when applying semiconductor chips of GaN or SiC, since the chip area is small and many parallel wirings are required, the area allocated for securing the space between the wiring patterns increases, and the area of the substrate becomes large. Furthermore, the gate wiring is routed while having a low magnetic coupling with other wirings such as the source and drain, and the lead frame and spacer in its path. Therefore, the inductance value generated in the gate wiring increases, and when switching and controlling the power semiconductor chip, it is also clarified that unstable operation is likely to occur in the gate waveform.

Prior Art Documents

Patent Documents

[0012]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0013] However, in order to equalize the switching losses between a plurality of power semiconductor chips arranged in parallel within a power semiconductor module, there are the following two problems.

[0014] The following will be described by taking an example in which the type of the power semiconductor chip is a MOSFET. The power semiconductor chip is electrically connected to the conductor layer pattern. One of the problems is that, for each of the power semiconductor chips, the impedance (particularly resistance and inductance) from the main terminals and control terminals of the power semiconductor module to the gate electrode, drain electrode, and source electrode of the plurality of chips varies.

[0015] Particularly, in the paths from each terminal where a steep current change occurs due to high-speed switching to the drain electrode or from each terminal to the source electrode, the variation in the inductance value has a great influence, and as a result, the value of the current flowing through each power semiconductor chip becomes non-uniform.

[0016] Another problem is that a noise voltage is superimposed on the gate voltage that controls the operation of the power semiconductor chip due to the magnetic field induced by the steep current change generated by high-speed switching, and the switching current itself varies between chips due to the non-uniformity of the noise voltage. This influence has become apparent as the operating speed of the switching element has increased from Si-IGBT to SiC or GaN.

[0017] That is, in order to reduce the variation in switching losses between a plurality of power semiconductor chips, it is necessary to minimize the deviation of the impedance between the power semiconductor chips and to equalize between the chips while minimizing the influence of the magnetic field generated in the vicinity of the path through which the switching current flows.

[0018] In Patent Document 1 above, in order to achieve high-speed switching, it is listed as problems to (1) reduce the inductance of the main current path and suppress the variation, and (2) suppress the variation in the inductance of the gate-source wiring between the power semiconductor chips as much as possible, and the countermeasures are described.

[0019] However, although problems related to variations in the inductance of gate-source wiring have been mentioned, there is no description regarding the speeding up of switching, that is, the generation of a magnetic field resulting from a steep change in the main current and the influence of that magnetic field on the gate-source wiring, nor is any countermeasure clearly stated, leaving the problems unresolved.

[0020] Also, in Patent Document 2 mentioned above, when parallel-wiring semiconductor chips, it is cited as a problem that the area of the substrate on which the semiconductor chips are mounted increases in order to ensure an insulation distance. As a countermeasure, it describes a measure of using a gate spacer to make the gate electrodes between a plurality of semiconductor chips to be parallel-wired into shared wiring, thereby reducing the planar area required for the gate wiring.

[0021] However, although measures for suppressing the area of the substrate occupied by a plurality of semiconductor chips to be parallel-wired have been mentioned, there is no description regarding variations in the inductance generated between the conductive layer patterns connecting the electrodes of adjacent semiconductor chips and its reduction, nor is any countermeasure clearly stated, leaving the problems unresolved.

[0022] Therefore, an object of the present invention is to provide a semiconductor device configured by parallel-connecting a plurality of power semiconductor elements, and a power conversion device using the same, which can reduce variations in the inductance generated between the power semiconductor elements, achieve both low switching loss due to high-speed switching and improved power cycle resistance due to the equalization of the switching losses of each power semiconductor element.

Means for Solving the Problems

[0023] In order to solve the above problems, the present invention provides a semiconductor device including one or more half-bridge circuits configured by connecting a first switch and a second switch using power semiconductor devices in series, the semiconductor device comprising: an insulating substrate; a first conductor layer pattern, a second conductor layer pattern, and a third conductor layer pattern that are disposed on one surface of the insulating substrate and are electrically insulated from each other; a plurality of power semiconductor devices that are disposed on the first conductor layer pattern and are connected in parallel to each other; a lead frame that connects each of the plurality of power semiconductor devices to the second conductor layer pattern; an individual gate wiring that connects a gate electrode of each of the plurality of power semiconductor devices to the third conductor layer pattern; and a main terminal that is connected to the second conductor layer pattern. The lead frame includes a first connection surface portion that is connected to an electrode surface of each of the plurality of power semiconductor devices, a lead frame branch portion that branches into a plurality of parts, and a second connection surface portion that is provided at an end of the lead frame branch portion and is connected to the second conductor layer pattern. In a top view of the insulating substrate, the gate electrode and the individual gate wiring are sandwiched between the two lead frame branch portions.

[0024] Further, the present invention provides a power conversion device including a main circuit having one or more pairs of high-voltage side and low-voltage side switch circuits, and a drive circuit that drives the high-voltage side and low-voltage side switch circuits, wherein the high-voltage side and low-voltage side switch circuits include the above semiconductor device.

Advantages of the Invention

[0025] According to the present invention, in a semiconductor device configured by connecting a plurality of power semiconductor devices in parallel, it is possible to reduce variations in inductance generated between the power semiconductor devices, achieve both low switching loss due to high-speed switching and improved power cycle resistance due to uniform switching loss of each power semiconductor device, and realize a semiconductor device and a power conversion device using the same.

[0026] This can contribute to improving the efficiency and reliability of the semiconductor device and the power conversion device using the same.

[0027] Problems, configurations, and effects other than those described above will be clarified by the following description of the embodiments.

Brief Description of the Drawings

[0028]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6A

Figure 6B

Figure 6C

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Figure 8A

Figure 8B

Figure 8C

Figure 9A

Figure 9B

Figure 10

Figure 11

Figure 12A

Figure 12B

Figure 13

Figure 14

Figure 15

Embodiments for Carrying Out the Invention

[0029] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the same reference numerals are given to the same configurations or configurations having similar functions, and detailed descriptions of overlapping portions are omitted.

Examples

[0030] Referring to FIGS. 1 to 12B, a power semiconductor module according to Embodiment 1 of the present invention will be described. This embodiment is an example applied to a power semiconductor module configured by multi-parallel connecting a plurality of power semiconductor chips constituting a half-bridge circuit arranged on the same substrate.

[0031] [Schematic Configuration] FIG. 1 is a diagram showing a schematic configuration of a power semiconductor module 100 of this embodiment, and is a plan view (top view) of the power semiconductor module 100 as viewed from above. FIG. 2 is a cross-sectional view taken along the line A-A' of FIG. 1.

[0032] Note that in the plan view of FIG. 1, for the component arrangement of the lower layer that cannot be seen because there are components in the upper layer originally, it is stated in advance that the arrangement is explicitly shown on the premise of making the upper layer components transparent for convenience. Also, the perspective structure of the power semiconductor module 100 in FIG. 1 will be described later with reference to FIG. 3.

[0033] As shown in FIG. 1, the power semiconductor module 100 forms a half-bridge circuit, that is, a 2in1 circuit, on a single insulating substrate 10, and includes main terminals consisting of a high-voltage side main terminal (high-potential side main terminal) 1, an intermediate voltage terminal (intermediate potential terminal) 2, and a low-voltage side main terminal (low-potential side main terminal) 3. Further, for the operation control of the power semiconductor module 100, auxiliary terminals (control terminals) 4 to 6 of the high-voltage side switch circuit and auxiliary terminals (control terminals) 7 to 9 of the low-voltage side switch circuit are provided.

[0034] Note that the high-voltage side potential indicates the voltage value applied to the high-voltage side main terminal 1, and the low-voltage side potential indicates the voltage value applied to the low-voltage side main terminal 3. Also, the intermediate voltage indicates the intermediate voltage value between the voltages applied to the high-voltage side main terminal 1 and the low-voltage side main terminal 3 respectively, and its potential varies by the switching operation.

[0035] [Connection of Main Terminals] The connection of the main terminals will be described with reference to FIG. 1.

[0036] As shown in FIG. 1, the high-voltage side main terminal 1 to which a high voltage side potential is applied is electrically connected to a conductor layer pattern 11 disposed on an insulating substrate 10. The intermediate voltage terminal 2 to which an intermediate voltage is applied and whose potential fluctuates by switching is electrically connected to a conductor layer pattern 13 of the insulating substrate 10. The low-voltage side main terminal 3 to which a low-voltage side potential is applied is electrically connected to a conductor layer pattern 15.

[0037] The conductor layer pattern 13 connecting the intermediate voltage terminal 2 is electrically connected to the conductor layer pattern 12 by lead frames 25 and 26.

[0038] As for the connection method between the high-voltage side main terminal 1, the intermediate voltage terminal 2, and the conductor patterns to which the low-voltage side main terminal 3 is electrically connected respectively, means such as soldering and metal bonding can be applied, and the means are not particularly limited.

[0039] [Planar Configuration] As shown in FIG. 1, an example is shown in which the high-voltage side switches of a half-bridge circuit (power semiconductor module 100) are configured by connecting four chips of power semiconductor elements 21 to 24 in parallel. On the other hand, the low-voltage side switches are configured by connecting four chips of power semiconductor elements 41 to 44 in parallel. Hereinafter, the power semiconductor elements 21 to 24 and the power semiconductor elements 41 to 44 will be described as MOSFET type transistors.

[0040] When the semiconductor substrate for forming the element is expensive, such as in the case of SiC-MOSFET, in order to improve the yield of the element, the element size is often small. For example, a typical element size is 5 mm square. Therefore, in order to realize one switch function of the half-bridge circuit and widely correspond to the value of the current flowing through the switch, a means of connecting a plurality of element chips in parallel is adopted. In FIG. 1, an example of four parallel connections is shown, but the number of parallel element chips is not limited.

[0041] The conductor layer pattern 11 electrically connected to the high-voltage side main terminal 1 branches to the left and right in the short side direction of the insulating substrate 10. On the left side, it is electrically and thermally connected to the drain electrodes provided on the power semiconductor elements 21 and 22, and on the right side, it is electrically and thermally connected to the drain electrodes provided on the power semiconductor elements 23 and 24 by soldering or sintering bonding.

[0042] The source electrodes of the power semiconductor elements 21 and 22 are connected to the conductor layer patterns 13 and 12 to which an intermediate voltage is applied via the conductive lead frame 25. Hereinafter, the conductive lead frame will be simply referred to as the "lead frame".

[0043] Similarly, the source electrodes of the power semiconductor elements 23 and 24 are connected to the conductor layer patterns 13 and 12 via the lead frame 26. The lead frames 25 and 26 connect between the source electrodes of the power semiconductor elements 21 to 24 and the conductor layer patterns 13 and 12 in a bridge-like shape.

[0044] For the operation control of the power semiconductor elements 21 to 24, the gate electrodes of each of the power semiconductor elements 21 to 24 (reference numerals 21G to 24G in FIG. 3 described later) are connected to the conductor layer pattern 14 via individual gate wirings 31 to 34. The individual gate wirings may be configured using bonding wires, for example. The conductor layer pattern 14, which is the gate control wiring of the high-voltage side switch circuit, is electrically connected to the gate potential control terminal pin 5 (G1 terminal; control terminal). The reference potential of the gate potential control terminal pin 5 is the source sense potential control terminal pin 6 (SS1 terminal; control terminal). The source sense potential control terminal pin 6 is connected to the conductor layer pattern 13 that connects the source electrodes of the power semiconductor elements 21 to 24 by the lead frames 25 and 26. Further, the drain sense potential control terminal pin 4 (DS1 terminal; control terminal) is connected to the conductor layer pattern 11 in a region that does not overlap the lead frames 25 and 26 and the power semiconductor elements 21 to 24 in a plan view. The above configuration realizes the switch function of the high-voltage side of the half-bridge circuit.

[0045] The conductor layer pattern 12 is connected to the drain electrodes of the power semiconductor elements 41 to 44 that perform the switching function on the low voltage side. The four-chip power semiconductor elements 41 to 44 are arranged at equal intervals in the short side direction of the insulating substrate 10. The lead frame 45 connects the source electrodes of the power semiconductor elements 41 to 44 to the conductor layer pattern 15 by its crosslinked shape.

[0046] The gate electrodes of the power semiconductor elements 41 to 44 (reference numerals 41G to 44G in FIG. 3 described later) are connected to the conductor layer pattern 16, which is the gate wiring for the low voltage side switch circuit, via the individual gate wirings 51 to 54, and the potential (voltage) thereof is controlled by the low voltage gate voltage control terminal pin 8 (G2 terminal; control terminal). The operating reference potential of the G2 terminal is the conductor layer pattern 17 connected to the source sense voltage control terminal pin 9 (SS2 terminal; control terminal). It is connected to the conductor layer pattern 17 via the arm structure and connection part (reference numeral 45S in FIG. 3 described later) for the source potential sense wiring provided on the lead frame 45.

[0047] In addition to the concave and convex portions for connecting to the source electrodes of the power semiconductor elements 41 to 44, the lead frame 45 is provided with a plurality of connection parts (described later in the perspective view of FIG. 3) to the conductor layer patterns 15 and 17 and the like. In addition to the connection part that also serves as one end of the electrical connection and crosslinked shape, there is also a connection part specialized for the support part for realizing the crosslinked shape. The above configuration realizes the switching function on the low voltage side of the half-bridge circuit.

[0048] In this way, the switching functions on the high voltage side and the low voltage side of the half-bridge circuit are realized, and the half-bridge circuit is constituted by a plurality of conductor layer patterns, a plurality of lead frames, and the main terminal group arranged on a single insulating substrate 10.

[0049] [Cross-sectional structure] Using FIG. 2, the cross-sectional structure of the power semiconductor module 100 will be described.

[0050] The power semiconductor module 100 of this embodiment uses a single insulating substrate 10 and adopts a single-sided cooling structure in which a heat dissipation path is provided via a base plate 99 on one side surface.

[0051] In FIG. 2, voids (not shown in the figure) of components are filled with an insulating resin. In the following description, the voids will be omitted from the description unless particularly necessary.

[0052] The insulating substrate 10 disposed below the power semiconductor module 100 has conductor layer patterns 11 to 20 (see FIGS. 1 and 3) on the upper surface of the insulating substrate 10 and a conductor layer pattern 98 (see FIG. 2) on the lower surface. The conductor layer pattern 98 is structured to be electrically and thermally connected to the base plate 99 via a solder layer 97.

[0053] Among the plurality of power semiconductor elements 21 to 24 and 41 to 44, the power semiconductor elements 24 and 44 shown in the cross-sectional view of FIG. 2 arrange the drain electrode in the direction of arranging the base plate 99, and arrange the source electrode and the gate electrode in the direction of arranging the lead frames 26 and 45. When a forward current flows, the current flows in the longitudinal direction from the drain electrode to the source electrode. Also, when flowing in the reverse direction, the current flows from the source electrode to the drain electrode direction. In FIG. 2, taking the power semiconductor element 44 as an example for the electrode structure on the drain side of the power semiconductor element, a solder layer 44DS is shown for the electrical and thermal connection between the drain electrode 44D and the conductor layer pattern 12. The source electrode 44S is connected to the lead frame 45 by a solder layer 44SS, and the gate electrode 44G is connected to an individual gate wiring 53 by wire bonding means. The on / off of the current is controlled by the voltage applied to the gate electrode 44G with reference to the potential of the source electrode 44S.

[0054] The cross-sectional view of the half-bridge circuit (power semiconductor module 100) shown in FIG. 2 shows both the high-voltage side switch circuit and the low-voltage side switch circuit. A power semiconductor element 24 is connected above the conductor layer pattern 11 (the side where the lead frame is arranged with respect to the insulating substrate 10) via a solder layer 24DS. A power semiconductor element 44 is connected above the conductor layer pattern 12 via a solder layer 44DS.

[0055] The source electrode 24S of the power semiconductor element 24 is connected to the lead frame 26 using a solder layer 24SS, and the source electrode 44S of the power semiconductor element 44 is connected to the lead frame 45 using a solder layer 44SS. The lead frame 26 has a joint portion with the conductor layer pattern on both sides with the power semiconductor element 24 at the center, and is connected via solder layers 26AS and 26BS which are joining materials.

[0056] As is clear from the plan view of FIG. 1 and the cross-sectional view of FIG. 2, the lead frames 26 and 45 have a lead frame shape in which the power semiconductor elements are arranged and connected in the central region and extend to both sides sandwiching the power semiconductor elements, and their tips are connected to the conductor layer pattern, adopting a so-called "both-side supported" structure. This is a structure that can ensure the thickness of the solder layers 24SS and 44SS (FIG. 2) during solder reflow due to the lead frame shape extending to both sides sandwiching the above-mentioned power semiconductor elements, and can prevent the inclination of the lead frame that may occur during solder reflow, making the planar portion of the lead frame as parallel as possible to the plane of the insulating substrate 10.

[0057] Also, in a top view with respect to the insulating substrate 10, individual gate wirings 31 to 34, a part of the conductor layer pattern 11, and a part of the conductor layer pattern 14 are arranged inside the region surrounded by the branch portions of the two lead frames 25 and 26 and the conductor layer pattern 13, and there is a region where the insulating substrate 10 is arranged without the conductor layer pattern 11, the conductor layer pattern 13, and the conductor layer pattern 14.

[0058] [Perspective structure] FIG. 3 is a perspective view of components arranged on the insulating substrate 10 shown in FIG. 1. By using the perspective view of FIG. 3, the relationship between the shape of the lead frame and the arrangement of the gate wiring path of the power semiconductor element is clarified.

[0059] [Shape of lead frame] The lead frame 25 used in the circuit configuration of the high-voltage side switch circuit is connected to the source electrode of the power semiconductor element 21 via a connection conductor such as solder at the connection portion 25P1. The connection portion 25P1 has a shape when manufactured by half pressing in the thickness direction of the lead frame 25. For example, the planar dimensions of the connection portion are 2 mm × 3 mm, the lead frame thickness is 1.5 mm, and the half pressing can have a value with an upper limit of about half of the thickness as a realizable value.

[0060] The surface connected to the source electrode 21S of the power semiconductor element 21 via the solder layer 21SS (not shown) is the lower plane of the connection portion 25P1 shown in FIG. 3. The connection portion 25P2 is the connection surface portion with the power semiconductor element 22, and the connection portion 25A is the connection surface portion to the conductor layer pattern 12. The connection portion 25B is the connection surface portion to the conductor layer pattern 13. The connection portions 25P1 and 25P2 form a stepped shape in a half pressing process or the like to form a connection surface to the source electrode of the power semiconductor element.

[0061] The shape of the connection portion of the lead frame connected to the conductor layer patterns 12 and 13 is an arm shape with a bent portion at an obtuse angle by bending. When forming a plurality of convex portions in one lead frame, if it is necessary to shorten the distance between the power semiconductor element and the connection surface portions, a shape by half pressing that can realize a sharp shape is used, and if the distance between the connection surface portions can be lengthened, an obtuse angle bending shape using a bending process is used, and they are used in combination. Appropriately using the shape of the connection surface portion and its manufacturing process according to the distance between the connection surface portions is a measure for miniaturizing the lead frame with a thick conductor material such as 1 mm or 1.5 mm. The lead frame 26 has the same structure as the lead frame 25. Consideration is given so that the switching current flowing through the power semiconductor elements 21 to 24 can be evenly divided with the vicinity of the longitudinal center of the insulating substrate 10 as the axis of symmetry.

[0062] The lead frame 45 is used for the circuit configuration of the low-voltage side switch circuit. The connection surface portion 45P1 formed with a concavo-convex shape using the same manufacturing method as the lead frames 25 and 26 is connected to the power semiconductor element 41, the connection surface portion 45P2 is connected to the power semiconductor element 42, the connection surface portion 45P3 is connected to the power semiconductor element 43, and the connection surface portion 45P4 is used for connection to the source electrode of the power semiconductor element 44.

[0063] Two connection surface portions 45A with the conductor layer pattern 15 are provided, namely 45A1 corresponding to the connection surface portions 45P1 and 45P2 with the power semiconductor element, and 45A2 corresponding to the connection surface portions 45P3 and 45P4 with the power semiconductor element.

[0064] Here, the "branch portion" of the lead frame 45 is defined. A part of the lead frame in the longitudinal direction of the connection surface portion 45P1 and in the direction where the connection surface portion 45A1 is arranged is defined as the lead frame branch portion. In other words, the portions arranged on both sides of the gap provided in the lead frame 45 so as not to interfere with the individual gate wirings 51 and 52 of the power semiconductor elements 41 and 42 are the lead frame branch portions. The current flowing through the power semiconductor elements 41 to 44 flows through the connection surface portions 45P1 to 45P4 and then through the "branch portion" and flows toward the conductor layer pattern 13.

[0065] Also, the hole portion 45H of the lead frame is a resin filling hole that prevents resin from flowing around the lead frame 45 and generating an unwanted unfilled portion of the resin when the power semiconductor module 100 is filled with an insulating resin. At the same time, it also serves as a current separation structure that guides the current flowing through the lead frame 45 from the connection surface portion 45P2 to the connection surface portion 45A1 and the current flowing through the lead frame 45 from the connection surface portion 45P3 to the connection surface portion 45A2.

[0066] Figure 4 shows the structure of the lead frame 45 on the side connected to the power semiconductor element. 45P1LP, which is the lower plane of the connection surface portion 45P1, is the surface that connects to the source electrode of the power semiconductor element 41 via the solder layer 41SS. Similarly, 45P2LP, which is the lower plane of the connection surface portion 45P2, connects to the source electrode of the power semiconductor element 42 via the solder layer 42SS, 45P3LP, which is the lower plane of the connection surface portion 45P3, connects to the source electrode of the power semiconductor element 43 via the solder layer 43SS, and 45P4LP, which is the lower plane of the connection surface portion 45P4, connects to the source electrode of the power semiconductor element 44 via the solder layer 44SS.

[0067] Also, the arrangement and shape of the connection surface portions 45A1 and 45A2, which are the connection surfaces of the lead frame connected via the conductive layer pattern and the solder layer and are one of the support structures of the "both-supported structure", and the connection surface portion 45B, which is the other support structure of the "both-supported structure", are clarified. 45B is connected to the conductor layer pattern 18 by a bonding material such as a solder layer as shown in FIG. 3. However, the conductor layer pattern 18 is an independent pattern that is not connected to other elements or conductor layer patterns, and no current flows through the connection surface portion 45B.

[0068] From the arrangement structure of the lead frame 45, the power semiconductor chips 41 to 44, and the individual gate wirings 51 to 54 described with reference to FIGS. 1 to 4, the following items are clear.

[0069] (1) In the gap of the lead frame sandwiched by the two branch portions of the lead frame, for example, the gate electrodes of two power semiconductor elements and the individual gate wirings connected thereto are arranged. The gap is a space formed inside the lead frame in a top view with respect to the plane of the insulating substrate 10, and indicates a space provided to prevent interference between the individual gate wiring and the lead frame.

[0070] For example, the gate electrodes 41G and 42G of the power semiconductor elements 41 and 42 and the individual gate wirings 51 and 52 are sandwiched by the two lead frame branch portions in a top view with respect to the plane of the insulating substrate 10.

[0071] (2) The currents flowing from the source electrodes of the power semiconductor elements 41 to 44 flow through the connection surfaces 45P1 to 45P4 and then to the connection surfaces 45A1 to 45A2 that are connected to the conductor layer pattern 15. The connection surface 45A1 is in a direction parallel to the plane of the insulating substrate 10, perpendicular to the direction in which the power semiconductor elements 41 and 42 are arranged, in the positional relationship between the connection surfaces 45P1 and 45P2, and is disposed between the connection surfaces 45P1 and 45P2. This is an arrangement for making the electrical path length from the connection surface 45P1 to the connection surface 45A1 equal to the electrical path length from the connection surface 45P2 to the connection surface 45A1. The same applies to the connection surface 45P3, the connection surface 45P4, and the connection surface 45A2. Consideration is given to ensure that the switching currents flowing through the power semiconductor elements 41 to 42 can be evenly divided with the vicinity of the longitudinal center of the insulating substrate 10 as the axis of symmetry. Similarly, consideration is given to ensure that the switching currents flowing through the power semiconductor elements 43 to 44 can be evenly divided.

[0072] (3) The connection portion (reference numeral 2A in FIG. 1) between the intermediate voltage terminal 2 and the conductor layer pattern 13 is arranged in the direction connecting the connection positions (25P1, 25P2, 26P1, 26P2) of the lead frames 25 and 26 and the power semiconductor element that constitute the high voltage side switch circuit, and the connection positions (25A2, 26A2) of the lead frames 25 and 26 and the conductor layer pattern 13. That is, the intermediate voltage terminal 2 is arranged in the longitudinal direction (in which the current flows) of the branch portion of the lead frames 25 and 26.

[0073] Also, the connection portion (reference numeral 3A in FIG. 1) between the low voltage side main terminal 3 and the conductor layer pattern 15 is arranged in the direction connecting the connection positions (45P1 to 45P4) of the lead frame 45 and the power semiconductor element that constitute the low voltage side switch circuit, and the connection positions (45A1, 45A2) of the lead frame 45 and the conductor layer pattern 15. This arrangement limitation is a consideration to prevent the unnecessary induced magnetic fields from being generated in the individual gate wirings 31 to 34, 51 to 54 of each power semiconductor element when the currents passing through the branch portions of the respective lead frames flow to the intermediate voltage terminal 2 and the low voltage side main terminal 3 via the conductor layer patterns 13 and 15.

[0074] Described with reference to the structure clarified above, taking the switching circuit on the low voltage side as an example, it becomes possible to reduce the noise voltage superimposed on the gate voltage that determines the switching operation of the power semiconductor elements 41 to 44 due to the influence of the magnetic field generated by the current flowing through the lead frame 45. This effect will be described later using a comparison with a <comparative example>.

[0075] In the power semiconductor module 100 of this embodiment, the source electrodes of the power semiconductor elements and the conductor layer patterns are electrically and thermally connected using the lead frames 25, 26, and 45. The heat generated by the power semiconductor elements is mainly dissipated from the drain electrode direction toward the base plate 99 (FIG. 2) that functions as a heat sink. However, when the lead frame is made of a material with good thermal conductivity, such as copper, it has the effect of lowering the temperature of the power semiconductor elements as a second heat dissipation path. When the lead frame is regarded as a heat conduction path, it has the effect of distributing the heat near the power semiconductor elements to the conductor layer pattern on the insulating substrate 10 away from the power semiconductor elements by the lead frame. Since this increases the area of the heat conduction path, it is clear that it functions as a heat dissipation path.

[0076] [Operating Effects] The operating effects obtained by this embodiment will be described. In explaining the operating effects of this embodiment, first, the <comparative example> will be described.

[0077] ≪Structure of <Comparative Example>≫ Referring to FIGS. 5 to 7, the comparative example will be described.

[0078] FIG. 5 is a plan view of the power semiconductor module 110 of the comparative example as viewed from above. The low voltage side switching circuit is shown.

[0079] In the comparative example shown in FIG. 5, the lead frame 46 is used. For the same components as in FIG. 1, such as the insulating substrate (insulating layer), power semiconductor elements, and conductor layer patterns, the description thereof is omitted because their functions are the same as those in FIG. 1.

[0080] The power semiconductor module 110 of the comparative example shown in FIG. 5, similar to the power semiconductor module 100 of FIG. 1, constitutes a half-bridge circuit using a plurality of conductive layers and power semiconductor elements on a single insulating substrate 10. The number of power semiconductor elements is also the same as that in FIG. 1, and it is an example in which four power semiconductor elements are used for the low-voltage side switch circuit to be compared.

[0081] What the power semiconductor module 110 of the comparative example differs from the power semiconductor module 100 of FIG. 1 is the arrangement of the gate electrodes of the power semiconductor elements and their individual gate wirings, and the shape of the lead frame 46.

[0082] The lead frame 46 is provided with joint surfaces 46P1 to 46P4 and is connected to the source electrodes of the power semiconductor elements 41 to 44.

[0083] The joint surfaces 46P1 and 46P2 are electrically joined to the source electrodes of the power semiconductor elements 41 and 42, and the current flowing through is connected to the conductor layer pattern 11 via the joint surface 46A1. What is different from the lead frame 45 shown in FIG. 1 is the arrangement relationship between the current-carrying part of the lead frame and the gate electrodes and individual gate wirings of the power semiconductor elements.

[0084] In the power semiconductor module 110, when viewed from above with respect to the plane of the insulating substrate 10, the gate electrode 41G and the individual gate wiring 51' are arranged alone on the left side with respect to the branch part of the lead frame 46 (the part from the joint surfaces 46P1 and 46P2 to the joint surface 46A1), and are connected to the conductive layer pattern 16 serving as the gate wiring.

[0085] On the other hand, the gate electrode 42G and the individual gate wiring 52', and the gate electrode 43G and the individual gate wiring 53' are arranged sandwiched between the part from the joint surfaces 46P1 and 46P2 to the joint surface 46A1, which is the branch part of the lead frame 46, and the part from the joint surfaces 46P3 and 46P4 to the joint surface 46A2. Further, the gate electrode 44G and the individual gate wiring 54' are arranged on the right side of the branch part of the lead frame from the joint surfaces 46P3 and 46P4 to the joint surface 46A2.

[0086] That is, the wirings related to the gates of the four power semiconductor elements 41 to 44 arranged in parallel are arranged in different ways with respect to the branch portion of the lead frame 46. The details will be described in detail with reference to FIGS. 6A to 6C.

[0087] <<Comparative Example: Explanation of Magnetic Field Distribution>> FIG. 6A is a diagram schematically showing the change in the magnetic field distribution due to the change in the main current with respect to the power semiconductor elements 41 to 44 constituting the low-voltage side switch circuit of the <Comparative Example> shown in FIG. 5. Here, the magnetic field H is used as a term indicating the nature of space, and the magnetic flux density B is used as an index indicating the strength of the local magnetic field in the magnetic field, that is, the distribution of the magnetic field. The magnetic flux density indicates the strength of the magnetic flux per unit area, and its unit is [Wb / m 2 .

[0088] FIG. 6B is a diagram showing a cross-sectional image along the line A-A' shown in FIG. 6A. FIG. 6C is a diagram schematically showing the relationship between the noise voltage generated in the individual gate wirings of each power semiconductor element and the magnetic flux density. It should be noted that FIGS. 6A and 6B are diagrams schematically showing only the elements necessary for the explanation for the convenience of explaining the operation and effect.

[0089] FIG. 6A is a diagram schematically showing a state in which the switching currents from the power semiconductor elements 41 to 44 transiently flow through the lead frame 46 of the <Comparative Example>. For example, when the switching current ΔI1 of the power semiconductor element 41 transiently flows, an induced magnetic field is generated. Since the induced magnetic field is generated according to the right-hand screw rule with respect to the traveling direction of the current ΔI1, in the vicinity of the individual gate wiring 51', the direction of the magnetic field is from the front to the back with respect to the paper surface. In FIG. 6B, this local magnetic field distribution is represented as the magnetic flux density B1. Also, as a notation indicating the direction of the magnetic field, the magnetic field is regarded as an arrow, and a symbol showing a cross in a circle is used to show the arrow feathers.

[0090] On one hand, when a switching current ΔI4 of the power semiconductor element 44 transiently flows and a current ΔI5 also flows through the conductor layer pattern, since the induced magnetic field is generated according to the right-hand screw rule with respect to the traveling directions of the currents ΔI4 and ΔI5 respectively, in the vicinity of the individual gate wiring 54’, the direction of the magnetic field is from the back to the front with respect to the paper surface. The notation in this case is shown by a symbol indicating a small circle inside a ○ as shown by the arrowhead.

[0091] That is, the magnetic flux density B1 in the vicinity of the individual gate wiring of the power semiconductor element 41 is generated in a direction from the front to the back with respect to the paper surface by the current ΔI1. The magnetic flux density in the vicinity of the individual gate wiring of the power semiconductor element 44 is generated in a direction from the back to the front with respect to the paper surface by the currents ΔI4 and ΔI5 respectively.

[0092] The magnetic flux density in the vicinity of the individual gate wiring 52’ of the power semiconductor element 42 is affected by the induced magnetic fields from the currents ΔI2 and ΔI3 flowing through the two adjacent lead frames 46 respectively, so it becomes a magnetic flux density obtained by synthesizing the magnetic flux density B21 in a direction from the back to the front with respect to the paper surface and the magnetic flux density B32 in a direction from the front to the back with respect to the paper surface.

[0093] The magnetic flux density in the vicinity of the individual gate wiring 53’ of the power semiconductor element 43 is also affected by the induced magnetic fields from the currents ΔI2 and ΔI3 respectively in the same way as in the vicinity of the individual gate wiring 52’, and becomes a magnetic flux density obtained by synthesizing the magnetic flux density B22 in a direction from the back to the front with respect to the paper surface and the magnetic flux density B31 in a direction from the front to the back with respect to the paper surface.

[0094] Using the schematic cross-sectional view shown in Fig. 6B, the magnitude and direction of the magnetic flux density having the properties of a vector will be described. Fig. 6B is a cross-sectional structure view seen in the direction from the conductor layer pattern 15 to the conductor layer pattern 12 along the A-A’ cross-sectional line of Fig. 6A. The source electrode and drain electrode of the power semiconductor element are not shown.

[0095] The drain electrode of each power semiconductor element is electrically and thermally connected to the conductor layer pattern 12 via a bonding material (41DS~44DS).

[0096] The gate electrodes of the respective power semiconductor elements are electrically connected to the conductor layer pattern 16, which is a gate wiring, via individual gate wirings (51’ to 54’).

[0097] The lead frame 46 has a convex portion facing the arrangement direction of the power semiconductor elements, and is electrically and thermally connected to the source electrodes of the power semiconductor elements 41 to 44 via bonding materials (41SS to 44SS).

[0098] Taking the individual gate wiring 52’ and the individual gate wiring 53’ as an example, the distribution of the magnetic flux density will be described. Near the individual gate wiring 52’ of the power semiconductor element 42, a magnetic flux density in the direction of B21 shown (dotted arrow) is generated by the change ΔI2 of the switching current. Similarly, near the individual gate wiring 53’, a magnetic flux density in the direction of B22 is generated by ΔI2. ΔI2 that generates the current change is at the edge portion of the lead frame 46A, and there is a relationship of being close to the individual gate wiring 52’ and far from the individual gate wiring 53’. Therefore, when arranging the magnitude relationship between B21 and B22, the relationship of |B21| > |B22| is obtained. The directions of B21 and B22 are the same direction.

[0099] Also, the influence of the magnetic field generated by the change ΔI3 of the switching current is superimposed near the individual gate wiring 52’. Near the individual gate wiring 53’ of the power semiconductor element 43, a magnetic flux density in the direction of B31 shown (dotted arrow) is generated by the change ΔI3 of the switching current flowing through the lead frame 46B. A magnetic flux density in the direction of B32 is also generated near the individual gate wiring 52’ by ΔI3. Since ΔI3 that generates the current change is at the edge portion of the lead frame 46B, there is a relationship of being close to the individual gate wiring 53’ and far from the individual gate wiring 52’. Therefore, when arranging the magnitude relationship between B31 and B32, the relationship of |B31| > |B32| is obtained.

[0100] Focusing on the vicinity of the individual gate wiring 52', it can be seen that the magnetic flux densities B21 and B32 are generated simultaneously, and their directions are opposite. Therefore, due to the cancellation of the magnetic fields, the magnitude of the effective magnetic flux density in the vicinity of the individual gate wiring 52' is |B21 - B32|. When the magnitudes of the current changes ΔI2 and ΔI3 are equal, the magnitude relationship of the magnetic flux density caused by the current change is proportional to the distance from the site where the current change occurs. Therefore, the relationship |B21| > |B32| holds. Consequently, as a result of adding up the overlapping magnetic fields, the direction of the magnetic flux density becomes the direction of B21.

[0101] Similarly, focusing on the vicinity of the individual gate wiring 53', the magnitude of the effective magnetic flux density is |B31 - B22|. Since the magnitude relationship of the magnetic flux density caused by the current change is |B31| > |B22|, as a result of adding up the overlapping magnetic fields, the direction of the magnetic flux density becomes the direction of B31.

[0102] In the vicinity of the individual gate wiring 51', the current changes ΔI1 and ΔI2 in the lead frame 46A are the factors causing the magnetic field. However, since there is a distance from the site where ΔI2 occurs, the magnetic field generation by the closest ΔI1 becomes the main factor. Therefore, a magnetic flux density B1 proportional to the magnitude of ΔI1 is generated.

[0103] In the vicinity of the individual gate wiring 54', due to the operation of the power semiconductor module equipped with both the high-voltage side and low-voltage side switch circuits, the current changes ΔI4 in the lead frame 46B and ΔI5 flowing through the conductor layer pattern 11 are current changes in opposite directions. Therefore, in the vicinity of the individual gate wiring 54' sandwiched between the sites where ΔI4 and ΔI5 occur, the directions of the magnetic flux density B4 proportional to the magnitude of ΔI4 and the magnetic flux density B5 proportional to the magnitude of ΔI5 are the same. Consequently, in the vicinity of the individual gate wiring 54', the two magnetic flux densities overlap in the same direction.

[0104] When organizing the effective magnetic flux density (magnetic flux density when overlapping magnetic fields are added up) in the vicinity of the individual gate wiring, it is as follows. For the sake of convenience, the direction of the magnetic flux density B1 described in FIG. 6B is determined to be the negative direction.

[0105] The magnetic flux density B51' in the vicinity of the individual gate wiring 51' is B51’≒B1<0···Equation (1) The magnetic flux density B52’ near the individual gate wiring 52’ is B52’≒B21―B32>0···Equation (2) The magnetic flux density B53’ near the individual gate wiring 53’ is B53’≒B31―B22<0···Equation (3) The magnetic flux density B54’ near the individual gate wiring 54’ is B54’≒B4+B5>0···Equation (4) Here, regarding the individual gate wirings 52’ and 53’ located between the switching currents ΔI2 and ΔI3, although there is a difference in sign, since the strength of the change in the magnetic field in their vicinity is the difference in magnetic flux density in opposite directions, the absolute value of that value is small. It can be understood that the absolute values of B51’ and B54’ that do not include the magnetic flux density in the opposite direction are large.

[0106] From the above, regarding the power semiconductor elements 41 to 44, it is clear that in the configuration of <Comparative Example>, the magnetic flux densities near the individual gate wirings 51’ to 54’ vary greatly, and the relationship described in the following equation holds.

[0107] |B52’|≒|B53’|<|B51’|<|B54’|···Equation (5) B51’<B53’<B52’<B54’ ···Equation (6) ≪Equivalent Circuit Description of Comparative Example and Relationship Equation of Gate Voltage Magnitude≫ Figure 6C shows the influence of the magnetic field distribution due to the switching current described with reference to FIGS. 6A and 6B above, represented by an equivalent circuit using the circuit diagram symbols (#41 to #44) of the power MOSFET.

[0108] The current changes ΔI1 to ΔI4 flow out from the sources of the respective power MOSFETs, and flow into the wiring corresponding to the conductor layer pattern 15 shown in FIG. 6A through the inductances Ls41 to Ls44 of the source current paths. The gates of the respective power MOSFETs are connected to the wiring corresponding to the conductor layer pattern 16 shown in FIG. 6A that serves as the gate wiring through the individual gate inductances (Lg51’ to Lg54’) corresponding to the respective individual gate wirings.

[0109] The symbol marks of the respective magnetic flux densities generated by the current changes ΔI1 to ΔI4 are placed near the individual gate inductances, and the mathematical expressions of the magnetic flux densities are described at the bottom of the figure.

[0110] Using FIG. 7, the noise voltage Vnoise superimposed on the gate voltage of each power semiconductor element corresponding to the magnetic flux density near the individual gate wiring will be described.

[0111] FIG. 7 is a basic diagram for explaining the operating principle from the change in the switching current to the superimposition of the noise voltage on the gate voltage, taking one power semiconductor element as an example.

[0112] Although not shown in detail, a closed circuit 60 for driving the gate voltage is formed between the gate (nG) and the source (nS) of the power semiconductor element 40, and a closed circuit 70 between the drain (nD) and the source (nS) including a part of the power semiconductor module is formed between the drain and the source. Also, regarding the individual gate wiring in the module structure diagram already described, it is equivalently represented by the individual gate inductance Lg.

[0113] The operating principle will be explained starting from the occurrence of a change ΔIs in the switching current at the source (STEP1).

[0114] As STEP1, when a change (switching current) ΔIs in the main current occurs, an induced magnetic field is induced.

[0115] In STEP2, a magnetic flux density B is generated corresponding to the induced magnetic field generated near the individual gate inductance Lg.

[0116] In STEP3, since the individual gate inductance Lg is a part of the closed circuit including the gate drive circuit, an induced current ΔImi is induced. Here, since the absolute value of ΔImi is proportional to the magnitude of the magnetic flux density B, it is clear that the magnitude of the current flowing through the individual gate inductance Lg changes depending on the magnitude of the magnetic flux density B.

[0117] In STEP4, since the induced current ΔImi flows into the individual gate inductance Lg, an induced electromotive force, that is, a noise voltage Vnoise, is generated in the individual gate inductance Lg, and its magnitude follows Equation (7).

[0118] Vnoise = Lg × d(Iim) / dt ··· Equation (7) Here, Lg is the inductance value of the individual gate wiring.

[0119] Since the magnitude of the induced current Iim is proportional to the magnitude of the magnetic flux density B, the transient change rate d(Iim) / dt of the induced current is also proportional to B. Therefore, it is clear from Equation (7) that a noise voltage Vnoise is generated in the gate voltage of the power semiconductor device depending on the magnitude of the magnetic flux density B.

[0120] The voltage sharing of the closed circuit for driving the gate including Vnoise is organized as follows.

[0121] The gate-source voltage VgsChip for each power semiconductor device is determined by the gate drive voltage VgsDrv, the voltage V_Ls generated in the inductance Ls of the source current path, and the noise voltage Vnoise.

[0122] VgsChip = VgsDrv - V_Ls - Vnoise ··· Equation (8) V_Ls = Ls × d(Is) / dt ··· Equation (9) Here, d(Is) / dt in Equation (9) is the time change rate of the switching current. Although the value of V_Ls is determined by ΔIs and Ls, it is uncorrelated with the magnetic flux density B generated in the vicinity of the individual gate wiring.

[0123] Therefore, when VgsDrv is a constant value and the values of Ls and d(Is) / dt are uniform for each power semiconductor device, it is clear that the gate-source voltage VgsChip applied to the power semiconductor device shown in Equation (8) changes due to Vnoise. That is, when it is uniform for each power semiconductor device, the direction and magnitude of the gate-induced current ΔImi determine Vnoise, and as a result, VgsChip fluctuates.

[0124] From the above, it can be seen that if the magnitude and direction of the magnetic flux density B corresponding to the change ΔIs in the switching current vary, differences will occur in the gate-source voltages of each power semiconductor device, and adverse effects will occur where the current and voltage waveforms during the switching period are significantly different between devices.

[0125] In the case of the <Comparative Example> described with reference to FIGS. 6A to 6C, when calculating the magnitude relationship of Vnoise that varies the gate-source voltage VgsChip of each power semiconductor device, it is as follows.

[0126] Citing the magnitude relationship of the magnetic flux density B shown in Equation (6), the absolute value relationship is as follows.

[0127] |Vnoise42|≒|Vnoise43|<|Vnoise41|<|Vnoise44| ··· Equation (10) Including the positive and negative signs, the magnitude relationship is Vnoise41<Vnoise43<0, 0<Vnoise42<Vnoise44| ··· Equation (11) Assuming that the voltage V_Ls generated in the inductance Ls of the source current path is uniform for each power semiconductor device, the magnitude relationship of VgsChip is as follows from Equations (8) and (11), and it is clear that there are differences between each power semiconductor device.

[0128] VgsChip44<VgsChip42<VgsChip43<VgsChip41 ··· Equation (12) ≪Switching waveform: In the case of the comparative example≫ The phenomenon of noise superposition on the gate voltage accompanying the change in the main current shown in FIGS. 6A to 6C and FIG. 7 can be verified by using the circuit network obtained by performing electromagnetic field analysis on the structure of the power semiconductor module. The circuit network mentioned here is a circuit network including a self-inductance component and a capacitance component generated in the wiring, and a mutual inductance component indicating the magnetic coupling generated between the wirings and between the lead frame and the wiring.

[0129] By extracting the magnetic coupling from the structure of the module and creating an equivalent circuit in the form of self-inductance and mutual inductance in the circuit network, the influence of the generation of the induced magnetic field and the accompanying generation of the induced current described above can be calculated. By performing a transient analysis by combining the circuit network and the transistor model of the power semiconductor element, the noise voltage superposition on the gate voltage can be analytically calculated.

[0130] First, the switching waveforms in the low-potential side switch circuit of the <comparative example> shown in FIG. 5 are calculated by circuit analysis, and the obtained results are shown in FIGS. 9A and 9B.

[0131] FIG. 9A shows an example in which the waveforms of the currents Is_43 and Is_44 (corresponding to ΔI3 and ΔI4 in FIG. 6) flowing through the power semiconductor elements 43 and 44 when the power semiconductor element is turned on are calculated. That is, in FIG. 6C, the magnitudes of the influences of the strengths B53' and B54' of the magnetic field change are shown by the waveforms of the switching current. In other words, it shows how the noise voltages Vnoise43 and Vnoise44 superimposed on the gate voltage of the power semiconductor element affect the switching waveform.

[0132] During the rising period of the switching current, a difference occurs in the current values of Is_43 and Is_44 and they separate. As shown in FIGS. 6A to 6C and FIG. 7, as the switching current transiently changes (in this case, it is a turn-on, so the current increases), a change in the magnetic field occurs, and noise voltages are superimposed on the gate voltages of the power semiconductor elements 43 and 44 at different values respectively, resulting in a deviation in the switching current value. This is an example that proves the phenomenon that the switching current values are different for each power semiconductor element during the process of increasing the switching current, and thus the peak current values of the turn-on current are also different.

[0133] Therefore, it becomes clear that a difference occurs in the switching loss during turn-on. Similarly, a difference also occurs in the switching loss for each power semiconductor element during turn-off.

[0134] The transient waveform of the instantaneous power obtained by multiplying the switching current and the drain-source voltage of the power semiconductor element is shown in FIG. 9B. As inferred from the difference in the transient waveform of the switching current, the instantaneous power shows a difference during the rising period at turn-on. Therefore, it can be seen that a difference occurs in the switching loss of the power semiconductor element in the arrangement of the power semiconductor element and the lead frame in the <Comparative Example> of FIG. 5.

[0135] For example, when calculating the switching loss with a power supply voltage of 800V and a switching current of 400A, the turn-on switching loss of the power semiconductor element 43 can be estimated to be 9.1mJ per switching. On the other hand, for the power semiconductor element 44, since the current during switching is small, it is 8.4mJ. It is clear that a difference of about 8% occurs between these two power semiconductor elements.

[0136] ≪Explanation of the magnetic field distribution of this embodiment≫ FIGS. 8A to 8C are diagrams schematically showing the effects of the embodiments of the present invention in comparison with the <Comparative Example>.

[0137] FIG. 8A is a diagram schematically showing the influence of a magnetic field due to a main current with respect to the power semiconductor elements 41 to 44 constituting the low-voltage side switch circuit of the first embodiment shown in FIGS. 1 to 3. FIG. 8B shows a cross-sectional image (along line A-A') of the schematic diagram of FIG. 8A, and FIG. 8C is a diagram briefly showing, using an equivalent circuit, the noise voltage generated in the inductance of the individual gate wirings of the respective power semiconductors.

[0138] FIG. 8A is a diagram schematically showing the distribution of a magnetic field when switching currents transiently flow from the power semiconductor elements 41 to 44 to the lead frame 45 of the present embodiment. For easy comparison with FIGS. 6A to 6C, for the convenience of explaining the operating principle, it is stated in advance that the lead frame 45 is shown divided into two parts, 45A and 45B. Even if the lead frame is in a shape connected to four power semiconductor elements as in the lead frame 45 shown in FIG. 1, the following explanation is applicable.

[0139] For the power semiconductor elements 41 to 44, their drain electrodes (not shown) are connected to the conductor layer pattern 12, the gate electrodes are connected to the conductor layer pattern 16 functioning as a gate wiring pattern via the individual gate wirings 51 to 54, and the source electrodes are connected to the lead frame (45A, 45B) via a bonding material such as solder.

[0140] The main current flowing through the lead frames 45A and 45B flows through the lead frame branch portion in the directions indicated by the arrows of the current changes ΔI1 to ΔI4. As shown in FIG. 8A, when viewing the insulating substrate 10 from above, it is a structural feature that the two lead frame branch portions sandwich the individual gate wirings 51 to 54. In the case of FIG. 8A, it is a configuration in which the two lead frame branch portions sandwich the individual gate wirings corresponding to two of the power semiconductor elements.

[0141] When current changes (ΔI1 to ΔI4) occur in the main current flowing from the source electrodes of the power semiconductor elements 41 to 44, an induced magnetic field is generated. Focusing on the vicinity of the individual gate wirings 51 to 54, it can be seen that the individual gate wirings are affected by the induced magnetic fields due to the plurality of current changes.

[0142] For example, in the vicinity of the individual gate wiring 51, a magnetic field due to the current change ΔI1 is generated in the direction from the back to the front with respect to the paper surface. Also, a magnetic field due to the current change ΔI2 is generated in the direction from the front to the back with respect to the paper surface.

[0143] The current changes ΔI1 and ΔI2 of the current flowing through the branch portion of the lead frame 45A flow through the conductor layer pattern 15 via the connection portion 45A1 between the lead frame and the conductive layer pattern 15. Also, the current changes ΔI3 and ΔI4 of the current flowing through the branch portion of the lead frame 45B flow through the conductor layer pattern 15 via the connection portion 45A2 between the lead frame and the conductive layer pattern 15. At the connection portion 3A between the low-voltage side main terminal 3 and the conductive layer pattern 15, ΔI1 + ΔI2 + ΔI3 + ΔI4, which is the sum of the above current changes, flows into the low-voltage side main terminal 3.

[0144] In this way, along the direction in which the current flows through the branch portion of the lead frame, the connection portions (45A1, 45A2) between the lead frames 45A and 45B and the conductive layer pattern 15 and the connection portion 3A between the low-voltage side main terminal 3 and the conductor layer pattern 15 are arranged. That is, the current changes flowing through the lead frame are arranged to be uniformly distant from the individual gate wirings 51 to 54. This is a measure for managing the induced magnetic field generated in the vicinity of the individual gate wiring and not generating a new induced magnetic field that becomes the noise voltage of the gate wiring.

[0145] To explain the direction and magnitude relationship of the local magnetic flux density, a cross-sectional image (the cross-section of the line segment A-A' in FIG. 8A) is shown in FIG. 8B. FIG. 8B is a cross-sectional structure in which the arrangement directions of the conductor layer patterns 16 and 12 are viewed in the cross-section at the line segment A-A'. The electrode patterns of the source electrode, drain electrode, and gate electrode of the power semiconductor element are not shown.

[0146] The drain electrodes of the power semiconductor elements are electrically and thermally connected to the conductor layer pattern 12 via bonding materials 41DS to 44DS. The gate electrodes of the power semiconductor elements are electrically connected to the conductor layer pattern 16 which is a gate wiring via individual gate wirings 51 to 54. The lead frames 45A and 45B have convex portions in the arrangement direction of the power semiconductor elements, and are electrically and thermally connected to the source electrodes of the power semiconductor elements 41 to 44 via bonding materials 41SS to 44SS.

[0147] The induced magnetic fields generated in the vicinity of the individual gate wirings 51 to 54 of the power semiconductor elements 41 to 44 are sorted out.

[0148] In the vicinity of the individual gate wiring 51, the magnetic flux density B11 due to the current change ΔI1 and the magnetic flux density B22 due to the current change ΔI2 are dominant. Although there are magnetic flux densities generated by other current changes, the dominant factors will be described based on the comparison of the absolute values of the magnetic flux densities. The magnetic flux densities B11 and B22 are in opposite directions, and the relationship between the absolute values is proportional to the distance from the edge of the lead frame branch portion where the current change occurs, so |B11| > |B22|.

[0149] In the vicinity of the individual gate wiring 52, the magnetic flux density B21 due to the current change ΔI2 and the magnetic flux density B12 due to the current change ΔI1 are dominant. The magnetic flux densities B21 and B12 are in opposite directions, and the relationship between the absolute values is |B21| > |B12| according to the same reasoning as above.

[0150] In the vicinity of the individual gate wirings 53 and 54 as well, the same reasoning as in the vicinity of the individual gate wirings 51 and 52 above can be applied. The magnetic flux density B31 and the magnetic flux density B42 are in opposite directions, and the relationship between the absolute values is |B31| > |B42|. Also, the magnetic flux density B41 and the magnetic flux density B32 are in opposite directions, and the relationship between the absolute values is |B41| > |B32|.

[0151] An induced magnetic field is generated due to the current change ΔI5 in the conductor layer pattern 11, and its magnetic flux density is shown as B5. However, since it is at a distance from the individual gate wirings of the power semiconductor elements, its influence is ignored.

[0152] Regarding FIG. 8B, when arranging the effective magnetic flux density (magnetic flux density when the overlapping magnetic fields are combined) near the individual gate wiring, it is as follows. For convenience, the direction of the magnetic flux density B21 shown in FIG. 8B, that is, the direction from the source electrode to the drain electrode of the power semiconductor element, is determined to be the negative direction.

[0153] The magnetic flux density B51 near the individual gate wiring 51 is B51 ≒ B11 - B22 > 0 ··· Equation (13) The magnetic flux density B52 near the individual gate wiring 52 is B52 ≒ B21 - B12 < 0 ··· Equation (14) The magnetic flux density B53 near the individual gate wiring 53 is B53 ≒ B31 - B42 > 0 ··· Equation (15) The magnetic flux density B54 near the individual gate wiring 54 is B54 ≒ B41 - B32 < 0 ··· Equation (16) |B51| ≒ |B52| ≒ |B53| ≒ |B54| ··· Equation (17) B51 > 0, B52 < 0, B53 > 0, B54 < 0 ··· Equation (18) As described in Equations (13) to (16), all of the magnetic flux densities B51 to B54 are the synthesis of magnetic flux densities in opposite directions. Although their directions are divided into positive and negative, the variation in absolute values can be suppressed to be small compared to the structure of FIG. 6B.

[0154] Assuming that the current changes ΔI1 to ΔI4 are equal in both the <comparative example> of FIG. 6B and the <present embodiment> of FIG. 8B, due to the difference in the positional relationship between the lead frame and the individual gate wiring, the variation in the magnetic flux density near the individual gate wiring is different between the <comparative example> and the <present embodiment>.

[0155] ≪Equivalent Circuit Description of the Present Embodiment and Relationship Equation of Gate Voltage Magnitudes≫ FIG. 8C shows the influence of the magnetic field distribution due to the switching current described with reference to FIGS. 8A and 8B above, represented by an equivalent circuit using the circuit diagram symbols (#41 to #44) of the power MOSFET.

[0156] The current changes ΔI1 to ΔI4 flow into the wiring corresponding to the conductor layer pattern 15 shown in FIG. 8A through the inductances Ls41 to Ls44 of the source current path. The gates of the respective power MOSFETs are connected to the wiring corresponding to the conductor layer pattern 16 shown in FIG. 8A serving as the gate wiring through the individual gate inductances Lg51 to Lg54 corresponding to the respective individual gate wirings. Also, symbol marks of the respective magnetic flux densities generated by the current changes ΔI1 to ΔI4 are placed near the individual gate inductances, and mathematical expressions of the magnetic flux densities are described at the lower part of the figure.

[0157] In the case of <this embodiment> described with reference to FIGS. 8A to 8C, when calculating the magnitude relationship of Vnoise that varies the gate-source voltage VgsChip of each power semiconductor element, the following results.

[0158] Citing the magnitude relationship of the magnetic flux densities B51 to B54 described in Expressions (13) to (18), the absolute value relationship is as follows.

[0159] |Vnoise41| ≒ |Vnoise42| ≒ |Vnoise43| ≒ |Vnoise44| ··· Expression (19) The magnitude relationship including the positive and negative signs is Vnoise42 ≒ Vnoise44 < 0, 0 < Vnoise41 ≒ Vnoise43 ··· Expression (20) Assuming that the voltage V_Ls generated in the inductance Ls of the source current path is uniform for each power semiconductor element, the magnitude relationship of VgsChip is as follows from Expressions (8) and (20).

[0160] VgsChip41 ≒ VgsChip43 < VgsChip42 ≒ VgsChip44 ··· Expression (21) ≪ Comparison between the comparative example and this embodiment: FIGS. 10 and 11 ≫ In FIG. 10, the magnetic flux densities B51’ to B54’ near the individual gate wirings of the <comparative example> are illustrated and arranged with reference to Expressions (5) and (6). Also, the magnitude relationships of the gate voltages VgsChip41 to 44 of the respective power semiconductor devices determined corresponding to the magnetic flux densities B51’ to B54’ are also illustrated.

[0161] In FIG. 10, it is shown that the absolute values of the magnetic flux densities B52’ and B53’ are approximately equal, but the directions of the magnetic flux densities are different. The magnetic flux density B51’ shows only a single induced magnetic field due to the current change ΔI1, and becomes a magnetic flux density in the negative direction. Its absolute value is larger than those of B52’ and B53’. This is because B52’ and B53’ themselves are generated by the difference between two magnetic flux densities with different directions. B54’ is composed of the sum of magnetic flux densities in the same direction due to the current changes ΔI4 and ΔI5. The direction of the magnetic flux density is the positive direction, and its absolute value is larger than that of B51’.

[0162] Here, for convenience, the difference in the magnetic flux densities between B51’ and B54’ is defined as ΔB1, and the difference in the magnetic flux densities between B53’ and B54’ is defined as ΔB2. The gate voltages VgsChip41 to 44 of the respective power semiconductor devices reflect the influence of the gate noise voltages proportional to the magnetic flux densities B51’ to B54’, so VgsChip44 is the smallest and VgsChip41 is the largest. Current deviations occur between the respective power semiconductor devices during switching according to the magnitudes of the gate voltages VgsChip. For example, since VgsChip43 > VgsChip44, in the current waveform at turn-on shown in FIG. 9A, Is_43 flowing through the power semiconductor device 43 is larger than Is_44 flowing through the power semiconductor device 44.

[0163] In Fig. 11, the magnetic flux density near the individual gate wiring of <this embodiment> is illustrated and arranged with reference to Expressions (13) to (18). Also, an image of the magnitude of the gate voltage VgsChip is shown. From Expression (17), the absolute values of the magnetic flux densities B51 to B54 are approximately equal, but B51 and B53 have magnetic flux densities in the positive direction, and B52 and B54 have magnetic flux densities in the negative direction. The magnetic flux density near the individual gate wiring of the four power semiconductor elements 41 to 44 is divided into positive and negative directions of the magnetic flux density, so an absolute value ΔB3 of the variation occurs, but it is clear that this variation can be suppressed to be smaller compared to the <comparative example> shown in Fig. 10. Comparing with the magnetic flux density differences ΔB1 and ΔB2 shown in Fig. 10, it can be said that ΔB3 < ΔB1 and ΔB3 < ΔB2.

[0164] The magnitude relationship of the gate voltage VgsChip in Fig. 11 is at two levels reflecting Expression (21), and the voltage difference ΔVgs3 is smaller than the gate voltage differences ΔVgs1 and ΔVgs2 shown in Fig. 10, and it can be said that ΔVgs3 < ΔVgs1 and ΔVgs3 < ΔVgs2.

[0165] The suppression effect of the variation range of the gate noise voltage between the power semiconductor elements in this embodiment and the suppression effect of the variation range of the gate voltage VgsChip are due to the structure where "when the insulating substrate is viewed from above, two lead frame branch portions sandwich the individual gate wirings 51 to 54" shown in Fig. 8A.

[0166] ≪Switching waveform: In the case of this embodiment≫ Fig. 12A shows an example of calculating the waveforms of the currents Is_43 and Is_44 flowing through the power semiconductor elements 43 and 44 when the power semiconductor element turns on in this embodiment. The calculation conditions are the same as those in Fig. 9A, but the arrangement of the power semiconductor element and the lead frame in the low-voltage side switch circuit has the structure of this embodiment.

[0167] Comparing with Fig. 9A, it can be seen that the waveform shapes of the currents Is_43 and Is_44 are similar at the rising edge of the switching current, and the difference between the currents is small.

[0168] The transient waveform of the instantaneous power obtained by multiplying the switching current by the value of the drain-source voltage of the power semiconductor device is shown in FIG. 12B. Similar to the transient waveform of the switching current, with respect to the instantaneous power as well, the difference that occurs during the rising period at turn-on is clearly smaller compared to FIG. 9B. Therefore, it is clear that by applying this embodiment, the difference in the switching losses of the power semiconductor devices arranged in parallel can be suppressed to a small level.

[0169] Similar to <Comparative Example>, in an example where the switching loss was calculated with a power supply voltage of 800 V and a switching current of 400 A, the switching loss at turn-on of the power semiconductor device 44 can be estimated to be 9.1 mJ per switching, and the loss of the power semiconductor device 43 is also 8.8 mJ. The difference in the switching losses at turn-on between these two power semiconductor devices is a difference of about 3%.

[0170] Since the difference in the switching losses at turn-on of <Comparative Example> (the difference between the power semiconductor devices 43 and 44) was 8%, it has become clear that by this embodiment, the difference in the switching losses between the power semiconductor devices can be reduced by about 40% from 8% to 3%.

[0171] By applying the structure of this embodiment, it is possible to reduce "the variation in the switching losses between the power semiconductor devices arranged in parallel", which is a major factor in the power cycle tolerance of the power semiconductor devices used in automotive inverters and the like.

Embodiment

[0172] With reference to FIG. 13, the power semiconductor module according to Embodiment 2 of the present invention will be described.

[0173] The present embodiment shown in FIG. 13 is obtained by changing the lead frames 25 and 26 of the high-voltage side switch circuit and the lead frame 45 of the low-voltage side switch circuit of the power semiconductor module 100 of Embodiment 1 (FIG. 1) to lead frames 27 and 28 and lead frame 47, respectively.

[0174] In the present embodiment, the lead frames of the high-voltage side and low-voltage side switch circuits have the connection portions to the conductor layer pattern 13 and the conductor layer pattern 15 separated.

[0175] In lead frames 27 and 28, as shown in the figure, the connection portions are separated into 27B-1 and 27B-2, 28B-1 and 28B-2 respectively. In lead frame 47, the connection portions are separated into 47A1-1, 47A1-2, 47A2-1, 47A2-2.

[0176] In addition to the effects described in Embodiment 1, the effects of the present embodiment include separating the connection portions between the lead frame and the conductor layer pattern into a plurality, reducing the total cross-sectional area of the connection portions, thereby maintaining the electrical characteristics equivalent to those of Embodiment 1 while reducing the stress exerted by the lead frame on the conductor layer pattern and the insulating substrate 10. In other words, the rigidity of the lead frame can be reduced. By adopting this structure, the reliability of the power semiconductor module can be enhanced.

[0177] The insulating substrate and the conductor layer pattern mounted on the power semiconductor module are periodically warped due to the heat generation of the power semiconductor element. For improving reliability, it is desired that the rigidities of the constituent members are of the same degree. Therefore, as a measure for adjusting the rigidity of the lead frame, the shape of the connection portion (the width of the connection portion of the lead frame) is designed as described above.

Embodiment

[0178] Referring to FIG. 14, the power semiconductor module according to Embodiment 3 of the present invention will be described.

[0179] In the present embodiment shown in FIG. 14, with respect to the power semiconductor module 100 of Embodiment 1 (FIG. 1), the lead frame 45 of the low-voltage side switch circuit is separated into two lead frames: a lead frame 45-1 that electrically connects between the source electrodes of the power semiconductor element, and a lead frame 45-2 that electrically connects between the source electrode of the power semiconductor element and the conductor layer pattern 15.

[0180] When an imbalance occurs in the current when each power semiconductor element discharges the switching current from the source electrode, the lead frame 45-1 serves as a current path for the unbalanced current. In FIG. 14, although the four power semiconductor elements are electrically connected, it is not necessary to connect all the power semiconductor elements, and the power semiconductor elements may be selectively connected as needed.

[0181] Therefore, the effects of this embodiment include, in addition to the effects described in Embodiment 1, selectively realizing the electrical connection of the source electrodes between the power semiconductor elements, while electrically connecting between the source electrode of the power semiconductor element that is functionally essential and the conductor layer pattern 15.

[0182] By adopting this lead frame structure, the variation in the switching elements between the power semiconductor elements connected in parallel in the power semiconductor module can be reduced.

Example

[0183] Referring to FIG. 15, the power conversion device according to Embodiment 4 of the present invention will be described.

[0184] FIG. 15 is a block diagram showing the circuit configuration of the power conversion device 260 of this embodiment.

[0185] FIG. 15 shows an example of a three-phase AC motor that drives the axle of an electric vehicle composed of a battery (or power supply circuit) 250, a power conversion device 260, and a load motor 270.

[0186] The power conversion device 260 of this embodiment includes a 6-in-1 power module configured by using the power semiconductor module 100 (FIG. 1) for one phase and its three-phase circuit, a capacitor 240, and a control circuit 230. The power semiconductor module 100 in FIG. 15 is a half-bridge circuit.

[0187] Note that the power conversion device 260 includes gate drive circuits 210(210a, 210b, 210c) equal in number to the number of phases of the alternating current. The power conversion device 260 holds the main voltage (Vcc) by the capacitor 240, and the gate drive signals of the power semiconductor elements in each of the power semiconductor modules 100 or 101 generated by the control circuit 230 are input to the respective power semiconductor modules 100, 101 via the gate drive circuits 210a, 210b, 210c.

[0188] The leg circuits 220a, 220b, 220c respectively constitute an inverter leg of the first phase, an inverter leg of the second phase, and an inverter leg of the third phase. The outputs of the respective inverter legs are connected to the electric motor 270.

[0189] In this embodiment, the leg circuits 220a, 220b, 220c have the same circuit configuration. Therefore, the circuit configuration will be described taking the leg circuit 220a as an example.

[0190] The leg circuit 220a includes a pair of upper and lower switch circuits constituted by the power semiconductor module 100 or 101, and a gate drive circuit 210a for on / off controlling the power semiconductor module.

[0191] According to this embodiment, the power semiconductor modules 100, 101 mounted on the power conversion device 260 are the power semiconductor modules described in any of Embodiment 1 to Embodiment 3, and by reducing the variation in the switching losses of the power semiconductor elements arranged in parallel and incorporated in the modules, the power cycle tolerance that determines the life of the power semiconductor module can be improved.

[0192] Therefore, the power conversion device 260 configured using these power semiconductor modules 100, 101 and the electric vehicle motor drive system configured to include the power conversion device 260 can perform high-speed switching and obtain high reliability.

[0193] Note that the present invention is not limited to the above-described embodiments, and various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Also, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, for a part of the configuration of each embodiment, addition, deletion, or replacement with other configurations is possible.

[0194] For example, the dimensions and insulation distances of the members constituting the power semiconductor module 100 may be arbitrary according to its application.

[0195] Furthermore, the chip arrangement of the power semiconductor elements constituting the power semiconductor module 100 is not limited to the illustrated form.

[0196] Also, for the embodiment in which the upper and lower switch circuits are mounted on the same power semiconductor module 100, although the description has been made focusing on one of the switch circuits, the other switch circuit also has the same effect, and there is no reduction in the effect by adopting the 2in1 configuration.

[0197] For example, in FIG. 1, the lead frames connecting the power semiconductor elements connect four power semiconductor elements with two lead frames 25 and 26 in the high-voltage side switch circuit, and one lead frame 45 connects four power semiconductor elements in the low-voltage side switch circuit. The number of lead frames and the combination of the power semiconductor elements to be connected are not limited as long as the functions and effects shown in the above embodiments are realized.

[0198] As the power semiconductor module 100, any of a unipolar device such as a JFET type (Junction Field Effect Transistor) in addition to an MOFET, or a bipolar device such as an IGBT may be used. Note that depending on the device, the names of the main terminals and sense terminals are referred to as "collector" and "emitter" instead of the above-mentioned "drain" and "source".

[0199] Also, the form of configuring the power semiconductor module may be the 2in1 configuration by the power semiconductor module 100 shown in the embodiment in units of modules, or the case of configuring a 6in1 module by combining three 2in1 configurations for three phases. It is obvious that the effects described in this specification can be obtained without change.

[0200] In addition, the power conversion device to which the power semiconductor module 100 is applied can be applied not only to motor drive systems of various moving bodies such as railway vehicles and electric vehicles, but also to industrial systems, and PCS (Power Conditioning System) and smart grids in solar power generation devices and wind power generation devices (power distribution).

Explanation of Signs

[0201] 1... High voltage side main terminal 2... Intermediate voltage terminal 2A... Connection part between intermediate voltage terminal 2 and conductor layer pattern 13 3... Low voltage side main terminal 3A... Connection part between low voltage side main terminal 3 and conductor layer pattern 15 4 to 9... Control terminal pins (auxiliary terminals) 10... Insulating substrate (insulating layer) 11 to 20, 98... Conductor layer patterns 21 to 24, 40 to 44... Power semiconductor elements 21G to 24G, 41G to 44G... Gate electrodes 21S, 24S, 44S... Source electrodes 21SS, 24DS, 24SS, 26AS, 26BS, 41SS, 42SS, 43SS, 44DS, 44SS, 97... Solder layers 25, 26, 27, 27B-1, 27B-2, 28, 28B-1, 28B-2, 45, 45A, 45B, 45-1, 45-2, 46, 46A, 46B, 47, 47A1-1, 47A1-2, 47A2-1, 47A2-2... Lead frame 25A, 25A2, 25B, 26A, 26A2, 26B, 45A, 45A1, 45A2, 45B... Connection surface part (connection part) for connection with the conductor layer pattern of the lead frame 25P1~25P2, 26P1~26P2, 45P1~45P4, 45P1LP~45P4LP... Connection surface part (connection part) for connection with the electrodes of the power semiconductor element of the lead frame 31~34, 51~54, 51’~54’... Individual gate wiring 41DS~44DS, 41SS~44SS... Bonding material 41G~44G... Gate electrode 44D... Drain electrode 45H... Hole part of the lead frame 46A1, 46A2... Bonding surface part with the conductor layer pattern of the lead frame 46P1~46P4... Bonding surface part with the electrodes of the power semiconductor element of the lead frame 60, 70... Closed circuit 99... Base plate 100, 101... Power semiconductor module (half-bridge circuit) 110... Power semiconductor module of the comparative example 210, 210a, 210b, 210c... Gate drive circuit 220, 220a, 220b, 220c... Leg circuit 230... Control circuit 240... Capacitor 250... Battery (or power supply circuit) 260... Power conversion device 270... Electric motor Lg51~Lg54, Lg51’~Lg54’... Individual gate inductance Ls41~Ls44... Inductance

Claims

1. A semiconductor device including one or more half-bridge circuits configured by connecting a first switch and a second switch using power semiconductor elements in series, an insulating substrate, a first conductor layer pattern, a second conductor layer pattern, and a third conductor layer pattern that are disposed on one surface of the insulating substrate and are electrically insulated from each other, a plurality of power semiconductor elements that are disposed on the first conductor layer pattern and are connected in parallel to each other, a lead frame that connects each of the plurality of power semiconductor elements to the second conductor layer pattern, individual gate wirings that connect gate electrodes of each of the plurality of power semiconductor elements to the third conductor layer pattern, and a main terminal connected to the second conductor layer pattern, wherein the lead frame includes a first connection portion that is connected to an electrode surface of each of the plurality of power semiconductor elements, a lead frame branch portion branched into a plurality, and a second connection portion that is provided at an end of the lead frame branch portion and is connected to the second conductor layer pattern, and in a top view with respect to the insulating substrate, the gate electrode and the individual gate wirings are sandwiched between two of the lead frame branch portions. A semiconductor device characterized by this.

2. The semiconductor device according to claim 1, wherein the main terminal is disposed in a longitudinal direction of the lead frame branch portion. A semiconductor device characterized by this.

3. The semiconductor device according to claim 1, wherein the lead frame has a plurality of the first connection portions, and is electrically connected to the plurality of power semiconductor elements. A semiconductor device characterized by this.

4. The semiconductor device according to claim 1, in a top view with respect to the insulating substrate, inside a region surrounded by two of the lead frame branch portions and the second conductor layer pattern, a part of the individual gate wiring, the first conductor layer pattern, and the third conductor layer pattern is disposed, and a region where the insulating substrate is disposed without the first conductor layer pattern, the second conductor layer pattern, and the third conductor layer pattern is provided. A semiconductor device characterized by this.

5. The semiconductor device according to claim 1, in a top view with respect to the insulating substrate, two of the lead frame branch portions are integrated at their ends to form one of the second connection portions, The semiconductor device is characterized in that the one second connection surface portion is disposed between the longitudinal extension lines of the two lead frame branch portions.

6. The semiconductor device according to claim 1, wherein the individual gate wiring is a bonding wire.

7. The semiconductor device according to claim 1, wherein, in a top view with respect to the insulating substrate, the two lead frame branch portions each have the second connection surface portion individually, and are connected to the second conductor layer pattern by the second connection surface portion.

8. The semiconductor device according to claim 1, wherein the lead frame is configured by being divided into a plurality of lead frames, and the first connection surface portion and the second connection surface portion are formed on different lead frames.

9. A main circuit having one or more pairs of high-voltage side and low-voltage side switch circuits, and a drive circuit for driving the high-voltage side and low-voltage side switch circuits, wherein the high-voltage side and low-voltage side switch circuits have the semiconductor device according to any one of claims 1 to 8.

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