Semiconductor module

Abstract

To provide a semiconductor module in which the power cycle tolerance can be improved.SOLUTION: A back surface of a semiconductor chip 1 is bonded to a conductive plate 22a on a front surface of a circuit board 2 through a bonding member 11. The circuit board 2 is accommodated inside a case 4. A lead frame (LF) 5 is bonded to an electrode pad 1a formed of a front surface electrode of the semiconductor chip 1 through a bonding member 13. The LF 5 is bonded to an electrode pad 2a formed of a conductive plate 22b on the front surface of the circuit board 2 through a bonding member 14. The LF 5 electrically connects the electrode pads 1a and 2a to each other. The semiconductor chip 1, the circuit board 2, and the LF 5 are protected with a sealing material 6 and an insulating layer 8. The insulating layer 8 is formed of an electrically insulating material with a lower elastic modulus than the sealing material 6. The insulating layer 8 covers the entire surface of the sealing material 6 and faces the LF 5 in a thickness direction of the semiconductor chip 1.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This disclosure relates to a semiconductor module.

Background Art

[0002] Patent Document 1 describes a technique for increasing the strength of the surface electrode of a semiconductor chip and extending the life in the power cycle evaluation of the semiconductor chip or power module. The same technique is also described in Patent Document 2. Patent Document 3 describes a technique for reducing the stress applied to the joint portion with the electrode pattern of the lead frame wiring and extending the fatigue life of the power cycle test.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1 above, since the lead terminal is fixed in position by the sealing material, when the semiconductor chip thermally expands during the power cycle test, the portion rising from the front surface electrode of the semiconductor chip of the lead terminal deforms. Due to the adverse effect of the deformation of the rising portion of the lead terminal, strain occurs in the front surface electrode of the semiconductor chip and leads to fracture. In the structure using a lead material in Patent Document 2 above, the same problem as in Patent Document 1 occurs. In Patent Document 3 above, the same problem as in Patent Document 1 occurs.

[0005] An object of this disclosure is to provide a semiconductor module capable of improving power cycle tolerance.

Means for Solving the Problem

[0006] A semiconductor module according to one aspect of this disclosure is as follows. The semiconductor chip has its back surface bonded to the upper surface of the laminated substrate and has a front surface electrode on its front surface. The lead frame electrically connects the front surface electrode and the conductive plate. The encapsulant encapsulates the semiconductor chip, the laminated substrate, and the lead frame. The insulating layer is provided on the side opposite to the laminated substrate side of the lead frame and faces the lead frame in the thickness direction of the semiconductor chip. The insulating layer is made of an electrically insulating material having a lower elastic modulus than the encapsulant.

Advantages of the Invention

[0007] According to the semiconductor module according to the present disclosure, there is an effect that the power cycle tolerance can be improved.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

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Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Mode for Carrying Out the Invention

[0009] <Summary of Embodiment of the Present Disclosure> (1) The semiconductor module according to one aspect of this disclosure is as follows. The laminated substrate has a conductive plate on the upper surface. The semiconductor chip has its back surface bonded to the upper surface of the laminated substrate and a front surface electrode on the front surface. The lead frame electrically connects the front surface electrode and the conductive plate. The encapsulant encapsulates the semiconductor chip, the laminated substrate, and the lead frame. The insulating layer is provided on the side opposite to the laminated substrate side of the lead frame and faces the lead frame in the thickness direction of the semiconductor chip. The insulating layer is made of an electrically insulating material having a lower elastic modulus than the encapsulant.

[0010] According to the above disclosure, since the insulating layer provided opposite to the lead frame can reduce the supporting force of the sealing material on the lead frame, even if a stress is generated to push up the rising part of the lead frame upward due to the thermal expansion of the semiconductor chip, the rising part of the lead frame is likely to move upward and is less likely to deform. As a result, stress concentration is less likely to occur at the end of the front surface electrode of the semiconductor chip, and the amount of strain at the end of the front surface electrode of the semiconductor chip can be reduced, so that the power cycle tolerance can be improved.

[0011] (2) Further, in the semiconductor module according to this disclosure, in the above (1), the insulating layer may face the entire lead frame.

[0012] According to the above disclosure, the greater the area of the insulating layer facing the lead frame in the thickness direction of the semiconductor chip, the higher the effect of the insulating layer.

[0013] (3) Further, in the semiconductor module according to this disclosure, in the above (1) or (2), the insulating layer may be in contact with the lead frame.

[0014] According to the above disclosure, the closer the insulating layer is to the lead frame in the thickness direction of the semiconductor chip, the higher the effect of the insulating layer.

[0015] (4) Further, in the semiconductor module according to this disclosure, in any one of the above (1) to (3), the thickness of the insulating layer may be 0.2 mm or more and 0.5 mm or less.

[0016] According to the above disclosure, the greater the thickness of the insulating layer provided opposite to the lead frame, the higher the effect of the insulating layer.

[0017] (5) Further, in any one of the above (1) to (4) regarding this disclosure, in the semiconductor module according to this disclosure, the lead frame has a flat plate-shaped joint portion that is surface-bonded to the front surface electrode, a flat plate-shaped rising portion that bends and rises from an end of the joint portion and shares one end with the joint portion, and a flat plate-shaped connecting portion that shares the other end of the rising portion and bends from the other end of the rising portion to electrically connect the other end of the rising portion and the conductive plate. The insulating layer may face the other end of the rising portion in the thickness direction of the semiconductor chip.

[0018] According to the above disclosure, by arranging the insulating layer so as to face at least the other end of the rising portion in the thickness direction of the semiconductor chip, the effect of the insulating layer can be obtained.

[0019] (6) Further, in the semiconductor module according to this disclosure, in the above (5), the insulating layer may be in contact with the entire surface on the side opposite to the laminated substrate side of the connecting portion.

[0020] According to the above disclosure, the larger the area where the insulating layer faces the lead frame in the thickness direction of the semiconductor chip, the higher the effect of the insulating layer.

[0021] (7) Further, in the semiconductor module according to this disclosure, in the above (6), the insulating layer may extend from the connecting portion along the rising portion to the non-bonding surface on the side opposite to the bonding surface with the front surface electrode of the joint portion.

[0022] According to the above disclosure, for example, the insulating layer can be formed to cover the entire upper surface of the lead frame using a sheet-like electrical insulating material, and the assembly process can be simplified.

[0023] (8) Further, in the semiconductor module according to this disclosure, in the above (5), the insulating layer may be provided only at the other end of the rising portion.

[0024] According to the above disclosure, for example, an insulating layer can be formed using a sheet-like electrical insulating material so as to cover only the other end of the rising portion, and thus the assembly process can be simplified.

[0025] (9) Further, the semiconductor module according to this disclosure may include, in the above (8), a hook-shaped portion that sandwiches and holds the insulating layer between the other end of the rising portion and the lead frame.

[0026] According to the above disclosure, for example, when forming an insulating layer using a sheet-like electrical insulating material, it is possible to prevent the insulating layer from falling during the assembly process.

[0027] <The knowledge underlying the present disclosure> First, the semiconductor module of the reference example will be described. FIG. 13 is a cross-sectional view showing the structure of the semiconductor device of the reference example. The semiconductor module 110 of the reference example shown in FIG. 13 has a structure in which one or more semiconductor chips 101 and components (not shown) are incorporated as one unit (functional unit), and is used, for example, in a power conversion device or the like. The front surface electrode (hereinafter referred to as the back surface electrode: not shown) on the back surface of the semiconductor chip 101 is joined to the conductive plate 122 (122a) on the front surface of the circuit board 102 via a joining member 111.

[0028] The conductive plates 122 (122a, 122b) constitute the circuit pattern of the circuit board 102. The metal foil 123 on the back surface of the circuit board 102 is joined to the front surface of the cooling base 103 via a joining member 112. The circuit board 102 is a laminated board having conductive plates 122 and metal foils 123 on both surfaces of the insulating substrate 121, respectively. A resin case 104 is adhered to the periphery of the cooling base 103. The circuit board 102 is housed in a box-shaped recess 107 surrounded by the cooling base 103 and the case 104.

[0029] The lead frame (LF) 105 is joined to the front surface electrodes (hereinafter referred to as the front surface electrodes, not shown) of the front surface of the semiconductor chip 101 via a joining member 113. Further, the LF 105 is joined to the conductive plate 122(122b) on the front surface of the circuit board 102 via a joining member 114. The LF 105 is a flat conductive wiring member. The LF 105 has an LF joining portion 105a, an LF rising portion 105b, and an LF connecting portion 105c.

[0030] The LF joining portion 105a is a portion of the LF 105 that is joined to the electrode pad (front surface electrode or conductive plate 122b) on the front surface of the circuit board 102, and has a substantially rectangular flat surface parallel to the surface of the electrode pad. The LF joining portion 105a is provided for each electrode pad on the front surface of the circuit board 102. The LF rising portion 105b has a substantially rectangular flat surface that bends substantially perpendicularly from an end (one side) of the LF joining portion 105a. The LF rising portion 105b is provided for each LF joining portion 105a.

[0031] The LF connecting portion 105c has a substantially rectangular flat surface that bends substantially perpendicularly from an end (one side that becomes the upper end portion 105b-1) of the LF rising portion 105b, and connects adjacent LF rising portions 105b to each other. The LF 105 has a substantially Z-shaped cross-sectional shape having a bent portion (right angle portion) at the boundary between the LF joining portion 105a and the LF rising portion 105b and a bent portion at the boundary between the LF rising portion 105b and the LF connecting portion 105c, and extends between adjacent electrode pads.

[0032] The inside of the recess 107 is filled with a sealing material 106 made of a resin such as silicone gel. The sealing material 106 covers all the members housed inside the recess 107 and surrounds the peripheries of all these members. The sealing material 106 covers the side surfaces of the circuit board 102 (the surface along the insulating substrate 121 and the ends of the metal foil 123), the semiconductor chip 101 and the conductive plate 122 on the front surface of the circuit board 102, the side surfaces of the joining members 111 to 114, and the LF 105 to electrically insulate from the external environment and has the function of mechanically, physically, and chemically protecting from the external environment.

[0033] In the semiconductor module 110 of this reference example, during the power cycle test, the semiconductor chip 101 and its peripheral members are deformed, and the front surface electrode of the semiconductor chip 101 becomes the fracture point. The power cycle test is a test for evaluating the bonding reliability between the members in the semiconductor module 110 by alternately repeating the increase (self-heating of the semiconductor chip 101) and decrease (natural heat dissipation: cooling of the semiconductor chip 101) of the junction temperature of the semiconductor element formed in the semiconductor chip 101 within a predetermined temperature difference ΔT vj inside.

[0034] The deformation mechanism of the semiconductor chip 101 and its peripheral members in the semiconductor module 110 of the reference example will be described. FIG. 14 is an explanatory diagram schematically showing the state at the time of deformation due to thermal stress of the members in the semiconductor module of the reference example. In FIG. 14, by alternately repeating the heating and cooling of the semiconductor chip 101 in the power cycle test, the state in which the semiconductor chip 101 and its peripheral members (the joining member 113 and the LF 105) in the semiconductor module 110 are deformed under the stress due to thermal stress is schematically shown.

[0035] As shown in FIG. 14, when the semiconductor chip 101 generates heat due to energization of the semiconductor element formed on the semiconductor chip 101, the front surface electrode (not shown) of the semiconductor chip 101, the bonding member 113, and the LF bonding portion 105a thermally expand in the vertical direction (the thickness direction of the semiconductor chip 101), and the upper surface moves upward (in the direction away from the circuit board 102). On the other hand, since the LF rising portion 105b is supported by the sealing material 106 and is fixed in position and hardly moves, it is pressed against the semiconductor chip 101 and bends, so that the height (length) becomes shorter.

[0036] When the semiconductor chip 101 is cooled, the sealing material 106 cools and contracts and plastically deforms, pushing down the semiconductor chip 101, the bonding member 113, and the LF bonding portion 105a downward (toward the circuit board 102 side). As described above, the LF rising portion 105b is supported by the sealing material 106 and hardly moves. In addition, the length of the LF rising portion 105b is shortened. For this reason, the end portion of the front surface electrode of the semiconductor chip 101 is pulled upward by the LF rising portion 105b, and strain occurs in the end portion of the front surface electrode of the semiconductor chip 101.

[0037] When the heating and cooling of the semiconductor chip 101 are alternately repeated, compressive stress and tensile stress are alternately and repeatedly applied to the front surface electrode and the bonding member 113 of the semiconductor chip 101 directly below the lower end portion (the end portion on the circuit board 102 side) 105b-2 of the LF rising portion 105b. For this reason, the front surface electrode and the bonding member 113 of the semiconductor chip 101 deteriorate and break directly below the lower end portion 105b-2 of the LF rising portion 105b. Therefore, an issue to be solved in the present embodiment is to improve the power cycle tolerance.

[0038] Hereinafter, with reference to the accompanying drawings, preferred embodiments of the semiconductor module according to this disclosure will be described in detail. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0039] (Details of Embodiment 1) The following describes a semiconductor module according to Embodiment 1 that solves the above-described problems. FIG. 1 is a plan view showing an example of the layout of the semiconductor module according to Embodiment 1 as viewed from the front side of the circuit board. FIG. 2 is a plan view showing an enlarged view of a portion A surrounded by a rectangle in FIG. 1. FIG. 2 shows an enlarged view of the semiconductor chip 1 and the LF joint 5a in FIG. 1. FIG. 3 is a cross-sectional view schematically showing the cross-sectional structure along the cutting line B - B' in FIG. 1. FIG. 4 is a cross-sectional view schematically showing another example of the cross-sectional structure along the cutting line B - B' in FIG. 1. In FIGS. 3 and 4, the members in the semiconductor module 10 are illustrated with dimensions different from those in FIG. 1.

[0040] The semiconductor module 10 according to Embodiment 1 shown in FIGS. 1 to 3 has a structure in which one or more semiconductor chips 1 and components (not shown) are incorporated as one unit (functional unit), and is used, for example, in a power conversion device or the like. As the material of the semiconductor chip 1, for example, silicon (Si) or silicon carbide (SiC) can be used. One or more semiconductor elements that constitute part or all of functions such as conversion (conversion of input signals such as voltage, current, frequency, etc.) and connection (on / off of external components) are fabricated on the semiconductor chip 1. On the front surface of the semiconductor chip 1, a surface electrode (front surface electrode: not shown) of the semiconductor element is provided.

[0041] Examples of the semiconductor elements fabricated on the semiconductor chip 1 include MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor having an insulated gate composed of a three-layer structure of metal - oxide film - semiconductor), IGBT (Insulated Gate Bipolar Transistor: an insulated gate bipolar transistor), and diodes. The front surface electrode of the semiconductor chip 1 is, for example, the source electrode of the MOSFET, the emitter electrode of the IGBT, or the anode electrode of the diode.

[0042] The front surface of the semiconductor chip 1 is covered with a passivation film 9. The front surface electrode has a substantially rectangular portion exposed in the opening 9a of the passivation film 9 that functions as an electrode pad 1a. In some cases, other electrode pads 1b that do not bond the LF5 described later may be exposed in other openings 9b of the passivation film 9. The front surface electrode (back surface electrode: not shown) on the back surface of the semiconductor chip 1 is bonded to the conductive plate 22(22a) on the front surface (upper surface) of the circuit board 2 via a bonding member 11. The conductive plate 22(22b) partially functions as an electrode pad 2a. The conductive plates 22(22a, 22b) constitute the circuit pattern of the circuit board 2.

[0043] The metal foil 23 on the back surface of the circuit board 2 is bonded to the front surface of the cooling base 3 via a bonding member 12. The circuit board 2 is a laminated board having conductive plates 22 and a metal foil 23 on both surfaces of an insulating substrate 21, respectively. The cooling base 3 is a conductive heat dissipation plate that conducts heat generated by the semiconductor chip 1 and transmitted through the circuit board 2 to a heat dissipation fin portion (not shown). The heat dissipation fin portion is bonded to the back surface of the cooling base 3. A resin case 4 is adhered to the periphery of the cooling base 3. An insulating substrate 21 is provided inside the case 4. The case 4 does not have to be in contact with the periphery of the insulating substrate 21, and there may be a gap between the case 4 and the insulating substrate 21. The case 4 may be adhered in contact with at least a part of the periphery of the insulating substrate 21. The circuit board 2 is housed in a box-shaped recess 7 surrounded by the cooling base 3 and the case 4.

[0044] The lead frame (LF) 5 is bonded to the front surface electrode (electrode pad 1a) of the semiconductor chip 1 via a bonding member 13. Further, the LF5 is bonded to the conductive plate 22b (electrode pad 2a) on the front surface of the circuit board 2 via a bonding member 14. The LF5 supports the semiconductor chip 1 and fixes it to the circuit board 2, and electrically connects the front surface electrode of the semiconductor chip 1 and the external lead-out wiring (not shown) of the semiconductor module 10. The LF5 is a flat conductive wiring member formed by, for example, pressing, bending, etching, etc. a copper-based flat plate such as a copper (Cu) alloy with excellent conductivity.

[0045] LF5 is joined to the front surface electrode of the semiconductor chip 1 (for example, the front surface electrode of the semiconductor element that performs the main operation of the semiconductor chip 1), has the function of conducting the semiconductor chip 1, and dissipating the heat generated in the semiconductor chip 1. By using LF5, miniaturization of the semiconductor module 10 becomes easier compared to wire bonding in which the front surface electrode of the semiconductor chip 1 and the external lead wiring are electrically connected by wires. Also, since a plurality of LF5s can be joined to a plurality of sites (electrode pads 1a, 2a) at once, the assembly process is simplified compared to wire bonding in which a plurality of wires are joined to each of the electrode pads 1a, 2a.

[0046] LF5 has an LF joint portion 5a, an LF rising portion 5b, and an LF connecting portion 5c. The thickness t1 of LF5 is, for example, about 0.5 mm. LF5 has a bent portion (substantially L-shaped right angle portion or substantially V-shaped obtuse angle portion) at the boundary between the LF joint portion 5a and the LF rising portion 5b, and has a substantially Z-shaped cross-sectional shape having a bent portion at the boundary between the LF rising portion 5b and the LF connecting portion 5c, and extends between adjacent semiconductor chips 1 (that is, between electrode pads 1a) or extends between adjacent semiconductor chips 1 and the conductive plate 22b (that is, between electrode pads 1a, 2a).

[0047] The LF joint portion 5a is a portion of LF5 that is surface-joined to the electrode pads 1a, 2a (front surface electrode of the semiconductor chip 1, conductive plate 22b) on the front surface of the circuit board 2, and has a substantially rectangular flat surface parallel to the front surface of the semiconductor chip 1. The joint surface (lower surface) of the LF joint portion 5a has, for example, substantially the same surface area as the electrode pads 1a, 2a, and covers substantially the entire surface of the electrode pads 1a, 2a via the joint members 13, 14. As the surface area of the LF joint portion 5a becomes smaller, the heat dissipation performance of the semiconductor chip 1 deteriorates, so the usefulness of the present disclosure is enhanced. The LF joint portion 5a is provided for each of the electrode pads 1a, 2a on the front surface of the circuit board 2. The width (width in the short side direction) w1 of the LF joint portion 5a is, for example, about 3.0 mm.

[0048] The LF rising part 5b is bent substantially perpendicularly from the end (one side) of the LF joint part 5a, and has a substantially rectangular flat surface that shares the LF joint part 5a and one side (the lower end part 5b-2 of the LF rising part 5b). The LF rising part 5b is provided for each LF joint part 5a. The LF rising part 5b may be inclined at an angle of 45 degrees or more and less than 90 degrees with respect to the front surface of the semiconductor chip 1 so as to form an obtuse angle with the LF joint part 5a. That is, the upper surface of the LF joint part 5a (the non-joint surface on the side opposite to the surface on the circuit board 2 side) and the flat surface of the LF rising part 5b form an angle within the range of 90 degrees or more and 135 degrees or less. The upper limit value of the height (length) h of the LF rising part 5b is appropriately set according to the height of the case 4 (the depth of the recess 7).

[0049] The higher the height h of the LF rising part 5b, the more likely it is to be affected by the heat generation of the semiconductor chip 1, so the usefulness of the present disclosure is higher. If the height h of the LF rising part 5b is too low, there is a possibility that the sealing material 6 described later cannot be filled between the LF rising part 5b and the circuit board 2. For this reason, the height h of the LF rising part 5b is preferably, for example, about 2.0 mm or more. The height h of the LF rising part 5b is the vertical distance from the upper surfaces of the joining members 13 and 14 to the lower surface (the surface on the circuit board 2 side) 5c-2 of the LF connecting part 5c. The width (the width in the short side direction) w2 of the LF rising part 5b is, for example, substantially the same as the width w1 of the LF joint part 5a.

[0050] The LF connecting part 5c is bent from the upper end part (one side that becomes the end part on the side opposite to the circuit board 2 side) 5b-1 of the LF rising part 5b, and has a substantially rectangular flat surface (the upper surface 5c-1 and the lower surface 5c-2) that shares the LF rising part 5b and one side (the upper end part 5b-1 of the LF rising part 5b). The LF connecting part 5c connects the LF rising parts 5b adjacent to each other. The flat surface of the LF connecting part 5c is substantially parallel to the flat surface of the LF joint part 5a. The angle formed by the lower surface 5c-2 of the LF connecting part 5c and the flat surface of the LF rising part 5b is substantially the same as the angle formed by the upper surface of the LF joint part 5a and the flat surface of the LF rising part 5b. The width (the width in the short side direction) w3 of the LF connecting part 5c may be narrower than the width w1 of the LF joint part 5a (for example, about 2.5 mm).

[0051] Inside the recess 7, a sealing material 6 made of a resin such as silicone gel is filled up to a predetermined height from the bottom surface of the recess 7 (the front surface of the cooling base 3). The sealing material 6 is filled up to at least the height position of the upper surface of the LF joint portion 5a from the bottom surface of the recess 7. Thereby, the joint members 11 to 14 that are relatively susceptible to adverse effects from the external environment are covered and protected by the sealing material 6. Therefore, the sealing material 6 at least covers the exposed portions of the circuit board 2 (the ends of the insulating substrate 21 and the ends of the metal foil 23), the semiconductor chip 1 and the conductive plate 22 on the front surface of the circuit board 2, the exposed portions of the joint members 11 to 14 (the side surfaces in FIG. 1), and the side surface of the LF joint portion 5a, and has a function of electrically insulating from the external environment and mechanically, physically, and chemically protecting from the external environment.

[0052] The sealing material 6 may be filled up to a height equal to or higher than the height position of the upper surface 5c-1 of the LF connection portion 5c, for example, from the bottom surface of the recess 7, so as to surround the upper surface of the LF joint portion 5a, the LF rising portion 5b, and the side surface and the lower surface 5c-2 of the LF connection portion 5c (FIG. 3). The higher the height position of the upper surface of the sealing material 6, the more the portions of the upper surface of the LF joint portion 5a, the LF rising portion 5b, and the side surface and the lower surface 5c-2 of the LF connection portion 5c that are mechanically, physically, and chemically protected from the external environment by the sealing material 6 can be increased. By thickly providing the insulating layer 8 described later on the sealing material 6, the upper surface of the LF joint portion 5a, the LF rising portion 5b, and the side surface and the lower surface 5c-2 of the LF connection portion 5c may be surrounded by the insulating layer 8.

[0053] Inside the recess 7, an insulating layer (hatched portion) 8 is further provided on the sealing material 6. The insulating layer 8 is provided on the side opposite to the circuit board 2 side of LF5, and is provided on the upper surface 5c-1 of the LF connection portion 5c so as to face at least the upper end portion 5b-1 of the LF rising portion 5b in the vertical direction (the thickness direction of the semiconductor chip 1). The insulating layer 8 may face the upper surface 5c-1 of the LF connection portion 5c through the sealing material 6 in the vertical direction. The insulating layer 8 may extend with a substantially uniform thickness parallel to the front surface of the circuit board 2 and contact the side wall of the recess 7 (the inner wall of the case 4). FIG. 3 shows a state where the sealing material 6 is filled up to the same height position as the upper surface 5c-1 of the LF connection portion 5c, and the insulating layer 8 covers the entire surface of the sealing material 6 and faces the entire LF5.

[0054] The insulating layer 8 may have a thickness t2 of, for example, about 0.2 mm or more and 0.5 mm or less in the portion facing the upper surface 5c-1 of the LF connection portion 5c in the vertical direction (see FIG. 12 described later). The insulating layer 8 only needs to have the above thickness t2 in the portion facing the upper surface 5c-1 of the LF connection portion 5c in the vertical direction, and the height position of the lower surface of the insulating layer 8 (that is, the upper surface of the sealing material 6) can be appropriately set within the range up to the height position of the upper surface of the LF bonding portion 5a on the circuit board 2 side. The insulating layer 8 may have a planar outer dimension equal to or larger than the outer dimension (width w3 and length) of the upper surface 5c-1 of the LF connection portion 5c and face the entire upper surface 5c-1 of the LF connection portion 5c. The larger the planar outer dimension of the insulating layer 8, the higher the effect of the insulating layer 8.

[0055] The insulating layer 8 has a function of reducing the supporting force of the sealing material 6 on the LF rising portion 5b and promoting the movement of the LF rising portion 5b according to the stress applied to the LF rising portion 5b. Since the insulating layer 8 faces the upper end portion 5b-1 of the LF rising portion 5b in the vertical direction, the insulating layer 8 can promote the vertical movement of the LF rising portion 5b. Since the insulating layer 8 makes it easier for the LF rising portion 5b to move in the vertical direction, even if a vertical stress is applied to the LF rising portion 5b due to the expansion of the front surface electrode caused by the self-heating of the semiconductor chip 1, the stress concentration on the lower end portion (one side serving as the end portion on the circuit board 2 side) 5b-2 of the LF rising portion 5b can be suppressed.

[0056] In addition, the insulating layer 8 has a function of electrically insulating LF5 from the external environment and protecting it mechanically, physically, and chemically from the external environment. That is, the members inside the recess 7 are surrounded and protected by the sealing material 6, the insulating layer 8, or both. The insulating layer 8 is formed of an insulating material that is softer (lower in hardness) than the sealing material 6. The elastic modulus of the insulating layer 8 is smaller than the elastic modulus of the sealing material 6 (for example, about 20 GPa), and is, for example, about 3 GPa or more and 10 GPa or less. Specifically, the insulating layer 8 may be formed of a material having electrical insulation properties. For example, it may be formed of a resin material such as an epoxy resin, or a sheet-like electrical insulating material such as electrical insulating paper or electrical insulating film generally used in electronic components.

[0057] As the sheet-like electrical insulating material, for example, raw materials such as aramid fiber, cellulosic fiber, and synthetic fiber (polyester fiber, polyimide fiber) can be used alone or in combination of a plurality. The electrical insulating paper is, for example, aramid paper made of aramid fiber as a raw material or cellulosic paper made of cellulosic fiber as a raw material. The electrical insulating film is, for example, a PET film made of polyethylene terephthalate (PET) as a raw material. The thickness of the sheet-like electrical insulating material is, for example, 0.3 mm or more, and can be thickened to about 1.0 mm by laminating a plurality of sheets. The insulating layer 8 may be formed by laminating a plurality of sheet-like electrical insulating materials having different raw materials.

[0058] To fabricate the semiconductor module 10, first, the back surface (back surface electrode) of the semiconductor chip 1 is joined to the conductive plate 22a on the front surface of the circuit board 2 via the joining member 11. Next, different LF joints 5a of one LF5 are joined to the electrode pad 1a (front surface electrode) of the semiconductor chip 1 and the electrode pad 2a (conductive plate 22b) of the circuit board 2 via the joining members 13 and 14, respectively, and the electrode pads 1a and 2a are electrically connected by the LF5. Next, the back surface of the circuit board 2 is joined to the front surface of the cooling base 3 via the joining member 12. Next, the case 4 is adhered to the periphery of the cooling base 3, and the circuit board 102 is housed in the case 4 (inside the recess 7). Thereafter, the members inside the recess 7 are protected by the sealing material 6 and the insulating layer 8.

[0059] In the formation of the sealing material 6 and the insulating layer 8, when the insulating layer 8 is formed of a resin material, after pouring the resin material that becomes the sealing material 6 into the recess 7 and curing it, the resin material that becomes the insulating layer 8 may be poured onto the sealing material 6 inside the recess 7 and cured. When the insulating layer 8 is formed of a sheet-like electrical insulating material, after pouring the resin material that becomes the sealing material 6 (6a) into the recess 7 and curing it, the upper surface of the sealing material 6a may be covered with the sheet-like electrical insulating material that becomes the insulating layer 8. Further, the resin material that becomes the sealing material 6 (6b) may be poured onto the sheet-like electrical insulating material inside the recess 7 and cured (see FIG. 4). The sealing material 6b suppresses the peeling of the sheet-like electrical insulating material (insulating layer 8), and the sealing material 6 improves the insulation property.

[0060] Even when the insulating layer 8 is formed of a resin material, it may be configured such that the pouring and curing of the resin material into the recess 7 are alternately repeated to form the sealing material 6a, the insulating layer 8, and the sealing material 6b in this order (see FIG. 4). When a plurality of LF5s are arranged inside the recess 7 (not shown), one insulating layer 8 facing in the vertical direction may be arranged for all the LF5s, or different insulating layers 8 may be arranged facing in the vertical direction for each LF5. The joining members 11 to 14 are, for example, conductive layers made of a solder material, a metal sintered material, or the like.

[0061] In the semiconductor module 10 according to the first embodiment, as described above, since the insulating layer 8 is provided facing the upper end portion 5b-1 of the LF rising portion 5b, it is possible to suppress the strain of the front surface electrode of the semiconductor chip 1 due to the thermal expansion of the semiconductor chip 1 and its peripheral members (bonding member 13 and LF bonding portion 5a) during the power cycle test. The reason is as follows. The power cycle test is a test for evaluating the bonding reliability between members in the semiconductor module 10 by alternately repeating the rise (self-heating of the semiconductor chip 1) and fall (natural heat dissipation: cooling of the semiconductor chip 1) of the junction temperature of the semiconductor element formed in the semiconductor chip 1 within a predetermined temperature difference ΔT vj inside.

[0062] When the semiconductor chip 1 generates heat due to the energization of the semiconductor element formed in the semiconductor chip 1, the front surface electrode of the semiconductor chip 1, the bonding member 13, and the LF bonding portion 5a thermally expand in the vertical direction, and the upper surface moves upward (in the direction away from the circuit board 2). The LF5 is easily movable in the vertical direction at the LF rising portion 5b by the insulating layer 8. When the upper surfaces of the front surface electrode of the semiconductor chip 1, the bonding member 13, and the LF bonding portion 5a move upward due to thermal expansion, the LF rising portion 5b is also easily moved upward by being pushed by the semiconductor chip 1, and stress concentration at the lower end portion 5b-2 of the LF rising portion 5b is suppressed. For this reason, it is possible to suppress the deformation (bending) of the LF rising portion 5b when the semiconductor chip 1 generates heat.

[0063] When the semiconductor chip 1 is cooled, the encapsulant 6 cools and shrinks, plastically deforming, and pushing down the semiconductor chip 1, the joining member 13, and the LF joint 5a downward (toward the circuit board 2 side). The LF 5 is easily movable vertically at the LF rising portion 5b by the insulating layer 8. Further, as described above, the LF rising portion 5b is less likely to deform due to the heat generation of the semiconductor chip 1 and substantially maintains the length before the power cycle test. Therefore, even if the semiconductor chip 1 is pushed downward by the encapsulant 6, the end of the front surface electrode of the semiconductor chip 1 is less likely to be pulled upward by the LF rising portion 5b. For this reason, the occurrence of strain at the end of the front surface electrode of the semiconductor chip 1 directly below the lower end portion 5b-2 of the LF rising portion 5b is suppressed.

[0064] As described above, according to the first embodiment, the insulating layer is provided so as to face the upper surface of the LF connecting portion in the vertical direction at least so as to face the upper end portion of the LF rising portion in the vertical direction. This insulating layer is formed of an insulating material having a lower elastic modulus than the encapsulant. Since this insulating layer can reduce the supporting force of the encapsulant on the LF rising portion, even if a stress is generated to push up the LF rising portion upward due to the thermal expansion of the semiconductor chip, the LF rising portion is likely to move upward and is less likely to deform. For this reason, stress concentration is less likely to occur at the end of the front surface electrode of the semiconductor chip, and the amount of strain at the end of the front surface electrode of the semiconductor chip is reduced. Therefore, the reliability of the front surface electrode of the semiconductor chip is improved, and the reliability of the semiconductor module is improved. Further, even if the heat generation and cooling of the semiconductor chip are repeated, the front surface electrode of the semiconductor chip is less likely to deteriorate, and the power cycle tolerance can be improved.

[0065] (Details of the Second Embodiment) The following describes a semiconductor module according to Embodiment 2 that solves the above problems. FIGS. 5 and 6 are cross-sectional views showing the structure of the semiconductor module according to Embodiment 2. FIGS. 7 and 8 are cross-sectional views showing another example of the structure of the semiconductor module according to Embodiment 2. The semiconductor modules 30 and 40 according to Embodiment 2 shown in FIGS. 5 and 7 are different from the semiconductor module 10 (see FIGS. 3 and 4) according to Embodiment 1 in the cross-sectional shape of the insulating layers (hatched portions) 31 and 41 that face the upper surface 5c-1 of the LF connection portion 5c in the vertical direction. The configuration other than the cross-sectional shape of the insulating layer 31 is the same as that of the insulating layer 8 in Embodiment 1.

[0066] In the semiconductor module 30 according to Embodiment 2 shown in FIG. 5, the insulating layer 31 extends along the upper surface of LF5 and has substantially the same cross-sectional shape as LF5. The insulating layer 31 is in contact with the upper surface of the LF joint portion 5a, the upper surface of the LF rising portion 5b (the surface connecting the upper surface of the LF joint portion 5a and the upper surface 5c-1 of the LF connection portion 5c), and the upper surface 5c-1 of the LF connection portion 5c to cover substantially the entire upper surface of LF5. The insulating layer 31 may be entirely covered by the encapsulant 6 or may be exposed outside the encapsulant 6 at a portion on the upper surface 5c-1 of the LF connection portion 5c.

[0067] The insulating layer 31 can be easily formed, for example, by using a sheet-like electrical insulating material. When forming the insulating layer 31 using a sheet-like electrical insulating material, first, the sheet-like electrical insulating material is formed into a predetermined planar shape by die-cutting or punching. Then, a resin material that becomes the encapsulant 6 is poured into the recess 7 and cured. After arranging the sheet-like electrical insulating material that becomes the insulating layer 31 on LF5, the resin material that becomes the encapsulant 6 may be poured again on the sheet-like electrical insulating material and cured.

[0068] When a sheet-like electrical insulating material that becomes the insulating layer 31 floats from the upper surface of the LF5 in the vicinity of the bent portion 5d (the lower end portion 5b-2 of the LF rising portion 5b) between the LF joint portion 5a and the LF rising portion 5b (FIG. 6), before pouring the resin material that becomes the sealing material 6 into the concave portion 7 again, the space between the sheet-like electrical insulating material that becomes the insulating layer 31 and the LF5 may be filled with the resin material 32. The resin material 32 may be an epoxy resin or the like with a low elastic modulus of the sealing material 6, or may be the same resin material as the sealing material 6. The sealing material 6 may be interposed between the insulating layer 31 and the LF5.

[0069] In the semiconductor module 40 according to the second embodiment shown in FIG. 7, the insulating layer 41 is disposed only on the upper end portion 5b-1 of the LF rising portion 5b. If the insulating layer 41 is disposed on the upper end portion 5b-1 of the LF rising portion 5b, it is presumed that the supporting force of the sealing material 6 on the LF rising portion 5b can be reduced. The insulating layer 41 may face the upper end portion 5b-1 of the LF rising portion 5b in the vertical direction via the sealing material 6. The configuration other than the cross-sectional shape of the insulating layer 41 is the same as that of the insulating layer 8 in the first embodiment. The insulating layer 41 may protrude around the upper end portion 5b-1 of the LF rising portion 5b. In particular, the effect of the insulating layer 41 becomes higher as the length w11 of the insulating layer 41 extends longer than the thickness t1 of the LF5 (the LF rising portion 5b) in the longitudinal direction of the LF connecting portion 5c along the upper surface 5c-1 of the LF connecting portion 5c.

[0070] A hook-shaped portion 5e may be provided at the upper end portion 5b-1 of the LF rising portion 5b (FIG. 8). The hook-shaped portion 5e protrudes upward from the upper surface 5c-1 of the LF connecting portion 5c and has a cross-sectional shape that is bent in a hook shape toward the center in the short side direction of the LF connecting portion 5c. The hook-shaped portions 5e are provided on opposite sides in the short side direction of the upper surface 5c-1 of the LF connecting portion 5c, respectively. The hook-shaped portion 5e has a function of sandwiching and holding the insulating layer 41 (sheet-like electrical insulating material) between the upper end portion 5b-1 of the LF rising portion 5b and the bent portion 5e-1 that is bent in a hook shape toward the center in the short side direction of the LF connecting portion 5c, and preventing the insulating layer 41 from falling from above the LF5 during the assembly process. The hook-shaped portion 5e may extend along opposite sides in the short side direction of the upper surface 5c-1 of the LF connecting portion 5c.

[0071] As described above, according to the second embodiment, if the insulating layer faces the upper end portion of the LF rising portion in the vertical direction, the same effects as those of the first embodiment can be obtained.

[0072] (Details of the Third Embodiment) The semiconductor module according to the third embodiment for solving the above problems will be described below. FIG. 9 is a cross-sectional view showing the structure of the semiconductor module according to the third embodiment. The difference between the semiconductor module 50 according to the third embodiment and the semiconductor module (FIGS. 3 and 4) according to the first embodiment is that the front surface electrodes (electrode pads 1a) of the plurality of semiconductor chips 1 mounted on the circuit board 2 and the conductive plate 22b (electrode pad 2a) on the front surface of the circuit board 2 are electrically connected by one LF 51.

[0073] The LF 51 has the same number of LF joint portions 5a, LF rising portions 5b, and LF connecting portions 5c as those in the first embodiment as required to electrically connect a predetermined number of electrode pads 1a and 2a on the circuit board 2 to each other. The LF 51 extends between adjacent semiconductor chips 1 and between adjacent semiconductor chips 1 and the conductive plate 22b so as to include a substantially Z-shaped cross-sectional shape formed by the LF joint portion 5a, the LF rising portion 5b, and the LF connecting portion 5c in the same manner as in the first embodiment.

[0074] The insulating layer 8 is provided on the side opposite to the circuit board 2 side of the LF 51 and faces the upper surfaces 5c-1 of all the LF connecting portions 5c in the vertical direction. One insulating layer 8 may be provided so as to face the upper surfaces 5c-1 of all the LF connecting portions 5c of the LF 51 in the vertical direction, or different insulating layers 8 may be provided so as to face the upper surfaces 5c-1 of the respective LF connecting portions 5c of the LF 51 in the vertical direction. That is, the insulating layer 8 may face the entire LF 51 in the vertical direction, or may face only the upper surfaces 5c-1 of the respective LF connecting portions 5c of the LF 51 in the vertical direction.

[0075] Apply Embodiment 2 to the semiconductor module 50 according to Embodiment 3. An insulating layer may be extended along the upper surface of the LF51 to provide an insulating layer having substantially the same cross-sectional shape as the LF51 (see the insulating layer 31 in FIGS. 5 and 6). Alternatively, the insulating layer may be disposed only at a portion vertically facing the upper end portion 5b-1 of each LF rising portion 5b of the LF51 (see the insulating layer 41 in FIG. 7). A hook-shaped portion for holding the insulating layer may be provided at the upper end portion 5b-1 of each LF rising portion 5b of the LF51 (see the hook-shaped portion 5e in FIG. 8).

[0076] As described above, according to Embodiment 3, even when a plurality of semiconductor chips are electrically connected to each other, the same effects as those of Embodiment 1 can be obtained.

[0077] (Verification Example 1) The power cycle tolerance of the semiconductor module 10 according to Embodiment 1 was verified. FIG. 10 is a graph showing the result of simulating the strain amount of the front surface electrode of the semiconductor chips of the examples and reference examples. For a semiconductor module (hereinafter referred to as an example) having the structure of the semiconductor module 10 (see FIGS. 1 to 3) according to Embodiment 1, a simulation of simulating a power cycle test by FEM (Finite Element Method) analysis was performed, and the strain amount of the front surface electrode of the semiconductor chip 1 (here, strain amount = longitudinal deformation amount / original thickness) The calculated results are shown in FIG. 10.

[0078] Regarding the amount of strain in the front surface electrode of the semiconductor chip 1, for example, when paying attention to the amount of deformation in the vertical direction as in the structure shown in FIG. 10, the strain in the vertical direction may be used, or the equivalent strain may be used if comprehensive strain is to be extracted. The comprehensive strain is a strain having a plurality of plastic components with different directions as the main axes respectively. The equivalent strain is the plastic component in the predetermined axial direction of the strain repeatedly generated by repeatedly applying a load during the power cycle. That is, the amount of strain in the front surface electrode of the semiconductor chip 1 is the amount of deformation in the predetermined axial direction (excluding the direction parallel to the front surface of the circuit board 2) of the front surface electrode with respect to the original thickness of the front surface electrode (the height from the front surface of the semiconductor chip 1) (= deformation amount / original thickness).

[0079] In a simulation simulating a power cycle test, the junction temperature T of the semiconductor element due to intermittent energization to the semiconductor element fabricated on the semiconductor chip 1 vj The temperature difference ΔT between the maximum temperature and the minimum temperature vj was set to 135°C. The maximum temperature during the temperature rise of the junction temperature T of the semiconductor element due to the heat generation (self-heating) of the semiconductor chip 1 vj was set to 175°C, and the junction temperature T of the semiconductor element during the temperature drop due to the cooling (natural heat dissipation) of the semiconductor chip 1 vj The minimum temperature of the junction temperature T during the temperature drop vj was set to 40°C. The temperature at which the stress from the semiconductor chip 1 no longer acts on the LF rising portion 5b of LF5 was set to 40°C. The heat generation time and the cooling time of the semiconductor chip 1 were set to 1 second and 9 seconds, respectively.

[0080] The insulating layer 8 has the same planar shape as the upper surface 5c-1 of the LF connection portion 5c and is in contact with the entire upper surface 5c-1 of the LF connection portion 5c. The thickness t1 of the LF5 was set to 0.5 mm. The height h of the LF rising portion 5b was set to 2.0 mm. The width w1 of the LF joint portion 5a and the width w2 of the LF rising portion 5b were set to 3.0 mm. The width w3 of the LF connection portion 5c was set to 2.5 mm. The semiconductor material of the semiconductor chip 1 was SiC. Regarding the semiconductor module (hereinafter simply referred to as the reference example) having the structure of the semiconductor module 110 (see FIG. 13) according to the reference example, the strain amount of the front surface electrode of the semiconductor chip 101 was calculated under the same simulation conditions as in the embodiment. The reference example had the same structure as the embodiment except for not having the insulating layer 8.

[0081] As shown in FIG. 10, it was confirmed that in the embodiment, as compared with the reference example, the strain amount of the front surface electrode of the semiconductor chip 1 in the power cycle test was reduced by about 20%. Therefore, it was confirmed that the power cycle tolerance was improved by the insulating layer 8 and the reliability could be ensured.

[0082] (Verification Example 2) The vertical deformation amounts of the semiconductor chip 1 and its peripheral members in the semiconductor module 10 according to Embodiment 1 were verified. FIG. 11 is a contour diagram showing the results of simulating the state of deformation due to thermal stress of the members in the semiconductor modules of the embodiment and the reference example. FIG. 11 shows the vertical deformation amounts of the semiconductor chips 1, 101 and their peripheral members (bonding members 13, 113 and LF5, 105) in the semiconductor modules 10, 110 when performing simulations that simulated the power cycle test under the above-described simulation conditions for the above-described embodiment and reference example, respectively.

[0083] As shown in FIG. 11, in the reference example, the deformation amount in the vertical direction was almost the same in almost the entire area of LF5. On the other hand, in the embodiment, compared with the reference example, the deformation amount was the largest at the upper end 5b-1 of the LF rising portion 5b. By providing the insulating layer 8, the supporting force of the sealing material 6 on the LF rising portion 5b was reduced, and when the LF rising portion 5b was pushed upward by the thermally expanded semiconductor chip 1, it is presumed that the LF rising portion 5b was more likely to move upward. It is presumed that when the LF rising portion 5b moves upward, the stress concentration point due to the thermal expansion of the semiconductor chip 1 moves to the upper end 5b-1 of the LF rising portion 5b.

[0084] (Verification Example 3) The thickness t2 of the insulating layer 8 was verified. FIG. 12 is a characteristic diagram showing the result of simulating the relationship between the thickness of the insulating layer of the embodiment and the reference example and the strain amount of the front surface electrode of the semiconductor chip. The relationship between the thickness t2 of the insulating layer 8 and the strain amount of the front surface electrode of the semiconductor chip 1 when the simulation was performed by variously changing the thickness t2 of the insulating layer 8 in the above-described embodiment and simulating the power cycle test under the above-described simulation conditions is shown in FIG. 12. In FIG. 12, the simulation result with the thickness t2 = 0 mm of the insulating layer 8 is the strain amount of the front surface electrode of the semiconductor chip 101 of the above-described reference example.

[0085] As shown in FIG. 12, the thicker the thickness t2 of the insulating layer 8, the lower the strain amount of the front surface electrode of the semiconductor chip 1. It is presumed that this is because the thicker the thickness t2 of the insulating layer 8, the lower the supporting force of the sealing material 6 on the LF rising portion 5b.

[0086] In the above, the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present disclosure, and it is applicable when mounting semiconductor chips having various configurations including a front surface electrode on a semiconductor module.

Industrial Applicability

[0087] As described above, the semiconductor module according to the present disclosure is useful for power semiconductor devices used in power supply devices such as power conversion devices and various industrial machines.

Description of Reference Numerals

[0088] 1,101 Semiconductor chip 1a,1b,2a Electrode pads 2,102 Circuit board 3,103 Cooling base 4,104 Case 5,105 Lead frame (LF) 5a,105a LF joint 5b,105b LF rising part 5b-1,105b-1 Upper end of LF rising part 5b-2,105b-2 Lower end of LF rising part 5c,105c LF connecting part 5c-1 Upper surface of LF connecting part 5c-2 Lower surface of LF connecting part 5d Bent part of LF 5e Hook-like part at the lower end of LF rising part 5e-1 Hook-like bent part of hook-like part 6,6a,6b,106 Sealing material 7,107 Recess for accommodating circuit board 8,31,41 Insulating layer 9 Passivation film 9a,9b Openings in passivation film 10,30,40,50,110 Semiconductor module 11~14,111~114 Joining members 21,121 Insulating substrate 22,22a,22b,122,122a,122b Conductive plates 23,123 Metal foil 32 Resin material h Height of LF rising part t1 Thickness of LF t2 Thickness of insulating layer w1 Width of LF joint Width of the rising part of w2 LF Width of the connecting part of w3 LF Length of the insulating layer of w11

Claims

1. A laminated substrate having a conductive plate on its upper surface, a semiconductor chip having a front surface electrode on its front surface and its back surface bonded to the upper surface of the laminated substrate, a lead frame electrically connecting the front surface electrode and the conductive plate, a sealing material for sealing the semiconductor chip, the laminated substrate, and the lead frame, an insulating layer provided on the side opposite to the laminated substrate side of the lead frame and facing the lead frame in the thickness direction of the semiconductor chip, comprising: The semiconductor module is characterized in that the insulating layer is made of an electrical insulating material having a lower elastic modulus than the sealing material.

2. The semiconductor module according to claim 1, wherein the insulating layer faces the entire lead frame.

3. The semiconductor module according to claim 1, wherein the insulating layer is in contact with the lead frame.

4. The semiconductor module according to claim 1, wherein the thickness of the insulating layer is 0.2 mm or more and 0.5 mm or less.

5. The lead frame has a flat bonding portion surface-bonded to the front surface electrode, a flat rising portion that bends and rises from an end of the bonding portion and shares one end with the bonding portion, and a flat connecting portion that shares the other end of the rising portion and bends from the other end of the rising portion to electrically connect the other end of the rising portion and the conductive plate. The semiconductor module according to claim 1, wherein the insulating layer faces the other end of the rising portion in the thickness direction of the semiconductor chip.

6. The semiconductor module according to claim 5, wherein the insulating layer is in contact with the entire surface on the side opposite to the laminated substrate side of the connecting portion.

7. The semiconductor module according to claim 6, wherein the insulating layer extends from the connecting portion along the rising portion to the non-bonding surface opposite to the bonding surface with the front surface electrode of the bonding portion.

8. The semiconductor module according to claim 5, wherein the insulating layer is provided only at the other end of the rising portion.

9. The semiconductor module according to claim 8, further comprising a hook-shaped portion for sandwiching and holding the insulating layer between the other end of the rising portion and the lead frame.

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