Improved architecture for storing and retrieving system data in non-volatile memory system

Abstract

To provide an improved architecture for storing and retrieving system data in a non-volatile memory system.SOLUTION: In a system data architecture, during a read operation, both word lines 601 and 603 are selected. Read currents from non-volatile memory (NVM) cells 801 and 802 are combined at a common bit line 604. The summed current is sensed by a sense amplifier 104 based on a reference current to determine its logic state.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] (Claim of Priority) This application claims the benefit of priority of U.S. Provisional Patent Application No. 63 / 131,624, entitled "Architectures for Storing and Retrieving System Data in a Non-Volatile Memory System", filed on December 29, 2020, and U.S. Patent Application No. 17 / 199,383, entitled "Architectures for Storing and Retrieving System Data in a Non-Volatile Memory System", filed on March 11, 2021.

[0002] (Field of the Invention) Numerous embodiments of an improved architecture for storing and retrieving system data in a non-volatile memory system are disclosed.

Background Art

[0003] Non-volatile memory systems are well-known in the prior art. FIG. 1 shows a prior art non-volatile memory system 100. The non-volatile memory system 100 includes an array 101, a row decoder 102, a column decoder 103, and a sense amplifier 104. The array 101 includes an array of non-volatile memory cells arranged in rows and columns. The row decoder 102 is coupled to each row of non-volatile memory cells in the array 101 and typically enables one or more rows for read, erase, or program operations in response to a received row address. The column decoder 103 is coupled to each column of non-volatile memory cells in the array 101 and typically enables one or more columns for read, erase, or program operations in response to a received column address. When the non-volatile memory cells are flash memory cells, the row decoder 102 is typically coupled to the word lines of each row of cells and the column decoder 103 is typically coupled to the bit lines of each column of cells. The sense amplifier 104 is used during a read operation to sense the value stored in the selected one or more cells.

[0004] Various designs of non-volatile memory cells are known in the prior art. For example, U.S. Patent No. 5,029,130 (the " '130 patent"), which is incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, and a channel region 18 is between the source region 14 and the drain region 16. A floating gate 20 is formed insulated above a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18), and extends over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) is disposed insulated above a second portion of the channel region 18, having a first portion (which controls the conductivity of the second portion of the channel region 18) and a second portion that extends upward above the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16.

[0005] The memory cell 210 is erased by applying a high positive voltage to the word line terminal 22 with respect to the substrate region 12 (in which case electrons are removed from the floating gate), whereby electrons on the floating gate 20 tunnel through an intermediate insulator from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim tunneling.

[0006] The memory cell 210 is programmed by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14 (electrons are supplied to the floating gate). Electrons flow from the drain region 16 toward the source region 14. The electrons are accelerated and heated as they move through the channel region 18 under the gap between the word line terminal 22 and the floating gate 20 and the channel region 18 under the floating gate 20. A portion of the heated electrons will be injected through the gate oxide into the floating gate 20 due to the electrostatic attraction from the floating gate 20 and the reduction of the oxide energy barrier caused by the above attraction.

[0007] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 with respect to the source region 14 (turning on the portion of the channel region 18 under the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel region 18 under the floating gate 20 is also turned on, and current flows through the channel region 18 to the source region 14, which is detected as the erased state, i.e., the "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region under the floating gate is almost or completely turned off, and current does not (or hardly) flow through the channel region 18 to the source region 14, which is detected as the programmed state, i.e., the "0" state.

[0008] Table 1 shows the typical voltage / current ranges that can be applied to the terminals of the memory cell 210 to perform read, erase, and program operations. Table 1: Operation of the flash memory cell 210 in FIG. 3

Table 1

[0009] As another type of flash memory cell, other split-gate memory cell configurations are also known. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 7,868,375, which is hereby incorporated by reference in its entirety for all purposes. Here, all gates are non-floating gates except for the floating gate 20, that is, they are electrically connected or connectable to a voltage source. Programming is performed by injecting hot electrons themselves from the channel region 18 into the floating gate 20. Erasure is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0010] Table 2 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the Flash Memory Cell 310 in FIG. 3

Table 2

[0011] FIG. 4 shows a three-gate memory cell 410, which is another type of flash memory cell. The memory cell 410 is identical to the memory cell 310 in FIG. 3 except that the memory cell 410 does not have a separate control gate. The erase operation (whereby erasure occurs through the use of the erase gate) and the read operation are similar to the operations in FIG. 3 except that no control gate bias is applied. Since the program operation is also performed without a control gate bias, as a result, a higher voltage must be applied to the source line during the program operation to compensate for the lack of the control gate bias.

[0012] Table 3 shows typical voltage / current ranges that can be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 410 of FIG. 4 [Table 3]

[0013] The methods and means described herein can be applied to other non-volatile memory technologies including, but not limited to, FINFET split gate flash or stacked gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapping in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapping in nitride), ReRAM (resistive change memory), PCM (phase change memory), MRAM (magnetoresistive memory), FeRAM (ferroelectric memory), CT (charge trap) memory, CN (carbon nanotube) memory, OTP (one-time programmable with bi-level or multi-level), and CeRAM (strongly correlated electron memory).

[0014] Referring to FIG. 5, a prior art non-volatile memory system 100 may create and maintain a protection region 501 within array 101. The protection region 501 can then be used to store configuration data, trim data, fuses, and other types of data essential to the operation of non-volatile memory system 100, referred to herein as "system data" or "system bits". User data is not stored in the protection region 501 and, optionally, the protection region 501 is not accessible for read, erase, and program operations initiated from a source external to non-volatile memory system 100.

[0015] The data stored in the protection area 501 is important for the accurate functioning of the non-volatile memory system 100. Therefore, the data stored in the protection area 501 requires additional protection from low-probability data loss events such as charge loss, charge movement, read disturbance, radiation-induced soft errors, and other mechanisms that cause changes in the read current / voltage of a very small part of the cells.

[0016] One prior art approach is to store each system bit within the protection area 501 redundantly in two non-volatile memory cells. In one approach, the read currents from the two cells can be summed and compared to a reference value to determine the stored value.

[0017] However, even with redundancy, in some non-volatile memory cell designs, charge loss, charge redistribution, disturbance, or other physical changes in the non-volatile memory cell will, depending on the architecture of the non-volatile memory cell, mainly cause the cell to flip from the "1" state to the "0" state or from the "0" state to the "1" state.

[0018] This can potentially corrupt the system bit. For example, if one of the two non-volatile memory cells flips from the "0" state to the "1" state, the total read current will exceed the reference current and the detected data will flip from "0" to "1".

[0019] What is needed are embodiments for storing important system data in a non-volatile memory array such that the system data is less likely to be corrupted from charge loss, charge redistribution, disturbance effects, or other physical changes in the non-volatile memory cell that cause changes in the read current or voltage, among other things. SUMMARY OF THE INVENTION

[0020] Numerous embodiments of an improved architecture for storing and retrieving system data in a non-volatile memory system are disclosed. Using these embodiments, system data is much less likely to be corrupted due to charge loss, charge redistribution, disturbance effects, and other phenomena that caused data corruption in prior art non-volatile memory systems.

[0021] In one embodiment, a non-volatile memory system includes an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns, a sense amplifier configured to receive currents from a first non-volatile memory cell in a first column of the array during a read operation to indicate a first value stored in the first non-volatile memory cell and from a second non-volatile memory cell in a second column of the array to indicate a second value stored in the second non-volatile memory cell, and a logic circuit configured to receive the first value and the second value from the sense amplifier and generate a data bit output based on the first value and the second value.

[0022] In another embodiment, a non-volatile memory system includes an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns, and a sense amplifier configured to receive a combined current from a first non-volatile memory cell and a second non-volatile memory cell in a selected column of the array during a read operation and generate a data bit output indicating a value based on the combined current.

[0023] In another embodiment, a non-volatile memory system includes an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns, where each row includes a word of non-volatile memory cells and error correction code data calculated from the word. The non-volatile memory system further includes a sense amplifier configured to receive a current from the array during a read operation and output the word and the error correction code data of the word, and an error correction code engine configured to use the error correction code data of the word to correct one or more errors in the word.

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Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0035] Figures 6 to 8 show embodiments particularly suitable for non-volatile memory (NVM) cell design, where due to charge loss, charge redistribution, interference, or other physical or electrical changes in the NVM cell, the cell can be drawn to the "1" state and invert the stored "0" to "1", but does not affect the stored "1".

[0036] Figure 6 shows a system data architecture 600. Each bit of the system data is written to two redundant NVM cells, such as cells 601 and 602, located in the same row accessible by the same word line, such as word line 601, and in different columns accessible by different bit lines, such as bit lines 604 and 605.

[0037] During the read operation, the currents from NVM cells 601 and 602 are simultaneously but independently sensed by sense amplifier 104 relative to a reference current to determine their respective logical states. The data read from the two cells as output by sense amplifier 104 (indicating a first value stored in one of the two NVM cells 601, 602 and a second value stored in the other of the two NVM cells 601, 602) is routed through an AND device 603 (a logic device that performs an AND function, which can be implemented using hardware logic or by firmware executed on a controller or processor) to generate the final system data (indicated by "output").

[0038] If NVM cells 601 and 602 initially store "0" and neither cell has inverted, the output is "0". If NVM cells 601 and 602 initially store "0" and one of the two NVM cells 601, 602 inverts from "0" to "1", the output of AND device 603 is "0", so the output remains "0". The probability that both NVM cells invert from "0" to "1" is extremely low.

[0039] When NVM cells 601 and 602 first store a 1, assuming that the underlying NVM cell architecture is of a type where leakage or disturbance will invert a "0" to a "1" but not a "1" to a "0", it is expected that both NVM cells 601 and 602 will still store a "1". Bit lines 606 and word line 603 are shown for completeness.

[0040] FIG. 7 shows a system data architecture 700. Each bit of system data is written to two redundant NVM cells. Each of the redundant NVM cells can be located in any row and any column. That is, there is no restriction on where the redundant NVM cells can be placed, and the redundant NVM cells do not need to be located in the same row or column or adjacent rows or columns. In this embodiment, a pair of redundant bits are stored in NVM cell 701 accessible by word line 601 and bit line 604, and NVM cell 702 accessible by word line 603 and bit line 606. Bit line 602 and word line 605 are shown for completeness.

[0041] During a read operation, the currents from NVM cells 701 and 702 are independently sensed by sense amplifier 104 relative to a reference current to determine their respective logical states. The read data from the two NVM cells output by sense amplifier 104 (indicating a first value stored in one of the two NVM cells 701, 702 and a second value stored in the other of the two NVM cells 701, 702) is processed by AND device 603 (a logic device that performs an AND function, which can be implemented using hardware logic or by firmware executed on a controller or processor) to generate the final system data (indicated by "output").

[0042] When NVM cells 701 and 702 initially store "0" and neither cell has been inverted, the output is "0". When NVM cells 701 and 702 initially store "0" and one of the two NVM cells 701, 702 is inverted from "0" to "1", since the output of the AND operation is "0", the final data still becomes "0". The probability that both NVM cells 701 and 702 are inverted from "0" to "1" is extremely low.

[0043] When NVM cells 701 and 702 initially store "1", it is assumed that the underlying NVM cell architecture is of the type where leakage, disturbance, or other changes invert "0" to "1" but do not invert "1" to "0", so it is expected that both still store "1".

[0044] Figure 8 shows a system data architecture 800. Each bit of the system data is written to two redundant NVM cells, such as NVM cells 801 and 802, which are located in the same column accessible by the same bit line, such as bit line 604, but in different rows accessible by different word lines, such as word lines 601 and 603. Bit lines 605, 606 and word line 602 are shown for completeness.

[0045] During the read operation, both word lines 601 and 603 are selected. The read currents from NVM cells 801 and 802 are combined at the common bit line 604. The combined current is sensed by sense amplifier 104 with respect to a reference current to determine its logical state. The reference current is set at a level within a range that is higher than the sum of the typical 0-state read current of the NVM cell and the upper limit of the floating gate (FG) read current (in the case of an NVM cell using charge storage in a polysilicon FG, the upper limit refers to the upper limit of the range of the neutral FG read current of the NVM cells in the array), or higher than the sum of the typical 0-state read current and the saturation point of the 0-state read current shift (in the case of an NVM cell using other memory mechanisms). The reference level is also lower than twice the lower limit of the read current of a 1-state cell read immediately after being set to the 1 state.

[0046] During the production test screening of a device according to system data architecture 800, a read using a reference current within the above range is performed over protection region 501 to ensure that two NVM cells 801 and 802 can be sufficiently erased to ensure that the combined read current exceeds the reference level under worst-case erase and read conditions, where "worst-case" can vary by technology and is the weakest erase and read conditions over a specific process / temperature / voltage range. These conditions are typically captured during testing.

[0047] If the data stored in the selected NVM cells 801 and 802 is "0" and neither NVM cell is inverted, the final data output by sense amplifier 104 (indicated by "output") is still "0". If the data stored in the selected NVM cells 801 and 802 is "0" and one of the two NVM cells 801, 802 is inverted from "0" to "1", the combined read current of the two NVM cells saturates before exceeding the reference current, and the final data still becomes "0" by sense amplifier 104. The probability that both NVM cells 801, 802 are inverted from "0" to "1" is extremely low.

[0048] When NVM cells 801 and 802 first store a "1", the underlying NVM cell architecture is presumed to be of a type where leakage, interference, or other changes can invert a "0" to a "1" but not a "1" to a "0", so both NVM cells 801 and 802 are expected to still store a "1".

[0049] Figures 9 - 10 show embodiments particularly suitable for an NVM cell design where charge loss, charge redistribution, or interference can pull the cell towards the "0" state and invert a stored "1" to a "0", but do not affect a stored "0".

[0050] Figure 9 shows a system data architecture 900. Each bit of the system data is written to two redundant NVM cells, such as cells 901 and 902, which are located in the same row accessible by the same word line, such as word line 601, but in different columns accessible by different bit lines, such as bit lines 604 and 605. Bit line 606 and word lines 602, 603 are shown for completeness.

[0051] During a read operation, the currents from NVM cells 901 and 902 are simultaneously but independently sensed by sense amplifier 104 relative to a reference current to determine the first value stored in NVM cell 901 and the second value stored in NVM 902. The read data from the two NVM cells output by sense amplifier 104 is processed by an OR device 903 (a logic device that performs an OR function, which can be implemented using hardware logic or firmware executed on a controller or processor) to generate the final system data (indicated by "output").

[0052] If NVM cells 901 and 902 initially store a "1" and neither cell has been inverted, the output is "1". If NVM cells 901 and 902 initially store a "1" and one of the two NVM cells is inverted from "1" to "0", the output of OR device 903 becomes "0", so the final data still becomes "1". The probability that both of NVM cells 901 and 902 are inverted from "1" to "0" is extremely low.

[0053] If NVM cells 901 and 902 initially store a "0", this method is only used in NVM cell architectures where leakage, disturbance, or other changes invert a "1" to a "0" but do not invert a "0", so it is expected that both of NVM cells 901 and 902 still store a "0".

[0054] FIG. 10 shows a system data architecture 1000. Each bit of the system data is written into two redundant NVM cells. Each of the redundant NVM cells can be located in any row and column. That is, there is no restriction on where the NVM cells can be placed, and the NVM cells do not need to be located in the same row or column or adjacent rows or columns.

[0055] In this embodiment, a pair of redundant bits are stored in NVM cell 1001 accessible by word line 601 and bit line 604, and NVM cell 1002 accessible by word line 603 and bit line 606. Bit line 605 and word line 602 are shown for completeness.

[0056] During the read operation, the currents from NVM cells 1001 and 1002 are sensed independently of the reference current by sense amplifier 104 to determine the first value stored in NVM cell 1001 and the second value stored in NVM cell 1002. The read data from the two NVM cells output by sense amplifier 104 is processed by an OR device 903 (a logic device that performs an OR function, which can be implemented using hardware logic or by firmware executed on a controller or processor) to generate the final system data (indicated by "output").

[0057] If NVM cells 1001 and 1002 initially store "1" and neither NVM cell has flipped, the output will be "1". If NVM cells 1001 and 1002 initially store "1" and one of the two NVM cells flips from "1" to "0", the output of OR device 903 will be "0", so the final data will still be "1". The probability that both of NVM cells 1001 and 1002 flip from "1" to "0" is extremely low.

[0058] If NVM cells 1001 and 1002 initially store "0", this method is only used in NVM cell architectures where leakage, disturbance, or other changes flip "1" to "0" but do not flip "0", so it is expected that both of NVM cells 1001 and 1002 still store "0".

[0059] FIG. 11 shows embodiments suitable for any of: (1) an NVM cell design in which a cell can be pulled towards the "0" state by charge loss, charge redistribution, perturbation, or other physical changes to the cell, causing the stored "1" to be inverted to "0", but not affecting the stored "0"; (2) an NVM cell design in which a cell can be pulled towards the "1" state by the aforementioned changes, causing the stored "0" to be inverted to "1", but not affecting the stored "1"; and (3) an NVM cell design in which the NVM cell can be pulled towards either state by the aforementioned changes, which can invert some of the stored "0"s to "1"s but can also invert some of the stored "1"s to "0"s.

[0060] FIG. 11 shows a system data architecture 1100. Here, each word of system data, such as word 1101, is stored in a row along with associated error correction code (ECC) data, such as ECC data 1102. Each system bit is stored in a word and is stored without redundancy. Without exceeding the range, multiple words can be stored in one row, and each word has associated error correction code data.

[0061] Here, the ECC data 1102 is generated for the word 1101 using an error correction code (ECC) such as a Hamming code, or a majority algorithm (where the data is stored in N redundant physical cells and the value of the stored data is considered to be the value indicated by the majority of the N cells), to perform error detection and correction such as a 2-bit error detection and 1-bit error correction scheme. Instead of the ECC data 1102, a parity bit scheme can also be utilized to indicate error detection without correction. When the bit 1101 is read, the entire word 1101 and the ECC data 1102 are read by the sense amplifier 104 and sent to the ECC engine 1103. That is, the sense amplifier 104 receives current from the array and outputs the word and its error correction code data of the word to the ECC engine 1103. If any single bit within the word 1101 is inverted in either direction, the error is successfully detected and / or corrected by the ECC engine 1103. The probability of more than 2-bit inversions is extremely low.

[0062] In one embodiment, the system data architecture 1100 is additionally implemented with redundancy, such as using multiple cells for each system bit, to further enhance reliability such as functional safety for automotive applications. For example, each system bit can be stored in two cells in two rows or two columns as described in the previous embodiments.

[0063] In one embodiment, the ECC engine 1103 is implemented using an external controller or firmware.

[0064] As used herein, it should be noted that both the terms "over" and "on" include both "directly on" (with no intervening material, element, or gap therebetween) and "indirectly on" (with an intervening material, element, or gap therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intervening material, element, or gap therebetween) and "indirectly adjacent" (with an intervening material, element, or gap therebetween), "attached to" includes "directly attached to" (with no intervening material, element, or gap therebetween) and "indirectly attached to" (with an intervening material, element, or gap therebetween), and "electrically coupled" includes "directly electrically coupled" (with no intervening material or element electrically connecting the elements together therebetween) and "indirectly electrically coupled" (with an intervening material or element electrically connecting the elements together therebetween). For example, forming an element "over a substrate" can include forming the element directly on the substrate without an intervening material / element therebetween and forming the element indirectly on the substrate with one or more intervening materials / elements therebetween.

Claims

1. A non-volatile memory system comprising: an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; a sense amplifier configured to receive currents from a first non-volatile memory cell in a first column of the array during a read operation to indicate a first value stored in the first non-volatile memory cell, and to receive currents from a second non-volatile memory cell in a second column of the array to indicate a second value stored in the second non-volatile memory cell; a logic circuit for receiving the indicated first value and the indicated second value from the sense amplifier and generating a data bit output based on the indicated first value and the indicated second value.

2. The non-volatile memory system according to claim 1, wherein the first non-volatile memory cell and the second non-volatile memory cell are in the same row within the array.

3. The non-volatile memory system according to claim 2, wherein the logic circuit performs an AND operation on the indicated first value and the indicated second value to generate the data bit output.

4. The non-volatile memory system according to claim 2, wherein the logic circuit performs an OR operation on the indicated first value and the indicated second value to generate the data bit output.

5. The non-volatile memory system according to claim 1, wherein the first non-volatile memory cell and the second non-volatile memory cell are in different rows within the array.

6. The non-volatile memory system according to claim 5, wherein the logic circuit performs an AND operation on the indicated first value and the indicated second value to generate the data bit output.

7. The non-volatile memory system according to claim 5, wherein the logic circuit performs an OR operation on the indicated first value and the indicated second value to generate the data bit output.

8. A non-volatile memory system comprising: an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns; a sense amplifier configured to receive a combined current from a first non-volatile memory cell and a second non-volatile memory cell in a selected column of the array during a read operation and generate a data bit output indicating a value based on the combined current.

9. A non-volatile memory system, an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns, each row comprising a word of the non-volatile memory cells and error correction code data calculated from the word, an array of non-volatile memory cells; a sense amplifier configured to receive a current from the array and output a word and error correction code data of the word during a read operation; an error correction code engine for correcting one or more errors in the word using the error correction code data of the word, a non-volatile memory system.

10. The non-volatile memory system according to claim 9, wherein the error correction code data of the word is generated using a Hamming code.

11. The non-volatile memory system according to claim 9, wherein the error correction code data of the word is generated using a majority decision algorithm.

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