Wiring board

Abstract

To provide a wiring board that has high adhesion between a board and a wiring.SOLUTION: A wiring board 100 includes: a substrate 102 containing a first element; a diffusion layer 106 in contact with the substrate and containing a first metal element; and a first metal film 104 in contact with the diffusion layer and containing a second metal element. The diffusion layer has a region containing at least the first element and the first metal element, and a region containing the first metal element and the second metal element. The concentration of the second metal element in the diffusion layer may decrease as it approaches the substrate in the thickness direction. The concentration of the first element in the diffusion layer may decrease as it approaches the first metal film in the thickness direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a wiring board in which wirings are formed on a substrate, a method for manufacturing the wiring board, and a semiconductor device including the wiring board.

Background Art

[0002] An electronic device usually uses a basic structure including a substrate and wirings provided thereon (hereinafter referred to as a wiring board). Such a wiring board not only functions as a semiconductor device itself but is also widely applied as a substrate for electrically connecting various electronic components or as a substrate (interposer) for mounting a semiconductor device on an electronic device. Various methods for providing wirings on a substrate have been developed. For example, in the methods disclosed in Patent Documents 1 and 2, a film containing a metal oxide is provided between an insulating substrate and the wirings, thereby improving the adhesion between the substrate and the wirings.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] One of the problems of the present disclosure is to provide a wiring board and a method for manufacturing the same. For example, one of the problems of the present disclosure is to provide a wiring board having high adhesion between a substrate and wirings and a method for manufacturing the same. Alternatively, one of the problems of the present disclosure is to provide a semiconductor device having this wiring board.

Means for Solving the Problems

[0005] One embodiment of the present disclosure is a wiring board. This wiring board has a substrate including a first element, a diffusion layer in contact with the substrate and including a first metal element, and a first metal film in contact with the diffusion layer and including a second metal element. The diffusion layer has a region including at least the first element and the first metal element and a region including the first metal element and the second metal element.

[0006] One embodiment of the present disclosure is a method for manufacturing a wiring board. This manufacturing method includes forming a first intermediate layer including an oxide of a first metal element on a substrate including a first element, converting the first intermediate layer into a second intermediate layer by diffusing the first element into the first intermediate layer, forming a first metal film including a second metal element on the second intermediate layer, and converting the second intermediate layer into a diffusion layer by diffusing the second metal element into the second intermediate layer.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings and the like. However, the present disclosure can be implemented in various modes without departing from the gist thereof, and is not to be construed as being limited to the description of the embodiments exemplified below.

[0009] The drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect for clearer explanation, but this is merely an example and does not limit the interpretation of the present disclosure. In this specification and each figure, elements having the same functions as those described with respect to the previously shown figures may be denoted by the same reference numerals, and redundant explanations may be omitted.

[0010] In this specification and the claims, when expressing the aspect of disposing another structure on or under a certain structure, when simply denoted as "on" or "under", unless otherwise specified, it includes both the case where another structure is disposed directly on or under so as to be in contact with a certain structure, and the case where another structure is disposed above or directly under a certain structure with still another structure interposed therebetween.

[0011] In this specification and the claims, the expression "a certain structure is exposed from another structure" means a mode in which a part of a certain structure is not covered by another structure, and the part not covered by this other structure also includes a mode in which it is covered by yet another structure.

[0012] (First Embodiment) In this embodiment, a wiring board 100 according to one of the embodiments of the present disclosure will be described.

[0013] 1. Basic Structure A cross-sectional schematic view of the wiring board 100 is shown in FIG. 1(A). The wiring board 100 includes a substrate 102, a diffusion layer 106 located on the substrate 102 and in contact with the substrate 102, and a first metal film 104 located on the diffusion layer 106 and in contact with the diffusion layer 106. The wiring board 100 may further include a second metal film 108 located on the first metal film 104 and in contact with the first metal film 104 in an arbitrary configuration.

[0014] The substrate 102 contains a first element. Here, the first element is selected from elements other than oxygen and is an element included in the main component of the substrate 102. In this specification and the claims, the main component of a certain configuration is a component that occupies 90% by weight or more of that configuration. Examples of the substrate 102 include a glass substrate, a quartz substrate, a semiconductor substrate including a semiconductor such as silicon, germanium, gallium arsenide, or gallium nitride, a ceramic substrate including a ceramic such as alumina or zirconia, and a substrate including a single crystal metal oxide such as a sapphire substrate. In the case of a substrate having glass as the main component, a resin may be compounded. When using the above-described substrates, the first element is selected from silicon, germanium, aluminum, zirconium, arsenic, nitrogen, and the like.

[0015] Among the above-described substrates, a glass substrate is preferable when the wiring board 100 is used as an interposer of a semiconductor device because it can be obtained at low cost and exhibits excellent insulation properties. Examples of the glass included in the glass substrate include soda-lime glass, fluoride glass, phosphate glass, and borate glass.

[0016] There is no restriction on the roughness of the surface of the substrate 102, and it may be, for example, 0.1 nm or more, 1 nm or more, 5 nm or more. The roughness of the surface of the substrate 102 may be 200 nm or less, 100 nm or less, or 50 nm or less. The roughness of the surface of the substrate 102 may be 0.1 nm or more and 200 nm or less, 1 nm or more and 100 nm or less, 5 nm or more and 50 nm or less. The surface roughness may be measured, for example, using an optical interference microscope. When a wiring with a relatively small thickness is provided on the substrate 102, the surface roughness of the substrate 102 is reflected on its surface. However, by adjusting the surface roughness of the substrate 102 within the above-described range, an increase in the surface roughness of the wiring is also suppressed. Therefore, when the wiring substrate 100 is applied to a high-frequency circuit substrate, transmission loss can be reduced. Further, when the wiring is processed by photolithography, scattering of light from the exposure machine can be suppressed, and it is possible to prevent the fine processing of the wiring from being hindered.

[0017] Here, the surface roughness can be evaluated by the arithmetic mean roughness Ra, which is a parameter represented by the following formula. In this formula, L is the measurement length on the substrate 102 that is the evaluation target, and f(x) is the height when the measurement length direction is x. Ra is the average of the absolute values of the heights in the measurement length divided by the measurement length.

Equation

[0018] An example of the method for measuring the arithmetic mean roughness Ra is as follows. First, a plurality of arbitrary measurement regions on the substrate 102 are selected. The size of the measurement region may be, for example, a rectangle of 0.30 mm × 0.22 mm. For example, five locations at the four corners and the center on the substrate 102 may be selected as the measurement regions. Next, any two points are set in each of the plurality of regions. The distance between these two points is 0.1 mm, which corresponds to the measurement length L. The arithmetic mean roughness Ra between these two points is measured, and the average of the arithmetic mean roughness Ra obtained in the plurality of measurement regions is adopted as the surface roughness of the substrate 102. For example, when five locations at the four corners and the center on the substrate 102 are selected as the measurement regions, the average of the five measurement results becomes the surface roughness of the substrate 102. Note that a plurality of measurements may be performed in each measurement region, and the average may be adopted as the arithmetic mean roughness Ra in one measurement region. The arithmetic mean roughness Ra can be measured, for example, using a 3D optical profiler (such as the 3D optical profiler Zygo New View 5000 manufactured by Zygo Corporation) using a white interferometer.

[0019] The first metal film 104 contains a zero-valent metal element (the second metal element) and can function as a wiring of the wiring substrate 100 or as a seed layer for forming various wirings (not shown) provided on the second metal film 108 or the wiring substrate 100 by an electrolytic plating method. Examples of the second metal element include copper, titanium, chromium, nickel, gold, and the like. There is no restriction on the thickness of the first metal film 104, and it can be, for example, 0.5 μm or more, 1 μm or more, or 5 μm or more, and 50 μm or less, 30 μm or less, or 20 μm or less. The thickness of the first metal film 104 may be 0.5 μm or more and 50 μm or less, 1 μm or more and 30 μm or less, or 5 μm or more and 20 μm or less. By setting the thickness of the first metal film 104 within this range, it is possible to ensure sufficient conductivity as a wiring. Also, for example, even when the first metal film 104 is formed by a plating method, it can be formed in a short time, and even when the first metal film 104 is formed by photolithography, fine processing can be easily performed.

[0020] The diffusion layer 106 has a function of firmly adhering the first metal film 104 to the substrate 102, and is thus also called an adhesion layer. The diffusion layer 106 is formed by the interdiffusion of an intermediate layer provided between the first metal film 104 and the substrate 102. The intermediate layer contains a first metal element. For example, the intermediate layer contains an oxide or a nitride of the first metal, and examples of the first metal include zinc, titanium, zirconium, aluminum, tin, and the like. The region containing the first metal in the intermediate layer is defined as the diffusion layer 106. The thickness of the diffusion layer 106 may be 1 nm or more. Thereby, the diffusion layer 106 can follow the surface roughness of the substrate 102, ensuring high adhesion between the first metal film 104 and the substrate 102, and at the same time, the first metal film 104 can be microfabricated. The thickness of the diffusion layer 106 may be 1 μm or less, 100 nm or less, 20 nm or less, or 10 nm or less. The thickness of the diffusion layer 106 may be 1 nm or more and 1 μm or less, 1 nm or more and 100 nm or less, 1 nm or more and 20 nm or less, or 1 nm or more and 10 nm or less. Thereby, the diffusion layer 106 can be formed in a short time, and no etching residue remains on the substrate 102 during processing such as etching, and reliable insulation between adjacent wirings can be ensured. For example, when the arithmetic mean roughness Ra of the substrate 102 is 5 nm, the thickness of the diffusion layer 106 may be set in the range of 10 nm or more and 20 nm or less.

[0021] 2. Composition of the Diffusion Layer In addition to the first metal element, the diffusion layer 106 further contains a first element contained in the substrate 102 and a second metal element contained in the first metal film 104. More specifically, the diffusion layer 106 includes at least one of a region where the first element, the first metal element, and the second metal element coexist, a region where the first metal element and the first element coexist, and a region where the first metal element and the second metal element coexist. For example, the diffusion layer 106 may have a region containing the first metal element and the first element and a region containing the first metal element and the second metal element.

[0022] Therefore, the thickness of the diffusion layer 106 does not necessarily match the thickness of the intermediate layer, and can be defined as the thickness of the portion where at least one of the above three regions exists. In this case, the thickness can be measured by energy dispersive X-ray (EDX) analysis. Specifically, a sample with at least the diffusion layer 106 and the first metal film 104 disposed on the substrate 102 is processed using a focused ion beam (FIB) to expose the cross section, an electron beam is irradiated from the substrate 102 side so as to scan the interface between the layers, and characteristic X-rays are detected using a Si drift detector or the like. The atomic composition ratio (atomic%) of each element is obtained based on the intensity of the characteristic X-rays. Thereby, the element distribution in the depth direction is obtained and the above regions are specified. The thickness of the diffusion layer 106 can be obtained by calculating the thickness of the portion where at least one of these regions exists.

[0023] FIG. 1(B) schematically shows the concentration profiles in the thickness direction of the wiring substrate 100 of the first element, the first metal element, and the second metal element. Hereinafter, in FIGS. 1(B) to 5(B), the vertical axis represents the normalized element concentration (that is, the number of atoms of the first element, the first metal element, and the second metal element per unit volume), and the horizontal axis represents the depth of the wiring substrate 100. The depth is the distance from the upper surface of the first metal film 104 in the direction toward the substrate 102 along the normal line of the upper surface of the first metal film 104.

[0024] As shown in FIG. 1(B), the concentration 102a of the first element decreases as it approaches the first metal film 104 from the interface 103 between the substrate 102 and the diffusion layer 106 in the thickness direction. Similarly, the concentration 104a of the second metal element decreases as it approaches the substrate 102 from the interface 105 between the diffusion layer 106 and the first metal film 104 in the thickness direction. These concentration changes may be continuous. Here, the interface 103 is located between a region where the first metal element is absent or substantially undetectable and a region where the first metal element is present or detectable, and is a surface closer to the substrate 102 than the first metal film 104. The interface 105 is located between a region where the first metal element is absent or substantially undetectable and a region where the first metal element is present or detectable, and is a surface closer to the first metal film 104 than the substrate 102 (see FIG. 1(B)). The region between these interfaces 103 and 105 is the diffusion layer 106, and in the diffusion layer 106, the plot of the concentration 106a of the first metal element against the depth gives at least one peak (FIG. 1(B)).

[0025] Therefore, in the diffusion layer 106, the plot of the concentration 104a of the second metal element against the depth of the wiring substrate 100 (the dashed-dotted line in FIG. 1(B)) intersects the plot of the first element against the depth (the dashed line in FIG. 1(B)). Note that the concentration 102a of the first element, the concentration 106a of the first metal element, and the concentration 104a of the second metal element can be measured by, for example, EDX analysis or the like.

[0026] In the example shown in FIG. 1(B), the concentration 104a of the second metal element decreases as it approaches the substrate 102 within the diffusion layer 106 and becomes substantially undetectable at the interface 103. Similarly, the concentration 102a of the first element decreases as it approaches the first metal film 104 within the diffusion layer 106 and becomes substantially undetectable at the interface 105. In other words, the first element, the first metal element, and the second metal element coexist throughout the diffusion layer 106.

[0027] The concentration profiles of the first element and the second metal element in the diffusion layer 106 are not limited to those shown in FIG. 1(B). For example, as shown in FIG. 2(A), the diffusion layer 106 may have a region 106b on the interface 105 side where the first element is absent or substantially undetectable. Alternatively, as shown in FIG. 2(B), the diffusion layer 106 may have a region 106c on the interface 103 side where the second metal element is absent or substantially undetectable.

[0028] Alternatively, as shown in FIG. 3(A), the second metal element may be included not only in the diffusion layer 106 but also in the substrate 102. In this case, the concentration 104a of the second metal element in the substrate 102 decreases as it moves away from the interface 103. Conversely, the first element may be included not only in the diffusion layer 106 but also in the first metal film 104 (FIG. 3(B)). In this case, the concentration 102a of the first element in the first metal film 104 decreases as it moves away from the interface 105.

[0029] The diffusion layer 106 may be configured such that the above-described concentration profiles are combined. For example, as shown in FIG. 4(A), the diffusion layer 106 may have both the region 106b and the region 106c on the interface 105 side and the interface 103 side, respectively. In this case, the region where the first element, the first metal element, and the second metal element coexist in the diffusion layer 106 is sandwiched between the regions 106b and 106c.

[0030] Alternatively, as shown in FIG. 4(B), the diffusion layer 106 may have the region 106c, and the first element may be included not only in the diffusion layer 106 but also in the first metal film 104. Conversely, as shown in FIG. 5(A), the diffusion layer 106 may have the region 106b, and the second metal element may be included not only in the diffusion layer 106 but also in the substrate 102. Alternatively, as shown in FIG. 5(B), the first element may be included not only in the diffusion layer 106 but also in the first metal film 104, and the second metal element may be included not only in the diffusion layer 106 but also in the substrate 102.

[0031] Regardless of the concentration profile, in the diffusion layer 106, the plot of the concentration 104a of the second metal element against the depth of the wiring substrate 100 intersects the plot of the concentration of the first element against the depth. Therefore, in any region of the diffusion layer 106, in addition to the first metal element, at least one of the first element and the second metal element is included, and there is no region where the first metal element is included but neither the first element nor the second metal element is included.

[0032] 3. Modification As shown in FIG. 6(A), the substrate 102 of the wiring substrate 100 may have a through hole 110. In this case, the diffusion layer 106 and the first metal film 104 are provided so as to cover the upper and lower surfaces of the substrate 102 and the side wall of the through hole 110. The second metal film 108 provided as an arbitrary configuration may also be arranged so as to cover the upper and lower surfaces of the substrate 102 and the side wall of the through hole 110. When the entire through hole 110 is not blocked by the first metal film 104 or the second metal film 108, a filler 112 may be formed so as to fill the through hole 110. Examples of the filler 112 include organic compounds such as epoxy resin, acrylic resin, polyimide, polyamide, and polyester. Inorganic materials such as silicon oxide may be mixed in the organic compound. Alternatively, as shown in FIG. 6(B), the second metal film 108 or the first metal film 104 may be provided so as to block the through hole 110. As will be described later, the first metal film 104 or the laminate of the first metal film 104 and the second metal film 108 can function as a through wiring for electrically connecting various elements and semiconductor devices mounted on the substrate 102.

[0033] In the wiring board 100 having the above-described configuration, as experimentally proven in the examples, a large adhesive force is obtained between the substrate 102 and the first metal film 104 due to the presence of the diffusion layer 106. Further, since there is substantially no region where the oxide of the first element exists alone in the diffusion layer 106, the diffusion layer 106 has higher etching resistance compared to a film having a region consisting essentially of only the oxide of the first element. For this reason, the diffusion layer 106 exhibits an etching rate comparable to that of the first metal film 104, and when the first metal film 104 is etched, etching (side etching) of the diffusion layer 106 located under the first metal film 104 is less likely to occur. In particular, when the diffusion layer 106 has a region where the first element, the first metal element, and the second metal element coexist, since the intermediate layer does not exist alone, such side etching is prevented, and a high adhesive force can be exhibited. As a result, the phenomenon of the first metal film 104 peeling off from the substrate 102 can be effectively suppressed, and a highly reliable wiring board and a semiconductor device including the same can be provided.

[0034] (Second Embodiment) In this embodiment, a method for manufacturing the wiring board 100 described in the first embodiment will be described. Explanation of configurations that are the same as or similar to those described in the first embodiment may be omitted.

[0035] First, a first intermediate layer 120 serving as a precursor of the diffusion layer 106 is formed on the substrate 102-1 (FIG. 7, S1). The first intermediate layer 120 contains an oxide of a first element and is formed by a physical vapor deposition (PVD) method such as sputtering, electron beam evaporation, or vacuum evaporation, or a sol-gel method. When using the sol-gel method, metal alkoxides such as tetraethyl zinc, tetraethoxytitanium, and tetraethoxyzirconium are used as raw materials, and a solution or mixture containing these is applied onto the substrate 102-1 by a spin coating method, dip coating method, printing method, etc. Then, the first intermediate layer 120 is formed by hydrolyzing the metal alkoxide. The thickness of the first intermediate layer 120 may be 5 nm or more, and may be 20 nm or 15 nm or less. The thickness of the first intermediate layer 120 may also be 5 nm or more and 20 nm or less, or 5 nm or more and 15 nm or less.

[0036] The thickness of the intermediate layer can be measured by a thin film calibration curve method. Specifically, first, a metal thin film having a known thickness and containing the metal included in the intermediate layer 120 is used as a standard sample, and the fluorescent X-ray intensity obtained by irradiating this with X-rays is measured. A plurality of samples with different thicknesses are used to create a calibration curve showing the relationship between the thickness and the fluorescent X-ray intensity. Next, the same measurement is performed on the intermediate layer 120 formed on the substrate 102, and the thickness is estimated using the calibration curve from the obtained fluorescent X-ray intensity. Also in this measurement, the measurement is performed in a plurality of regions of the intermediate layer 120, and the value obtained by averaging the thicknesses obtained in each region can be adopted as the thickness of the intermediate layer 120. As the plurality of regions, for example, five regions at the four corners and the center of the substrate 102 can be selected.

[0037] As an example of the measuring device, a fluorescent X-ray analyzer SFT9450 manufactured by Seiko Instruments, which is equipped with both a semiconductor detector and a proportional counter as detectors and has a 0.1 mm diameter collimator, can be mentioned. Using this device, the thickness of the intermediate layer 120 is measured according to the method described above under the conditions of a tube current of 1500 μA and a measurement time of 30 seconds.

[0038] Thereafter, heat treatment is performed on the substrate 102-1 and the first intermediate layer 120 formed thereon to diffuse the first element contained in the substrate 102-1 into the first intermediate layer 120. The heat treatment can be carried out at a temperature, for example, of 100 °C or higher, 200 °C or higher, 250 °C or higher, or 350 °C or higher, and can be set within a temperature range of 700 °C or lower, 600 °C or lower, or 550 °C or lower. This temperature range may also be 100 °C or higher and 700 °C or lower, 200 °C or higher and 700 °C or lower, 250 °C or higher and 600 °C or lower, or 350 °C or higher and 550 °C or lower. Depending on the heating temperature, the heating time can be, for example, 10 minutes or longer, 15 minutes or longer, or 30 minutes or longer, and can be 5 hours or shorter, or 2 hours or shorter. A typical heating time is 1 hour. The heating time may also be 10 minutes or longer and 5 hours or shorter, 15 minutes or longer and 5 hours or shorter, or 30 minutes or longer and 2 hours or shorter. When heating at a temperature higher than the heat-resistant temperature (glass transition temperature or melting point) of the substrate 102, it is preferable to perform the heat treatment in a short time of about 1 second to 30 seconds. By this heat treatment, the first intermediate layer 120 is converted into a second intermediate layer 122 containing a first metal element and the first element (FIG. 7, S2). At least a part of the first metal element exists as an oxide. The substrate 102-1 and the first intermediate layer 120 are each converted into a substrate 102-2 and a second intermediate layer 122 by mutual diffusion.

[0039] Subsequently, a metal film 104-1 is formed on the second intermediate layer 122. The second intermediate layer 122 may be formed, for example, by an electroless plating method, a sputtering method, a chemical vapor deposition (CVD) method including a metal-organic chemical vapor deposition (MOCVD) method, a physical vapor deposition (PVD) method such as vacuum evaporation or electron beam evaporation. The temperature at this time is room temperature (20 °C or higher and 25 °C or lower) or room temperature or higher, and can be carried out at a temperature of 100 °C or lower or 50 °C or lower (FIG. 7, S3). The temperature at the time of forming the metal film 104-1 may also be room temperature or higher and 100 °C or lower, or room temperature or higher and 50 °C or lower.

[0040] Thereafter, heat treatment is performed again to diffuse the first metal contained in the metal film 104-1 into the second intermediate layer 122. The temperature and time of the heat treatment can be appropriately selected from the ranges described above. At this time, the first element contained in the substrate 102 may further diffuse into the second intermediate layer 122. By this heat treatment, the second intermediate layer 122 is converted into a diffusion layer 106 having the concentration profile described in the first embodiment (FIG. 7, S4). Also, the metal film 104-1 after interdiffusion with the second intermediate layer 122 is designated as the first metal film 104. Although not shown, a second metal film 108 may be formed on the first metal film 104. The second metal film 108 can be formed by a sputtering method, a CVD method, a PVD method, or the like. Alternatively, the first metal film 104 may be used as a seed layer, and the second metal film 108 may be formed by supplying power to the first metal film 104.

[0041] When manufacturing a wiring substrate 100 having a through hole 110, first, a through hole 110 is provided in the substrate 102 (FIG. 8, S10). The through hole 110 may be formed by etching such as plasma etching or wet etching, laser irradiation, or mechanical processing such as sandblasting or ultrasonic drilling. If necessary, after forming the through hole 110, the substrate 102 may be treated with hydrofluoric acid to planarize the upper surface, the lower surface, and the side walls of the through hole 110 of the substrate 102.

[0042] After forming the through hole 110, a first intermediate layer 120 is formed so as to cover the upper surface, the lower surface, and the side walls of the through hole 110 of the substrate 102 (FIG. 8, S11). Thereafter, the first intermediate layer 120 is converted into a second intermediate layer 122 by the heat treatment described above (FIG. 8, S12), and a metal film 104-1 is formed on the second intermediate layer 122 (FIG. 8, S13). Thereafter, the heat treatment described above is performed to convert the second intermediate layer 122 into a diffusion layer 106 (FIG. 9, S14).

[0043] Thereafter, a second metal film 108 is formed on a part of the upper surface and the lower surface of the substrate 102. For example, as shown in S15 of FIG. 9, a resist mask 124 is provided on the first metal film 104 so as to cover the region where the second metal film 108 is not provided. The resist mask 124 may be formed by applying and curing a liquid resist. However, since the substrate 102 has the through holes 110, the resist mask 124 can be efficiently formed by attaching a film-shaped resist to the upper surface and the lower surface of the substrate 102 and then performing exposure and development.

[0044] Thereafter, power is supplied to the first metal film 104 to perform electrolytic plating. As a result, a second metal film 108 is formed on the first metal film 104 exposed from the resist mask 124 (FIG. 9, S16). Thereafter, the resist mask 124 is removed (FIG. 10, S17), and the first metal film 104 and the diffusion layer 106 exposed from the second metal film 108 are removed by etching (FIG. 10, S18). The etching can be performed using an etchant containing an acid such as sulfuric acid. Through the above process, a wiring board 100 having the through holes 110 can be manufactured. Although detailed description is omitted, the through holes 110 may be formed after forming the first metal film 104 or after forming the second metal film 108.

[0045] As described above, since the diffusion layer 106 of the present disclosure exhibits an etching rate similar to that of the first metal film 104, side etching of the diffusion layer 106 does not occur or is very slow even in the etching process (S18) of the first metal film 104. Therefore, a sufficient contact area can be provided between the first metal film 104 and the substrate 102 through the diffusion layer 106. As a result, peeling of the first metal film 104 and the second metal film 108 can be effectively prevented.

[0046] (Third Embodiment) In this embodiment, a semiconductor device using the wiring board 100 described in the first and second embodiments will be described. Here, a semiconductor device using the wiring board 100 obtained in step S18 of FIG. 10 will be described as a representative example.

[0047] The semiconductor device 130 shown in FIG. 11 has a main substrate 132 and a plurality of wiring substrates 100 (wiring substrates 100-1, 100-2, 100-3) stacked thereon. The number of wiring substrates 100 is not limited and is determined according to the performance required for the semiconductor device 130. Various semiconductor chips (memory devices, central processing units) and semiconductor elements (such as microelectromechanical systems (MEMS)) are connected to the main substrate 132. FIG. 11 shows an example in which a central processing unit 133 is installed on the main substrate 132. As described in the first embodiment, the wiring substrate 100 functions as a through-wiring and has a second metal film 108 and a first metal film 104 (hereinafter, these are collectively referred to as connection wiring 134) provided on the upper and lower surfaces of the substrate 102. The connection wiring 134 contributes to the vertical electrical connection in the semiconductor device 130. The connection wiring 134 of the lowermost wiring substrate 100-1 is electrically connected to a terminal 138 provided on the main substrate 132 via a bump 136-1 through a via hole or wiring disposed between the interlayer insulating layers 142, 142. The connection wiring 134 provided on the upper part of the wiring substrate 100-1 is electrically connected to the wiring substrate 100-2 via a bump 136-2 through a via hole or wiring installed between the interlayer insulating layers 139, 140. Similarly, the wiring substrate 100-2 and the wiring substrate 100-3 are also electrically connected via a bump 136-3. The bump 136 contains a metal such as indium, copper, gold, or an alloy such as solder.

[0048] As in the semiconductor device 150 shown in FIG. 12, the stacked wiring substrates 100 may have different sizes and shapes from each other, and the number of wiring substrates 100 stacked on the main substrate 132 may also be different. In the example shown in FIG. 12, two wiring substrates 100-4, 100-5 are stacked in some regions, and three wiring substrates 100-1, 100-2, 100-3 are stacked in some regions.

[0049] The semiconductor device 160 shown in FIG. 13 has a structure in which a plurality of semiconductor chips 162-1 and 162-2 are stacked on the main substrate 132 via the wiring substrate 100. Terminals 164 and 166 are formed on the semiconductor chips 162-1 and 162-2, respectively, and these are electrically connected to the connection wiring 134 of the wiring substrate 100-1 via bumps 168. As an example of the semiconductor chip, the semiconductor chip 162-1 is a drive chip, and the semiconductor chip 162-2 is a memory chip or the like. Thereby, the semiconductor chips 162-1 and 162-2 are electrically connected to each other. Also, the semiconductor chip 162-2 and the main substrate 132 may be electrically connected by wire wiring 170. In FIGS. 11 to 13, the connection wiring 134 is shown as being directly connected to the bumps 136 and 168, but other wirings such as lead wirings may be provided between the bumps 136 and 168 and the connection wiring 134.

Example

[0050] 1. Example 1 In this example, the results of analyzing the elements included in the wiring substrate 100 manufactured according to the manufacturing method described in the second embodiment will be described.

[0051] The structure of the wiring substrate 100 is as shown in FIG. 1(A), and the specific manufacturing method was as follows. A first intermediate layer 120 (thickness: 15 nm) was formed by forming a film containing zinc oxide on a glass substrate (30 cm × 40 cm, thickness: 0.5 mm, surface roughness: 5 nm) by the sol-gel method. Thereafter, heating was performed at 550°C for 1 hour to convert the first intermediate layer 120 into a second intermediate layer 122. Subsequently, an electroless plating method was applied to form a copper film (thickness: 0.5 μm) as a first metal film 104 on the second intermediate layer 122. Thereafter, heating was performed again at 450°C for 1 hour to convert the second intermediate layer 122 into a diffusion layer 106.

[0052] As a comparative example, samples were also prepared in which three substrates with surface roughnesses of 5 nm, 200 nm, and 1 μm (1000 nm) were used, and the first metal film 104 was directly formed on the substrate without forming the first intermediate layer 120. These samples respectively correspond to Samples 8 to 10 in Table 1 described later and are samples without the diffusion layer 106.

[0053] For elemental analysis, after heating, the wiring substrate 100 was processed using FIB to expose the cross-section, and elemental analysis was performed by EDX from the substrate 102 side so as to scan the interface between each layer. The obtained characteristic X-ray intensity was converted into the atomic composition ratio, and the elemental distribution in the depth direction was evaluated. As the measuring device, a transmission electron microscope (manufactured by Hitachi High-Technologies Corporation, model number: HD-2700) equipped with an elemental analyzer was used. An electron beam with an acceleration voltage of 200 kV and a beam diameter of about 0.2 nm was irradiated onto the wiring substrate 100, and the generated characteristic X-rays were detected using a Si drift detector. As the elemental analyzer, EMAX Evolution manufactured by Horiba, Ltd. was used. The energy resolution was about 130 eV, the X-ray extraction angle was 24.8°, and the solid angle was 2.2 sr. The number of sampling points was 100, and each sampling time was 1 second.

[0054] The EDX analysis results are shown in FIG. 14. In FIG. 14, the concentration changes of zinc, silicon, and copper with respect to the depth of the wiring substrate 100 are shown. As shown in FIG. 14, zinc cannot be substantially detected in the region where the depth is from 0 nm to 35 nm and in the region deeper than 50 nm. Therefore, it can be understood that the interface 103 between the substrate 102 and the diffusion layer 106 and the interface 105 between the diffusion layer 106 and the first metal film 104 are located at depths of 35 nm and 50 nm, respectively. It was confirmed that the plot of the concentration of zinc contained in the diffusion layer 106 shows one peak in the diffusion layer 106.

[0055] As can be seen from FIG. 14, the concentration of silicon, which is the first element contained in the substrate 102, decreases as it approaches the first metal film 104 from the interface 103. Similarly, it is understood that the concentration of copper contained in the first metal film 104 also decreases as it approaches the substrate 102 from the interface 105. From the above, it was confirmed that the diffusion layer 106 contains zinc, which is the first metal element, and also contains silicon, which is the first element, and copper, which is the second metal element. Further, in the diffusion layer 106, the concentration plots of silicon and copper with respect to depth intersect each other. From this, it was found that the diffusion layer 106 contains at least one of the first element and the second metal element in addition to the first metal element in any region.

[0056] 2. Example 2 In this example, the results of evaluating the effect of the diffusion layer 106 on the adhesive force between the substrate 102 and the first metal film 104 are shown.

[0057] Power was supplied to the first metal film 104 of the wiring substrate 100 manufactured in Example 1, and a copper film (thickness: 3 μm) was formed as the second metal film 108 by electrolytic plating. In this example, the thickness of the first intermediate layer 120 was 15 nm, the heating temperature after forming the second metal film 108 was changed, and the effect of the diffusion layer 106 was evaluated. Also, samples 8 to 10, that is, wiring substrates without the diffusion layer 106, were also evaluated as comparative examples.

[0058] The effect of the diffusion layer 106 on the adhesiveness between the first metal film 104 and the substrate 102 was evaluated by a tape peel test and an etching test. In the former, an adhesive tape made of polyimide (manufactured by Nitto Denko Corporation, model number: Polyimide Adhesive Tape for Heat Insulation No. 360UL) was attached to the second metal film 108, and then the adhesive tape was peeled off and visually observed to evaluate. In the latter, the wiring substrate 100 was etched, and the presence or absence of peeling of the first metal film 104 and the second metal film 108 during etching was visually confirmed. The etching was performed using 1% ammonium persulfate as an etchant under the conditions of 23°C and 1 minute.

[0059] The results are shown in Table 1. As shown in Table 1, when the diffusion layer 106 having the structure disclosed in the present disclosure is used, if the heating temperature after the formation of the second metal film 108 is 250°C or higher (sample numbers 3 to 7), no peeling was observed in the tape peel test, and it was found that the first metal film 104 and the second metal film 108 remained on the substrate 102. Further, if the heating temperature was 350°C or higher (sample numbers 4 to 7), no peeling was observed in either the tape peel test or the etching test. On the other hand, in the comparative example (sample number 8) without using the diffusion layer 106, that is, when the first intermediate layer 120 was not formed on the substrate 102, peeling was observed in the tape peel test even when the heating temperature after the formation of the second metal film 108 was 450°C. These results clearly show that when the diffusion layer 106 of the present disclosure is not provided, the adhesion between the first metal film 104 and the substrate 102 is small, and the first metal film 104 and the second metal film 108 are easily peeled from the substrate 102, whereas by providing the diffusion layer 106 of the present disclosure, a metal wiring can be formed on the substrate 102 with a strong adhesive force.

[0060] Here, when the surface roughness of the substrate increases, the anchor effect appears, and usually, the adhesion with the metal film formed thereon is improved. However, even when the surface roughness of the substrate 102 was 200 nm, peeling was observed in the tape peel test (sample 9), and it was confirmed from the results of sample 10 that when the diffusion layer 106 was not provided, a rough surface with a surface roughness of 1000 nm was required. However, when a diffusion layer 106 as thick as 1000 nm is provided, microfabrication becomes difficult as described above, and for example, it becomes extremely disadvantageous to form a wiring with a line-space (L / S) of 10 μm / 10 μm. Therefore, by using the diffusion layer 106 of the present disclosure, it becomes possible to form a wiring subjected to microfabrication on a substrate having a surface roughness at a level where the anchor effect is not expected, that is, a substrate with extremely high surface flatness. This contributes to the manufacture of wiring substrates such as high-frequency circuit boards that require high flatness of the wiring.

[0061]

Table 1

[0062] As embodiments of the present disclosure, the above-described embodiments can be implemented in appropriate combination as long as they do not conflict with each other. Also, based on each embodiment, those in which those skilled in the art appropriately add, delete, or change the design of components are included in the scope of the present disclosure as long as they have the gist of the present disclosure.

[0063] Also, other operational effects different from those brought about by the above-described embodiments, which are obvious from the description in this specification or can be easily predicted by those skilled in the art, are naturally understood to be brought about by the present disclosure.

Description of Reference Numerals

[0064] 100: Wiring board, 100-1: Wiring board, 100-2: Wiring board, 100-3: Wiring board, 100-4: Wiring board, 100-5: Wiring board, 102: Substrate, 102-1: Substrate, 102-2: Substrate, 102a: Concentration of the first element, 103: Interface, 104: First metal film, 104-1: Metal film, 104a: Concentration of the second metal element, 105: Interface, 106: Diffusion layer, 106a: Concentration of the first metal element, 106b: Region, 106c: Region, 108: Second metal film, 110: Through hole, 112: Filling material, 120: First intermediate layer, 122: Second intermediate layer, 124: Resist mask, 130: Semiconductor device, 132: Main board, 133: Central processing unit, 134: Connection wiring, 136: Bump, 136-1: Bump, 136-2: Bump, 136-3: Bump, 138: Terminal, 140: Interlayer insulating layer, 141: Interlayer insulating layer, 150: Semiconductor device, 160: Semiconductor device, 162-1: Semiconductor chip, 162-2: Semiconductor chip, 164: Terminal, 166: Terminal, 168: Bump, 170: Wire wiring

Claims

1. A substrate containing silicon, a diffusion layer in contact with the substrate and containing a first metal element, and a first metal film in contact with the diffusion layer and containing a second metal element, wherein the diffusion layer contains silicon, the first metal element, and the second metal element, the substrate has a through hole, a part of the upper surface of the substrate and / or a part of the lower surface of the substrate are exposed from the diffusion layer and the first metal film, a wiring substrate, wherein the diffusion layer and the first metal film cover the side wall of the through hole.

2. The wiring substrate according to claim 1, wherein the first metal element is titanium.

3. further comprising a second metal film located on the first metal film and in contact with the first metal film, the wiring substrate according to claim 1, wherein the second metal film covers the side wall of the through hole.

4. The wiring substrate according to claim 3, wherein a part of the upper surface of the substrate and / or a part of the lower surface of the substrate are exposed from the second metal film.

5. In the diffusion layer, the concentration of the second metal element decreases as it approaches the substrate in the thickness direction, the wiring substrate according to claim 1, wherein the concentration of silicon in the diffusion layer decreases as it approaches the first metal film in the thickness direction.

6. The wiring substrate according to claim 5, wherein in the diffusion layer, there is a region where the plot of the concentration of the second metal element against the thickness of the diffusion layer intersects with the plot of the concentration of silicon against the thickness.

7. The wiring substrate according to claim 1, wherein the second metal element is selected from copper, titanium, chromium, nickel, and gold.

8. The wiring substrate according to claim 1, wherein the first metal element exists as an oxide in the diffusion layer.

9. The wiring substrate according to claim 1, wherein the substrate is selected from a glass substrate, a quartz substrate, a semiconductor substrate, and a ceramic substrate.

10. an insulating layer located on the diffusion layer and the first metal film and having an opening overlapping the through hole, and the wiring substrate according to claim 1, further comprising a first wiring located in the opening.

11. The wiring substrate according to claim 10, further comprising a second wiring electrically connected to the first wiring on the first wiring.

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