Wiring board and method for manufacturing the same

Abstract

To provide a wiring board and a method for manufacturing the same that suppresses variations in amount of reduction in thickness and width of mounting pads.SOLUTION: A wiring board 1 includes: a base having a first surface 3A; a first pad 401 and a second pad 402 for mounting provided on the first surface 3A; a third pad 501 for external connection electrically connected to the first pad 401; a fourth pad 602 for dummy electrically connected to the second pad 402; a first plating layer 231 covering the surface of the third pad 501; and a second plating layer 232 covering the surface of the fourth pad 602. The ionization tendency of the first plating layer 231 and the second plating layer 232 is lower than the ionization tendency of the first pad 401 and the second pad 402.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a wiring board and a method for manufacturing the wiring board.

Background Art

[0002] A wiring board provided with pads for mounting electronic components such as semiconductor elements and pads for wire bonding is known.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional wiring board, during manufacturing, the thickness and width of the mounting pads (wiring) may decrease. Also, the amount of decrease in thickness and width may vary among a plurality of mounting pads. Variations in the amount of decrease in the thickness and width of the mounting pads can lead to a decrease in the stability of the connection of electronic components to the wiring board.

[0005] An object of the present disclosure is to provide a wiring board and a method for manufacturing the wiring board that can suppress variations in the amount of decrease in the thickness and width of mounting pads.

Means for Solving the Problems

[0006] According to one embodiment of the present disclosure, there is provided a wiring board having a base portion with a first surface, a first pad and a second pad for mounting provided on the first surface, a third pad for external connection electrically connected to the first pad, a fourth pad for dummy electrically connected to the second pad, a first plating layer covering the surface of the third pad, and a second plating layer covering the surface of the fourth pad, wherein the ionization tendency of the first plating layer and the second plating layer is lower than the ionization tendency of the first pad and the second pad.

Advantages of the Invention

[0007] According to the disclosed technology, variations in the reduction amounts of the thickness and width of the pads for mounting can be suppressed.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

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Figure 6

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Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Mode for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present disclosure will be specifically described with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and redundant descriptions may be omitted. In the following description, an XYZ orthogonal coordinate system is used, but the coordinate system is defined for the purpose of explanation.

[0010] [Structure of Wiring Board According to Embodiment] First, the structure of the wiring board according to the embodiment will be described. FIG. 1 is a diagram illustrating the layout of the wiring board according to the embodiment. FIG. 2 is a plan view illustrating the wiring board according to the embodiment. FIGS. 3 and 4 are cross-sectional views illustrating the wiring board according to the embodiment. FIG. 2 shows a portion corresponding to one of the plurality of units included in the wiring board. FIG. 3(a) corresponds to a cross-sectional view taken along line IIIa-IIIa in FIG. 2. FIG. 3(b) corresponds to a cross-sectional view taken along line IIIb-IIIb in FIG. 2. FIG. 4(a) corresponds to a cross-sectional view taken along line IVa-IVa in FIG. 2. FIG. 4(b) corresponds to a cross-sectional view taken along line IVb-IVb in FIG. 2.

[0011] As shown in FIG. 1, the wiring board 1 according to the embodiment has a plurality of units 2. For example, 30 units 2 are arranged to form a 5-row and 6-column matrix. There is a cutting region between adjacent units 2, and by fragmenting the wiring board 1 along the cutting region, 30 units 2 each used for a semiconductor device can be obtained. The number of units 2 included in the wiring board 1 is not limited. Hereinafter, mainly one unit 2 will be described with reference to FIGS. 2 to 4.

[0012] As shown in FIGS. 3 and 4, the wiring board 1 according to the embodiment has, for example, a core layer 100, a build-up layer 200 provided on one surface of the core layer 100, and a build-up layer 300 provided on the other surface of the core layer 100. The wiring board 1 may be a coreless board that does not include a core layer.

[0013] In this embodiment, for the sake of convenience, with the core layer 100 as a reference, the build-up layer 200 side (+Z side) is the upper side or one side, and the build-up layer 300 side (-Z side) is the lower side or the other side. Also, the upper surface of each part is one surface or the upper surface, and the lower surface is the other surface or the lower surface. However, the wiring board 1 can be used in an upside-down state or arranged at an arbitrary angle. Also, a plan view means viewing the object from the normal direction of one surface of the core layer 100, and a planar shape means the shape of the object viewed from the normal direction of one surface of the core layer 100.

[0014] The core layer 100 has an insulating base material 111 in which a plurality of through holes 112 are formed, and a conductive layer 113 formed on the inner wall surface of the through holes 112. For example, the material of the base material is glass epoxy or the like, and the material of the conductive layer 113 is copper (Cu) or the like. The core layer 100 may have a filler filled inside the conductive layer 113.

[0015] The build-up layer 200 has wiring layers 210 and 230, an insulating layer 220, and a solder resist layer 240. The build-up layer 300 has wiring layers 310 and 330, an insulating layer 320, and a solder resist layer 340. The insulating layer 220 is provided between the adjacent wiring layers 210 and 230 in the thickness direction (Z-axis direction). The insulating layer 320 is provided between the adjacent wiring layers 310 and 330 in the thickness direction.

[0016] The wiring layer 210 is formed on one surface of the core layer 100. The wiring layer 310 is formed on the other surface of the core layer 100. A part of the wiring layer 210 and a part of the wiring layer 310 are electrically connected to each other by the conductive layer 113. The materials of the wiring layers 210 and 310 are, for example, copper (Cu), copper alloy, or the like. The thicknesses of the wiring layers 210 and 310 are, for example, about 5 μm to 30 μm.

[0017] The insulating layer 220 is formed so as to cover the wiring layer 210 on one surface of the core layer 100. The material of the insulating layer 220 is, for example, an insulating resin mainly composed of an epoxy-based resin or a polyimide-based resin. The thickness of the insulating layer 220 is, for example, about 10 μm to 100 μm. The insulating layer 220 may contain a filler such as silica (SiO2). The content of the filler in the insulating layer 220 can be appropriately set according to the required coefficient of thermal expansion (CTE).

[0018] A plurality of via holes 221 are formed in the insulating layer 220. The via holes 221 penetrate the insulating layer 220. The via holes 221 overlap the wiring layer 210 in a plan view and reach the wiring layer 210. The via holes 221 may be concave portions having an inverted frustum shape. That is, in the via holes 221, the opening diameter at the upper end may be larger than the opening diameter at the lower end.

[0019] The wiring layer 230 is formed on one surface of the insulating layer 220. The wiring layer 230 includes via conductors in the via holes 221 and wiring patterns on one surface of the insulating layer 220. The wiring patterns of the wiring layer 230 are electrically connected to the wiring layer 210 via the via conductors. The material and thickness of the wiring layer 230 are, for example, the same as those of the wiring layer 210.

[0020] As shown in FIG. 2, the wiring layer 230 includes, for example, 16 wiring patterns 701 to 716. The wiring patterns 701 to 704 extend along the X axis, and the +X side ends of the wiring patterns 701 to 704 are aligned. The wiring patterns 705 to 708 extend along the X axis, and the -X side ends of the wiring patterns 705 to 708 are aligned. The wiring pattern 701 and the wiring pattern 705 are on the same straight line, the wiring pattern 702 and the wiring pattern 706 are on the same straight line, the wiring pattern 703 and the wiring pattern 707 are on the same straight line, and the wiring pattern 704 and the wiring pattern 708 are on the same straight line. The wiring patterns 709 to 712 extend along the Y axis, and the +Y side ends of the wiring patterns 709 to 712 are aligned. The wiring patterns 713 to 716 extend along the Y axis, and the -Y side ends of the wiring patterns 713 to 716 are aligned. The wiring pattern 709 and the wiring pattern 713 are on the same straight line, the wiring pattern 710 and the wiring pattern 714 are on the same straight line, the wiring pattern 711 and the wiring pattern 715 are on the same straight line, and the wiring pattern 712 and the wiring pattern 716 are on the same straight line. The number of wiring patterns included in the wiring layer 230 is not limited.

[0021] The solder resist layer 240 is formed to cover the wiring layer 230 on one surface of the insulating layer 220. As shown in FIG. 2, the solder resist layer 240 is formed with an opening 800 for mounting an electronic component such as a semiconductor element, seven openings 801, 805, 807, 810, 812, 813, and 815 for wire bonding, and eight dummy openings 802, 803, 806, 808, 809, 811, 814, and 816. The openings 800, 801, 805, 807, 810, 812, 813, 815, 802, 803, 806, 808, 809, 811, 814, and 816 penetrate the solder resist layer 240.

[0022] The opening 800 is formed in a rectangular shape in plan view. From the opening 800, the +X-side ends of the wiring patterns 701 to 704, the -X-side ends of the wiring patterns 705 to 708, the +Y-side ends of the wiring patterns 709 to 712, and the -Y-side ends of the wiring patterns 713 to 716 are exposed.

[0023] The portions of the wiring patterns 701 to 716 exposed from the opening 800 are pads 401 to 416 for mounting an electronic component, respectively. For example, the thickness (dimension along the Z-axis) of the pads 401 to 416 is about 10 μm to 30 μm, and the width (dimension along the Y-axis) of the pads 401 to 408 and the width (dimension along the X-axis) of the pads 409 to 416 are about 5 μm to 35 μm. Between the pads 401 to 416, the shape and dimensions of the cross section perpendicular to the longitudinal direction are substantially equal.

[0024] As shown in FIGS. 3 and 4, a protective layer 235 is formed on the surfaces of pads 401 to 416, and a plurality of protective layers 235 cover the surfaces of pads 401 to 416 respectively. The protective layer 235 contains, for example, an organic material and is formed by OSP (organic solder preservative) treatment. The thickness of the protective layer 235 is, for example, about 0.1 μm to 0.5 μm. For example, as will be described later, in the semiconductor device 10 configured by using the unit 2, the electrodes 21 of the semiconductor element 20 are electrically connected to the pads 401 to 416 via the solder 22 (see FIGS. 16 and 17). The protective layer 235 disappears during the soldering of the solder 22. Note that the protective layer 235 is omitted in FIG. 2.

[0025] The openings 801, 805, 807, 810, 812, 813, and 815 are formed in a rectangular shape in plan view. The -X side end portion of the wiring pattern 701 is exposed from the opening 801. The +X side end portion of the wiring pattern 705 is exposed from the opening 805. The +X side end portion of the wiring pattern 707 is exposed from the opening 807. The -Y side end portion of the wiring pattern 710 is exposed from the opening 810. The -Y side end portion of the wiring pattern 712 is exposed from the opening 812. The +Y side end portion of the wiring pattern 713 is exposed from the opening 813. The +Y side end portion of the wiring pattern 715 is exposed from the opening 815. The planar shape of the openings 801, 805, 807, 810, 812, 813, and 815 is not limited to a rectangular shape.

[0026] The exposed portions of the wiring patterns 701, 705, 707, 710, 712, 713, and 715 from the openings 801, 805, 807, 810, 812, 813, and 815 are pads 501, 505, 507, 510, 512, 513, and 515 for wire bonding. As shown in FIGS. 3 and 4, a plating layer 231 is formed on the surfaces of the pads 501, 505, and 507, and the plating layer 231 covers the surfaces of the pads 501, 505, and 507. Similarly, a plating layer 231 is also formed on the surfaces of the pads 510, 512, 513, and 515, and the plating layer 231 covers the surfaces of the pads 510, 512, 513, and 515. The ionization tendency of the plating layer 231 is lower than that of the pads 401 to 416. The material of the plating layer 231 is, for example, gold (Au). The thickness of the plating layer 231 is, for example, about 0.05 μm to 1.0 μm. As will be described later, for example, in the semiconductor device 10 configured using the unit 2, the electrode 31 of the semiconductor element 30 is wire-bonded to the surface of the plating layer 231 (see FIGS. 16 and 17). The pads 501, 505, 507, 510, 512, 513, and 515 are an example of the third pads for external connection, and the plating layer 231 is an example of the first plating layer. The pads 401, 405, 407, 410, 412, 413, and 415 electrically connected to the pads 501, 505, 507, 510, 512, 513, and 515 respectively are an example of the first pads. Note that in FIG. 2, the plating layer 231 is omitted. As the plating layer 231, in addition to the gold (Au layer), a Ni / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order) or a Ni / Pd / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order) may be used. In any case, a gold (Au layer) having a lower ionization tendency than the pads 401 to 416 is positioned on the outermost surface of the plating layer 231.

[0027] The openings 802, 803, 806, 808, 809, 811, 814, and 816 are formed in a circular shape in plan view. The -X side end of the wiring pattern 702 is exposed from the opening 802. The -X side end of the wiring pattern 703 is exposed from the opening 803. The +X side end of the wiring pattern 706 is exposed from the opening 806. The +X side end of the wiring pattern 708 is exposed from the opening 808. The -Y side end of the wiring pattern 709 is exposed from the opening 809. The -Y side end of the wiring pattern 711 is exposed from the opening 811. The +Y side end of the wiring pattern 714 is exposed from the opening 814. The +Y side end of the wiring pattern 716 is exposed from the opening 816. The planar shape of the openings 802, 803, 806, 808, 809, 811, 814, and 816 is not limited to a circular shape.

[0028] The exposed portions of the wiring patterns 702, 703, 706, 708, 709, 711, 714, and 716 from the openings 802, 803, 806, 808, 809, 811, 814, and 816 are dummy pads 602, 603, 606, 608, 609, 611, 614, and 616. As shown in FIGS. 3 and 4, a plating layer 232 is formed on the surfaces of the pads 602, 603, 606, and 608, and the plating layer 232 covers the surfaces of the pads 602, 603, 606, and 608. Similarly, a plating layer 232 is also formed on the surfaces of the pads 609, 611, 614, and 616, and the plating layer 232 covers the surfaces of the pads 609, 611, 614, and 616. The ionization tendency of the plating layer 232 is lower than that of the pads 401 to 416. The material and thickness of the plating layer 232 are, for example, the same as those of the plating layer 231. As will be described later, for example, in the semiconductor device 10 configured using the unit 2, signals are not transmitted or received and voltage is not supplied through the pads 602, 603, 606, 608, 609, 611, 614, and 616, and the plating layer 232 is covered with the encapsulation resin 60 (see FIGS. 16 and 17). The pads 602, 603, 606, 608, 609, 611, 614, and 616 are an example of the fourth dummy pad, and the plating layer 232 is an example of the second plating layer. The pads 402, 403, 406, 408, 409, 411, 414, and 416 electrically connected to the pads 602, 603, 606, 608, 609, 611, 614, and 616 respectively are an example of the second pad. Note that in FIG. 2, the plating layer 232 is omitted.

[0029] The wiring pattern 704 is covered with the solder resist layer 240 except for the portion exposed from the opening 800.

[0030] The insulating layer 320 is formed to cover the wiring layer 310 on the other surface of the core layer 100. The material and thickness of the insulating layer 320 are, for example, the same as those of the insulating layer 220. The insulating layer 320 may contain a filler such as silica (SiO2). The content of the filler in the insulating layer 320 is, for example, the same as that in the insulating layer 220.

[0031] A plurality of via holes 321 are formed in the insulating layer 320. The via holes 321 penetrate the insulating layer 320. The via holes 321 overlap the wiring layer 310 in a plan view and reach the wiring layer 310. The via holes 321 may be frustum-shaped recesses. That is, in the via holes 321, the opening diameter at the lower end may be larger than the opening diameter at the upper end.

[0032] The wiring layer 330 is formed on the other surface of the insulating layer 320. The wiring layer 330 includes a via conductor in the via hole 321 and a wiring pattern on the other surface of the insulating layer 320. The wiring pattern of the wiring layer 330 is electrically connected to the wiring layer 310 via the via conductor. The material and thickness of the wiring layer 330 are, for example, the same as those of the wiring layer 210.

[0033] The solder resist layer 340 is formed to cover the wiring layer 330 on the other surface of the insulating layer 320. A plurality of openings 820 are formed in the solder resist layer 340. The openings 820 penetrate through the solder resist layer 340. A part of the wiring layer 330 is exposed from the openings 820. The portion of the wiring layer 330 exposed from the openings 820 is the pad 331 for external connection. Some of the plurality of pads 331 are electrically connected to any one of the pads 401 to 416 via the conductive layer 113. As shown in FIGS. 3 and 4, a plating layer 431 is formed on the surface of the pad 331, and the plating layer 431 covers the surface of the pad 331. The ionization tendency of the plating layer 431 is lower than that of the pads 401 to 416. The material and thickness of the plating layer 431 are the same as those of the plating layer 231, for example. As will be described later, for example, in the semiconductor device 10 configured using the unit 2, the external connection terminal 50 is provided on the surface of the plating layer 431 covering the pad 331. Among the plurality of pads 331, the pad 331 electrically connected to any one of the pads 401 to 416 via the conductive layer 113 is an example of the third pad for external connection. In the example shown in FIGS. 2 to 4, the pad 331 electrically connected to the pad 401, 404 or 412 is an example of the third pad for external connection, and the pads 401, 404 and 412 are examples of the first pads. Among the plurality of plating layers 431, the plating layer 431 covering the pad 331 electrically connected to the pad 401, 404 or 412 is an example of the first plating layer.

[0034] In the present embodiment, the core layer 100, the wiring layer 210, the insulating layer 220, the via conductor of the wiring layer 230, the wiring layer 310, the insulating layer 320, and the via conductor of the wiring layer 330 are included in the base 3. The upper surface 3A (the upper surface of the insulating layer 220) of the base 3 is an example of the first surface, and the lower surface 3B (the lower surface of the insulating layer 320) is an example of the second surface.

[0035] [Method of manufacturing a wiring board] Next, a method for manufacturing the wiring board 1 according to the embodiment will be described. FIGS. 5 to 8 are cross-sectional views illustrating the method for manufacturing the wiring board according to the embodiment. FIGS. 5 to 6 show changes in the cross-section along line IIIa-IIIa in FIG. 2. FIGS. 7 to 8 show changes in the cross-section along line IIIb-IIIb in FIG. 2.

[0036] First, as shown in FIGS. 5(a) and 7(a), the core layer 100, the wiring layer 210, and the core part of the wiring layer 310 are prepared. The core layer 100 has an insulating base material 111 in which through holes 112 are formed, and a conductive layer 113.

[0037] Next, an uncured resin film is attached so as to cover the wiring layer 210 on one surface of the core layer 100, and an uncured resin film is attached so as to cover the wiring layer 310 on the other surface of the core layer 100. Then, these resin films are heat-treated and cured to form the insulating layers 220 and 320. The insulating layers 220 and 320 are formed from an insulating resin such as an epoxy resin or a polyimide resin. The insulating layers 220 and 320 may be formed by applying a liquid resin. Subsequently, via holes 221 reaching the wiring layer 210 are formed in the insulating layer 220, and via holes 321 reaching the wiring layer 310 are formed in the insulating layer 320.

[0038] Next, a wiring layer 230 including a via conductor in the via hole 221 and a wiring pattern on one surface of the insulating layer 220 is formed, and a wiring layer 330 including a via conductor in the via hole 321 and a wiring pattern on the other surface of the insulating layer 320 is formed. The wiring layers 230 and 330 can be formed, for example, by a semi-additive method. The wiring layers 230 and 330 may be formed by a subtractive method. Thereafter, a solder resist layer 240 is formed on the insulating layer 220, and a solder resist layer 340 is formed under the insulating layer 320. Subsequently, openings 800 for mounting electronic components, seven openings 801, 805, 807, 810, 812, 813, and 815 for wire bonding, and eight dummy openings 802, 803, 806, 808, 809, 811, 814, and 816 are formed in the solder resist layer 240. Also, a plurality of openings 820 are formed in the solder resist layer 340. In this way, the laminate 5 is prepared.

[0039] Next, as shown in FIGS. 5(b) and 7(b), a plating resist layer 239 covering the opening 800 is formed. The openings 801, 805, 807, 810, 812, 813, and 815 and the openings 802, 803, 806, 808, 809, 811, 814, and 816 are not covered by the plating resist layer 239. The openings 801, 805, 807, 810, 812, 813, and 815 and the openings 802, 803, 806, 808, 809, 811, 814, and 816 are exposed from the plating resist layer 239.

[0040] Thereafter, as shown in FIGS. 5(c) and 7(c), a plating layer 231 is formed on the surfaces of the pads 501, 505, 507, 510, 512, 513, and 515, and a plating layer 232 is formed on the surfaces of the pads 602, 603, 606, 608, 609, 611, 614, and 616. Also, a plating layer 431 is formed on the surface of the pad 331. The plating layers 231, 232, and 431 can be formed, for example, by an electroless plating method.

[0041] Subsequently, as shown in FIGS. 6(a) and 8(a), the plating resist layer 239 is removed. Next, soft etching of pads 401 to 416 is performed to remove residues of the plating resist layer 239 and native oxide films or the like present on the surfaces of the pads 401 to 416. During soft etching, the respective surfaces of pads 401 to 416, the respective surfaces of plating layer 231, the respective surfaces of plating layer 232, and the respective surfaces of plating layer 431 are brought into contact with the etching solution. For example, the structure from which the plating resist layer 239 has been removed is immersed in the etching solution. At this time, an etching solution that dissolves the material (copper) of pads 401 to 416 and does not dissolve the materials (gold) of plating layers 231, 232, and 431 is used. As the etching solution, for example, a mixed solution of hydrogen peroxide water and sulfuric acid is used. Soft etching is an example of etching.

[0042] Next, as shown in FIGS. 6(b) and 8(b), protective layers 235 are formed on the surfaces of pads 401 to 416, respectively. The protective layer 235 can be formed, for example, by OSP treatment. By OSP treatment, for example, a protective layer 235 made of an organic film containing an azole compound, an imidazole compound, or the like is formed.

[0043] In this way, the wiring board 1 according to the embodiment can be manufactured.

[0044] [Effect of Wiring Board] Next, the effect of the wiring board 1 will be described with reference to reference examples. FIG. 9 is a plan view illustrating a wiring board according to a reference example. In FIG. 9, as in FIG. 2, a portion corresponding to one unit among a plurality of units included in the wiring board is shown. FIGS. 10 and 11 are cross-sectional views illustrating the wiring board according to the reference example. FIG. 10(a) corresponds to a cross-sectional view taken along line Xa-Xa in FIG. 9. FIG. 10(b) corresponds to a cross-sectional view taken along line Xb-Xb in FIG. 9. FIG. 11(a) corresponds to a cross-sectional view taken along line XIa-XIa in FIG. 9. FIG. 11(b) corresponds to a cross-sectional view taken along line XIb-XIb in FIG. 9.

[0045] In the wiring board 1X according to the reference example, as shown in FIGS. 9 to 11, eight dummy openings 802, 803, 806, 808, 809, 811, 814, and 816 are not formed in the solder resist layer 240, and the -X side end of the wiring pattern 702, the -X side end of the wiring pattern 703, the +X side end of the wiring pattern 706, the +X side end of the wiring pattern 708, the -Y side end of the wiring pattern 709, the -Y side end of the wiring pattern 711, the +Y side end of the wiring pattern 714, and the +Y side end of the wiring pattern 716 are covered by the solder resist layer 240. Also, the wiring board 1X does not have the plating layer 232. Further, as will be described later, there are dimensional differences in a part of the mounting pads 401 to 416 between the wiring board 1 and the wiring board 1X. Other configurations of the wiring board 1X are the same as those of the wiring board 1.

[0046] In the manufacturing process of the wiring boards 1 and 1X, as described above, soft etching of the pads 401 to 416 is performed. Among the pads 401 to 416, the pads 401, 404, 405, 407, 410, 412, 413, and 415 that are electrically connected to any of the external connection pads are collectively referred to as the pads 400A, and the pads 402, 403, 406, 408, 409, 411, 414, and 416 that are not electrically connected to any of the external connection pads may be collectively referred to as the pads 400B. Also, the external connection (wire bonding) pads 501, 505, 507, 510, 512, 513, and 515 on the upper surface 3A side of the base 3 may be collectively referred to as the pads 500. The dummy pads 602, 603, 606, 608, 609, 611, 614, and 616 may be collectively referred to as the pads 600. The wiring patterns 701, 705, 707, 710, 712, 713, and 715 may be collectively referred to as the wiring pattern 700.

[0047] Here, the soft etching in the manufacturing process of the wiring board 1X according to the reference example will be described. Fig. 12(a) is a plan view illustrating the change in the pad 400A before and after the soft etching in the manufacturing process of the wiring board 1X according to the reference example. Fig. 12(b) is a plan view illustrating the change in the pad 400B before and after the soft etching in the manufacturing process of the wiring board 1X according to the reference example. Fig. 13(a) is a cross-sectional view illustrating the change in the pad 400A before and after the soft etching in the manufacturing process of the wiring board 1X according to the reference example. Fig. 13(b) is a cross-sectional view illustrating the change in the pad 400B before and after the soft etching in the manufacturing process of the wiring board 1X according to the reference example. Fig. 13(a) corresponds to the cross-sectional view along the line XIIIa-XIIIa in Fig. 12(a). Fig. 13(b) corresponds to the cross-sectional view along the line XIIIb-XIIIb in Fig. 12(b).

[0048] When manufacturing the wiring board 1X, during soft etching, as shown in Table 1 below, the pad 400A is electrically connected to the external connection pad 500, and these external connection pads 500 are covered by the plating layers 231 or 431. On the other hand, the pad 400B is not connected to the external connection pad. Also, the ionization tendency of the plating layers 231 and 431 is lower than that of the pads 401 to 416.

[0049]

Table 1

[0050] Therefore, during soft etching, while galvanic corrosion occurs on pad 400A, no galvanic corrosion occurs on pad 400B. For this reason, as shown in FIGS. 12 and 13, in soft etching, the width and thickness of pad 400B hardly decrease, while the width and thickness of pad 400A decrease more than those of pad 400B. That is, the amount of decrease in the width and thickness of pad 400A is larger than the amount of decrease in the width and thickness of pad 400B. Even if the width and thickness are equal between pad 400A and pad 400B before soft etching, the width and thickness of pad 400A become smaller than those of pad 400B after soft etching. Therefore, variations in dimensions occur among pads 401 to 416.

[0051] Next, soft etching in the manufacturing process of the wiring board 1 according to the embodiment will be described. FIG. 14(a) is a plan view illustrating changes in pad 400A before and after soft etching in the manufacturing process of the wiring board 1 according to the embodiment. FIG. 14(b) is a plan view illustrating changes in pad 400B before and after soft etching in the manufacturing process of the wiring board 1 according to the embodiment. FIG. 15(a) is a cross-sectional view illustrating changes in pad 400A before and after soft etching in the manufacturing process of the wiring board 1 according to the embodiment. FIG. 15(b) is a cross-sectional view illustrating changes in pad 400B before and after soft etching in the manufacturing process of the wiring board 1 according to the embodiment. FIG. 15(a) corresponds to a cross-sectional view taken along line XVa-XVa in FIG. 14(a). FIG. 15(b) corresponds to a cross-sectional view taken along line XVb-XVb in FIG. 14(b).

[0052] When manufacturing the wiring board 1, during soft etching, as shown in Table 2 below, pad 400A is electrically connected to the external connection pad 500, and these external connection pads 500 are covered with the plating layer 231 or 431. Also, pad 400B is electrically connected to the dummy pad 600, and these dummy pads 600 are covered with the plating layer 232. Further, the ionization tendency of the plating layers 231, 232, and 431 is lower than the ionization tendency of pads 401 to 416.

[0053]

Table 2

[0054] Therefore, during soft etching, galvanic corrosion occurs not only on the pad 400A but also on the pad 400B. For this reason, as shown in FIGS. 14 and 15, in soft etching, the widths and thicknesses of the pads 400A and 400B decrease to the same extent. That is, the amounts of decrease in the width and thickness of the pad 400A are the same as those of the pad 400B. If the widths and thicknesses are equal between the pad 400A and the pad 400B before soft etching, the width and thickness of the pad 400A are substantially equal to those of the pad 400B even after soft etching. Therefore, variations in dimensions among the pads 401 to 416 are suppressed. By forming the wiring layers 230 and 330 in consideration of the amounts of decrease in width and thickness during soft etching (see FIGS. 5 and 7), desired dimensions (width and thickness) can be obtained for the pads 401 to 416 of the completed wiring board 1.

[0055] Thus, according to the wiring board 1 according to the embodiment, variations in the amounts of decrease in the thickness and width of the mounting pads 401 to 416 can be suppressed.

[0056] [Semiconductor device] Next, a semiconductor device manufactured using the wiring board 1 (unit 2) will be described. FIGS. 16 and 17 are cross-sectional views illustrating a semiconductor device manufactured using the wiring board according to the embodiment. FIGS. 16(a), 16(b), 17(a), and 17(b) show the same cross-sections as FIGS. 3(a), 3(b), 4(a), and 4(b), respectively.

[0057] As shown in FIGS. 16 and 17, a semiconductor device 10 manufactured using a wiring board 1 (unit 2) includes a wiring board 1 in which a protective layer 235 has disappeared, a semiconductor element 20 having a plurality of electrodes 21, a semiconductor element 30 having a plurality of electrodes 31, solder 22, bonding wires 32, an adhesive layer 40, external connection terminals 50, and a sealing resin 60.

[0058] The electrodes 21 are provided on the surface of the semiconductor element 20 facing the wiring board 1. The electrodes 21 are joined to and electrically connected to any one of the mounting pads 401 to 416 by solder 22. That is, the semiconductor element 20 is flip-chip mounted on the wiring board 1. The protective layer 235 has disappeared during soldering of the solder 22. The electrodes 21 are, for example, metal posts.

[0059] The semiconductor element 30 is provided on the semiconductor element 20. There is an adhesive layer 40 between the semiconductor element 20 and the semiconductor element 30, and the semiconductor elements 20 and 30 are adhered to each other by the adhesive layer 40. The electrodes 31 are provided on the surface of the semiconductor element 30 opposite to the surface facing the semiconductor element 20. One end of a bonding wire 32 is connected to the electrode 31, and the other end of the bonding wire 32 is connected to a plating layer 231 covering the surface of any one of the wire bonding pads 501, 505, 507, 510, 512, 513, and 515. That is, the electrode 31 is electrically connected to any one of the pads 501, 505, 507, 510, 512, 513, and 515.

[0060] The external connection terminals 50 are provided on the surface of a plating layer 431 covering the pads 331. The external connection terminals 50 are, for example, solder balls.

[0061] The sealing resin 60 seals the semiconductor element 20 including the electrodes 21, the semiconductor element 30 including the electrodes 31, the solder 22, and the bonding wires 32. The surface of the wiring board 1 on the semiconductor elements 20 and 30 sides is covered by the sealing resin 60. The plating layer 232 is also covered by the sealing resin 60.

[0062] Thus, in the semiconductor device 10, the plating layer 232 is covered with the encapsulation resin 60, and signal transmission / reception and voltage supply through the pads 602, 603, 606, 608, 609, 611, 614, and 616 are not performed.

[0063] The semiconductor device 10 may include three or more semiconductor elements, or may include one semiconductor element.

[0064] Note that in the present disclosure, the number of mounting pads electrically connected to one dummy pad is not limited to one. For example, as shown in FIG. 18, two mounting pads 400B may be electrically connected to one dummy pad 600. Further, three or more mounting pads 400B may be electrically connected to one dummy pad 600. Conversely, a plurality of dummy pads may be connected to one mounting pad 400B. FIG. 18 is a plan view showing a part of a wiring board according to a modified example of the embodiment.

[0065] As described above in detail with respect to the preferred embodiments, etc., the present disclosure is not limited to the above-described embodiments, etc., and various modifications and substitutions can be made to the above-described embodiments, etc. without departing from the scope described in the claims.

Description of Reference Numerals

[0066] 1 Wiring board 2 Unit 3 Base 3A Upper surface 3B Lower surface 231, 232, 431 Plating layer 235 Protective layer 240 Solder resist layer 400A, 400B, 401 - 416 Pads 500, 501, 505, 507, 510, 512, 513, 515 Pads 600, 602, 603, 606, 608, 609, 611, 614, 616 Pads 700 - 716 Wiring patterns

Claims

1. A base having a first surface, a first pad and a second pad for mounting provided on the first surface, a third pad for external connection electrically connected to the first pad, a fourth pad for dummy electrically connected to the second pad, a first plating layer covering the surface of the third pad, a second plating layer covering the surface of the fourth pad, and having a wiring board in which the ionization tendency of the first plating layer and the second plating layer is lower than the ionization tendency of the first pad and the second pad.

2. The wiring board according to claim 1, wherein the fourth pad is provided on the first surface.

3. The third pad is provided on the first surface, The wiring board according to claim 1 or 2, wherein a bonding wire is connected to the first plating layer.

4. The base has a second surface opposite to the first surface, The third pad is provided on the second surface, The wiring board according to claim 1 or 2, wherein an external connection terminal is provided on the first plating layer.

5. Copper is exposed on the surfaces of the first pad and the second pad, The wiring board according to claim 1 or 2, wherein gold is exposed on the surfaces of the first plating layer and the second plating layer.

6. The wiring board according to claim 1 or 2, having a plurality of protective layers covering the surfaces of the first pad and the second pad, respectively.

7. A step of preparing a laminate including a base having a first surface, a first pad and a second pad for mounting provided on the first surface, a third pad for external connection electrically connected to the first pad, and a fourth pad for dummy electrically connected to the second pad; A step of forming a first plating layer covering the surface of the third pad and a second plating layer covering the surface of the fourth pad; After the step of forming the first plating layer and the second plating layer, a step of etching the surfaces of the first pad and the second pad by bringing the surfaces of the first pad, the second pad, the first plating layer, and the second plating layer into contact with an etching solution; and having A method for manufacturing a wiring board in which the ionization tendency of the first plating layer and the second plating layer is lower than the ionization tendency of the first pad and the second pad.

8. The method of manufacturing a wiring board according to claim 7, further comprising a step of forming a plurality of protective layers covering the surface of the first pad and the surface of the second pad respectively after the step of etching the surface of the first pad and the surface of the second pad.

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