Doherty amplifier

Abstract

To provide a Doherty amplifier which can improve isolation between a main amplifier and a peak amplifier at a low cost.SOLUTION: A Doherty amplifier includes a heat sink, a resin substrate that is provided on the heat sink, in which a cavity is formed so as to expose the heat sink, and a plurality of resin layers and a plurality of metal layers are stacked, a main amplifier provided on the cavity, a peak amplifier provided on the cavity, and an inductor, wherein the resin substrate has a partition wall part for partitioning at least a part of the main amplifier and at least a part of the peak amplifier, the plurality of metal layers of the partition wall part is electrically connected to the heat sink, and the inductor is provided on the partition wall part, and is electrically connected to the plurality of metal layers.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a Doherty amplifier.

Background Art

[0002] Patent Document 1 discloses a semiconductor package having a wire bond wall for reducing coupling. This package includes a substrate and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array that interconnects the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, and the second circuit includes a second wire bond array that interconnects a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds on the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce electromagnetic coupling between the first circuit and the second circuit during operation of at least one of the first circuit and the second circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In wireless communication, in order to support high-speed and high-capacity communication, a digital modulation signal with a large PAPR (Peak to Average Power Ratio) is used. Even for such a modulation signal with a large PAPR, a Doherty amplifier is widely used as a circuit for amplifying the signal with low distortion and high efficiency. The Doherty amplifier is composed of a main amplifier biased in class AB and a peak amplifier biased in class C, which are combined in parallel via a 90-degree delay line arranged at the input and output. Also, for miniaturization and cost reduction, the main amplifier and the peak amplifier are often arranged adjacent to each other. When the circuits are adjacent, the isolation between the main amplifier path and the peak amplifier path may deteriorate. As a result, problems such as characteristic degradation and oscillation may occur.

[0005] Regarding such problems, Patent Document 1 shows that an electrical shield is provided between the paths. With this structure, it is possible to improve the isolation between the paths. However, in Patent Document 1, a dedicated member and a special assembly process are required to form the shield. Therefore, there is a possibility that the manufacturing cost may increase.

[0006] The present disclosure has been made to solve the above-described problems, and an object thereof is to obtain a Doherty amplifier capable of improving the isolation between the main amplifier and the peak amplifier at low cost.

Means for Solving the Problems

[0007] The Doherty amplifier according to the present disclosure includes a heat sink, a resin substrate provided on the heat sink with a cavity formed to expose the heat sink and formed by laminating a plurality of resin layers and a plurality of metal layers, a main amplifier provided in the cavity, a peak amplifier provided in the cavity, and an inductor. The resin substrate has a partition portion that separates at least a part of the main amplifier and at least a part of the peak amplifier. The plurality of metal layers of the partition portion are electrically connected to the heat sink. The inductor is provided on the partition portion and is electrically connected to the plurality of metal layers.

Advantages of the Invention

[0008] In the Doherty amplifier according to the present disclosure, the isolation between the main amplifier and the peak amplifier can be improved at low cost by the partition portion and the inductor.

Brief Description of the Drawings

[0009]

Figure 1

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Figure 8

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Figure 10

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Figure 14

Embodiments for Carrying Out the Invention

[0010] The Doherty amplifier according to each embodiment will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and the repeated description may be omitted.

[0011] Embodiment 1. FIG. 1 is a diagram for explaining the circuit configuration of the Doherty amplifier 1 according to Embodiment 1. The Doherty amplifier 1 is used, for example, as a power amplifier for wireless communication. The Doherty amplifier 1 includes a main amplifier 4, a peak amplifier 5, 90-degree delay circuits 30 and 31, a distribution circuit 40, a combining circuit 41, an input terminal 2, and an output terminal 3. The input terminal 2 is connected to the distribution circuit 40. The output of the distribution circuit 40 is connected to the main amplifier 4 and the 90-degree delay circuit 30. The output of the 90-degree delay circuit 30 is connected to the input of the peak amplifier 5. A 90-degree delay circuit 31 is connected to the output of the main amplifier 4. In the combining circuit 41, the output of the 90-degree delay circuit 31 and the output of the peak amplifier 5 are connected. The output of the combining circuit 41 is connected to the output terminal 3.

[0012] In the main amplifier 4, an input matching circuit 20, a first-stage transistor 10, an inter-stage matching circuit 21, a final-stage transistor 11, and an output matching circuit 22 are connected in this order. The first-stage transistor 10 corresponds to the first main amplifier connected to the input terminal 2 side of the Doherty amplifier 1, and the final-stage transistor 11 corresponds to the second main amplifier connected to the output terminal 3 side of the Doherty amplifier 1. The inter-stage matching circuit 21 connects the first main amplifier and the second main amplifier.

[0013] In the peak amplifier 5, an input matching circuit 23, a first-stage transistor 12, an inter-stage matching circuit 24, a final-stage transistor 13, and an output matching circuit 25 are connected in this order. The first-stage transistor 12 corresponds to the first peak amplifier connected to the input terminal 2 side of the Doherty amplifier 1, and the final-stage transistor 13 corresponds to the second peak amplifier connected to the output terminal 3 side of the Doherty amplifier 1. The inter-stage matching circuit 24 connects the first peak amplifier and the second peak amplifier.

[0014] FIG. 2 is a perspective view of the Doherty amplifier 1 according to Embodiment 1. In the main amplifier 4, the first-stage transistor 10 is configured as a first-stage transistor chip 100, and the final-stage transistor 11 is configured as a final-stage transistor chip 101. Also, a part of the output matching circuit 22 is configured as the final-stage transistor chip 101. The remaining part of the output matching circuit 22 is formed on the resin substrate 60. The inter-stage matching circuit chip 121 has a circuit formed thereon and constitutes a part of the inter-stage matching circuit 21 of the main amplifier 4. Thus, the main amplifier 4 is composed of a plurality of chips. The surface metal of the transistor chip and the resin substrate 60, the transistor chip and the inter-stage matching circuit chip 121, and the inter-stage matching circuit chip 121 and the surface metal of the resin substrate 60 are connected by wires 201 to 205 which are bonding wires.

[0015] In the peak amplifier 5, the first-stage transistor 12 is configured as a first-stage transistor chip 102, and the final-stage transistor 13 is configured as a final-stage transistor chip 103. Also, a part of the output matching circuit 25 is configured as the final-stage transistor chip 103. The remaining part of the output matching circuit 25 is formed on the resin substrate 60. The inter-stage matching circuit chip 124 has a circuit formed thereon and constitutes a part of the inter-stage matching circuit 24 of the peak amplifier 5. Thus, the peak amplifier 5 is composed of a plurality of chips. The surface metal of the transistor chip and the resin substrate 60, the transistor chip and the inter-stage matching circuit chip 124, and the surface metal of the inter-stage matching circuit chip 124 and the resin substrate 60 are connected by bonding wires 206 to 210, respectively.

[0016] The wires 202, 203, 207, and 208 are connected to the electrode pads on the resin substrate 60. Thereby, a part of the inter-stage matching circuits 21 and 24 can be formed on the resin substrate 60. Also, with the above configuration, the drain voltages of the first-stage transistors 10 and 12 and the gate voltages of the final-stage transistors 11 and 13 can be supplied. In FIGS. 1 and 2, the detailed layout of the drain bias circuit, the gate bias circuit, and the semiconductor chip is omitted.

[0017] The Doherty amplifier 1 is integrated in one package. The package includes a heat sink 80 and a resin substrate 60 provided on the heat sink 80. The multi-layer resin substrate 60 is formed by laminating a plurality of resin layers and a plurality of metal layers. A cavity is formed in the resin substrate 60 with a part thereof cut out to expose the heat sink 80. The main amplifier 4 and the peak amplifier 5 are provided in the cavity.

[0018] By directly die-bonding the first-stage transistor chips 100 and 102, the final-stage transistor chips 101 and 103, and the inter-stage matching circuit chips 121 and 124 to the heat sink 80 in the cavity, a low thermal resistance can be achieved.

[0019] Further, the input matching circuits 20 and 23, the output matching circuits 22 and 25, the distribution circuit 40, and the combining circuit 41 are formed on the resin substrate 60. These circuits are configured by combining circuit lines, chip inductors, chip capacitors, chip resistors, etc. on the resin substrate 60.

[0020] The resin substrate 60 has an annular portion 61 that forms a cavity and a partition portion 62 that extends from the annular portion 61 between the second main amplifier and the second peak amplifier. That is, the partition portion 62 extends between the final-stage transistor chips 101 and 103. In the present embodiment, the cavity is divided into a first cavity 50 and a second cavity 51 by the partition portion 62. The main amplifier 4 is provided in the first cavity 50, and the peak amplifier 5 is provided in the second cavity 51.

[0021] Note that the state where the main amplifier 4 is provided in the cavity indicates a state where at least a part of the main amplifier 4 is provided in the cavity, and it is not necessary for the entire main amplifier 4 to be provided in the cavity. Similarly, the state where the peak amplifier 5 is provided in the cavity indicates a state where at least a part of the peak amplifier 5 is provided in the cavity, and it is not necessary for the entire peak amplifier 5 to be provided in the cavity.

[0022] Also, a plurality of inductors 300 are provided on the partition portion 62. The plurality of inductors 300 are, for example, chip inductors.

[0023] FIG. 3 is a cross-sectional view of the shield 70 according to Embodiment 1. The shield 70 is disposed between the first cavity 50 and the second cavity 51. The shield 70 has the partition portion 62 of the resin substrate 60 and the inductor 300. In the partition portion 62 which is a part of the resin substrate 60, a plurality of resin layers 303 and a plurality of metal layers 302 are laminated. The surface layer metal 320 of the partition portion 62, the plurality of metal layers 302, and the heat sink 80 are electrically connected by a plurality of VIA holes 301 formed in the resin substrate 60.

[0024] In addition, a plurality of inductors 300 are arranged on the surface layer metal 320. The inductor 300 is electrically connected to a plurality of metal layers 302. FIG. 4 is a diagram for explaining the connection between the inductor 300 according to Embodiment 1 and the heat sink 80. Electrodes 310 and 311 at both ends of the inductor 300 are connected to the heat sink 80 via the surface layer metal 320 and the VIA hole 301, respectively. The heat sink 80 is GND. From the above, the inductor 300, the VIA hole 301, and the heat sink 80 are at the same potential.

[0025] The VIA hole 301 and the inductor 300 are preferably arranged at high density within the design rules of the resin substrate 60. The resin substrate 60 is formed of a material such as FR4, and the substrate thickness is 200 to 400 μm. The heat sink 80 is formed of a material with low thermal resistance such as copper. The first-stage transistor chips 100 and 102 and the final-stage transistor chips 101 and 103 are, for example, GaN-HEMTs formed on an SiC substrate. For the inter-stage matching circuit chips 121 and 124, an inexpensive semiconductor substrate such as a GaAs or Si substrate is used. Not limited to this, for example, a circuit may be formed on a thin dielectric plate to constitute the inter-stage matching circuit chips 121 and 124. The inductor 300 is, for example, a general-purpose chip inductor of 0603 size or 0402 size. The inductor 300 desirably has a high internal metal density and a large inductance value, and the allowable current value is not limited.

[0026] FIG. 5 is a diagram for explaining the circuit configuration of the Doherty amplifier 801 according to the comparative example. FIG. 6 is a perspective view of the Doherty amplifier 801 according to the comparative example. FIG. 7 is a plan view of the Doherty amplifier 801 according to the comparative example. In the comparative example, it is different from this embodiment in that the partition portion 62 and the inductor 300 are not provided. That is, the main amplifier 4 and the peak amplifier 5 are provided in the common cavity 52. Other configurations are the same as those of this embodiment.

[0027] The problems in the Doherty amplifier 801 according to such a comparative example will be described. For miniaturization, the final-stage transistor chips 101 and 103, the inter-stage matching circuit chips 121 and 124, and the first-stage transistor chips 100 and 102 are arranged adjacent to each other. Therefore, the wires 204 and 209 are likely to be electromagnetically coupled. As a result, the isolation between the main amplifier 4 and the peak amplifier 5 deteriorates, and there is a risk of problems such as deterioration of RF characteristics and oscillation.

[0028] On the other hand, in the present embodiment, the cavity is divided into two, and a shield 70 composed of a partition wall portion 62 and an inductor 300 is arranged therebetween. The VIA hole 301 is electrically connected to the heat sink 80 which is the GND of the circuit, and further, the VIA hole 301 and the inductor 300 are also electrically connected. By such a shield 70 having the same potential as the GND, the isolation between the main amplifier 4 and the peak amplifier 5 can be improved. Therefore, deterioration of RF characteristics, occurrence of oscillation, and reduction of stability can be suppressed.

[0029] Also, by adding the inductor 300, the shield 70 can be made higher. When a current flows through the bonding wire, a magnetic flux is generated around the current. By forming the shield 70 so as to block this magnetic flux, electromagnetic coupling can be effectively suppressed. The upper surface of the inductor 300 may be provided at a position higher than the wires connecting the plurality of chips constituting the main amplifier 4 or the peak amplifier 5.

[0030] Also, inside the chip inductor, metal winding wires are integrated at a high density. By using a chip inductor filled with metal at a high density as the inductor 300, the isolation can be further improved.

[0031] Furthermore, the shield 70 can be composed of VIA holes 301 formed at the time of creating the resin substrate 60 and chip inductors which are off-the-shelf products. That is, no dedicated parts are required, and no special assembly process is required. Therefore, isolation between the main amplifier 4 and the peak amplifier 5 can be improved at low cost. As described above, in the present embodiment, a chip inductor, a chip capacitor, and a chip resistor are used for the matching circuit. The inductor 300 serving as the shield 70 may be mounted in the process of mounting these components. Thereby, a chip inductor can be provided for the shield 70 without adding a manufacturing process.

[0032] In the present embodiment, an example in which the main amplifier 4 and the peak amplifier 5 are each a two-stage amplifier has been described. However, the present invention is not limited to this, and the same effects can be obtained even if the main amplifier 4 and the peak amplifier 5 are each a single-stage or three-stage or more amplifier.

[0033] These modifications can be appropriately applied to the Doherty amplifier according to the following embodiment. Since the Doherty amplifier according to the following embodiment has many common points with Embodiment 1, the description will focus on the differences from Embodiment 1.

[0034] Embodiment 2. FIG. 8 is a diagram for explaining the circuit configuration of the Doherty amplifier 1a according to Embodiment 2. FIG. 9 is a perspective view of the Doherty amplifier 1a according to Embodiment 2. In the present embodiment, the structure of the shield 70a is different from the structure of Embodiment 1. The shield 70a is not divided into two cavities, and is arranged between the final-stage transistor chips 101 and 103 and between the inter-stage matching circuit chips 121 and 124. That is, in the present embodiment, one cavity 50a is formed in the resin substrate 60. Thus, the partition portion 62a may separate at least a part of the main amplifier 4 and at least a part of the peak amplifier 5.

[0035] In addition, the first-stage transistor chips 100 and 102 are made common and configured as one transistor chip 105. That is, the first-stage transistors 10 and 12 are provided on one transistor chip 105. The transistor chip 105 has two gate pads and two drain pads. Other configurations are the same as those in the first embodiment.

[0036] Also in this embodiment, the isolation between the main amplifier 4 and the peak amplifier 5 can be improved by the shield 70a. In addition, since the first-stage transistor chips can be integrated into one, the Doherty amplifier 1a can be manufactured at a lower cost.

[0037] Here, interference between wires is likely to affect the degradation of isolation. Also, the lower the impedance of the circuit to which the wire is connected, the greater the influence tends to be. The gate of a transistor has a particularly low impedance. Also, the gate impedance is lower when the transistor size is larger. For this reason, it is considered that the interference between the wires 204 and 209 connected to the gates of the final-stage transistor chips 101 and 103 particularly easily affects isolation. In this embodiment, a shield 70a can be provided between the wires 204 and 209 to efficiently improve isolation.

[0038] Embodiment 3. FIG. 10 is a perspective view of a Doherty amplifier 1b according to Embodiment 3. In this embodiment, the arrangement of the inductor 300 is different from the arrangement in Embodiment 2. Other configurations are the same as those in the second embodiment. The plurality of inductors 300 are locally provided at positions adjacent to the wires 204, 205, 209, and 210 connected to the final-stage transistor chip 101 or the final-stage transistor chip 103 on the upper surface of the partition portion 62a.

[0039] Specifically, one of the inductors 300 separates the wire 204 connecting the inter-stage matching circuit chip 121 and the final-stage transistor chip 101 from the wire 209 connecting the inter-stage matching circuit chip 124 and the final-stage transistor chip 103. Also, one of the inductors 300 separates the wire 205 connected to the output side of the final-stage transistor chip 101 from the wire 210 connected to the output side of the final-stage transistor chip 103.

[0040] As described above, the deterioration of the isolation between the main amplifier 4 and the peak amplifier 5 is dominated by the interference between the bonding wires. Therefore, even if the inductor 300 is arranged only limitedly between the wires, the effect of improving the isolation can be sufficiently obtained. Also, since the number of mounted inductors 300 can be reduced, further cost reduction becomes possible.

[0041] Note that in Embodiment 1, the arrangement of the inductor 300 as in this embodiment may be adopted. The inductor 300 may be provided, for example, only between the wires 204 and 209.

[0042] Embodiment 4. FIG. 11 is a diagram for explaining the circuit configuration of the isolation improvement circuit 71 according to Embodiment 4. In this embodiment, it is different from Embodiment 1 in that the isolation improvement circuit 71 is provided instead of the shield 70. Other configurations are the same as those in Embodiment 1.

[0043] The circuit 180 shows a part of the inter-stage matching circuit 21 of the main amplifier 4, and the circuit 181 shows a part of the inter-stage matching circuit 24 of the peak amplifier 5. The inductor 160 corresponds to the wire 204, and the inductor 161 corresponds to the wire 209. The capacitors 151 and 153 are the capacitors of the inter-stage matching circuits 21 and 24, and the capacitors 150 and 152 are the DC cut capacitors of the inter-stage matching circuits 21 and 24. Let the input and output of the circuit 180 be nodes 170 and 171 respectively. Let the input and output of the circuit 181 be nodes 172 and 173 respectively.

[0044] The isolation improvement circuit 71 is arranged between the main amplifier 4 and the peak amplifier 5. The isolation improvement circuit 71 has a parallel circuit in which an inductor 163 and a capacitor 155 are connected in parallel. Further, the isolation improvement circuit 71 has a series circuit in which an inductor 162 and a capacitor 154 are connected in series. One end of the parallel circuit is electrically connected to GND, that is, the heat sink 80. The other end of the parallel circuit is electrically connected to one end of the series circuit. The other end of the series circuit is electrically connected to the heat sink 80.

[0045] Deterioration of isolation between the paths of the main amplifier 4 and the peak amplifier 5 easily occurs between the inductors 160 and 161. Therefore, it is preferable to arrange the inductor 162 adjacent to the inductors 160 and 161. The resonance frequency of the parallel circuit is set to be equal to the operating center frequency of the Doherty amplifier 1c. Also, the inductance and capacitance values of the inductor 162 and the capacitor 154 are set according to the frequency of the isolation to be improved between the main amplifier 4 and the peak amplifier 5.

[0046] Since the inductor 162 is adjacent to the inductors 160 and 161, it is mutually coupled with the inductors 160 and 161. However, since the parallel circuit composed of the inductor 163 and the capacitor 155 is open at the operating center frequency, even if the inductor 162 is coupled with the inductors 160 and 161, the isolation improvement circuit 71 does not affect the Doherty amplifier 1c at the operating center frequency. On the other hand, at frequencies other than the operating center frequency, the parallel circuit of the inductor 163 and the capacitor 155 is not open. Therefore, by appropriately setting the constants of the inductor 162 and the capacitor 154, a short-circuit point can be formed at a specific frequency. At this frequency, the isolation improvement circuit 71 improves the isolation between paths like a shield.

[0047] FIG. 12 and FIG. 13 are diagrams for explaining the effects of the isolation improvement circuit 71 according to Embodiment 4. The solid line in FIG. 12 shows the calculation result of the passing characteristics from node 170 to node 171 when the isolation improvement circuit 71 is not present. The dashed line in FIG. 12 shows the calculation result of the passing characteristics from node 172 to node 171, which indicates the isolation between paths, when the isolation improvement circuit 71 is not present. The inductors 160 and 161 are 0.44 nH each, the capacitors 151 and 153 are 4.5 pF each, and the coupling coefficient between the inductors 160 and 161 is 0.1. Also, the operating frequency of the circuit is 3.5 GHz.

[0048] The solid line in FIG. 13 shows the calculation result of the passing characteristics from node 170 to node 171 when the isolation improvement circuit 71 is applied. The dashed line in FIG. 13 shows the calculation result of the passing characteristics from node 172 to node 171 when the isolation improvement circuit 71 is applied. The inductor 162 constituting the isolation improvement circuit 71 is 0.35 nH, the inductor 163 is 0.69 nH, the capacitor 154 is 5 pF, and the capacitor 155 is 3.0 pF. The coupling coefficients between the inductor 160 and the inductor 162, and between the inductor 161 and the inductor 162 are 0.2 each.

[0049] From the comparison of the calculation results in FIGS. 12 and 13, it can be seen that the passing characteristics of the path of the main amplifier 4 do not change at the center frequency of 3.5 GHz. That is, it can be understood that the isolation improvement circuit 71 does not affect the characteristics in the operating frequency band of the Doherty amplifier 1c. Also, it can be seen that by providing the isolation improvement circuit 71, the isolation between the paths on the low-frequency side is improved.

[0050] From the above, in this embodiment, it is possible to selectively improve the isolation at a specific frequency without affecting the operation at the operating center frequency. This embodiment is particularly useful when the entire Doherty amplifier becomes unstable due to the deterioration of the isolation between paths at a specific frequency.

[0051] FIG. 14 is a perspective view of the Doherty amplifier 1c according to Embodiment 4. The inductor 162 and the capacitor 154 that form a series circuit are provided on the partition portion 62. Also, the inductor 163 and the capacitor 155 that form a parallel circuit are provided on the annular portion 61. Also in the present embodiment, the series circuit and the parallel circuit are electrically connected to the heat sink 80 via the metal layer of the resin substrate 60 and the VIA hole 301.

[0052] The inductor 162 separates the wire 204 that connects the inter-stage matching circuit chip 121 and the final-stage transistor chip 101, and the wire 209 that connects the inter-stage matching circuit chip 124 and the final-stage transistor chip 103.

[0053] In the isolation improvement circuit 71, the inductors 162 and 163 are, for example, chip inductors, and the capacitors 154 and 155 are, for example, chip capacitors. Therefore, the isolation improvement circuit 71 can be configured by changing the connection of the wiring of the resin substrate 60 from Embodiment 1. Since the isolation improvement circuit 71 can be configured using chip inductors and chip capacitors, dedicated components are not required and a special assembly process is not required. Therefore, the isolation between the main amplifier 4 and the peak amplifier 5 can be improved at low cost.

[0054] As a modification of the present embodiment, the inductor 163 that forms a parallel circuit may separate the wires 204 and 209. The inductor 162 or the inductor 163 may separate the wire 205 connected to the output side of the final-stage transistor chip 101 and the wire 210 connected to the output side of the final-stage transistor chip 103. Also, the isolation improvement circuit 71 of the present embodiment may be applied to the partition portion 62a of Embodiment 2.

[0055] Note that the technical features described in each embodiment may be used in appropriate combinations.

[0056] Hereinafter, various aspects of the present disclosure will be collectively described as appendices. (Appendix 1) A heat sink and, A resin substrate provided on the heat sink and having a cavity formed to expose the heat sink, the resin substrate being formed by laminating a plurality of resin layers and a plurality of metal layers, A main amplifier provided in the cavity, A peak amplifier provided in the cavity, An inductor, Comprising, The resin substrate has a partition portion that separates at least a part of the main amplifier and at least a part of the peak amplifier, The plurality of metal layers of the partition portion are electrically connected to the heat sink, The inductor is provided on the partition portion and is electrically connected to the plurality of metal layers, and is a Doherty amplifier characterized by this. (Appendix 2) The Doherty amplifier according to Appendix 1, characterized in that the inductor is a chip inductor. (Appendix 3) The Doherty amplifier according to Appendix 1 or 2, characterized in that the plurality of metal layers and the heat sink are electrically connected by VIA holes formed in the resin substrate. (Appendix 4) The main amplifier has a first main amplifier connected to the input terminal side of the Doherty amplifier, a second main amplifier connected to the output terminal side of the Doherty amplifier, and a first inter-stage matching circuit connecting the first main amplifier and the second main amplifier. The peak amplifier has a first peak amplifier connected to the input terminal side of the Doherty amplifier, a second peak amplifier connected to the output terminal side of the Doherty amplifier, and a second inter-stage matching circuit connecting the first peak amplifier and the second peak amplifier, and is the Doherty amplifier according to any one of Appendices 1 to 3, characterized by this. (Appendix 5) The resin substrate has an annular portion that forms the cavity, The partition part extends from the annular part between the second main amplifier and the second peak amplifier, and is the Doherty amplifier according to appended claim 4. (Appended claim 6) The inductor separates a wire connecting the first inter-stage matching circuit and the second main amplifier from a wire connecting the second inter-stage matching circuit and the second peak amplifier, and is the Doherty amplifier according to appended claim 4 or 5. (Appended claim 7) The inductor separates a wire connected to the output side of the second main amplifier from a wire connected to the output side of the second peak amplifier, and is the Doherty amplifier according to any one of appended claims 4 to 6. (Appended claim 8) The inductor is locally provided at a position adjacent to a wire connected to the second main amplifier or the second peak amplifier on the upper surface of the partition part, and is the Doherty amplifier according to any one of appended claims 4 to 7. (Appended claim 9) The main amplifier is composed of a plurality of chips. The upper surface of the inductor is provided at a position higher than a wire connecting the plurality of chips, and is the Doherty amplifier according to any one of appended claims 1 to 8. (Appended claim 10) The cavity is divided into a first cavity and a second cavity by the partition part. The main amplifier is provided in the first cavity. The peak amplifier is provided in the second cavity, and is the Doherty amplifier according to any one of appended claims 1 to 9. (Appended claim 11) The first main amplifier and the first peak amplifier are provided on one chip, and are the Doherty amplifier according to any one of appended claims 4 to 8. (Appended claim 12) A parallel circuit in which a first inductor and a first capacitor are connected in parallel. A series circuit in which a second inductor and a second capacitor are connected in series. And includes. One end of the parallel circuit is electrically connected to the heat sink, The other end of the parallel circuit is electrically connected to one end of the series circuit, The other end of the series circuit is electrically connected to the heat sink, The inductor includes the first inductor or the second inductor, The Doherty amplifier according to Supplementary Note 1, wherein the resonance frequency of the parallel circuit is equal to the operating center frequency of the Doherty amplifier. (Supplementary Note 13) The main amplifier includes a first main amplifier connected to the input terminal side of the Doherty amplifier, a second main amplifier connected to the output terminal side of the Doherty amplifier, and a first inter-stage matching circuit connecting the first main amplifier and the second main amplifier. The Doherty amplifier according to Supplementary Note 12, wherein the peak amplifier includes a first peak amplifier connected to the input terminal side of the Doherty amplifier, a second peak amplifier connected to the output terminal side of the Doherty amplifier, and a second inter-stage matching circuit connecting the first peak amplifier and the second peak amplifier. (Supplementary Note 14) The Doherty amplifier according to Supplementary Note 13, wherein the inductor separates a wire connecting the first inter-stage matching circuit and the second main amplifier from a wire connecting the second inter-stage matching circuit and the second peak amplifier. (Supplementary Note 15) The first inductor and the second inductor are chip inductors, The Doherty amplifier according to any one of Supplementary Notes 12 to 14, wherein the first capacitor and the second capacitor are chip capacitors.

Explanation of Reference Signs

[0057] 1, 1a, 1b, 1c Doherty amplifier, 2 input terminal, 3 output terminal, 4 main amplifier, 5 peak amplifier, 10 first-stage transistor, 11 final-stage transistor, 12 first-stage transistor, 13 final-stage transistor, 20 input matching circuit, 21 inter-stage matching circuit, 22 output matching circuit, 23 input matching circuit, 24 inter-stage matching circuit, 25 output matching circuit, 30, 31 90-degree delay circuit, 40 distribution circuit, 41 combining circuit, 50 first cavity, 50a cavity, 51 second cavity, 52 cavity, 60 resin substrate, 61 annular portion, 62, 62a partition portion, 70, 70a shield, 71 isolation improvement circuit, 80 heat sink, 100 first-stage transistor chip, 101 final-stage transistor chip, 102 first-stage transistor chip, 103 final-stage transistor chip, 105 transistor chip, 121 inter-stage matching circuit chip, 124 inter-stage matching circuit chip, 150, 151, 154, 155 capacitor, 160, 161, 162, 163 inductor, 170, 171, 172, 173 node, 180, 181 circuit, 201 - 210 wire, 300 inductor, 301 via hole, 302 metal layer, 303 resin layer, 310 electrode, 320 surface metal, 801 Doherty amplifier

Claims

1. A heat sink, a resin substrate provided on the heat sink, with a cavity formed to expose the heat sink, and formed by laminating a plurality of resin layers and a plurality of metal layers, a main amplifier provided in the cavity, a peak amplifier provided in the cavity, an inductor, characterized in that it comprises: the resin substrate has a partition portion separating at least a part of the main amplifier and at least a part of the peak amplifier, the plurality of metal layers of the partition portion are electrically connected to the heat sink, the inductor is provided on the partition portion and is electrically connected to the plurality of metal layers. A Doherty amplifier.

2. The Doherty amplifier according to claim 1, characterized in that the inductor is a chip inductor.

3. The Doherty amplifier according to claim 1 or 2, characterized in that the plurality of metal layers and the heat sink are electrically connected by a VIA hole formed in the resin substrate.

4. The main amplifier has a first main amplifier connected to the input terminal side of the Doherty amplifier, a second main amplifier connected to the output terminal side of the Doherty amplifier, and a first inter-stage matching circuit connecting the first main amplifier and the second main amplifier. The peak amplifier has a first peak amplifier connected to the input terminal side of the Doherty amplifier, a second peak amplifier connected to the output terminal side of the Doherty amplifier, and a second inter-stage matching circuit connecting the first peak amplifier and the second peak amplifier. The Doherty amplifier according to claim 1 or 2, characterized by having.

5. The resin substrate has an annular portion forming the cavity, The Doherty amplifier according to claim 4, characterized in that the partition portion extends from the annular portion between the second main amplifier and the second peak amplifier.

6. The Doherty amplifier according to claim 4, characterized in that the inductor separates a wire connecting the first inter-stage matching circuit and the second main amplifier and a wire connecting the second inter-stage matching circuit and the second peak amplifier.

7. The Doherty amplifier according to claim 4, characterized in that the inductor separates a wire connected to the output side of the second main amplifier and a wire connected to the output side of the second peak amplifier.

8. The Doherty amplifier according to claim 4, wherein the inductor is locally provided at a position adjacent to a wire connected to the second main amplifier or the second peak amplifier among the upper surfaces of the partition walls.

9. The main amplifier is composed of a plurality of chips, The Doherty amplifier according to claim 1 or 2, wherein the upper surface of the inductor is provided at a position higher than a wire connecting the plurality of chips.

10. The cavity is divided into a first cavity and a second cavity by the partition wall, The main amplifier is provided in the first cavity, The Doherty amplifier according to claim 1 or 2, wherein the peak amplifier is provided in the second cavity.

11. The Doherty amplifier according to claim 4, wherein the first main amplifier and the first peak amplifier are provided on one chip.

12. A parallel circuit in which a first inductor and a first capacitor are connected in parallel, A series circuit in which a second inductor and a second capacitor are connected in series, Comprising, One end of the parallel circuit is electrically connected to the heat sink, The other end of the parallel circuit is electrically connected to one end of the series circuit, The other end of the series circuit is electrically connected to the heat sink, The inductor includes the first inductor or the second inductor, The Doherty amplifier according to claim 1, wherein the resonance frequency of the parallel circuit is equal to the operating center frequency of the Doherty amplifier.

13. The main amplifier includes a first main amplifier connected to the input terminal side of the Doherty amplifier, a second main amplifier connected to the output terminal side of the Doherty amplifier, and a first inter-stage matching circuit connecting the first main amplifier and the second main amplifier. The Doherty amplifier according to claim 12, wherein the peak amplifier includes a first peak amplifier connected to the input terminal side of the Doherty amplifier, a second peak amplifier connected to the output terminal side of the Doherty amplifier, and a second inter-stage matching circuit connecting the first peak amplifier and the second peak amplifier.

14. The Doherty amplifier according to claim 13, wherein the inductor separates a wire connecting the first inter-stage matching circuit and the second main amplifier from a wire connecting the second inter-stage matching circuit and the second peak amplifier.

15. The first inductor and the second inductor are chip inductors, The Doherty amplifier according to any one of claims 12 to 14, wherein the first capacitor and the second capacitor are chip capacitors.

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