Method of manufacturing semiconductor device
The method of using a mask with varying shielding densities to ion-implant dopants in a semiconductor device's regions with different doping concentrations addresses the challenge of reducing reverse recovery loss, achieving improved performance without additional processes.
Patent Information
- Application Number
- JP2023222034
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-12-27
- Publication Date
- 2025-07-09
AI Technical Summary
Existing semiconductor devices face challenges in reducing reverse recovery loss without increasing the number of manufacturing processes.
A method for manufacturing a semiconductor device involving a semiconductor substrate with a transistor portion and a diode portion, utilizing a mask with varying shielding densities to ion-implant dopants, forming regions with different doping concentrations through controlled diffusion, and adjusting the width and area ratios of shielding and non-shielding portions to optimize conductivity type regions.
This approach effectively reduces reverse recovery loss by suppressing hole injection during reverse recovery, enhancing the device's performance without adding extra manufacturing steps.
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Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor device.
Background Art
[0002] Patent Document 1 describes a semiconductor device having a semiconductor substrate in which an IGBT region and a diode region are defined. In this semiconductor device, the impurity concentration of the anode layer in the diode region is lowered to suppress carriers accumulated in the diode during reflux and reduce recovery loss. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2021-52078
Summary of the Invention
Problems to be Solved by the Invention
[0003] It is desirable to provide a method for manufacturing a semiconductor device with reduced reverse recovery loss without increasing the number of processes.
Means for Solving the Problems
[0004] In a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device including a first-conductivity-type semiconductor substrate having a transistor portion and a diode portion and provided with a plurality of trench portions. The method includes forming a mask over the semiconductor substrate such that a shielding density of the mask with respect to a predetermined first region of the semiconductor substrate is lower than a shielding density of the mask with respect to a predetermined second region of the semiconductor substrate; ion-implanting a dopant for forming a second-conductivity-type region in a front surface of the semiconductor substrate into each of the first region and the second region; and diffusing the implanted dopant into the semiconductor substrate. The mask has a shielding portion and a non-shielding portion, a width of the shielding portion is 0.25 times or more and 0.8 times or less of a diffusion depth of the dopant, and a width of the non-shielding portion is 1 / 3 times or more and 1 time or less of the width of the shielding portion.
[0005] The mask may not have the shielding portion above the first region and may have at least the shielding portion above the second region.
[0006] The first region may correspond to the main region of the transistor portion, and the second region may correspond to the diode portion.
[0007] The second region may include a region corresponding to a boundary region closer to the diode portion than the main region.
[0008] The shielding portion may have a stripe shape extending in the trench array direction.
[0009] The width of the shielding portion may be 0.5 μm or more and 1.6 μm or less.
[0010] The step of ion implanting the dopant may include the step of ion implanting into each of the first region, the second region, and a predetermined third region of the semiconductor substrate. In a top view, the area ratio of the shielding portion in the first region may be lower than the area ratio of the shielding portion in the second region, and the area ratio of the shielding portion in the second region may be lower than the area ratio of the shielding portion in the third region.
[0011] The first region may correspond to an end region closer to the diode portion than the main region of the transistor portion, the second region may correspond to the main region, and the third region may correspond to the diode portion.
[0012] The doping concentration of the second conductivity type region formed in the end region may be 1.5 times or more and 2 times or less the doping concentration of the second conductivity type region formed in the main region.
[0013] The mask may not have the shielding portion above the first region and may have at least the shielding portion above the second region and the third region.
[0014] The first region corresponds to an end region on the diode portion side rather than the main region of the transistor portion. The second region and the third region correspond to regions included in the main region, and a region corresponding to the third region may be spaced apart from the end region more than a region corresponding to the second region.
[0015] The step of ion implanting the dopant may include a step of ion implanting a predetermined fourth region of the semiconductor substrate. In a top view, an area ratio of the shielding portion in the third region may be lower than an area ratio of the shielding portion in the fourth region, and the fourth region may be the diode portion.
[0016] A width in a trench arrangement direction of the end region may be 20 μm or more and 100 μm or less.
[0017] The shielding portion may have a stripe shape extending in a trench arrangement direction, and a width of the shielding portion may be smaller than that of the second region in the first region and may be smaller than that of the third region in the second region.
[0018] The first region may include a region corresponding to an extended region outside an end of the diode portion in a trench extending direction.
[0019] The plurality of trench portions may extend to the extended region.
[0020] The mask may be a resist.
[0021] A thickness of the shielding portion may be 0.3 μm or more and 3 μm or less.
[0022] Note that the above summary of the invention does not enumerate all features of the present invention. Also, sub - combinations of these feature groups can also be inventions.
Brief Description of Drawings
[0023]
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Mode for Carrying Out the Invention
[0024] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.
[0025] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "front", and the other side is referred to as "back". Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the front surface and the other surface is referred to as the back surface. The directions of "front" and "back" are not limited to the direction of gravity or the direction at the time of mounting the semiconductor device.
[0026] In this specification, when explaining technical matters, orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis may be used. The orthogonal coordinate axes only specify the relative positions of the components and do not limit a specific direction. For example, the Z-axis does not limit and indicate the height direction with respect to the ground. Note that the +Z-axis direction and the -Z-axis direction are directions opposite to each other. When described as the Z-axis direction without specifying positive or negative, it means directions parallel to the +Z-axis and -Z-axis.
[0027] In this specification, orthogonal axes parallel to the front surface and the back surface of the semiconductor substrate are defined as the X-axis and the Y-axis. Also, an axis perpendicular to the front surface and the back surface of the semiconductor substrate is defined as the Z-axis. In this specification, the direction of the Z-axis may sometimes be referred to as the depth direction. Also, in this specification, a direction parallel to the front surface and the back surface of the semiconductor substrate, including the X-axis and the Y-axis, may sometimes be referred to as the horizontal direction.
[0028] In this specification, when referred to as "identical" or "equal", it may include cases having errors due to manufacturing variations or the like. The error is, for example, within 10%.
[0029] When described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of P type or N type. When described as P− type or N− type, it means that the doping concentration is lower than that of P type or N type. Also, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. In this specification, an example in which the first conductivity type is N type and the second conductivity type is P type will be described, but the first conductivity type may be P type and the second conductivity type may be N type.
[0030] When the concentration distribution of donors, acceptors, or net doping has a peak, the peak value may be taken as the concentration of donors, acceptors, or net doping in the region. In cases where the concentration of donors, acceptors, or net doping is substantially uniform, etc., the average value of the concentration of donors, acceptors, or net doping in the region may be taken as the concentration of donors, acceptors, or net doping.
[0031] FIG. 1 is a diagram showing an example of the front surface of the semiconductor device 100 according to Example 1. In FIG. 1, the positions where each member is projected onto the front surface of the semiconductor substrate 10 are shown. In FIG. 1, only some members of the semiconductor device 100 are shown, and some members are omitted.
[0032] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has side edges 102 in a top view. When simply referred to as a top view in this specification, it means viewing from the front surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of side edges 102 facing each other in a top view. In FIG. 1, the X axis and the Y axis are parallel to any of the side edges 102. Also, the Z axis is perpendicular to the front surface of the semiconductor substrate 10.
[0033] An active region 160 is provided in the semiconductor substrate 10. The active region 160 is a region where a main current flows in the depth direction between the front surface and the back surface of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode is provided above the active region 160, but is omitted in FIG. 1.
[0034] At least one of a transistor section 70 including transistor elements such as IGBTs and a diode section 80 including diode elements such as a freewheeling diode (FWD) is provided in the active region 160. In the example of FIG. 1, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front surface of the semiconductor substrate 10. In other examples, only one of the transistor section 70 and the diode section 80 may be provided in the active region 160.
[0035] In FIG. 1, the symbol "I" is attached to the region where the transistor section 70 is arranged, and the symbol "F" is attached to the region where the diode section 80 is arranged. In this specification, the direction perpendicular to the arrangement direction in the top view may be referred to as the stretching direction (the Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a length in the stretching direction. That is, the length of the transistor section 70 in the Y-axis direction is larger than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is larger than the width in the X-axis direction. The stretching direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.
[0036] The diode portion 80 has an N+-type cathode region in a region in contact with the back surface of the semiconductor substrate 10. In this specification, the region where the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is a region that overlaps the cathode region in a top view. A P+-type collector region may be provided in a region other than the cathode region on the back surface of the semiconductor substrate 10. In this specification, the extended region 81 obtained by extending the diode portion 80 in the Y-axis direction up to the gate runner described later may also be included in the diode portion 80. A collector region is provided on the back surface of the extended region 81.
[0037] The transistor portion 70 has a P+-type collector region in a region in contact with the back surface of the semiconductor substrate 10. Further, in the transistor portion 70, a gate structure including an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film is periodically arranged on the front surface side of the semiconductor substrate 10.
[0038] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. As an example, the semiconductor device 100 shown in FIG. 1 has a gate pad G, but this is merely an example. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is arranged in the vicinity of the end side 102. The vicinity of the end side 102 refers to a region between the end side 102 in a top view and the emitter electrode. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via a wiring such as a wire.
[0039] A gate potential is applied to the gate pad G. The gate pad G is electrically connected to the conductive portion of the gate trench portion of the active region 160. The semiconductor device 100 includes a gate runner that connects the gate pad G and the gate trench portion.
[0040] The gate runner 48 is disposed between the active region 160 and the edge 102 of the semiconductor substrate 10 in a top view. The gate runner 48 in this example surrounds the active region 160 in a top view. The region surrounded by the gate runner in a top view may be regarded as the active region 160. The gate runner 48 may be formed of impurity-doped polysilicon or the like.
[0041] The semiconductor device 100 in this example includes an edge termination structure portion 120 between the active region 160 and the edge 102. The edge termination structure portion 120 in this example is disposed between the gate runner 48 and the edge 102. The edge termination structure portion 120 alleviates the electric field concentration on the front surface side of the semiconductor substrate 10. The edge termination structure portion 120 may have a plurality of guard rings. The guard ring is a P-type region in contact with the front surface of the semiconductor substrate 10. By providing a plurality of guard rings, the depletion layer on the front surface side of the active region 160 can be extended outward, and the breakdown voltage of the semiconductor device 100 can be improved. The edge termination structure portion 120 may further include at least one of a field plate and RESURF provided annularly surrounding the active region 160.
[0042] Further, the semiconductor device 100 may include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting portion (not shown) which operates in the same manner as the transistor portion provided in the active region 160.
[0043] FIG. 2 is an enlarged view of region A in FIG. 1. Region A includes the transistor portion 70 and the diode portion 80.
[0044] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, an anode region 84, and a contact region 15 provided inside the front surface side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. Further, the semiconductor device 100 of this example includes an emitter electrode 52 provided above the front surface of the semiconductor substrate 10. The emitter electrode 52 and the gate runner 48 are provided separately from each other.
[0045] An interlayer insulating film is provided between the emitter electrode 52, the gate runner 48, and the front surface of the semiconductor substrate 10, but is omitted in FIG. 2. Contact holes 49, 54, and 56 are provided through the interlayer insulating film of this example. In FIG. 2, each contact hole is hatched with oblique lines.
[0046] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, the anode region 84, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, the anode region 84, and the base region 14 on the front surface of the semiconductor substrate 10 through the contact hole 54. Further, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through the contact hole 56. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.
[0047] The gate runner 48 is connected to the gate conductive portion within the gate trench portion 40 on the front surface of the semiconductor substrate. The gate runner 48 is not connected to the dummy conductive portion within the dummy trench portion 30. The gate runner 48 in this example is provided from below the contact hole 49 to the tip of the gate trench portion 40. An insulating film such as an oxide film is provided between the gate runner 48 and the front surface of the semiconductor substrate 10. At the tip of the gate trench portion 40, the gate conductive portion is exposed on the front surface of the semiconductor substrate. The gate trench portion 40 contacts the gate runner 48 at the exposed portion of the gate conductive portion. The gate runner 48 may be formed simultaneously with the deposition of the gate conductive portion.
[0048] The emitter electrode 52 is formed of a material containing metal. For example, at least a part of the region of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium, a titanium compound, or the like under the region formed of aluminum or the like. Further, each electrode may have a plug formed of tungsten or the like within the contact hole. Under the contact hole of the plug, there may be a P++ type plug region 17 having a higher doping concentration than the contact region 15. The plug region 17 improves the latch-up tolerance by improving the contact resistance between the barrier metal and the contact region 15.
[0049] The well region 11 is provided overlapping the gate runner 48. The well region 11 is also provided extending with a predetermined width in a range where it does not overlap the gate runner 48. The well region 11 in this example is provided away from the gate runner 48 side from the Y-axis direction end of the contact hole 54. The well region 11 is a region of the second conductivity type having a higher doping concentration than the base region 14. The base region 14 in this example is P-type, and the well region 11 is P+-type. Further, the well region 11 is formed from the front surface of the semiconductor substrate 10 to a position deeper than the lower end of the base region 14.
[0050] Each of the transistor portion 70 and the diode portion 80 has a plurality of trench portions arranged in the array direction. In the transistor portion 70 of this example, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately provided along the array direction. In the diode portion 80 of this example, a plurality of dummy trench portions 30 are provided along the array direction. The diode portion 80 of this example is not provided with a gate trench portion 40.
[0051] The gate trench portion 40 of this example may have two straight portions 39 (portions of the trench that are linear along the extending direction) extending along an extending direction perpendicular to the array direction, and a tip portion 41 connecting the two straight portions 39. The extending direction in FIG. 2 is the Y-axis direction.
[0052] At least a part of the tip portion 41 is preferably provided in a curved shape in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, the electric field concentration at the ends of the straight portions 39 can be alleviated.
[0053] In the transistor portion 70, the dummy trench portion 30 is provided between the respective straight portions 39 of the gate trench portion 40. One dummy trench portion 30 may be provided between the respective straight portions 39, or a plurality of dummy trench portions 30 may be provided. The dummy trench portion 30 may have a linear shape extending in the extending direction, and may have a straight portion 29 and a tip portion 31, similar to the gate trench portion 40. The semiconductor device 100 shown in FIG. 2 includes both a linear dummy trench portion 30 without a tip portion 31 and a dummy trench portion 30 with a tip portion 31.
[0054] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The Y-axis direction ends of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 in a top view. That is, at the Y-axis direction ends of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 11. Thereby, the electric field concentration at the bottom of each trench portion can be alleviated.
[0055] In the array direction, mesa portions are provided between the trench portions. The mesa portion refers to a region sandwiched by the trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the front surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion in this example is sandwiched by the trench portions adjacent in the X-axis direction and is provided to extend in the extending direction (Y-axis direction) along the trench on the front surface of the semiconductor substrate 10. In this example, the mesa portion 60 is provided in the transistor portion 70, and the mesa portion 61 is provided in the diode portion 80. When simply referred to as the mesa portion in this specification, it refers to each of the mesa portion 60 and the mesa portion 61.
[0056] The mesa portion 60 is provided adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40 in the transistor portion 70. The mesa portion 60 has the well region 11, the emitter region 12, and the contact region 15 on the front surface of the semiconductor substrate 10. The mesa portion 61 is provided adjacent to the dummy trench portion 30 in the diode portion 80. The mesa portion 61 has the well region 11 and the anode region 84 on the front surface of the semiconductor substrate 10.
[0057] The base region 14 is a region provided on the front surface side of the semiconductor substrate 10 in the transistor portion 70. The base region 14 in this example is P-type as an example.
[0058] On the front surface of each mesa portion 60, at least one of an emitter region 12 of a first conductivity type and a contact region 15 of a second conductivity type may be provided. The emitter region 12 in this example is of N+ type, and the contact region 15 is of P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction.
[0059] The mesa portion 60 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. A contact region 15 exposed on the front surface of the semiconductor substrate 10 may be provided in the mesa portion 60 in contact with the gate trench portion 40.
[0060] Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion in the X-axis direction to the other trench portion. As an example, the contact region 15 and the emitter region 12 of the mesa portion 60 are alternately arranged along the extending direction (Y-axis direction) of the trench portion.
[0061] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extending direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched by the emitter regions 12.
[0062] On the front surface of the mesa portion 61, an anode region 84 is provided. On the front surface of the mesa portion 61, an emitter region 12 is not provided. On the front surface of the mesa portion 61, a contact region 15 may be provided. The anode region 84 in this example is P--type as an example. The doping concentration of the anode region 84 in this example is lower than the doping concentration of the base region 14. In this example, by lowering the doping concentration of the anode region 84, hole injection during reverse recovery can be suppressed. However, in other examples, the doping concentration of the anode region 84 may be the same as the doping concentration of the base region 14. In this case, the base region 14 and the anode region 84 can be formed by the same process.
[0063] Above each mesa portion, a contact hole 54 is provided. The contact hole 54 is provided above each region of the emitter region 12 and the contact region 15 in the mesa portion 60 of the transistor portion 70. The contact hole 54 is also provided above the anode region 84 in the mesa portion 61 of the diode portion 80. The contact hole 54 may be disposed at the center in the arrangement direction (X-axis direction) of each mesa portion. None of the contact holes 54 are provided above the well regions 11 provided at both ends in the Y-axis direction. In this way, the interlayer insulating film is provided with one or more contact holes 54. The contact hole 54 in this example may be provided to extend in the Y-axis direction.
[0064] In the diode portion 80, an N+-type cathode region 82 is provided in a region adjacent to the back surface of the semiconductor substrate 10. On the back surface of the semiconductor substrate 10, a P+-type collector region 22 may be provided in a region where the cathode region 82 is not provided. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80.
[0065] The cathode region 82 is arranged away from the well region 11 in the Y-axis direction. Thereby, a distance between the P-type region (well region 11) that is relatively highly doped and formed to a deep position and the cathode region 82 can be secured, and the breakdown voltage can be improved. The end portion of the cathode region 82 in the Y-axis direction in this example is arranged away from the well region 11 more than the end portion of the contact hole 54 in the Y-axis direction. In other examples, the end portion of the cathode region 82 in the Y-axis direction may be arranged between the well region 11 and the contact hole 54.
[0066] The semiconductor device 100 may have a boundary region 90 provided between the transistor portion 70 and the diode portion 80. Since the boundary region 90 is a region where the collector region 22 is provided on the back surface of the semiconductor substrate 10, it may be a part of the transistor portion 70. However, since the boundary region 90 has a front surface structure different from other regions of the transistor portion 70, it will be described separately from the transistor portion 70 in this specification.
[0067] An anode region 84 is provided on the front surface of the mesa portion 60 of the boundary region 90. However, a contact region 15 may be provided extending in the Y-axis direction on the front surface of the mesa portion 60 closest to the transistor portion 70 side. The boundary region 90 has a dummy trench portion 30 and does not have a gate trench portion 40. By providing the boundary region 90, the influence of holes injected from the contact region 15 of the transistor portion 70 during the reverse recovery of the diode portion 80 can be reduced.
[0068] FIG. 3A is a diagram showing an example of the a-a' cross-section in FIG. 2. FIG. 3B is a diagram showing an example of the b-b' cross-section in FIG. 2. The a-a' cross-section is an XZ plane passing through the contact region 15, the base region 14, the anode region 84, the gate trench portion 40, and the dummy trench portion 30. The semiconductor device 100 in this example has the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in the a-a' cross-section.
[0069] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is an insulating film such as silicate glass doped with impurities such as boron or phosphorus. The interlayer insulating film 38 may be in contact with the front surface 21, and another film such as an oxide film may be provided between the interlayer insulating film 38 and the front surface 21. The interlayer insulating film 38 is provided with the contact hole 54 described in FIG. 2.
[0070] The emitter electrode 52 is provided on the front surface 21 of the semiconductor substrate 10 and the front surface of the interlayer insulating film 38. The emitter electrode 52 is electrically connected to the front surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. A contact plug such as tungsten (W) may be provided inside the contact hole 54. The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a material containing metal.
[0071] The semiconductor substrate 10 may be a silicon substrate, may be a silicon carbide substrate, or may be a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate.
[0072] The semiconductor substrate 10 includes a drift region 18 of the first conductivity type. The drift region 18 in this example is N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doping regions being provided.
[0073] One or more accumulation regions 16 may be provided in the Z-axis direction above the drift region 18. The accumulation region 16 is a region where the same dopant as the drift region 18 accumulates at a higher concentration than the drift region 18. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced.
[0074] In the transistor section 70, an emitter region 12 is provided in contact with the front surface 21 of the semiconductor substrate 10 above the base region 14. The emitter region 12 is provided in contact with the gate trench portion 40. The doping concentration of the emitter region 12 is higher than that of the drift region 18. The dopant of the emitter region 12 is, for example, arsenic (As), phosphorus (P), antimony (Sb), or the like.
[0075] A buffer region 20 of the first conductivity type may be provided below the drift region 18. The buffer region 20 in this example is of the N type. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the back surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.
[0076] In the diode section 80, a cathode region 82 is provided below the buffer region 20. The cathode region 82 may be provided at the same depth as the collector region 22 of the transistor section 70. The diode section 80 may function as a freewheeling diode (FWD) that conducts a reverse-directional freewheeling current when the transistor section 70 turns off.
[0077] In the transistor section 70, a collector region 22 is provided below the buffer region 20. The collector region 22 may be provided in contact with the cathode region 82 on the back surface 23 of the semiconductor substrate 10.
[0078] The semiconductor substrate 10 is provided with a gate trench portion 40 and a dummy trench portion 30. The gate trench portion 40 and the dummy trench portion 30 are provided so as to penetrate a doping region such as the base region 14 or the anode region 84 from the front surface 21 of the semiconductor substrate 10 and reach the drift region 18. The fact that the trench portion penetrates the doping region is not limited to the case where the trench portion is formed in the order of forming the doping region and then the trench portion. Even in the case where a doping region is formed between the trench portions after the trench portions are formed, it is included in the case where the trench portion penetrates the doping region.
[0079] The gate trench portion 40 has a gate trench provided on the front surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 inside the gate trench. The front surface of the gate conductive portion 44 may be in the same XY plane as the front surface 21. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a semiconductor such as polysilicon doped with impurities.
[0080] The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction of the semiconductor substrate 10. The gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21. When a predetermined voltage is applied to the gate conductive portion 44, a channel due to an inversion layer of electrons is formed in the surface layer of the interface of the base region 14 in contact with the gate trench.
[0081] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the XZ cross-section. The dummy trench portion 30 has a dummy trench provided on the front surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy insulating film 32 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy insulating film 32 within the dummy trench. The front surface of the dummy conductive portion 34 may be in the same XY plane as the front surface 21 of the semiconductor substrate 10. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.
[0082] The gate trench portion 40 and the dummy trench portion 30 in this example are covered by the interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. Note that the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be convex curved surfaces (curved in cross-section) facing downward.
[0083] When the diode portion 80 conducts, an electron current flows from the cathode region 82 to the anode region 84. When the electron current reaches the anode region 84, conductivity modulation occurs, and a hole current flows from the anode region 84. Also, due to the electron current diffused from the cathode region 82, hole injection is promoted from the contact region 15 of the transistor portion 70, and the hole density of the semiconductor substrate 10 increases. As a result, the time until the holes disappear when the diode portion 80 turns off becomes longer, so the reverse recovery peak current increases and the reverse recovery loss increases.
[0084] As a technique for suppressing such hole current, a technique of providing a lifetime control region containing a lifetime killer on the front surface side of a semiconductor substrate is known. The lifetime killer is, for example, an electron beam injected into the entire semiconductor substrate, helium, an electron beam or a proton injected at a predetermined depth, etc., and the lifetime control region is crystal defects formed inside the semiconductor substrate by injecting the lifetime killer. The lifetime control region promotes the recombination disappearance of electrons and holes generated when the diode portion conducts, and reduces the reverse recovery loss.
[0085] In this example, a lifetime control region containing a lifetime killer is not provided on the front surface 21 side of the semiconductor substrate 10. In this example, by making the doping concentration of the anode region 84 lower than the doping concentration of the base region 14, even if no lifetime control region is provided, hole injection during reverse recovery can be suppressed.
[0086] FIG. 4 is a flowchart showing an example of a manufacturing method of the semiconductor device 100 according to the first embodiment. FIG. 4 mainly shows a dopant injection process and an annealing process for forming the base region 14 and the anode region 84. The base region 14 and the anode region 84 are an example of a second conductivity type region.
[0087] In this example, a plurality of trench portions are formed in the N-type semiconductor substrate 10 (step S100), and then a mask is formed above the semiconductor substrate 10 (step S110). Here, the semiconductor substrate 10 has a predetermined first region and second region. The mask is formed such that the shielding density for the second region is higher than the shielding density for the first region.
[0088] Next, a P-type dopant is ion-injected into each of the first region and the second region through the mask, and then the mask is removed (step S120). The P-type dopant is boron, for example.
[0089] Thereafter, an annealing process is performed (step S130). As a result, the implanted P-type dopant thermally diffuses in the semiconductor substrate 10, and a second conductivity type region with a high doping concentration is formed in the first region with a low shielding density, and a second conductivity type region with a low doping concentration is formed in the second region with a high shielding density. In this way, by using a mask having different shielding densities for the predetermined first region and second region in the semiconductor substrate 10, second conductivity type regions with different doping concentrations can be formed in one process.
[0090] Next, the manufacturing method of the semiconductor device 100 described with reference to FIG. 4 will be described again with reference to the top view and cross-sectional view of the semiconductor substrate 10. FIGS. 5A and 5B are diagrams showing an example of the manufacturing method of the semiconductor device 100 according to the first embodiment. FIGS. 5A and 5B show an example of a schematic top view of the semiconductor substrate 10.
[0091] In step S100, a gate trench portion 40 and a dummy trench portion 30 are formed in the semiconductor substrate 10. The semiconductor substrate 10 has a predetermined first region R1 and second region R2. The first region R1 is a region into which a dopant is implanted so as to have a higher doping concentration than the second region R2. The first region R1 in this example is a region where the transistor portion 70 is formed, and the second region R2 in this example is a region where the diode portion 80 is formed. The second region R2 may further include a region where the boundary region 90 is formed.
[0092] In step S110, a mask 62 is formed above the semiconductor substrate 10. The mask 62 in this example is a resist mask. The mask 62 has a shielding portion 63 and a non-shielding portion 64 formed in a stripe shape extending in the X-axis direction. The shielding density by the shielding portion 63 in this example is proportional to the total area ratio of the shielding portion 63. In other words, in a top view of the upper surface of the semiconductor substrate 10, the area ratio of the shielding portion 63 in the first region R1 is lower than the area ratio of the shielding portion 63 in the second region R2. Therefore, by adjusting the width of the shielding portion 63 and the width of the non-shielding portion 64, the doping concentration of the formed second conductivity type region can be adjusted. Only the non-shielding portion 64 is formed above the first region R1 in this example, and the shielding portion 63 is not formed. Above the second region R2 in this example, a plurality of shielding portions 63 and a plurality of non-shielding portions 64 are formed. That is, in the first region R1 of this example, the entire front surface 21 of the semiconductor substrate 10 is exposed, and in the second region R2 of this example, the front surface 21 of the semiconductor substrate 10 is partially exposed through the non-shielding portion 64.
[0093] In step S120, a P-type dopant is ion-implanted into each of the first region R1 and the second region R2 through the mask 62. That is, the P-type dopant is implanted into the entire surface of the first region and the portion corresponding to the non-shielding portion 64 of the second region R2. Then, the mask 62 is removed. FIG. 5B shows the implanted region 65 into which the dopant is implanted with diagonal hatching to distinguish it from the non-implanted region 66. Then, in step S130, an annealing process is performed to thermally diffuse the implanted P-type dopant in the semiconductor substrate 10 to form a second conductivity type region.
[0094] In the second region R2, the P-type dopant implanted into the front surface 21 of the semiconductor substrate 10 through the non-shielding portion 64 thermally diffuses. In this way, in the second region R2, a second conductivity type region (anode region 84) with a lower doping concentration than the second conductivity type region (base region 14) of the first region R1 can be formed.
[0095] FIG. 6A and FIG. 6B are diagrams showing an example of a method for manufacturing the semiconductor device 100 according to Embodiment 1. FIG. 6A and FIG. 6B show the c-c' cross section in FIG. 5A. The c-c' cross section is an example of a YZ plane in the second region R2 where the mask 62 is formed.
[0096] A plurality of trench portions are formed in the semiconductor substrate 10 (not shown), and then a mask 62 is formed above the semiconductor substrate 10 (step S110). In the Y-axis direction, the shielding portion 63 has a width Wm, and the non-shielding portion 64 has a width Ws. The width Wm of the shielding portion 63 in this example is 0.25 times or more and 0.8 times or less of the diffusion depth Xj of the dopant described later, and the width Ws of the non-shielding portion 64 is 1 / 3 times or more and 1 time or less of the width Wm of the shielding portion 63. As an example, the width Wm of the shielding portion 63 is 0.5 μm or more and 1.6 μm or less.
[0097] Next, a P-type dopant is ion-implanted through the mask 62, and then the mask 62 is removed (step S120). FIG. 6B shows the implanted region 65 into which the dopant has been implanted with hatched lines to distinguish it from the non-implanted region 66. Thereafter, an annealing process is performed (step S130). As a result, the implanted P-type dopant thermally diffuses in the semiconductor substrate 10 to form a second conductivity type region. Here, the diffusion depth Xj of the dopant refers to the distance from the front surface 21 of the semiconductor substrate 10 to the lower end of the second conductivity type region in the Z-axis direction.
[0098] In the second region R2, the dopant is implanted only into the front surface 21 of the semiconductor substrate 10 exposed through the non-shielding portion 64, and no dopant is implanted below the shielding portion 63. However, due to the annealing process, the implanted dopant thermally diffuses, and a second conductivity type region is formed over the entire second region R2.
[0099] In this example, the shielding portion 63 and the non-shielding portion 64 each have the width Wm and the width Ws within the numerical ranges described above, in relation to the diffusion depth Xj of the dopant. Thereby, a second conductivity type region having a uniform profile can be formed. Also, by adjusting the width Wm of the shielding portion 63 and the width Ws of the non-shielding portion 64 within the numerical ranges described above, a second conductivity type region having a desired doping concentration can be formed.
[0100] Also, the thickness Tm of the shielding portion 63 in this example is 0.3 μm or more and 3 μm or less. Thereby, the injection of the dopant below the shielding portion 63 is shielded without preventing the dopant injection through the non-shielding portion 64.
[0101] Figs. 7A to 7D are diagrams showing an example of a method for manufacturing the semiconductor device 100 according to Example 1. Figs. 7A to 7D respectively show a comparison of the d-d' cross-section and the e-e' cross-section in Fig. 5A. The d-d' cross-section and the e-e' cross-section are examples of XZ planes passing through a plurality of trench portions in the first region R1 and the second region R2.
[0102] As shown in Fig. 7A, in step S100, a gate trench portion 40 and a dummy trench portion 30 are formed in the semiconductor substrate 10, and in step S110, a mask 62 is formed above the semiconductor substrate 10. In the second region R2, the d-d' cross-section passes through the shielding portion 63, and the e-e' cross-section passes through the non-shielding portion 64.
[0103] Next, as shown in Figs. 7B and 7C, in step S120, a P-type dopant is ion-implanted into each of the first region R1 and the second region R2, and then the mask 62 is removed. Fig. 7C shows the implanted region 65 into which the dopant has been implanted with diagonal hatching to distinguish it from the non-implanted region 66. As shown by the d-d' cross-section, below the shielding portion 63 is the non-implanted region 66 into which the P-type dopant is not implanted, and as shown by the e-e' cross-section, below the non-shielding portion 64 is the implanted region 65 into which the P-type dopant has been implanted.
[0104] Thereafter, as shown in FIG. 7D, in step S130, an annealing process is performed to thermally diffuse the implanted P-type dopant in the semiconductor substrate 10 to form a second conductivity type region. In the second region R2, the dopant thermally diffuses from the implanted region 65 to the non-implanted region 66, and a second conductivity type region having a uniform profile is formed.
[0105] Thus, according to the method of manufacturing the semiconductor device 100 according to this example, by using masks having different shielding densities for the first region and the second region of the semiconductor substrate 10, second conductivity type regions having different doping concentrations can be formed in one process.
[0106] FIG. 8 is a diagram showing an example of the front surface of the semiconductor device 200 according to Example 2. In this example, the transistor portion 70 is different from the semiconductor device 100 according to Example 1 in that it has a main region 71 and an end region 72. Here, elements common to the semiconductor device 100 are denoted by the same reference numerals and the description thereof is omitted, and the description will be centered on the differences from the semiconductor device 100.
[0107] The transistor portion 70 of this example has a main region 71 provided apart from the diode portion 80 in a top view of the semiconductor substrate 10, and an end region 72 provided at an end portion on the diode portion 80 side. The end region 72 of this example is provided adjacent to the boundary region 90. The width of the end region 72 in the X-axis direction is 20 μm or more and 100 μm or less.
[0108] The doping concentration of the base region 14 (base region 14A in FIG. 8) of the end region 72 is higher than the doping concentration of the base region 14 (base region 14B in FIG. 8) of the main region 71. The doping concentration of the base region 14A is 1.5 times or more and 2 times or less the doping concentration of the base region 14B. When the transistor portion 70 is turned on, an electron current flows from the emitter region 12 of the transistor portion 70 toward the cathode region 82 of the diode portion 80, and then, a problem operation called snapback occurs in which conductivity modulation is delayed and holes are injected from the collector region 22.
[0109] In the semiconductor device 200 of this example, by making the doping concentration of the base region 14A in the end region 72 of the transistor portion 70 higher than the doping concentration of the base region 14B in the main region 71, the end region 72 becomes less likely to perform transistor operation, and snapback can be suppressed.
[0110] FIG. 9 is a diagram showing an example of a manufacturing method of the semiconductor device 200 according to Example 2. FIG. 9 shows a step S110 of forming a mask 62 above the semiconductor substrate 10. The manufacturing method of the semiconductor device 200 of this example has steps S100 to S130 in the same manner as the manufacturing method of the semiconductor device 100 shown in FIG. 4, but the configuration of the mask 62 is different.
[0111] The semiconductor substrate 10 of this example has a predetermined first region R1, second region R2, and third region R3. The first region R1 is a region into which a dopant is implanted so as to have a higher doping concentration than the second region R2, and the second region R2 is a region into which a dopant is implanted so as to have a higher doping concentration than the third region R3. The first region R1 of this example is a region where the end region 72 of the transistor portion 70 is formed, the second region R2 of this example is a region where the main region 71 of the transistor portion 70 is formed, and the third region R3 of this example is a region where the diode portion 80 is formed. The third region R3 may further include a region where the boundary region 90 is formed.
[0112] The width of the shielding portion 63 is smaller than that of the second region R2 in the first region R1 and smaller than that of the third region R3 in the second region R2. Therefore, in a top view of the semiconductor substrate 10, the area ratio of the shielding portion 63 in the first region R1 is lower than the area ratio of the shielding portion 63 in the second region R2, and the area ratio of the shielding portion 63 in the second region R2 is lower than the area ratio of the shielding portion 63 in the third region R3. Above the first region R1 of this example, no shielding portion 63 is formed, and only the non-shielding portion 64 is formed. Above the second region R2 and the third region R3, a plurality of shielding portions 63 and a plurality of non-shielding portions 64 are formed, and the width of the shielding portion 63 is smaller than the width of the shielding portion 63 formed in the third region R3. The area ratio of the shielding portion 63 in the third region R3 may be 1.5 times or more and 3 times or less the area ratio of the shielding portion 63 in the second region R2.
[0113] In step S120, a P-type dopant is ion-implanted into each of the first region R1, the second region R2, and the third region R3, and then thermally diffused by the annealing process in step S130. Since the shielding density by the mask 62 is proportional to the total area ratio of the shielding portions 63, a second conductivity type region (base region 14A) having a higher doping concentration than the second conductivity type region (base region 14B) of the second region R2 can be formed in the first region R1, and a second conductivity type region (anode region 84) having a lower doping concentration than the second conductivity type region (base region 14B) of the second region R2 can be formed in the third region R3.
[0114] Thus, according to the manufacturing method of the semiconductor device 200 of this example, by making the doping concentration of the base region 14A in the end region 72 of the transistor portion 70 higher than the doping concentration of the base region 14B in the main region 71, the end region 72 becomes less likely to perform transistor operation, and snapback can be suppressed.
[0115] FIGS. 10A and 10B are diagrams showing another example of the manufacturing method of the semiconductor device 200 according to the second embodiment. FIGS. 10A and 10B show a configuration of the mask 62 different from that in FIG. 9.
[0116] The semiconductor substrate 10 of this example has a predetermined first region R1, second region R2, third region R3, and fourth region R4. The first region R1 is a region into which a dopant is implanted so as to have a higher doping concentration than the second region R2. The second region R2 is a region into which a dopant is implanted so as to have a higher doping concentration than the third region R3. The third region R3 is a region into which a dopant is implanted so as to have a higher doping concentration than the fourth region R4. The first region R1 of this example is a region where the end region 72 of the transistor portion 70 is formed. Both the second region R2 and the third region R3 of this example correspond to regions included in the main region 71 of the transistor portion 70, and the region corresponding to the third region R3 is separated from the region corresponding to the second region R2 on the side of the end region 72. The fourth region R4 of this example is a region where the diode portion 80 is formed. The fourth region R4 may further include a region where the boundary region 90 is formed.
[0117] As shown in FIG. 10A, the width of each shielding portion 63 increases in the order of the first region R1, the second region R2, the third region R3, and the fourth region R4. Therefore, as described above, the doping concentration of the formed p-type region decreases in the order of the first region R1, the second region R2, the third region R3, and the fourth region R4.
[0118] Alternatively, as shown in FIG. 10B, the widths of the respective shielding portions 63 are equal in the first region R1, the second region R2, and the third region R3, and are larger than this in the fourth region R4. The number per unit area of the shielding portions 63 is the largest in the first region R1 and the fourth region R4, and decreases in the order of the second region R2 and the third region R3. Therefore, as in FIG. 10A, the doping concentration of the formed p-type region decreases in the order of the first region R1, the second region R2, the third region R3, and the fourth region R4.
[0119] In FIG. 10A or FIG. 10B, the area ratio of the shielding portion 63 in the third region R3 may be 1.2 times or more and 2 times or less the area ratio of the shielding portion 63 in the second region R2. The area ratio of the shielding portion 63 in the fourth region R4 may be 1.5 times or more and 3 times or less the area ratio of the shielding portion 63 in the third region R3.
[0120] In this example, in the transistor portion 70, the base region 14 having three different doping concentrations is formed, but the present invention is not limited to this, and the base region 14 having more than three different doping concentrations can be formed. As described above, by changing the shielding density by the mask 62 in each region, the doping concentration of the second conductivity type region (base region 14) formed can be gradually increased from the main region 71 to the end region 72 of the transistor portion 70, and snapback can be effectively suppressed.
[0121] FIG. 11A is a diagram showing an example of the front surface of the semiconductor device 300 according to the third embodiment. FIG. 11B is a diagram showing an example of the f-f' cross section in FIG. 11A. The semiconductor device 300 of this example is different from the semiconductor device 100 according to the first embodiment in the range where the base region 14, the anode region 84, and the well region 11 are provided. Here, the same reference numerals are given to the elements common to the semiconductor device 100 and the description thereof is omitted, and the description will be centered on the differences from the semiconductor device 100.
[0122] The anode region 84 of this example includes an anode region 84A and an anode region 84B. The anode region 84A is provided to extend to the outer periphery of the active region 160 on the end side in the Y-axis direction with respect to the anode region 84B. The doping concentration of the anode region 84A is higher than the doping concentration of the anode region 84B. As an example, the anode region 84A is P-type, and the anode region 84B is P--type. The doping concentration of the anode region 84A may be the same as the doping concentration of the base region 14. The boundary region 90 of this example also has the anode region 84A in the same manner as the diode portion 80.
[0123] The semiconductor device 300 of this example does not have the well region 11. Instead, in the transistor portion 70, the base region 14 is provided to extend to the outer periphery of the active region 160, and in the boundary region 90, the anode region 84 (anode region 84A) is provided to extend to the outer periphery of the active region 160.
[0124] On the front surface of the extension region 81 where the diode portion 80 is extended in the Y-axis direction, an anode region 84A is provided. The dummy trench portion 30 of the diode portion 80 is provided so as to extend to the extension region 81. Note that the boundary between the anode region 84A and the anode region 84B may or may not coincide with the boundary between the cathode region 82 and the collector region 22 provided on the back surface 23 of the semiconductor substrate 10 (that is, the boundary between the extension region 81 and the diode portion 80).
[0125] During the reverse recovery of the diode portion 80, holes accumulated in the edge termination structure portion 120 concentrate at the end of the diode portion 80, so the end of the contact hole 54 is likely to be damaged. In the semiconductor device 300 of this example, an anode region 84B with a low doping concentration is provided in the diode portion 80, and an anode region 84A with a higher doping concentration than the anode region 84B is provided in the extension region 81, thereby ensuring a desired doping concentration while ensuring the reverse recovery tolerance at the end. As a result, the process of having the P+-type well region 11 can be omitted.
[0126] FIG. 12 is a diagram showing an example of a method for manufacturing the semiconductor device 300 according to the third embodiment. The method for manufacturing the semiconductor device 300 of this example has steps S100 to S130 in the same manner as the method for manufacturing the semiconductor device 100 shown in FIG. 4, but the configurations of the first region R1 and the second region R2 predetermined in the semiconductor substrate 10 are different. FIG. 12 schematically shows the configurations of the first region R1 and the second region R2 of this example.
[0127] The first region R1 includes a region where the transistor portion 70 is formed and a region where the extension region 81 is formed. The second region R2 of this example is a region where the diode portion 80 is formed. The second region R2 may further include a region where the boundary region 90 is formed. The second region R2 is surrounded by the first region R1 in a top view of the semiconductor substrate 10.
[0128] By varying the shielding density of the masks for the first region R1 and the second region R2, varying the doping concentration of the formed second conductivity type regions is common to Example 1. In the first region R1 of this example, a base region 14 and an anode region 84A are formed, and in the second region R2 of this example, an anode region 84B is formed. Thus, by using masks having different shielding densities for the first region and the second region predetermined in the semiconductor substrate 10, second conductivity type regions having different doping concentrations can be formed in one step.
[0129] Note that FIGS. 10A and 10B vary the doping concentration of the second conductivity type regions formed in each region by changing the width of the shielding portion 63 or the number per unit area in the X-axis direction. In this example, in the Y-axis direction, the doping concentration of the anode region 84 of the extension region 81 may be changed by changing the width of the shielding portion 63 or the number per unit area.
[0130] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.
[0131] It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not explicitly stated as "earlier" or "preceding", etc., and unless the output of the previous process is used in the subsequent process, it can be realized in any order. Regarding the operation flows in the claims, the specification, and the drawings, even if "first," "next," etc. are used for convenience of explanation, it does not mean that it is essential to implement in this order.
Explanation of Reference Numerals
[0132] 10 ··· semiconductor substrate, 11 ··· well region, 12 ··· emitter region, 14 ··· base region, 15 ··· contact region, 16 ··· storage region, 17 ··· plug region, 18 ··· drift region, 20 ··· buffer region, 21 ··· front surface, 22 ··· collector region, 23 ··· back surface, 24 ··· collector electrode, 29 ··· straight portion, 30 ··· dummy trench portion, 31 ··· tip portion, 32 ··· dummy insulating film, 34 ··· dummy conductive portion, 38 ··· interlayer insulating film, 39 ··· straight portion, 40 ··· gate trench portion, 41 ··· tip portion, 42 ··· gate insulating film, 44 ··· gate conductive portion, 48 ··· gate runner, 49 ··· contact hole, 52 ··· emitter electrode, 54 ··· contact hole, 56 ··· contact hole, 60 ··· mesa portion, 61 ··· mesa portion, 62 ··· mask, 63 ··· shielding portion, 64 ··· non-shielding portion, 65 ··· implantation region, 66 ··· non-implantation region, 70 ··· transistor portion, 71 ··· main region, 72 ··· end region, 80 ··· diode portion, 81 ··· extension region, 82 ··· cathode region, 84 ··· anode region, 90 ··· boundary region, 100 ··· semiconductor device, 102 ··· side edge, 120 ··· edge termination structure portion, 160 ··· active region, 200 ··· semiconductor device, 300 ··· semiconductor device
Claims
1. A method for manufacturing a semiconductor device including a semiconductor substrate of a first conductivity type having a transistor portion and a diode portion, and provided with a plurality of trench portions, comprising: forming a mask above the semiconductor substrate, the mask being formed such that a shielding density of the mask with respect to a predetermined second region of the semiconductor substrate is higher than a shielding density of the mask with respect to a predetermined first region of the semiconductor substrate; ion-implanting a dopant for forming a second conductivity type region on a front surface of the semiconductor substrate into each of the first region and the second region; diffusing the implanted dopant into the semiconductor substrate; wherein the mask has a shielding portion and a non-shielding portion, a width of the shielding portion is 0.25 times or more and 0.8 times or less of a diffusion depth of the dopant, and a width of the non-shielding portion is 1 / 3 times or more and 1 time or less of the width of the shielding portion A method for manufacturing a semiconductor device.
2. the mask does not have the shielding portion above the first region and has at least the shielding portion above the second region The method for manufacturing a semiconductor device according to claim 1.
3. the first region corresponds to a main region of the transistor portion, and the second region corresponds to the diode portion The method for manufacturing a semiconductor device according to claim 1.
4. the second region includes a region corresponding to a boundary region closer to the diode portion than the main region The method for manufacturing a semiconductor device according to claim 3.
5. the shielding portion has a stripe shape extending in a trench array direction The method for manufacturing a semiconductor device according to claim 1.
6. the width of the shielding portion is 0.5 μm or more and 1.6 μm or less The method for manufacturing a semiconductor device according to claim 1.
7. the step of ion-implanting the dopant includes ion-implanting the dopant into each of the first region, the second region, and a predetermined third region of the semiconductor substrate, in a top view, an area ratio of the shielding portion in the first region is lower than an area ratio of the shielding portion in the second region, and the area ratio of the shielding portion in the second region is lower than an area ratio of the shielding portion in the third region The method for manufacturing a semiconductor device according to any one of claims 1 to 6.
8. The first region corresponds to an end region on the diode portion side rather than the main region of the transistor portion, the second region corresponds to the main region, and the third region corresponds to the diode portion. The method of manufacturing a semiconductor device according to claim 7.
9. The doping concentration of the second conductivity type region formed in the end region is 1.5 times or more and 2 times or less the doping concentration of the second conductivity type region formed in the main region. The method of manufacturing a semiconductor device according to claim 8.
10. The mask does not have the shielding portion above the first region and has the shielding portion at least above the second region and the third region. The method of manufacturing a semiconductor device according to claim 7.
11. The first region corresponds to an end region on the diode portion side rather than the main region of the transistor portion, the second region and the third region correspond to regions included in the main region, and the region corresponding to the third region is separated from the end region more than the region corresponding to the second region. The method of manufacturing a semiconductor device according to claim 7.
12. The step of ion implanting the dopant includes the step of ion implanting into a predetermined fourth region of the semiconductor substrate. In a top view, the area ratio of the shielding portion in the third region is lower than the area ratio of the shielding portion in the fourth region. The fourth region is the diode portion. The method of manufacturing a semiconductor device according to claim 11.
13. The width in the trench arrangement direction of the end region is 20 μm or more and 100 μm or less. The method of manufacturing a semiconductor device according to claim 11.
14. The shielding portion has a stripe shape extending in the trench arrangement direction. The width of the shielding portion is smaller than that of the second region in the first region and smaller than that of the third region in the second region. The method of manufacturing a semiconductor device according to claim 11.
15. The first region includes a region corresponding to an extended region outside the end of the diode portion in the trench extension direction. The method of manufacturing a semiconductor device according to claim 1.
16. The plurality of trench portions extend to the extended region. The method of manufacturing a semiconductor device according to claim 15.
17. The mask is a resist. The method of manufacturing a semiconductor device according to claim 1.
18. The thickness of the shielding portion is 0.3 μm or more and 3 μm or less. The method of manufacturing a semiconductor device according to claim 1.