Integrated circuit

Abstract

To provide an integrated circuit with high withstanding voltage, in which a plurality of protection rings are provided at an outer periphery of a transistor array in order to avoid damage of the transistor array due to surge large current or high voltage, and each ring region includes a doped region at a certain proportion.SOLUTION: An integrated circuit 1000 includes a transistor array 1100 and a protection ring 1300. The protection ring is formed at an outer periphery 1110 of the transistor array and includes a plurality of ring regions 1310. Each ring region includes a doped region. The area of the doped region inside the ring region is larger than the area of the doped region outside the ring region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an integrated circuit. Specifically, the present invention relates to an integrated circuit in which a plurality of protection rings are provided on the outer periphery of a transistor array.

Background Art

[0002] A common problem in the manufacture of metal-oxide-semiconductor field-effect transistor (MOSFET) arrays is insufficient breakdown voltage. This is particularly prominent in high-voltage applications. This problem leads to electrical connections between MOSFETs and breakdown voltage defects, which may reduce the performance and reliability of components.

[0003] In order to solve the problem of insufficient breakdown voltage, currently, the mainstream approach is to increase the number of MOSFETs in the MOSFET array to achieve the required breakdown voltage of the entire circuit. However, increasing the number of MOSFETs will significantly increase the cost of the entire circuit.

[0004] In view of the above circumstances, the present invention proposes an integrated circuit design with low manufacturing cost and significantly improved circuit breakdown voltage.

Summary of the Invention

[0005] An object of the present invention is to provide a high-breakdown-voltage integrated circuit in which a plurality of ring regions are provided on the outer periphery of a transistor array, and each ring region has a doped region at a certain ratio. When a surge occurs in the transistor array during circuit operation, the ring region can allow the surge current to flow outward. By doing so, damage to the transistor array caused by the large current and large voltage of the surge can be avoided. The breakdown voltage of the transistor array of this circuit can be significantly improved to 1500 volts or more.

[0006] To achieve the above object, the present invention provides an integrated circuit including a transistor array and a protection ring. The protection ring is formed on the periphery of the transistor array. The protection ring includes a plurality of ring regions, each of the ring regions has a doped region, and an area of the doped region inside the ring region is larger than an area of the doped region outside the ring region.

[0007] In an embodiment of the present invention, an area of the doped region of the innermost ring region among the plurality of ring regions is a total area of the innermost ring region.

[0008] In an embodiment of the present invention, a ratio of a side length of the transistor array to an overall width of the ring region is less than 10.

[0009] In an embodiment of the present invention, the ratio of the side length to the overall width is 5:3.

[0010] In an embodiment of the present invention, the plurality of ring regions are divided into an inner portion and an outer portion, and a width of the inner portion is larger than 100 micrometers (μm).

[0011] In an embodiment of the present invention, an undoped region of the inner portion of the plurality of ring regions and the doped region of the outer portion of the plurality of ring regions are composed of a plurality of dispersed portions, and the dispersed portions are rectangular, circular, or polygonal.

[0012] In an embodiment of the present invention, when the number of the ring regions is one, a breakdown voltage of the transistor array is improved by 20% to 50%.

[0013] In an embodiment of the present invention, the breakdown voltage of the transistor array increases as the overall width increases.

[0014] In an embodiment of the present invention, the doped region of the ring region is annular.

[0015] In an embodiment of the present invention, when the number of the ring regions is one, the breakdown voltage of the transistor array is improved by 20% to 50%.

[0016] In an embodiment of the present invention, the transistor array is composed of a plurality of Metal-Oxide-Semiconductor Field-Effect Transistors.

[0017] Those skilled in the art can understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described below.

Brief Description of the Drawings

[0018]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying out the Invention

[0019] Hereinafter, the content of the present invention will be described through examples. It should be noted that the examples of the present invention show examples of the embodiments, and are not intended to be limited to the environments, applications, or specific modes as described in the examples. Therefore, the description of the examples is for explaining the present invention, but does not limit the present invention. In the embodiments and the drawings, components not directly related to the present invention are omitted and not shown. The dimensional relationships of the components in the drawings are for facilitating understanding and do not limit the actual dimensions.

[0020] Figures 1 to 5 show the first embodiment of the present invention. FIG. 1 is a schematic diagram showing an integrated circuit 1000 of the present invention. The integrated circuit 1000 includes a transistor array 1100 and a protection ring 1300. The transistor array 1100 is composed of a plurality of Metal-Oxide-Semiconductor Field-Effect Transistors.

[0021] This will be described with reference to FIGS. 2 and 3. FIG. 2 is a partial cross-sectional view showing the integrated circuit of the present invention. FIG. 3 is a partial schematic diagram showing the protection ring 1300 of the present invention. The protection ring 1300 is formed on the periphery 1110 of the transistor array 1100, thereby significantly improving the breakdown voltage of the entire transistor array 1100.

[0022] Specifically, the protection ring 1300 includes a plurality of ring regions 1310. These ring regions 1310 are divided into an inner portion 1311 and an outer portion 1313. The width of the inner portion 1311 is greater than 100 micrometers (μm). The ratio of the side length L of the transistor array 1100 to the total width W of the ring region 1310 is less than 10. The optimal ratio of the side length of the transistor array 1100 to the total width of the ring region 1310 is 5:3.

[0023] The ring region 1310 has doped regions (the gray portions in FIGS. 3 to 5). The area of the doped region inside the ring region 1310 is larger than the area of the doped region outside the ring region 1310.

[0024] The areas of these doped regions can be regarded as doping concentrations. During the manufacturing process of the Metal-Oxide-Semiconductor Field-Effect Transistor, P-type ions such as boron ions, aluminum ions, gallium ions, indium ions, and other positive charge ions are implanted into the N-type epitaxial layer to form P-type doped regions.

[0025] Each ring region 1310 has P-type doped regions with different doping ratios. In the inner part 1311 of the ring region 1310, the ratio of the area of the undoped region of each ring is predetermined, and then P-type ions are implanted into the remaining parts of each ring in the inner part 1311. On the other hand, in the outer part 1313 of the ring region 1310, after the ratio of the area of the region to be doped is predetermined, P-type ions are directly implanted into the part to be doped.

[0026] The undoped regions in the inner part 1311 of the plurality of ring regions 1310 and the doped regions in the outer part 1313 of the plurality of ring regions are composed of a plurality of dispersed parts. As shown in FIGS. 3 to 5, the dispersed parts are rectangles, circles, or polygons.

[0027] In short, the inner part 1311 of the ring region 1310 determines the ratio of the area of the undoped region and selects the position of the undoped region. The outer part 1313 of the ring region 1310 determines the ratio of the area of the region to be doped and selects the position to be doped.

[0028] The area of the doped region of the innermost ring region among the plurality of ring regions 1310 is the total area of the innermost ring region. In other words, the innermost ring region among the plurality of ring regions 1310 is connected to the transistor array 1100. The area of the doped region of the innermost ring region is 100%.

[0029] The breakdown voltage of the transistor array 1100 increases as the total width of the ring region 1310 increases. The total width of the ring region 1310 increases as the number of the ring regions 1310 increases. In this embodiment, when the number of the ring regions 1310 is one, the breakdown voltage of the transistor array 1100 is improved by 20% to 50%.

[0030] When a surge current occurs in a circuit using the transistor array 1100, the current flows outward through the P-type doped region, and the surge current and heat are conducted in the outward direction. Therefore, the integrated circuit 1000 of the present invention can improve the instantaneous dispersion effect and heat dissipation effect of the surge current.

[0031] FIG. 6 shows a second embodiment of the present invention. The second embodiment is a modification of the first embodiment. The undoped region of the inner part 1311 and the doped region of the outer part 1313 of the first embodiment are formed by a dispersion part of an arbitrary shape, and the second embodiment is different from the first embodiment. In this embodiment, the doped region of the ring region 1310 is annular. When the number of ring regions is one, the breakdown voltage of the transistor array 1100 is improved by 20% to 50%.

[0032] As described above, the integrated circuit of the present invention includes a protection ring on the outer periphery of the transistor array. The doped region and the undoped region of each ring region of the protection ring have a specific ratio, and the area of the doped region of the ring region decreases toward the outside. Thereby, when a surge occurs in the integrated circuit, the surge current is dispersed to the outside by the protection ring, avoiding damage to the circuit and improving the breakdown voltage of the entire circuit.

[0033] The above-described embodiments illustrate the embodiments of the present invention and explain the characteristic configurations of the present invention. The present invention is not limited to the above embodiments. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention shall be based on the scope of the claims.

Description of Reference Numerals

[0034] 1000 Integrated circuit 1100 Transistor array 1110 Outer periphery 1300 Protection ring 1310 Ring region L Side length W Total width

Claims

1. An integrated circuit, comprising: a transistor array; and a protection ring formed on the periphery of the transistor array, wherein the protection ring includes a plurality of ring regions, each ring region has a doped region, and an area of the doped region inside the ring region is larger than an area of the doped region outside the ring region.

2. The integrated circuit according to claim 1, wherein an area of the doped region of the innermost ring region among the plurality of ring regions is equal to a total area of the innermost ring region.

3. The integrated circuit according to claim 1, wherein a ratio of a side length of the transistor array to a total width of the plurality of ring regions is less than 10.

4. The integrated circuit according to claim 3, wherein the ratio of the side length to the total width is 5:

3.

5. The integrated circuit according to claim 3, wherein the plurality of ring regions are divided into an inner portion and an outer portion, and a width of the inner portion is greater than 100 micrometers (μm).

6. The integrated circuit according to claim 5, wherein an undoped region of the inner portion of the plurality of ring regions and the doped region of the outer portion of the plurality of ring regions are composed of a plurality of dispersed portions, and the dispersed portions are rectangular, circular, or polygonal.

7. The integrated circuit according to claim 6, wherein when the number of the ring regions is one, a breakdown voltage of the transistor array is improved by 20% to 50%.

8. The integrated circuit according to claim 3, wherein the breakdown voltage of the transistor array increases as the total width increases.

9. The integrated circuit according to claim 1, wherein the doped region of the ring region is annular.

10. The integrated circuit according to claim 9, wherein when the number of the ring regions is one, a breakdown voltage of the transistor array is improved by 20% to 50%.

11. The integrated circuit according to claim 1, wherein the transistor array is composed of a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs).

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