Controller

Abstract

To provide a controller that reduces the processing load on a processor.SOLUTION: A controller 10 comprises: a first storage unit that does not need refreshing and has volatility; a first processor that accesses the first storage unit; a bus arbiter that arbitrates an access request from the first processor; and a first control circuit 41 that performs mode control of the first storage unit on the basis of the access request received from the first processor through the bus arbiter. When the time during which the access request is not received in a state where the first storage unit is in a normal mode exceeds a predetermined time, the first control circuit instructs the first storage unit to make a transition from the normal mode to a power-saving mode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a control device.

Background Art

[0002] As a volatile memory that does not require refreshing, an SRAM (Static Random Access Memory) having a normal mode and a power-saving mode is known. Patent Document 1 discloses a technique for switching the operation mode of an SRAM to a power-saving mode that suppresses power consumption while holding data when data to be held in the SRAM is stored.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the prior art, a processor such as a CPU (Central Processing Unit) determines whether the SRAM is being accessed based on the current flowing through the SRAM, so the processing load on the processor is large.

Means for Solving the Problems

[0005] The control device according to one aspect of the present invention includes a first storage unit that does not require refreshing and is volatile, a first processor that accesses the first storage unit, a bus arbiter that arbitrates access requests from the first processor, and a first control circuit that controls the mode of the first storage unit based on the access request received from the first processor via the bus arbiter. The first control circuit instructs the first storage unit to shift from the normal mode to the power-saving mode when the time during which the first storage unit does not receive the access request in the normal mode exceeds a predetermined time.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Modes for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a control device 10 in the present embodiment. For example, the control device 10 is an IC (Integrated Circuit) chip mounted on an electronic device such as a GPS (Global Positioning System) receiver.

[0008] As shown in FIG. 1, the control device 10 includes a first processor 11, a second processor 12, a first bus bridge 21, a second bus bridge 22, a bus arbiter 30, a first memory controller 41, a second memory controller 42, a third memory controller 43, a first storage unit 51, a second storage unit 52, and a third storage unit 53.

[0009] The first storage unit 51 is a storage device that does not require refreshing and is volatile. For example, the first storage unit 51 is a memory bank including a plurality of first memories 51a that do not require refreshing and are volatile. In FIG. 1, as an example, the first storage unit 51 including three first memories 51a is shown, but the number of first memories 51a included in the first storage unit 51 is not limited to three. As an example, each first memory 51a is an SRAM.

[0010] Each first memory 51a has a normal mode and a sleep mode as operation modes. The normal mode is a mode in which data can be written to or read from the memory cells of the first memory 51a. The sleep mode is a mode in which the power consumption of the first memory 51a is reduced while maintaining the data written in the memory cells of the first memory 51a. When the first memory 51a is in the sleep mode, data cannot be written to or read from the memory cells. The sleep mode is an example of a power-saving mode.

[0011] The first storage unit 51 receives a first mode switching signal MD1 output from the first memory controller 41. The first mode switching signal MD1 is input to each first memory 51a included in the first storage unit 51. The operation mode of each first memory 51a is switched to either a normal mode or a sleep mode according to the first mode switching signal MD1. For example, when the first mode switching signal MD1 is asserted, the operation mode of each first memory 51a is switched to the sleep mode. On the other hand, when the first mode switching signal MD1 is negated, the operation mode of each first memory 51a is switched to the normal mode.

[0012] In this embodiment, "the signal is asserted" means that the level of the signal is switched from the low level to the high level, and "the signal is negated" means that the level of the signal is switched from the high level to the low level. That is, in this embodiment, an example is given in which the control device 10 is configured by an active-high logic circuit, but the control device 10 may be configured by an active-low logic circuit.

[0013] The first storage unit 51 receives an eighth data read signal RD8 and an eighth data write signal WR8 output from the first memory controller 41. When the eighth data read signal RD8 is asserted while each first memory 51a is in the normal mode, each first memory 51a becomes in a state where data can be read. On the other hand, when the eighth data write signal WR8 is asserted while each first memory 51a is in the normal mode, each first memory 51a becomes in a state where data can be written.

[0014] The second storage unit 52 is a storage device that does not require refreshing and has volatility. For example, the second storage unit 52 is a memory bank including a plurality of second memories 52a that do not require refreshing and have volatility. In FIG. 1, as an example, a second storage unit 52 including three second memories 52a is shown, but the number of second memories 52a included in the second storage unit 52 is not limited to three. As an example, each second memory 52a is a SRAM.

[0015] The second storage unit 52 receives a second mode switching signal MD2 output from the second memory controller 42. The second mode switching signal MD2 is input to each second memory 52a included in the second storage unit 52. The operation mode of each second memory 52a is switched to either a normal mode or a sleep mode according to the second mode switching signal MD2. For example, when the second mode switching signal MD2 is asserted, the operation mode of each second memory 52a is switched to the sleep mode. On the other hand, when the second mode switching signal MD2 is negated, the operation mode of each second memory 52a is switched to the normal mode.

[0016] The second storage unit 52 receives a ninth data read signal RD9 and a ninth data write signal WR9 output from the second memory controller 42. When the ninth data read signal RD9 is asserted while each second memory 52a is in the normal mode, each second memory 52a becomes capable of reading data. On the other hand, when the ninth data write signal WR9 is asserted while each second memory 52a is in the normal mode, each second memory 52a becomes capable of writing data.

[0017] The third storage unit 53 is a memory device that does not require refreshing and has volatility. For example, the third storage unit 53 is a memory bank including a plurality of third memories 53a that do not require refreshing and have volatility. In FIG. 1, as an example, a third storage unit 53 including three third memories 53a is shown, but the number of third memories 53a included in the third storage unit 53 is not limited to three. As an example, each third memory 53a is an SRAM.

[0018] The third memory unit 53 receives a third mode switching signal MD3 output from the third memory controller 43. The third mode switching signal MD3 is input to each third memory 53a included in the third memory unit 53. The operating mode of each third memory 53a is switched to either a normal mode or a sleep mode according to the third mode switching signal MD3. For example, when the third mode switching signal MD3 is asserted, the operating mode of each third memory 53a is switched to the sleep mode. On the other hand, when the third mode switching signal MD3 is negated, the operating mode of each third memory 53a is switched to the normal mode.

[0019] The third memory unit 53 receives a tenth data read signal RD10 and a tenth data write signal WR10 output from the third memory controller 43. When the tenth data read signal RD10 is asserted while each third memory 53a is in the normal mode, each third memory 53a becomes capable of reading data. On the other hand, when the tenth data write signal WR10 is asserted while each third memory 53a is in the normal mode, each third memory 53a becomes capable of writing data.

[0020] The first processor 11 accesses any one of the first memory unit 51, the second memory unit 52, and the third memory unit 53. For example, the first processor 11 is a CPU. The first processor 11 communicates with the bus arbiter 30 via the first bus bridge 21. The first processor 11 outputs a first access request signal REQ1, a first data read signal RD1, and a first data write signal WR1 to the first bus bridge 21.

[0021] When the first processor 11 issues an access request, it asserts the first access request signal REQ1. Also, when the first processor 11 withdraws an access request, it negates the first access request signal REQ1. When the first processor 11 reads data from any one of the first storage unit 51, the second storage unit 52, and the third storage unit 53, it asserts the first data read signal RD1. Also, when the first processor 11 writes data to any one of the first storage unit 51, the second storage unit 52, and the third storage unit 53, it asserts the first data write signal WR1.

[0022] The first processor 11 receives the sixth acknowledge signal ACK6 output from the first bus bridge 21. When the first processor 11 asserts the first access request signal REQ1, if the level of the sixth acknowledge signal ACK6 is low, it asserts the first data read signal RD1 or the first data write signal WR1. On the other hand, when the first processor 11 asserts the first access request signal REQ1, if the level of the sixth acknowledge signal ACK6 is high, it does not assert the first data read signal RD1 or the first data write signal WR1 until the sixth acknowledge signal ACK6 is negated. In other words, when the first processor 11 issues an access request and the level of the sixth acknowledge signal ACK6 is high, it waits until the sixth acknowledge signal ACK6 is negated.

[0023] The first bus bridge 21 is connected to the first master port 31 of the bus arbiter 30 and relays communication between the first processor 11 and the bus arbiter 30. Specifically, the first bus bridge 21 performs mutual conversion between the bus protocol of the first processor 11 and the bus protocol of the bus arbiter 30.

[0024] The first bus bridge 21 outputs a second access request signal REQ2, a second data read signal RD2, and a second data write signal WR2 to the bus arbiter 30. The first bus bridge 21 receives a first access request signal REQ1, a first data read signal RD1, and a first data write signal WR1 output from the first processor 11. The first bus bridge 21 asserts the second access request signal REQ2 when the first access request signal REQ1 is asserted. The first bus bridge 21 negates the second access request signal REQ2 when the first access request signal REQ1 is negated.

[0025] The first bus bridge 21 asserts the second data read signal RD2 when the first data read signal RD1 is asserted. The first bus bridge 21 negates the second data read signal RD2 when the first data read signal RD1 is negated. The first bus bridge 21 asserts the second data write signal WR2 when the first data write signal WR1 is asserted. The first bus bridge 21 negates the second data write signal WR2 when the first data write signal WR1 is negated.

[0026] The first bus bridge 21 outputs a sixth acknowledge signal ACK6 to the first processor 11. The first bus bridge 21 receives a first acknowledge signal ACK1 output from the bus arbiter 30. The first bus bridge 21 outputs, as the sixth acknowledge signal ACK6, a signal indicating the exclusive logical sum of the first access request signal REQ1 and the first acknowledge signal ACK1.

[0027] The second processor 12 accesses any one of the first storage unit 51, the second storage unit 52, and the third storage unit 53. For example, the second processor 12 is a CPU. The second processor 12 communicates with the bus arbiter 30 via the second bus bridge 22. The second processor 12 outputs a third access request signal REQ3, a third data read signal RD3, and a third data write signal WR3 to the second bus bridge 22.

[0028] When the second processor 12 issues an access request, it asserts a third access request signal REQ3. Also, when the second processor 12 cancels an access request, it negates the third access request signal REQ3. When the second processor 12 reads data from any one of the first storage unit 51, the second storage unit 52, and the third storage unit 53, it asserts a third data read signal RD3. Also, when the second processor 12 writes data to any one of the first storage unit 51, the second storage unit 52, and the third storage unit 53, it asserts a third data write signal WR3.

[0029] A seventh acknowledge signal ACK7 output from the second bus bridge 22 is input to the second processor 12. When the second processor 12 asserts the third access request signal REQ3, if the level of the seventh acknowledge signal ACK7 is low, it asserts the third data read signal RD3 or the third data write signal WR3. On the other hand, when the second processor 12 asserts the third access request signal REQ3, if the level of the seventh acknowledge signal ACK7 is high, it does not assert the third data read signal RD3 or the third data write signal WR3 until the seventh acknowledge signal ACK7 is negated. In other words, when the second processor 12 issues an access request and the level of the seventh acknowledge signal ACK7 is high, it waits until the seventh acknowledge signal ACK7 is negated.

[0030] The second bus bridge 22 is connected to a second master port 32 of the bus arbiter 30 and relays communication between the second processor 12 and the bus arbiter 30. Specifically, the second bus bridge 22 performs mutual conversion between the bus protocol of the second processor 12 and the bus protocol of the bus arbiter 30.

[0031] The second bus bridge 22 outputs a fourth access request signal REQ4, a fourth data read signal RD4, and a fourth data write signal WR4 to the bus arbiter 30. Input to the second bus bridge 22 are a third access request signal REQ3, a third data read signal RD3, and a third data write signal WR3 output from the second processor 12. The second bus bridge 22 asserts the fourth access request signal REQ4 when the third access request signal REQ3 is asserted. The second bus bridge 22 negates the fourth access request signal REQ4 when the third access request signal REQ3 is negated.

[0032] The second bus bridge 22 asserts the fourth data read signal RD4 when the third data read signal RD3 is asserted. The second bus bridge 22 negates the fourth data read signal RD4 when the third data read signal RD3 is negated. The second bus bridge 22 asserts the fourth data write signal WR4 when the third data write signal WR3 is asserted. The second bus bridge 22 negates the fourth data write signal WR4 when the third data write signal WR3 is negated.

[0033] The second bus bridge 22 outputs a seventh acknowledge signal ACK7 to the second processor 12. Input to the second bus bridge 22 is a second acknowledge signal ACK2 output from the bus arbiter 30. The second bus bridge 22 outputs, as the seventh acknowledge signal ACK7, a signal indicating the exclusive logical sum of the third access request signal REQ3 and the second acknowledge signal ACK2.

[0034] The bus arbiter 30 arbitrates between an access request from the first processor 11 and an access request from the second processor 12. The bus arbiter 30 outputs a fifth access request signal REQ5, a fifth data read signal RD5, and a fifth data write signal WR5 to the first memory controller 41. Input to the bus arbiter 30 is a third acknowledge signal ACK3 output from the first memory controller 41.

[0035] When the first processor 11 requests access to the first storage unit 51 (the first case), the bus arbiter 30 asserts the fifth access request signal REQ5 when the second access request signal REQ2 input from the first bus bridge 21 is asserted. In the first case, the bus arbiter 30 negates the fifth access request signal REQ5 when the second access request signal REQ2 is negated.

[0036] In the first case, the bus arbiter 30 asserts the fifth data read signal RD5 when the second data read signal RD2 input from the first bus bridge 21 is asserted. In the first case, the bus arbiter 30 negates the fifth data read signal RD5 when the second data read signal RD2 is negated. In the first case, the bus arbiter 30 asserts the fifth data write signal WR5 when the second data write signal WR2 input from the first bus bridge 21 is asserted. In the first case, the bus arbiter 30 negates the fifth data write signal WR5 when the second data write signal WR2 is negated.

[0037] The bus arbiter 30 outputs the first acknowledge signal ACK1 to the first bus bridge 21. In the first case, the bus arbiter 30 asserts the first acknowledge signal ACK1 when the third acknowledge signal ACK3 is asserted. In the first case, the bus arbiter 30 negates the first acknowledge signal ACK1 when the third acknowledge signal ACK3 is negated.

[0038] When the second processor 12 requests access to the first storage unit 51 (the second case), the bus arbiter 30 asserts the fifth access request signal REQ5 when the fourth access request signal REQ4 input from the second bus bridge 22 is asserted. In the second case, the bus arbiter 30 negates the fifth access request signal REQ5 when the fourth access request signal REQ4 is negated.

[0039] In the second case, when the fourth data read signal RD4 input from the second bus bridge 22 is asserted, the bus arbiter 30 asserts the fifth data read signal RD5. In the second case, when the fourth data read signal RD4 is negated, the bus arbiter 30 negates the fifth data read signal RD5. In the second case, when the fourth data write signal WR4 input from the second bus bridge 22 is asserted, the bus arbiter 30 asserts the fifth data write signal WR5. In the second case, when the fourth data write signal WR4 is negated, the bus arbiter 30 negates the fifth data write signal WR5.

[0040] The bus arbiter 30 outputs the second acknowledge signal ACK2 to the second bus bridge 22. In the second case, when the third acknowledge signal ACK3 is asserted, the bus arbiter 30 asserts the second acknowledge signal ACK2. In the second case, when the third acknowledge signal ACK3 is negated, the bus arbiter 30 negates the second acknowledge signal ACK2.

[0041] The bus arbiter 30 outputs the sixth access request signal REQ6, the sixth data read signal RD6, and the sixth data write signal WR6 to the second memory controller 42. The bus arbiter 30 receives the fourth acknowledge signal ACK4 output from the second memory controller 42.

[0042] When the first processor 11 requests access to the second storage unit 52 (the third case), the bus arbiter 30 asserts the sixth access request signal REQ6 when the second access request signal REQ2 input from the first bus bridge 21 is asserted. In the third case, when the second access request signal REQ2 is negated, the bus arbiter 30 negates the sixth access request signal REQ6.

[0043] In the third case, when the second data read signal RD2 input from the first bus bridge 21 is asserted, the bus arbiter 30 asserts the sixth data read signal RD6. In the third case, when the second data read signal RD2 is negated, the bus arbiter 30 negates the sixth data read signal RD6. In the third case, when the second data write signal WR2 input from the first bus bridge 21 is asserted, the bus arbiter 30 asserts the sixth data write signal WR6. In the third case, when the second data write signal WR2 is negated, the bus arbiter 30 negates the sixth data write signal WR6.

[0044] In the third case, when the fourth acknowledge signal ACK4 is asserted, the bus arbiter 30 asserts the first acknowledge signal ACK1. In the third case, when the fourth acknowledge signal ACK4 is negated, the bus arbiter 30 negates the first acknowledge signal ACK1.

[0045] When the second processor 12 requests access to the second storage unit 52 (fourth case), the bus arbiter 30 asserts the sixth access request signal REQ6 when the fourth access request signal REQ4 input from the second bus bridge 22 is asserted. In the fourth case, when the fourth access request signal REQ4 is negated, the bus arbiter 30 negates the sixth access request signal REQ6.

[0046] In the fourth case, when the fourth data read signal RD4 input from the second bus bridge 22 is asserted, the bus arbiter 30 asserts the sixth data read signal RD6. In the fourth case, when the fourth data read signal RD4 is negated, the bus arbiter 30 negates the sixth data read signal RD6. In the fourth case, when the fourth data write signal WR4 input from the second bus bridge 22 is asserted, the bus arbiter 30 asserts the sixth data write signal WR6. In the fourth case, when the fourth data write signal WR4 is negated, the bus arbiter 30 negates the sixth data write signal WR6.

[0047] In the fourth case, when the fourth acknowledge signal ACK4 is asserted, the bus arbiter 30 asserts the second acknowledge signal ACK2. In the fourth case, when the fourth acknowledge signal ACK4 is negated, the bus arbiter 30 negates the second acknowledge signal ACK2.

[0048] The bus arbiter 30 outputs the seventh access request signal REQ7, the seventh data read signal RD7, and the seventh data write signal WR7 to the third memory controller 43. The bus arbiter 30 receives the fifth acknowledge signal ACK5 output from the third memory controller 43.

[0049] When the first processor 11 requests access to the third storage unit 53 (the fifth case), the bus arbiter 30 asserts the seventh access request signal REQ7 when the second access request signal REQ2 input from the first bus bridge 21 is asserted. In the fifth case, the bus arbiter 30 negates the seventh access request signal REQ7 when the second access request signal REQ2 is negated.

[0050] In the fifth case, when the second data read signal RD2 input from the first bus bridge 21 is asserted, the bus arbiter 30 asserts the seventh data read signal RD7. In the fifth case, when the second data read signal RD2 is negated, the bus arbiter 30 negates the seventh data read signal RD7. In the fifth case, when the second data write signal WR2 input from the first bus bridge 21 is asserted, the bus arbiter 30 asserts the seventh data write signal WR7. In the fifth case, when the second data write signal WR2 is negated, the bus arbiter 30 negates the seventh data write signal WR7.

[0051] In the fifth case, when the fifth acknowledge signal ACK5 is asserted, the bus arbiter 30 asserts the first acknowledge signal ACK1. In the fifth case, when the fifth acknowledge signal ACK5 is negated, the bus arbiter 30 negates the first acknowledge signal ACK1.

[0052] When the second processor 12 requests to access the third storage unit 53 (the sixth case), the bus arbiter 30 asserts the seventh access request signal REQ7 when the fourth access request signal REQ4 input from the second bus bridge 22 is asserted. In the sixth case, when the fourth access request signal REQ4 is negated, the bus arbiter 30 negates the seventh access request signal REQ7.

[0053] In the sixth case, when the fourth data read signal RD4 input from the second bus bridge 22 is asserted, the bus arbiter 30 asserts the seventh data read signal RD7. In the sixth case, when the fourth data read signal RD4 is negated, the bus arbiter 30 negates the seventh data read signal RD7. In the sixth case, when the fourth data write signal WR4 input from the second bus bridge 22 is asserted, the bus arbiter 30 asserts the seventh data write signal WR7. In the sixth case, when the fourth data write signal WR4 is negated, the bus arbiter 30 negates the seventh data write signal WR7.

[0054] In the sixth case, when the fifth acknowledge signal ACK5 is asserted, the bus arbiter 30 asserts the second acknowledge signal ACK2. In the sixth case, when the fifth acknowledge signal ACK5 is negated, the bus arbiter 30 negates the second acknowledge signal ACK2.

[0055] The first memory controller 41 is connected to the first slave port 33 of the bus arbiter 30. Input to the first memory controller 41 are the fifth access request signal REQ5, the fifth data read signal RD5, and the fifth data write signal WR5 output from the bus arbiter 30. The first memory controller 41 outputs the third acknowledge signal ACK3 to the bus arbiter 30. The first memory controller 41 outputs the first mode switching signal MD1, the eighth data read signal RD8, and the eighth data write signal WR8 to the first storage unit 51.

[0056] The first memory controller 41 performs mode control of the first storage unit 51 based on an access request received from the first processor 11 or the second processor 12 via the bus arbiter 30. The first memory controller 41 is an example of the first control circuit and is configured by hardware.

[0057] For example, when the time during which the first memory controller 41 does not receive an access request in the normal mode exceeds a predetermined time, the first memory controller 41 instructs the first storage unit 51 to shift from the normal mode to the sleep mode. The first memory controller 41 measures the time during which no access request is received. More specifically, the first memory controller 41 starts measuring the time after the fifth access request signal REQ5 is negated while the first storage unit 51 is in the normal mode, and asserts the first mode switching signal MD1 when the measured time exceeds the predetermined time without the fifth access request signal REQ5 being asserted.

[0058] When the first memory controller 41 receives an access request from the first processor 11 or the second processor 12 via the bus arbiter 30 while the first storage unit 51 is in the sleep mode, the first memory controller 41 instructs the first storage unit 51 to shift from the sleep mode to the normal mode. More specifically, when the fifth access request signal REQ5 is asserted while the first storage unit 51 is in the sleep mode, the first memory controller 41 negates the first mode switching signal MD1.

[0059] After the first storage unit 51 has shifted to the sleep mode, the first memory controller 41 returns an acknowledgment for an access request from the first processor 11 to the first bus bridge 21 via the bus arbiter 30. More specifically, after the first storage unit 51 has shifted to the sleep mode, the first memory controller 41 asserts the third acknowledgment signal ACK3. When an access request is issued from the first processor 11 and the third acknowledgment signal ACK3 is asserted, the bus arbiter 30 asserts the first acknowledgment signal ACK1.

[0060] Also, after the first memory controller 41 determines that the first storage unit 51 has shifted to the sleep mode, the first memory controller 41 replies to an access request from the second processor 12 with an acknowledgement via the bus arbiter 30 to the second bus bridge 22. More specifically, after the first storage unit 51 has shifted to the sleep mode, the first memory controller 41 asserts a third acknowledgement signal ACK3. When an access request is issued from the second processor 12 and the third acknowledgement signal ACK3 is asserted, the bus arbiter 30 asserts a second acknowledgement signal ACK2.

[0061] When the first storage unit 51 is in the normal mode, the first memory controller 41 asserts an eighth data read signal RD8 when a fifth data read signal RD5 is asserted. When the first storage unit 51 is in the normal mode, the first memory controller 41 negates the eighth data read signal RD8 when the fifth data read signal RD5 is negated.

[0062] When the first storage unit 51 is in the normal mode, the first memory controller 41 asserts a eighth data write signal WR8 when a fifth data write signal WR5 is asserted. When the first storage unit 51 is in the normal mode, the first memory controller 41 negates the eighth data write signal WR8 when the fifth data write signal WR5 is negated.

[0063] The second memory controller 42 is connected to a second slave port 34 of the bus arbiter 30. Inputs to the second memory controller 42 include a sixth access request signal REQ6, a sixth data read signal RD6, and a sixth data write signal WR6 output from the bus arbiter 30. The second memory controller 42 outputs a fourth acknowledgement signal ACK4 to the bus arbiter 30. The second memory controller 42 outputs a second mode switching signal MD2, a ninth data read signal RD9, and a ninth data write signal WR9 to the second storage unit 52.

[0064] The second memory controller 42 performs mode control of the second storage unit 52 based on an access request received from the first processor 11 or the second processor 12 via the bus arbiter 30. The second memory controller 42 is an example of a second control circuit and is configured by hardware.

[0065] For example, when the time during which the second storage unit 52 does not receive an access request in the normal mode exceeds a predetermined time, the second memory controller 42 instructs the second storage unit 52 to shift from the normal mode to the sleep mode. The second memory controller 42 measures the time during which no access request is received. More specifically, the second memory controller 42 starts measuring time after the sixth access request signal REQ6 is negated while the second storage unit 52 is in the normal mode, and asserts the second mode switching signal MD2 when the measured time exceeds the predetermined time without the sixth access request signal REQ6 being asserted.

[0066] When the second storage unit 52 receives an access request from the first processor 11 or the second processor 12 via the bus arbiter 30 while in the sleep mode, the second memory controller 42 instructs the second storage unit 52 to shift from the sleep mode to the normal mode. More specifically, the second memory controller 42 negates the second mode switching signal MD2 when the sixth access request signal REQ6 is asserted while the second storage unit 52 is in the sleep mode.

[0067] After the second storage unit 52 has shifted to the sleep mode, the second memory controller 42 returns an acknowledgement for an access request from the first processor 11 to the first bus bridge 21 via the bus arbiter 30. More specifically, the second memory controller 42 asserts the fourth acknowledgement signal ACK4 after the second storage unit 52 has shifted to the sleep mode. When an access request is issued from the first processor 11, the bus arbiter 30 asserts the first acknowledgement signal ACK1 when the fourth acknowledgement signal ACK4 is asserted.

[0068] Also, after the second memory controller 42 determines that the second storage unit 52 has shifted to the sleep mode, the second memory controller 42 returns an acknowledgement for an access request from the second processor 12 to the second bus bridge 22 via the bus arbiter 30. More specifically, after the second storage unit 52 has shifted to the sleep mode, the second memory controller 42 asserts the fourth acknowledgement signal ACK4. When an access request is issued from the second processor 12 and the fourth acknowledgement signal ACK4 is asserted, the bus arbiter 30 asserts the second acknowledgement ACK2.

[0069] When the second storage unit 52 is in the normal mode, the second memory controller 42 asserts the ninth data read signal RD9 when the sixth data read signal RD6 is asserted. When the second storage unit 52 is in the normal mode, the second memory controller 42 negates the ninth data read signal RD9 when the sixth data read signal RD6 is negated.

[0070] When the second storage unit 52 is in the normal mode, the second memory controller 42 asserts the ninth data write signal WR9 when the sixth data write signal WR6 is asserted. When the second storage unit 52 is in the normal mode, the second memory controller 42 negates the ninth data write signal WR9 when the sixth data write signal WR6 is negated.

[0071] The third memory controller 43 is connected to the third slave port 35 of the bus arbiter 30. The third memory controller 43 receives the seventh access request signal REQ7, the seventh data read signal RD7, and the seventh data write signal WR7 output from the bus arbiter 30. The third memory controller 43 outputs the fifth acknowledgement signal ACK5 to the bus arbiter 30. The third memory controller 43 outputs the third mode switching signal MD3, the tenth data read signal RD10, and the tenth data write signal WR10 to the third storage unit 53.

[0072] The third memory controller 43 controls the mode of the third storage unit 53 based on an access request received from the first processor 11 or the second processor 12 via the bus arbiter 30. The third memory controller 43 is configured by hardware.

[0073] For example, when the time during which the third storage unit 53 does not receive an access request in the normal mode exceeds a predetermined time, the third memory controller 43 instructs the third storage unit 53 to shift from the normal mode to the sleep mode. The third memory controller 43 measures the time during which no access request is received. More specifically, the third memory controller 43 starts measuring the time after the seventh access request signal REQ7 is negated while the third storage unit 53 is in the normal mode, and asserts the third mode switching signal MD3 when the measured time exceeds the predetermined time without the seventh access request signal REQ7 being asserted.

[0074] When the third storage unit 53 receives an access request from the first processor 11 or the second processor 12 via the bus arbiter 30 while in the sleep mode, the third memory controller 43 instructs the third storage unit 53 to shift from the sleep mode to the normal mode. More specifically, when the seventh access request signal REQ7 is asserted while the third storage unit 53 is in the sleep mode, the third memory controller 43 negates the third mode switching signal MD3.

[0075] After the third memory controller 43 determines that the third storage unit 53 has shifted to the sleep mode, the third memory controller 43 returns an acknowledgment of an access request from the first processor 11 to the first bus bridge 21 via the bus arbiter 30. More specifically, after the third memory controller 43 determines that the third storage unit 53 has shifted to the sleep mode, the third memory controller 43 asserts the fifth acknowledgment signal ACK5. When an access request is issued from the first processor 11 and the fifth acknowledgment signal ACK5 is asserted, the bus arbiter 30 asserts the first acknowledgment signal ACK1.

[0076] Also, after the third memory controller 43 determines that the third storage unit 53 has shifted to the sleep mode, the third memory controller 43 returns an acknowledgment of an access request from the second processor 12 to the second bus bridge 22 via the bus arbiter 30. More specifically, after the third memory controller 43 determines that the third storage unit 53 has shifted to the sleep mode, the third memory controller 43 asserts the fifth acknowledgment signal ACK5. When an access request is issued from the second processor 12 and the fifth acknowledgment signal ACK5 is asserted, the bus arbiter 30 asserts the second acknowledgment ACK2.

[0077] When the third memory controller 43 determines that the third storage unit 53 is in the normal mode, the third memory controller 43 asserts the tenth data read signal RD10 when the seventh data read signal RD7 is asserted. When the third memory controller 43 determines that the third storage unit 53 is in the normal mode, the third memory controller 43 negates the tenth data read signal RD10 when the seventh data read signal RD7 is negated.

[0078] When the third memory controller 43 determines that the third storage unit 53 is in the normal mode, the third memory controller 43 asserts the tenth data write signal WR10 when the seventh data write signal WR7 is asserted. When the third memory controller 43 determines that the third storage unit 53 is in the normal mode, the third memory controller 43 negates the tenth data write signal WR10 when the seventh data write signal WR7 is negated.

[0079] The above is the description of the configuration of the control device 10. Below, the operation of the control device 10 will be described with reference to FIGS. 2 and 3.

[0080] FIG. 2 is a first timing chart showing an operation example of the control device 10 in the first case, that is, when the first processor 11 requests access to the first storage unit 51. In FIG. 2, an example of the waveforms of the first access request signal REQ1, the sixth acknowledgment signal ACK6, the second access request signal REQ2, the first acknowledgment signal ACK1, the fifth access request signal REQ5, the third acknowledgment signal ACK3, and the first mode switching signal MD1 is shown before and after the operation mode of the first storage unit 51 is switched from the normal mode to the sleep mode.

[0081] In addition, in FIG. 2, "CLK" indicates a clock signal used in the control device 10. In FIG. 2, "Count" indicates the count value of a timer (not shown) built in the first memory controller 41. In FIG. 2, "Tout" indicates an output signal of a timer built in the first memory controller 41.

[0082] Also, in FIG. 2, "DISABLE ACK" is understood as a signal indicating a period during which it is prohibited to return an acknowledgment to an access request. Specifically, the first memory controller 41 does not assert the third acknowledgment signal ACK3 even if the fifth access request signal REQ5 is asserted during the period when "DISABLE ACK" is at a high level. "DISABLE ACK" is not an input / output signal of the first memory controller 41.

[0083] As shown in FIG. 2, in the period before time t1, all levels of the first access request signal REQ1, the sixth acknowledgment signal ACK6, the second access request signal REQ2, the first acknowledgment signal ACK1, the fifth access request signal REQ5, the third acknowledgment signal ACK3, the first mode switching signal MD1, the output signal Tout of the timer, and "DISABLE ACK" are at the low level. Since the level of the first mode switching signal MD1 is at the low level, the first storage unit 51 is in the normal mode.

[0084] At time t1, the first processor 11 asserts the first access request signal REQ1. Specifically, at time t1, the first processor 11 switches the level of the first access request signal REQ1 from the low level to the high level. That is, at time t1, the first processor 11 issues an access request.

[0085] In this case, at time t1, the first bus bridge 21 asserts the second access request signal REQ2 in synchronization with the first access request signal REQ1. Also, at time t1, the bus arbiter 30 asserts the fifth access request signal REQ5 in synchronization with the second access request signal REQ2.

[0086] At time t1, since the level of "DISABLE ACK" is at the low level, the first memory controller 41 asserts the third acknowledgment signal ACK3. In this case, at time t1, the bus arbiter 30 asserts the first acknowledgment signal ACK1 in synchronization with the third acknowledgment signal ACK3. Also, at time t1, the first bus bridge 21 outputs, as the sixth acknowledgment signal ACK6, a signal indicating the exclusive OR of the first access request signal REQ1 and the first acknowledgment signal ACK1. That is, at time t1, the level of the sixth acknowledgment signal ACK6 remains at the low level.

[0087] Subsequently, at time t2, the first processor 11 negates the first access request signal REQ1. Specifically, at time t2, the first processor 11 switches the level of the first access request signal REQ1 from high level to low level. That is, at time t2, the first processor 11 withdraws the access request.

[0088] In this case, at time t2, the first bus bridge 21 negates the second access request signal REQ2 in synchronization with the first access request signal REQ1. Also, at time t2, the bus arbiter 30 negates the fifth access request signal REQ5 in synchronization with the second access request signal REQ2.

[0089] At time t2, the first memory controller 41 negates the third acknowledge signal ACK3. In this case, at time t2, the bus arbiter 30 negates the first acknowledge signal ACK1 in synchronization with the third acknowledge signal ACK3. Also, at time t2, the first bus bridge 21 outputs, as the sixth acknowledge signal ACK6, a signal indicating the exclusive logical sum of the first access request signal REQ1 and the first acknowledge signal ACK1. That is, at time t2, the level of the sixth acknowledge signal ACK6 remains low.

[0090] When the fifth access request signal REQ5 is negated at time t2, the first memory controller 41 starts a counting operation by a timer. In other words, when the access request disappears, the first memory controller 41 starts a counting operation by a timer. The timer counts up the count value Count in synchronization with the rising edge of the clock signal CLK.

[0091] Subsequently, at time t3, the first processor 11 asserts the first access request signal REQ1 again. Specifically, at time t3, the first processor 11 switches the level of the first access request signal REQ1 from a low level to a high level. That is, at time t3, the first processor 11 issues an access request again.

[0092] In this case, at time t3, the first bus bridge 21 asserts the second access request signal REQ2 in synchronization with the first access request signal REQ1. Also, at time t3, the bus arbiter 30 asserts the fifth access request signal REQ5 in synchronization with the second access request signal REQ2.

[0093] At time t3, since the level of "DISABLE ACK" is low, the first memory controller 41 asserts the third acknowledge signal ACK3. In this case, at time t3, the bus arbiter 30 asserts the first acknowledge signal ACK1 in synchronization with the third acknowledge signal ACK3. Also, at time t3, the first bus bridge 21 outputs, as the sixth acknowledge signal ACK6, a signal indicating the exclusive OR of the first access request signal REQ1 and the first acknowledge signal ACK1. That is, at time t3, the level of the sixth acknowledge signal ACK6 remains low.

[0094] In synchronization with the rising edge of the clock signal CLK occurring at time t3, the count value Count of the timer is incremented to "2". However, since the fifth access request signal REQ5 is asserted at time t3, the first memory controller 41 resets the count value Count of the timer to "0" in synchronization with the rising edge of the clock signal CLK occurring immediately after time t3. That is, when an access request is received during the counting operation by the timer, the first memory controller 41 resets the count value Count of the timer to "0".

[0095] Subsequently, at time t4, the first processor 11 negates the first access request signal REQ1. Specifically, at time t4, the first processor 11 switches the level of the first access request signal REQ1 from high level to low level. That is, at time t4, the first processor 11 withdraws the access request.

[0096] In this case, at time t4, the first bus bridge 21 negates the second access request signal REQ2 in synchronization with the first access request signal REQ1. Also, at time t4, the bus arbiter 30 negates the fifth access request signal REQ5 in synchronization with the second access request signal REQ2.

[0097] At time t4, the first memory controller 41 negates the third acknowledge signal ACK3. In this case, at time t4, the bus arbiter 30 negates the first acknowledge signal ACK1 in synchronization with the third acknowledge signal ACK3. Also, at time t4, the first bus bridge 21 outputs, as the sixth acknowledge signal ACK6, a signal indicating the exclusive logical sum of the first access request signal REQ1 and the first acknowledge signal ACK1. That is, at time t4, the level of the sixth acknowledge signal ACK6 remains low.

[0098] When the fifth access request signal REQ5 is negated at time t4, that is, when the access request disappears, the first memory controller 41 starts the counting operation by the timer. After time t4, the timer counts up the count value Count in synchronization with the rising edge of the clock signal CLK.

[0099] After time t4, the first processor 11 does not assert the first access request signal REQ1. In this case, at time t5 after a predetermined time has elapsed from time t4, the count value Count of the timer is incremented to "7". Thus, when the count value Count of the timer is incremented to "7" at time t5, the output signal Tout of the timer is asserted.

[0100] The first memory controller 41 resets the count value Count of the timer to "0" in synchronization with the rising edge of the clock signal CLK that occurs at time t6 immediately after time t5. As a result, at time t6, the output signal Tout of the timer is negated. When the output signal Tout of the timer is negated at time t6, the level of "DISABLE ACK" switches from the low level to the high level.

[0101] The first memory controller 41 asserts the first mode switching signal MD1 at time t7 after a certain time from time t6. For example, when the first memory 51a included in the first storage unit 51 is SRAM, several sequences may be executed to switch the first memory 51a from the normal mode to the sleep mode. The period from time t6 to time t7 is the period during which the above sequence is executed. After time t7, the operation mode of each first memory 51a included in the first storage unit 51 becomes the sleep mode. Note that before time t6 is the period during which the first storage unit 51 can be accessed, and after time t6 is the period during which the first storage unit 51 cannot be accessed.

[0102] As described above, when the time during which the first memory controller 41 does not receive an access request in the state of the first storage unit 51 being in the normal mode exceeds a predetermined time, the first memory controller 41 instructs the first storage unit 51 to shift from the normal mode to the sleep mode. More specifically, the first memory controller 41 starts timing after the fifth access request signal REQ5 is negated while the first storage unit 51 is in the normal mode, and asserts the first mode switching signal MD1 when the timing time exceeds the predetermined time without the fifth access request signal REQ5 being asserted.

[0103] In the present embodiment, the first memory controller 41 asserts the first mode switching signal MD1 after the time has elapsed from when the fifth access request signal REQ5 is negated until the count value Count of the timer is counted up to "7". Thus, in the present embodiment, the maximum value of the count value Count of the timer is set to "7", but the maximum value of the count value Count may be appropriately changed. By adjusting the maximum value of the count value Count, the predetermined time from when the access request disappears until the first storage unit 51 is shifted to the sleep mode can be adjusted.

[0104] FIG. 3 is a second timing chart showing an operation example of the control device 10 in the first case. In FIG. 3, an example of waveforms of the first access request signal REQ1, the sixth acknowledge signal ACK6, the second access request signal REQ2, the first acknowledge signal ACK1, the fifth access request signal REQ5, the third acknowledge signal ACK3, and the first mode switching signal MD1 before and after the operation mode of the first storage unit 51 is switched from the sleep mode to the normal mode is shown.

[0105] Also, similar to FIG. 2, in FIG. 3, the clock signal CLK, the count value Count of the timer built in the first memory controller 41, the output signal Tout of the timer, and "DISABLE ACK" are shown.

[0106] As shown in FIG. 3, in the period before time t11, the levels of the first access request signal REQ1, the sixth acknowledgment signal ACK6, the second access request signal REQ2, the first acknowledgment signal ACK1, the fifth access request signal REQ5, the third acknowledgment signal ACK3, and the output signal Tout of the timer are all low levels. On the other hand, the levels of the first mode switching signal MD1 and "DISABLE ACK" are high levels. Since the level of the first mode switching signal MD1 is high, the first storage unit 51 is in the sleep mode.

[0107] At time t11, the first processor 11 asserts the first access request signal REQ1. Specifically, at time t11, the first processor 11 switches the level of the first access request signal REQ1 from low level to high level. That is, at time t11, the first processor 11 issues an access request.

[0108] In this case, at time t11, the first bus bridge 21 asserts the second access request signal REQ2 in synchronization with the first access request signal REQ1. Also, at time t11, the bus arbiter 30 asserts the fifth access request signal REQ5 in synchronization with the second access request signal REQ2.

[0109] At time t11, since the level of "DISABLE ACK" is high, the first memory controller 41 does not assert the third acknowledgment signal ACK3. In this case, at time t11, the bus arbiter 30 does not assert the first acknowledgment signal ACK1 in synchronization with the third acknowledgment signal ACK3. Also, at time t11, the first bus bridge 21 outputs a signal indicating the exclusive logical sum of the first access request signal REQ1 and the first acknowledgment signal ACK1 as the sixth acknowledgment signal ACK6. As a result, at time t11, the level of the sixth acknowledgment signal ACK6 switches from low level to high level. In other words, at time t11, the first bus bridge 21 asserts the sixth acknowledgment signal ACK6.

[0110] Subsequently, at time t12 which is a certain time after time t11, the first memory controller 41 negates the first mode switching signal MD1. For example, when the first memory 51a included in the first storage unit 51 is SRAM, several sequences may be executed to switch the first memory 51a from the sleep mode to the normal mode. Therefore, each first memory 51a included in the first storage unit 51 does not immediately enter the normal mode immediately after the first mode switching signal MD1 is negated.

[0111] For example, at time t13 which is a certain time after time t12, the sequence ends and each first memory 51a included in the first storage unit 51 enters the normal mode. At this time t13, since the level of "DISABLE ACK" switches from the high level to the low level, the first memory controller 41 asserts the third acknowledge signal ACK3 at time t13.

[0112] In this case, at time t13, the bus arbiter 30 asserts the first acknowledge signal ACK1 in synchronization with the third acknowledge signal ACK3. Also, at time t13, the first bus bridge 21 outputs, as the sixth acknowledge signal ACK6, a signal indicating the exclusive logical sum of the first access request signal REQ1 and the first acknowledge signal ACK1. Thereby, at time t13, the level of the sixth acknowledge signal ACK6 switches from the high level to the low level. In other words, at time t13, the first bus bridge 21 negates the sixth acknowledge signal ACK6.

[0113] After time t13, the operation mode of each first memory 51a included in the first storage unit 51 becomes the normal mode. Note that the period before time t13 is a period during which the first storage unit 51 is inaccessible, and the period after time t13 is a period during which the first storage unit 51 is accessible. The operation after time t13 is the same as the operation described with reference to FIG. 2.

[0114] As described above, when the first memory controller 41 receives an access request from the first processor 11 via the bus arbiter 30 while the first storage unit 51 is in the sleep mode, the first memory controller 41 instructs the first storage unit 51 to shift from the sleep mode to the normal mode. More specifically, when the fifth access request signal REQ5 is asserted while the first storage unit 51 is in the sleep mode, the first memory controller 41 negates the first mode switching signal MD1.

[0115] After the first storage unit 51 has shifted to the sleep mode, the first memory controller 41 returns an acknowledgement for the access request from the first processor 11 to the first bus bridge 21 via the bus arbiter 30. More specifically, after the first storage unit 51 has shifted to the sleep mode, the first memory controller 41 asserts the third acknowledgement signal ACK3. When an access request is issued from the first processor 11, when the third acknowledgement signal ACK3 is asserted, the bus arbiter 30 asserts the first acknowledgement signal ACK1.

[0116] The first bus bridge 21 instructs the first processor 11 to wait until it receives an acknowledgement from the bus arbiter 30. Specifically, as shown in FIG. 3, the first bus bridge 21 outputs a high-level sixth acknowledgement signal ACK6 to the first processor 11 during the period from time t11 to time t13. As a result, the first processor 11 waits until the sixth acknowledgement signal ACK6 is negated without asserting the first data read signal RD1 or the first data write signal WR1 during the period from time t11 to time t13.

[0117] Note that, in the present embodiment, an operation example of the control device 10 has been described assuming the first case, but the operations of the control device 10 in each of the second case, the third case, the fourth case, the fifth case, and the sixth case are the same as the operation in the first case.

[0118] (Effect of the present embodiment) The control device 10 of this embodiment includes a first storage unit 51 that does not require refreshing and has volatility, a first processor 11 that accesses the first storage unit 51, a bus arbiter 30 that arbitrates access requests from the first processor 11, and a first memory controller 41 that controls the mode of the first storage unit 51 based on an access request received from the first processor 11 via the bus arbiter 30. When the time during which the first storage unit 51 does not receive an access request in the normal mode exceeds a predetermined time, the first memory controller 41 instructs the first storage unit 51 to shift from the normal mode to the sleep mode. According to this embodiment as described above, when the time during which the first storage unit 51 does not receive an access request in the normal mode exceeds a predetermined time, the first memory controller 41 instructs the first storage unit 51 to shift from the normal mode to the sleep mode. Therefore, the first processor 11 does not need to execute a process of determining whether the first storage unit 51 is being accessed by another processor and a process of shifting the first storage unit 51 that is not being accessed to the sleep mode. Thus, according to this embodiment, the processing load on the first processor 11 when shifting the first storage unit 51 from the normal mode to the sleep mode can be reduced.

[0119] The control device 10 of this embodiment further includes a first bus bridge 21 that relays communication between the first processor 11 and the bus arbiter 30. When the first storage unit 51 receives an access request in the sleep mode, the first memory controller 41 instructs the first storage unit 51 to shift from the sleep mode to the normal mode, and after the first storage unit 51 has shifted to the sleep mode, returns an acknowledgment for the access request to the first bus bridge 21 via the bus arbiter 30. The first bus bridge 21 instructs the first processor 11 to wait until it receives an acknowledgment from the bus arbiter 30. According to the present embodiment as described above, when the first memory controller 41 receives an access request while the first storage unit 51 is in the sleep mode, it instructs the first storage unit 51 to shift from the sleep mode to the normal mode. Therefore, the processing load on the first processor 11 when shifting the first storage unit 51 from the sleep mode to the normal mode can be reduced. Further, after the first storage unit 51 has shifted to the sleep mode, the first memory controller 41 returns an acknowledgement for the access request to the first bus bridge 21 via the bus arbiter 30, and the first bus bridge 21 instructs the first processor 11 to wait until it receives the acknowledgement from the bus arbiter 30. Thereby, it is possible to prevent the first processor 11 from accessing the first storage unit 51 until the first storage unit 51 has completely switched to the normal mode.

[0120] The control device 10 of the present embodiment further includes a second storage unit 52 that does not require refreshing and has volatility, and a second memory controller 42 that controls the mode of the second storage unit 52 based on an access request received from the first processor 11 via the bus arbiter 30. When the time during which the second storage unit 52 does not receive an access request while in the normal mode exceeds a predetermined time, the second memory controller 42 instructs the second storage unit 52 to shift from the normal mode to the power-saving mode. According to the present embodiment as described above, when the time during which the second storage unit 52 does not receive an access request while in the normal mode exceeds a predetermined time, the second memory controller 42 instructs the second storage unit 52 to shift from the normal mode to the power-saving mode. Therefore, the first processor 11 does not need to execute a process of determining whether the second storage unit 52 is being accessed by another processor and a process of shifting the second storage unit 52 that is not being accessed to the sleep mode. Therefore, according to the present embodiment, the processing load on the first processor 11 when shifting the second storage unit 52 from the normal mode to the sleep mode can be reduced.

[0121] The control device 10 of this embodiment further includes a first bus bridge 21 that relays communication between the first processor 11 and the bus arbiter 30. When the second memory controller 42 receives an access request while the second storage unit 52 is in the sleep mode, it instructs the second storage unit 52 to shift from the sleep mode to the normal mode. After the second storage unit 52 has shifted to the sleep mode, the second memory controller 42 returns an acknowledgment for the access request to the first bus bridge 21 via the bus arbiter 30. The first bus bridge 21 instructs the first processor 11 to wait until it receives an acknowledgment from the bus arbiter 30. According to this embodiment as described above, when the second memory controller 42 receives an access request while the second storage unit 52 is in the sleep mode, it instructs the second storage unit 52 to shift from the sleep mode to the normal mode, so the processing load on the first processor 11 when shifting the second storage unit 52 from the sleep mode to the normal mode can be reduced. Also, after the second storage unit 52 has shifted to the sleep mode, the second memory controller 42 returns an acknowledgment for the access request to the first bus bridge 21 via the bus arbiter 30, and the first bus bridge 21 instructs the first processor 11 to wait until it receives an acknowledgment from the bus arbiter 30. Thereby, it is possible to prevent the first processor 11 from accessing the second storage unit 52 until the second storage unit 52 has completely switched to the normal mode.

[0122] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present disclosure. For example, the following modification examples are conceivable.

[0123] (1) Fig. 4 is a block diagram showing a first modification example of the control device 10. In the above embodiment, the form in which the first memory controller 41 has the function of measuring the time when it does not receive an access request from the first processor 11 is exemplified, but the present disclosure is not limited thereto. For example, as shown in Fig. 4, the control device 10 may further include a timing circuit 61 that measures the time when it does not receive an access request from the first processor 11. As an example, the timing circuit 61 is a timer.

[0124] The output signal of the timing circuit 61 is input to the first memory controller 41. The timing circuit 61 starts a counting operation when the fifth access request signal REQ5 is negated. In other words, the timing circuit 61 starts a counting operation when the access request disappears. The timing circuit 61 counts up the count value in synchronization with the rising edge of the clock signal CLK. The timing circuit 61 asserts the output signal when the count value is counted up to "7".

[0125] (2) Fig. 5 is a block diagram showing a second modification example of the control device 10. In the above embodiment, the form in which the first storage unit 51, the second storage unit 52, and the third storage unit 53 are each a memory bank including a plurality of memories that do not require refreshing and are volatile is exemplified, but the present disclosure is not limited thereto. For example, as shown in Fig. 5, the control device 10 may include a first storage unit 71, a second storage unit 72, and a third storage unit 73 instead of the first storage unit 51, the second storage unit 52, and the third storage unit 53. The first storage unit 71, the second storage unit 72, and the third storage unit 73 are each one memory that does not require refreshing and is volatile. For example, the first storage unit 71, the second storage unit 72, and the third storage unit 73 are each SRAM.

[0126] (3) In the above embodiment, the control device 10 including two processors, i.e., the first processor 11 and the second processor 12, is illustrated. However, the number of processors is not limited to two. Also, in the above embodiment, the control device 10 including three storage units, i.e., the first storage unit 51, the second storage unit 52, and the third storage unit 53, is illustrated. However, the number of storage units is not limited to three. The number of memory controllers (control circuits) may be the same as the number of storage units, and the number of bus bridges may be the same as the number of processors.

[0127] (4) In the above embodiment, the control device 10 including the first bus bridge 21 and the second bus bridge 22 is illustrated. However, the control device 10 does not necessarily include the first bus bridge 21 and the second bus bridge. In this case, the first processor 11 and the second processor 12 may directly communicate with the bus arbiter 30, respectively.

[0128] 〔Summary of the present disclosure〕 The summary of the present disclosure is appended below.

[0129] (Appended Note 1) A control device comprising: a first storage unit that does not require refreshing and has volatility; a first processor that accesses the first storage unit; a bus arbiter that mediates access requests from the first processor; and a first control circuit that performs mode control of the first storage unit based on the access request received from the first processor via the bus arbiter, wherein the first control circuit instructs the first storage unit to shift from the normal mode to the power-saving mode when the time during which the first storage unit does not receive the access request in the normal mode exceeds a predetermined time.

[0130] According to the control device described in Supplementary Note 1, when the time during which the first storage unit does not receive an access request in the normal mode exceeds a predetermined time, the first control circuit instructs the first storage unit to shift from the normal mode to the power-saving mode. Therefore, the first processor does not need to execute a process of determining whether the first storage unit is being accessed by another processor and a process of shifting the first storage unit that is not being accessed to the power-saving mode. Accordingly, according to the control device described in Supplementary Note 1, the processing load on the first processor when shifting the first storage unit from the normal mode to the power-saving mode can be reduced.

[0131] (Supplementary Note 2) The control device according to Supplementary Note 1 further includes a first bus bridge that relays communication between the first processor and the bus arbiter. When the first storage unit receives the access request in the power-saving mode, the first control circuit instructs the first storage unit to shift from the power-saving mode to the normal mode. After the first storage unit has shifted to the power-saving mode, the first control circuit returns an acknowledgment for the access request to the first bus bridge via the bus arbiter. The first bus bridge instructs the first processor to wait until it receives the acknowledgment from the bus arbiter.

[0132] According to the control device described in Supplementary Note 2, when the first storage unit receives the access request in the power-saving mode, the first control circuit instructs the first storage unit to shift from the power-saving mode to the normal mode. Therefore, the processing load on the first processor when shifting the first storage unit from the power-saving mode to the normal mode can be reduced. Further, after the first storage unit has shifted to the power-saving mode, the first control circuit returns an acknowledgment for the access request to the first bus bridge via the bus arbiter, and the first bus bridge instructs the first processor to wait until it receives the acknowledgment from the bus arbiter. Thereby, it is possible to prevent the first processor from accessing the first storage unit until the first storage unit has completely switched to the normal mode.

[0133] (Supplementary Note 3) The control device according to Supplementary Note 1 or Supplementary Note 2, wherein the first control circuit measures the time during which the access request is not received.

[0134] (Supplementary Note 4) The control device according to Supplementary Note 1 or Supplementary Note 2, further comprising a timing circuit that measures the time during which the access request is not received.

[0135] (Supplementary Note 5) A second storage unit that does not require refreshing and has volatility, and a second control circuit that performs mode control of the second storage unit based on an access request received from the first processor via the bus arbiter, wherein the second control circuit instructs the second storage unit to shift from the normal mode to the power-saving mode when the time during which the second storage unit does not receive the access request in the normal mode exceeds a predetermined time. The control device according to Supplementary Note 1.

[0136] According to the control device described in Supplementary Note 5, since the second control circuit instructs the second storage unit to shift from the normal mode to the power-saving mode when the time during which the second storage unit does not receive the access request in the normal mode exceeds a predetermined time, the first processor does not need to execute a process of determining whether the second storage unit is being accessed by another processor and a process of shifting the second storage unit that is not being accessed to the power-saving mode. Therefore, according to the control device described in Supplementary Note 5, the processing load on the first processor when shifting the second storage unit from the normal mode to the power-saving mode can be reduced.

[0137] (Appendix 6) The control device further includes a first bus bridge for relaying communication between the first processor and the bus arbiter. When the second storage unit receives the access request in the power-saving mode, the second control circuit instructs the second storage unit to shift from the power-saving mode to the normal mode. After the second storage unit has shifted to the power-saving mode, the second control circuit returns an acknowledgement for the access request to the first bus bridge via the bus arbiter. The first bus bridge instructs the first processor to wait until it receives the acknowledgement from the bus arbiter. The control device according to Appendix 5.

[0138] According to the control device described in Appendix 6, when the second storage unit receives an access request in the power-saving mode, the second control circuit instructs the second storage unit to shift from the power-saving mode to the normal mode. Therefore, the processing load on the first processor when shifting the second storage unit from the power-saving mode to the normal mode can be reduced. Further, after the second storage unit has shifted to the power-saving mode, the second control circuit returns an acknowledgement for the access request to the first bus bridge via the bus arbiter. The first bus bridge instructs the first processor to wait until it receives the acknowledgement from the bus arbiter. Thereby, it is possible to prevent the second processor from accessing the second storage unit until the second storage unit has completely switched to the normal mode.

[0139] (Appendix 7) The first storage unit and the second storage unit are each a memory bank including a plurality of memories that do not require refreshing and have volatility. The control device according to Appendix 5 or Appendix 6.

[0140] (Appendix 8) The first storage unit and the second storage unit are each one memory that does not require refreshing and has volatility. The control device according to Appendix 5 or Appendix 6.

Description of Reference Numerals

[0141] 10... Control difference, 11... First processor, 12... Second processor, 21... First bus bridge, 22... Second bus bridge, 30... Bus arbiter, 41... First memory controller, 42... Second memory controller, 43... Third memory controller, 51... First storage unit, 52... Second storage unit, 53... Third storage unit

Claims

1. A first memory unit that does not require refreshing and has volatility, A first processor that accesses the first memory unit, A bus arbiter that mediates access requests from the first processor, A first control circuit that performs mode control of the first memory unit based on the access request received from the first processor via the bus arbiter, Comprising, When the time that the first memory unit does not receive the access request in the normal mode exceeds a predetermined time, the first control circuit instructs the first memory unit to shift from the normal mode to the power-saving mode, Control device.

2. Further comprising a first bus bridge that relays communication between the first processor and the bus arbiter, The first control circuit, When the first memory unit receives the access request in the power-saving mode, the first control circuit instructs the first memory unit to shift from the power-saving mode to the normal mode, After the first memory unit shifts to the power-saving mode, the first control circuit returns an acknowledgment for the access request to the first bus bridge via the bus arbiter, The first bus bridge instructs the first processor to wait until it receives the acknowledgment from the bus arbiter, The control device according to claim 1.

3. The first control circuit measures the time when it does not receive the access request. The control device according to claim 1 or 2.

4. The control device according to claim 1 or 2, further comprising a timing circuit that measures the time when it does not receive the access request.

5. A second memory unit that does not require refreshing and has volatility, A second control circuit that performs mode control of the second memory unit based on the access request received from the first processor via the bus arbiter, Further comprising, When the time that the second memory unit does not receive the access request in the normal mode exceeds a predetermined time, the second control circuit instructs the second memory unit to shift from the normal mode to the power-saving mode, The control device according to claim 1.

6. Further comprising a first bus bridge that relays communication between the first processor and the bus arbiter, The second control circuit, When the second memory unit receives the access request in the power-saving mode, the second control circuit instructs the second memory unit to shift from the power-saving mode to the normal mode, After the second memory unit shifts to the power-saving mode, an acknowledgement for the access request is returned to the first bus bridge via the bus arbiter. The first bus bridge instructs the first processor to wait until it receives the acknowledgement from the bus arbiter. The control device according to claim 5. **Claim 7** The control device according to claim 5 or 6, wherein the first memory unit and the second memory unit are each a memory bank including a plurality of memories that do not require refreshing and are volatile. **Claim 8** The control device according to claim 5 or 6, wherein the first memory unit and the second memory unit are each one memory that does not require refreshing and is volatile.

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