Circuit arrangement and oscillator

Abstract

To provide a circuit arrangement that can predict in advance a failure in a PLL circuit due to aging of a voltage control-type oscillation circuit.SOLUTION: A circuit arrangement comprises: a first oscillation circuit that generates a first clock signal; a PLL circuit that includes a second oscillation circuit that generates a second clock signal, and a frequency control voltage generation circuit that generates a frequency control voltage for controlling the frequency of the second clock signal, and synchronizes the phase of the second clock signal to the phase of the first clock signal; and a failure detection circuit that monitors the frequency control voltage, and detects whether the frequency control voltage is likely to fall out of a predetermined voltage range in which the second oscillation circuit can normally operate.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a circuit device and an oscillator.

Background Art

[0002] Patent Document 1 describes a circuit device that detects a failure of an oscillator in advance based on a change in the threshold voltage of a transistor inside the oscillator.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the circuit device described in Patent Document 1, it is impossible to predict in advance a failure of a PLL circuit due to aging of a voltage-controlled oscillation circuit.

Means for Solving the Problems

[0005] One aspect of the circuit device according to the present invention is a first oscillation circuit that generates a first clock signal, a second oscillation circuit that generates a second clock signal, and a frequency control voltage generation circuit that generates a frequency control voltage for controlling the frequency of the second clock signal, including a PLL circuit that phase-locks the second clock signal to the first clock signal, a failure detection circuit that monitors the frequency control voltage and detects whether the frequency control voltage may deviate from a predetermined voltage range in which the second oscillation circuit can operate normally.

[0006] One aspect of the oscillator according to the present invention is comprising one aspect of the circuit device.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0008] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Also, not all of the configurations described below are essential constituent elements of the present invention.

[0009] 1. First Embodiment 1-1. Structure of the Oscillator FIG. 1 is a cross-sectional view showing the oscillator of the present embodiment. FIG. 2 is a plan view of the oscillator as viewed from the upper surface side. FIG. 3 is a cross-sectional view showing the inner package of the oscillator and its interior. FIG. 4 is a cross-sectional view showing the vibrator of the oscillator.

[0010] The oscillator 1 shown in FIGS. 1 and 2 is a thermostatic crystal oscillator, and includes an outer package 2, an inner package 3, a control IC 4, and a vibrator 5. The inner package 3, the control IC 4, and the vibrator 5 are housed in the outer package 2.

[0011] As shown in FIG. 1, the outer package 2 has an outer base 21 and an outer lid 22. The outer base 21 has a substrate 27, a frame-shaped wall portion 28 standing upright upward from the edge of the upper surface of the substrate 27, and a frame-shaped leg portion 29 standing upright downward from the edge of the lower surface of the substrate 27. An upper recess 211 that opens to the upper surface 21a of the outer base 21 is formed by the upper surface of the substrate 27 and the wall portion 28, and a lower recess 212 that opens to the lower surface 21b of the outer base 21 is formed by the lower surface of the substrate 27 and the leg portion 29. Therefore, the outer base 21 has a substantially H shape in cross-section.

[0012] The upper recess 211 has a first upper recess 211a that opens to the upper surface 21a, a second upper recess 211b that opens to the bottom surface of the first upper recess 211a and has a smaller opening than the first upper recess 211a, and a third upper recess 211c that opens to the bottom surface of the second upper recess 211b and has a smaller opening than the second upper recess 211b. The control IC 4 is disposed on the bottom surface of the first upper recess 211a, and the inner package 3 is disposed on the bottom surface of the third upper recess 211c.

[0013] The outer lid 22 closes the opening of the upper recess 211 and is joined to the upper surface 21a of the outer base 21 via a sealing member 23 such as a seal ring or low-melting glass. As a result, the upper recess 211 is hermetically sealed, and an outer accommodation space S2 as an accommodation space is formed inside the outer package 2. On the other hand, the opening of the lower recess 212 is not sealed and faces the outside of the outer package 2. The inner package 3 and the control IC 4 are accommodated in the outer accommodation space S2, and the vibrator 5 is disposed in the lower recess 212.

[0014] On the outer base 21, a plurality of internal terminals 241 disposed on the bottom surface of the first upper recess 211a, a plurality of internal terminals 242 disposed on the bottom surface of the second upper recess 211b, a plurality of internal terminals 243 disposed on the bottom surface of the lower recess 212, and a plurality of external terminals 244 disposed on the lower surface 21b, that is, the top surface of the leg portion 29, are disposed. Each internal terminal 241 is electrically connected to the control IC 4 via a bonding wire BW1, each internal terminal 242 is electrically connected to the inner package 3 via a bonding wire BW2, and each internal terminal 243 is electrically connected to the vibrator 5 via a conductive bonding member B1.

[0015] These respective terminals 241, 242, 243, 244 are appropriately electrically connected via internal wiring 25 formed inside the outer base 21, electrically connecting the control IC 4, the inner package 3, the vibrator 5, and the external terminal 244. The internal wiring 25 is connected to the external terminal 244 through the inside of the leg portion 29. Then, connection to an external device (not shown) is made at the external terminal 244. A side terminal 245 connected to the external terminal 244 is disposed on the side surface of the leg portion 29. The side terminal 245 is a castellation. Therefore, the solder H spreads over the side terminal 245 to form a fillet, making the mechanical and electrical bonding with the external device stronger. However, the present invention is not limited thereto, and for example, the side terminal 245 may be omitted.

[0016] As shown in FIG. 3, the inner package 3 has an inner base 31 and an inner lid 32. The inner base 31 has a recess 311 that opens to the lower surface 31b.

[0017] The recess 311 has a first recess 311a that opens to the lower surface 31b, a second recess 311b that opens to the bottom surface of the first recess 311a and has a smaller opening than the first recess 311a, and a third recess 311c that opens to the bottom surface of the second recess 311b and has a smaller opening than the second recess 311b. The vibration element 6 is disposed on the bottom surface of the first recess 311a, and the heat generating IC 7 and the oscillation IC 8 are arranged side by side in the X-axis direction on the bottom surface of the third recess 311c.

[0018] The inner lid 32 is joined to the lower surface 31b of the inner base 31 via a sealing member 33 such as a seal ring or a low melting point glass so as to close the opening of the recess 311. As a result, the recess 311 is hermetically sealed, and an inner accommodation space S3 is formed inside the inner package 3. The vibration element 6, the heat generating IC 7, and the oscillation IC 8 are accommodated in the inner accommodation space S3.

[0019] Such an inner accommodation space S3 is airtight and is in a reduced pressure state, preferably a state closer to a vacuum. As a result, the viscous resistance of the inner accommodation space S3 is reduced, and the vibration characteristics of the vibration element 6 are improved. However, the atmosphere in the inner accommodation space S3 is not particularly limited.

[0020] A plurality of internal terminals 341 disposed on the bottom surface of the first recess 311a, a plurality of internal terminals 342 and 343 disposed on the bottom surface of the second recess 311b, and a plurality of external terminals 344 disposed on the upper surface 31a of the inner base 31 are disposed on the inner base 31. Each internal terminal 341 is electrically connected to the vibration element 6 via a conductive bonding member B2 and a bonding wire BW3, each internal terminal 342 is electrically connected to the heat generating IC 7 via a bonding wire BW4, and each internal terminal 343 is electrically connected to the oscillation IC 8 via a bonding wire BW5.

[0021] Each of these terminals 341, 342, 343, and 344 is electrically connected as appropriate via internal wiring (not shown) formed within the inner package 3, electrically connecting the vibration element 6, the heat-generating IC 7, the oscillation IC 8, and the external terminal 344. In such an inner package 3, the inside and outside thereof are electrically connected via the external terminal 344.

[0022] The inner package 3 as described above is fixed to the bottom surface of the third upper recess 211c via a joining member B3 having a sufficiently low thermal conductivity in the inner lid 32.

[0023] As shown in FIG. 3, the heat-generating IC 7 is disposed on the bottom surface of the third recess 311c with the active surface facing downward (toward the inner lid 32 side), and is electrically connected to a plurality of internal terminals 342 via bonding wires BW4. The oscillation IC 8 is disposed on the bottom surface of the third recess 311c with the active surface facing downward (toward the inner lid 32 side), and is electrically connected to a plurality of internal terminals 343 via bonding wires BW5.

[0024] As shown in FIG. 4, the vibrator 5 includes a package 51 and a vibration element 55 housed in the package 51.

[0025] The package 51 has a base 52 and a lid 53. The base 52 has a recess 521 that opens to the lower surface 52b. The vibration element 55 is disposed on the bottom surface of the recess 521.

[0026] The lid 53 is joined to the lower surface 52b of the base 52 via a sealing member 54 such as a seal ring or a low melting point glass so as to close the opening of the recess 521. Thereby, the recess 521 is hermetically sealed, and an accommodation space S5 is formed within the package 51. The vibration element 55 is accommodated in the accommodation space S5. The accommodation space S5 is airtight and in a depressurized state, preferably a state closer to a vacuum. Thereby, the viscous resistance of the accommodation space S5 is reduced, and the vibration characteristics of the vibration element 55 are improved. However, the atmosphere of the accommodation space S5 is not particularly limited.

[0027] The base 52 is provided with a plurality of internal terminals 561 disposed on the bottom surface of the recess 521 and a plurality of external terminals 564 disposed on the upper surface 52a of the base 52. Each internal terminal 561 is electrically connected to the vibration element 55 via a conductive bonding member B4. These terminals 561 and 564 are electrically connected as appropriate via internal wiring (not shown) formed in the base 52, and electrically connect the vibration element 55 and the external terminal 564. In such a package 51, the inside and outside are electrically connected via the external terminal 564.

[0028] The vibration element 55 is an AT-cut crystal vibration element. However, the vibration element 55 does not have to be an AT-cut crystal vibration element, and for example, an SC-cut crystal vibration element, a BT-cut crystal vibration element, a tuning fork type crystal vibration element, a surface acoustic wave resonator, other piezoelectric vibration elements, MEMS resonator elements, etc. may be used.

[0029] As shown in FIG. 4, the vibrator 5 is fixed to the bottom surface of the lower recess 212 via a conductive bonding member B1. Also, the external terminal 564 and the internal terminal 243 are electrically connected via the bonding member B1.

[0030] 1-2. Functional Configuration of the Oscillator FIG. 5 is a functional block diagram of the oscillator 1 according to the first embodiment. In FIG. 5, the same components as those shown in FIGS. 1 to 4 are denoted by the same reference numerals. As shown in FIG. 5, the oscillator 1 according to the first embodiment includes a control IC 4, a vibrator 5, a vibration element 6, a heat generating IC 7, and an oscillation IC 8.

[0031] The oscillation IC8 includes an oscillation circuit 81 and a temperature sensor 82, and operates with the supply of the power supply voltage VOSC from the control IC4. The oscillation circuit 81 is electrically connected to both ends of the vibration element 6, and is a circuit that oscillates the vibration element 6 and outputs an oscillation signal OSCO by amplifying the output signal of the vibration element 6 and feeding it back to the vibration element 6. For example, the oscillation circuit 81 may be an oscillation circuit using an inverter as an amplification element, or may be an oscillation circuit using a bipolar transistor as an amplification element. The oscillation signal OSCO output from the oscillation circuit 81 is input to the control IC4.

[0032] The temperature sensor 82 is a temperature-sensitive element that detects temperature and outputs a temperature detection signal TS1 having a voltage level corresponding to the detected temperature. The temperature sensor 82 is built into the oscillation IC8 and detects the temperature of the oscillation IC8. The temperature detection signal TS1 output from the temperature sensor 82 is input to the control IC4. The temperature sensor 82 may be, for example, a sensor that utilizes the temperature dependence of the forward voltage of the PN junction of a diode.

[0033] The heating IC7 includes a temperature control element 71 and a temperature sensor 72. The temperature control element 71 is an element that controls the temperature of the vibration element 6 based on the temperature control signal OVC output from the control IC4, and may be a heating element. For example, the temperature control element 71 is a CMOS transistor, and the amount of heat generated changes according to the voltage of the temperature control signal OVC input to the gate. The higher the amount of heat generated by the temperature control element 71, the higher the temperature of the vibration element 6, and the amount of heat generated by the temperature control element 71 is controlled by the control IC4 so that the temperature of the vibration element 6 becomes constant at a target set temperature. For example, the set temperature may be a fixed value such as 80 °C, or may be arbitrarily set within a predetermined range such as a range of 70 °C or more and 125 °C or less.

[0034] The temperature sensor 72 is a temperature-sensitive element that detects temperature and outputs a temperature detection signal TS2 having a voltage level corresponding to the detected temperature. The temperature sensor 72 is built into the heat-generating IC 7 and detects the temperature of the heat-generating IC 7. Since the temperature control element 71 is also built into the heat-generating IC 7, the temperature sensor 72 will detect the temperature of the temperature control element 71. The temperature detection signal TS2 output from the temperature sensor 72 is input to the control IC 4. The temperature sensor 72 may be, for example, a sensor that utilizes the temperature dependence of the forward voltage of the PN junction of a diode.

[0035] As shown in FIG. 3, the vibration element 6, the heat-generating IC 7, and the oscillation IC 8 are housed in the inner package 3, and the heat generation of the heat-generating IC 7 is controlled by the control IC 4 so that the temperature of the vibration element 6 is kept constant. Since the heat-generating IC 7 is the heat source and the radiant heat from the heat-generating IC 7 is transmitted to the vibration element 6 and the oscillation IC 8, a difference occurs between the temperatures of the vibration element 6 and the oscillation IC 8 and the temperature of the heat-generating IC 7. In contrast, the vibration element 6 and the oscillation IC 8 are arranged separately from the heat-generating IC 7. If it is considered that the thermal distance between the heat-generating IC 7 and the vibration element 6 is approximately the same as the thermal distance between the heat-generating IC 7 and the oscillation IC 8, it can be said that the temperature of the oscillation IC 8 is close to the temperature of the vibration element 6. That is, the temperature detected by the temperature sensor 82 built into the oscillation IC 8 is closer to the temperature of the vibration element 6 than the temperature detected by the temperature sensor 72 built into the heat-generating IC 7. Therefore, as will be described later, the control IC 4 controls the heat generation of the heat-generating IC 7 based on the temperature detection signal TS1 output from the temperature sensor 82. However, depending on the arrangement of the vibration element 6, the heat-generating IC 7, and the oscillation IC 8, there may be a case where the temperature of the heat-generating IC 7 is closer to the temperature of the vibration element 6 than the temperature of the oscillation IC 8. In that case, the control IC 4 may control the heat generation of the heat-generating IC 7 based on the temperature detection signal TS2 output from the temperature sensor 72.

[0036] The control IC4 includes a microcontroller 40, a selector 41, a temperature sensor 42, an A / D conversion circuit 43, a D / A conversion circuit 44, a fractional N-PLL circuit 45, a PLL circuit 46, a switch circuit 47, a power supply circuit 48, an interface circuit 49, a memory 90, and a register 94. PLL is the abbreviation of Phase Locked Loop.

[0037] Based on the power supply voltage VDD and the ground voltage VSS supplied from outside the oscillator 1, the power supply circuit 48 generates a power supply voltage VOSC which is a constant voltage lower than the power supply voltage VDD. For example, the power supply circuit 48 generates a power supply voltage VOSC which is a constant voltage based on the output voltage of a bandgap reference circuit. The power supply voltage VOSC is supplied to the oscillation IC8.

[0038] The fractional N-PLL circuit 45 receives the oscillation signal OSCO output from the oscillation IC8, and generates and outputs a clock signal CK1 in which the frequency f OSCO of the oscillation signal OSCO is converted to a frequency f CK1 corresponding to the division ratio indicated by the division ratio control signal DIVC.

[0039] FIG. 6 is a diagram showing a configuration example of the fractional N-PLL circuit 45. As shown in FIG. 6, the fractional N-PLL circuit 45 includes a phase comparator 111, a charge pump 112, a low-pass filter 113, a voltage-controlled oscillation circuit 114, and a division circuit 115.

[0040] The phase comparator 111 compares the phases of the oscillation signal OSCO and the clock signal FBCLK output from the division circuit 115, and outputs the comparison result as a pulse voltage.

[0041] The charge pump 112 converts the pulse voltage output from the phase comparator 111 into a current, and the low-pass filter 113 smoothes and converts the current output from the charge pump 112 into a voltage.

[0042] The voltage-controlled oscillator circuit 114 uses the output voltage of the low-pass filter 113 as a frequency control voltage and outputs a clock signal CK1 whose frequency changes according to the frequency control voltage. The voltage-controlled oscillator circuit 114 can be realized as various types of oscillator circuits such as an LC oscillator circuit composed of an inductance element such as a coil and a capacitance element such as a capacitor, or an oscillator circuit using a piezoelectric oscillator such as a crystal oscillator.

[0043] The frequency division circuit 115 uses the value of the frequency division ratio control signal DIVC as a frequency division ratio and outputs a clock signal FBCLK obtained by dividing the clock signal CK1 output from the voltage-controlled oscillator circuit 114.

[0044] The fractional-N PLL circuit 45 configured as described above performs feedback control so that the phase of the oscillation signal OSCO matches the phase of the signal obtained by dividing the clock signal CK1 by the frequency division ratio specified by the frequency division ratio control signal DIVC, thereby generating the clock signal CK1. The frequency division ratio control signal DIVC is delta-sigma modulated, and the frequency division ratio specified by the frequency division ratio control signal DIVC switches between a plurality of integer frequency division ratios and becomes a fractional frequency division ratio when averaged. Therefore, the frequency f CK1 is not an integer multiple of the frequency f OSCO The fractional-N PLL circuit 45 may output a clock signal CK1 having a frequency f OSCO that is different from f CK1 and is substantially constant regardless of the outside air temperature.

[0045] Returning to the description of FIG. 5, the PLL circuit 46 receives the clock signal CK1 output from the fractional-N PLL circuit 45 and generates and outputs a clock signal CK2 having the same frequency f CK1 as the frequency f CK2 of the clock signal CK1.

[0046] FIG. 7 is a diagram showing a configuration example of the PLL circuit 46. As shown in FIG. 7, the PLL circuit 46 includes a phase comparator 121, a charge pump 122, a low-pass filter 123, and an oscillator circuit 124.

[0047] The phase comparator 121 compares the phases of the clock signal CK1 and the clock signal CK2 output by the oscillation circuit 124, and outputs the comparison result as a pulse voltage.

[0048] The charge pump 122 converts the pulse voltage output by the phase comparator 121 into a current, and the low-pass filter 123 smoothes and voltage-converts the current output by the charge pump 122.

[0049] The oscillation circuit 124 uses the output voltage of the low-pass filter 123 as the frequency control voltage VC, and outputs a clock signal CK2 whose frequency f CK2 changes according to the frequency control voltage VC. Specifically, the oscillation circuit 124 is connected to the oscillator 5, oscillates the oscillator 5, and generates a clock signal CK2 with a frequency f CK2 corresponding to the frequency control voltage VC.

[0050] In this way, the oscillator 5 and the oscillation circuit 124 constitute a voltage-controlled oscillator 9 whose oscillation frequency changes according to the frequency control voltage VC. Also, the phase comparator 121, the charge pump 122, and the low-pass filter 123 constitute a frequency control voltage generation circuit 120 that inputs the clock signal CK1 and generates a frequency control voltage VC for controlling the frequency f CK2 of the clock signal CK2.

[0051] The PLL circuit 46 configured in this way inputs the clock signal CK1 output from the fractional N-PLL circuit 45, and phase-aligns the clock signal CK2 with the clock signal CK1. That is, the PLL circuit 46 feedback-controls the frequency control voltage VC so that the phases of the clock signal CK1 and the clock signal CK2 match, and thereby generates and outputs a clock signal CK2 with a frequency f CK1 the same as the frequency f CK2 of the clock signal CK1.

[0052] Returning to the description of FIG. 5, the clock signal CK1 output from the fractional N-PLL circuit 45 has a frequency f CK1 that is a non-integer multiple of the frequency f OSCO of the oscillation signal OSCO, and has a large jitter. In contrast, the clock signal CK2 output from the PLL circuit 46 has a frequency f CK2 that is the same as the frequency f CK1 of the clock signal CK1, and is generated by oscillating the oscillator 5 with high frequency stability, so the jitter is smaller than that of the clock signal CK1.

[0053] The switch circuit 47 outputs a clock signal CK that selects either the clock signal CK1 or the clock signal CK2 according to the logic level of the switch control signal SWC output from the register 94. The clock signal CK is output to the outside of the oscillator 1. The clock signal CK may be supplied to the external device 100 or to a device different from the external device 100. For example, during normal operation of the oscillator 1, the clock signal CK2 with small jitter may be selected as the clock signal CK, and the clock signal CK1 may be selected as the clock signal CK during inspection of the clock signal CK1.

[0054] The temperature sensor 42 is a temperature-sensitive element that detects temperature and outputs a temperature detection signal TS3 having a voltage level corresponding to the detected temperature. The temperature sensor 42 is built into the control IC4 and detects the temperature of the control IC4. As shown in FIG. 1, the control IC4 is arranged close to the outer lid 22, the distance between the vibration element 6 and the temperature sensor 42 is larger than the distance between the vibration element 6 and the temperature sensor 82 included in the oscillation IC8, and the temperature of the control IC4 is easily affected by the outside air temperature of the oscillator 1. Therefore, assuming that the heat generation amount of the control IC4 is substantially constant, the temperature sensor 42 can detect the change in the outside air temperature of the oscillator 1. The temperature detection signal TS2 output from the temperature sensor 72 is input to the control IC4. The temperature sensor 72 may be, for example, a sensor that utilizes the temperature dependence of the forward voltage of the PN junction of a diode.

[0055] The selector 41 selects and outputs any one of the temperature detection signal TS1 output from the oscillation IC8, the temperature detection signal TS2 output from the heating IC7, the temperature detection signal TS3 output from the temperature sensor 42, and the frequency control voltage VC output from the PLL circuit 46. In this embodiment, the selector 41 selects the temperature detection signals TS1, TS2, TS3, and the frequency control voltage VC in a time-division manner and outputs them periodically.

[0056] The A / D conversion circuit 43 converts the voltages of the temperature detection signals TS1, TS2, TS3, which are analog signals output from the selector 41 in a time-division manner, and the frequency control voltage VC into temperature codes DTS1, DTS2, DTS3, which are digital signals, and the frequency control code DVC, respectively. The A / D conversion circuit 43 may convert the temperature detection signals TS1, TS2, TS3, and the frequency control voltage VC into the temperature codes DTS1, DTS2, DTS3, and the frequency control code DVC after converting the voltage levels by means such as resistor voltage division.

[0057] The microcontroller 40 includes a CPU 10 and a memory 15. The CPU is an abbreviation for Central Processing Unit. The non-volatile memory 90 stores temperature control data 91 and temperature compensation data 92, which are transferred to the memory 15 when the oscillator 1 is started. The non-volatile memory 90 also stores a temperature control program, a temperature compensation program, and a failure detection program (not shown), which are transferred to the memory 15 when the oscillator 1 is started.

[0058] By executing the temperature control program transferred to the memory 15, the CPU 10 functions as a temperature control circuit 11. The temperature control circuit 11 controls the operation of the temperature control element 71 built in the heat generating IC 7. Specifically, the temperature control circuit 11 outputs a temperature control code DOVC for controlling the heat generation amount of the temperature control element 71 based on the temperature code DTS1 and the stored temperature control data 91 transferred to the memory 15. For example, the temperature control data 91 may include information on the set temperature that is the target of the temperature of the vibration element 6 and information on the gain for controlling the heat generation amount of the temperature control element 71. Alternatively, when the set temperature that is the target of the temperature of the vibration element 6 varies depending on the outside air temperature, the temperature control data 91 may include information indicating the relationship between the temperature code DTS3 and the set temperature. In this case, the temperature control circuit 11 outputs the temperature control code DOVC based on the temperature codes DTS1, DTS3 and the temperature control data 91.

[0059] By executing the temperature compensation program transferred to the memory 15, the CPU 10 functions as a temperature compensation circuit 12. The temperature compensation circuit 12 compensates the frequency of the oscillation signal OSCO generated by the oscillation circuit 81 built in the oscillation IC 8 for oscillating the vibration element 6. Specifically, the temperature compensation circuit 12 outputs a division ratio control signal DIVC for causing the fractional N-PLL circuit 45 to output a clock signal CK1 having a constant frequency regardless of the temperature based on the temperature code DTS3 and the temperature compensation data 92 transferred to the memory 15. For example, the temperature compensation data 92 may be table information indicating the relationship between the temperature code DTS3 and the frequency of the oscillation signal OSCO, or may be information on the coefficient values of each order of the mathematical formula indicating the relationship. Alternatively, the temperature compensation data 92 may be information indicating the relationship between the temperature code DTS3 and the value of the fractional division ratio of the fractional N-PLL circuit 45 calculated from the relationship between the temperature code DTS3 and the frequency of the oscillation signal OSCO.

[0060] The CPU 10 functions as a failure detection circuit 13 by executing the failure detection program transferred to the memory 15. The failure detection circuit 13 monitors the frequency control voltage VC, and detects whether the frequency control voltage VC may deviate from a predetermined voltage range in which the oscillation circuit 124 can operate normally. Details of the processing of the failure detection circuit 13 will be described later.

[0061] The D / A conversion circuit 44 converts the temperature control code DOVC, which is a digital signal output from the temperature control circuit 11, into the temperature control signal OVC, which is an analog signal. The temperature control signal OVC is supplied to the temperature control element 71 of the heat generating IC 7.

[0062] The interface circuit 49 is a circuit for performing data communication with an external device 100 connected to the oscillator 1. Specifically, the interface circuit 49 writes and reads data to and from the memory 90, the register 94, or the memory 15 of the microcontroller 40 in response to a request from the external device 100. The interface circuit 49 may be, for example, an interface circuit corresponding to the I 2 C bus, or an interface circuit corresponding to the SPI bus. I 2 C is an abbreviation for Inter-Integrated Circuit. Also, SPI is an abbreviation for Serial Peripheral Interface.

[0063] In the inspection process during the manufacture of the oscillator 1, an inspection device, which is the external device 100, may set a switch control signal SWC for selecting the clock signal CK1 to the switch circuit 47 via the interface circuit 49 and inspect the clock signal CK1. Further, the inspection device, which is the external device 100, writes the temperature control data 91 and the temperature compensation data 92 to the memory 90 via the interface circuit 49, and further writes the temperature control program and the temperature compensation program. Note that the temperature control data 91 and the temperature compensation data 92 may be set by the external device 100 to the register 94 at the start-up of the oscillator 1.

[0064] 1-3. Processing of Fault Detection Circuit As shown in FIG. 8, in order to correct the decrease in the frequency f of the clock signal CK1 due to aging and the decrease in the oscillation frequency of the voltage-controlled oscillator 9 and maintain the frequency f of the clock signal CK2 constant, the frequency control voltage VC increases with the passage of time. Since there are an upper limit voltage VC CK1 and a lower limit voltage VC CK2 for the frequency control voltage VC, when the frequency control voltage VC increases with the passage of time and reaches the upper limit voltage VC MAX it becomes the operating limit of the oscillation circuit 124, and thereafter the frequency f of the clock signal CK2 decreases with the passage of time. MIN MAX CK2 On the other hand, since the voltage-controlled oscillator 9 has temperature characteristics, its oscillation frequency changes according to the temperature. Therefore, as shown in FIG. 9, in order for the PLL circuit 46 to maintain the frequency f of the clock signal CK2 constant even when the temperature changes within a predetermined temperature range, taking the frequency control voltage VC at the reference temperature T0 such as 25°C as V0, the frequency control voltage VC is changed according to the temperature so as to cancel the temperature characteristics of the voltage-controlled oscillator 9. In the example of FIG. 9, the frequency control voltage VC becomes the maximum voltage V1 at the temperature T1 and the minimum voltage V2 at the temperature T2, and varies between the maximum voltage V1 and the minimum voltage V2 according to the temperature. Note that the temperature characteristics of the voltage-controlled oscillator 9 are measured before the oscillator 1 is shipped, and the data of these temperature characteristics are stored in the memory 90. CK2 MAX

[0065] MAX CK2 MAX

[0066] Therefore, even before the frequency control voltage VC reaches the upper limit voltage VC MAX with the passage of time, at a predetermined temperature, if the frequency control voltage VC is not set to a voltage higher than the upper limit voltage VC MAX the frequency f of the clock signal CK2 cannot be maintained constant, and there is a possibility that the oscillation circuit 124 cannot operate normally. That is, when temperature changes are not considered, as shown in FIG. 8, when the frequency control voltage VC reaches the upper limit voltage VC CK2 MAX ​When it reaches this point, it becomes the operating limit of the oscillation circuit 124. However, in reality, when the frequency control voltage VC reaches the upper limit of a predetermined voltage range considering the temperature change within a predetermined temperature range, the operating limit of the oscillation circuit 124 will be reached. Therefore, the failure detection circuit 13 monitors the frequency control voltage VC and detects whether the frequency control voltage VC may deviate from a predetermined voltage range within which the oscillation circuit 124 can operate normally. Then, the failure detection circuit 13 generates a detection flag indicating whether the oscillation circuit 124 may deviate from a predetermined voltage range within which it can operate normally, and stores the detection flag in the register 94. The external device 100 may read the detection flag stored in the register 94 and notify the user if the oscillation circuit 124 may deviate from a predetermined voltage range within which it can operate normally.

[0067] Here, the frequency control voltage VC is the voltage component VC T changing according to temperature and the voltage component VC A due to aging. Therefore, as shown in FIG. 10, by subtracting the voltage component VC T changing according to temperature from the frequency control voltage VC, the voltage component VC A due to aging when the temperature is the reference temperature T0 can be obtained. From the change in this voltage component VC A due to aging, the timing of the operating limit of the oscillation circuit 124 can be predicted.

[0068] FIG. 11 is a diagram showing an example of the relationship between the change in the voltage component VC A due to aging and the timing of the operating limit of the oscillation circuit 124. In the example of FIG. 11, so far, with the passage of time, the voltage component VC A due to aging when the temperature is the reference temperature T0 has been linearly increasing. When the voltage component VC A increases in the same way in the future, the time when the voltage obtained by adding the voltage V1 - V0 to the voltage component VC A reaches VC MAX + V1 - V0 is predicted to be the timing of the operating limit of the oscillation circuit 124. VC MAX+V1 - V0 corresponds to the upper limit of a predetermined voltage range within which the oscillation circuit 124 operates normally when considering the variation of the frequency control voltage VC with temperature. The lower limit of the predetermined voltage range within which the oscillation circuit 124 operates normally is VC MIN +V0 - V2.

[0069] Therefore, the failure detection circuit 13, based on the frequency control code DVC which is the A / D conversion result of the frequency control voltage VC by the A / D conversion circuit 43 and the temperature code DTS3 which is the A / D conversion result of the voltage of the temperature detection signal TS3 which is the temperature detection voltage, calculates the voltage component VC T due to aging excluding the voltage component VC A corresponding frequency control voltage data DVCX. Specifically, the failure detection circuit 13 periodically acquires the frequency control code DVC and the temperature detection signal TS3, and based on the temperature detection signal TS3 and the data of the temperature characteristics of the voltage controlled oscillator 9 stored in the memory 90, calculates the digital code corresponding to the voltage component VC T included in the frequency control voltage VC. Further, the failure detection circuit 13 subtracts the digital code corresponding to the voltage component VC T from the frequency control code DVC to calculate the frequency control voltage data DVCX corresponding to the voltage component VC A due to aging. Then, the failure detection circuit 13 predicts the timing at which the frequency control voltage VC deviates from the predetermined voltage range based on the calculated frequency control voltage data DVCX. This predetermined voltage range has an upper limit of VC MAX +V1 - V0 and a lower limit of VC MIN +V0 - V2. The failure detection circuit 13 stores the predicted timing in the register 94. The external device 100 may read the timing stored in the register 94 and notify the user.

[0070] For example, when it is assumed that the frequency control voltage data DVCX changes linearly over time, the failure detection circuit 13 may approximate the frequency control voltage data DVCX by a linear equation with respect to time, and based on the linear equation, predict the timing at which the frequency control voltage VC deviates from a predetermined voltage range.

[0071] Also, for example, when it is assumed that the frequency control voltage data DVCX changes non-linearly over time, the failure detection circuit 13 may approximate the frequency control voltage data DVCX by a polynomial with respect to time, and based on the polynomial, predict the timing at which the frequency control voltage VC deviates from a predetermined voltage range.

[0072] Note that the control IC 4 is an example of a "circuit device". Also, the voltage-controlled oscillator 114 included in the fractional N-PLL circuit 45 is an example of a "first oscillator", and the clock signal CK1 is an example of a "first clock signal". Further, the oscillator 124 included in the PLL circuit 46 is an example of a "second oscillator", and the clock signal CK2 is an example of a "second clock signal".

[0073] 1-4. Operational Effects As described above, according to the oscillator 1 of the first embodiment, in the control IC 4, the failure detection circuit 13 monitors the frequency control voltage VC that changes over time, so that it is possible to predict in advance the failure of the PLL circuit 46 due to the aging of the voltage-controlled oscillator 124.

[0074] Also, according to the oscillator 1 of the first embodiment, in the control IC 4, the failure detection circuit 13 removes the voltage component VC T that changes due to aging from the frequency control voltage VC A and based on the frequency control voltage data DVCX corresponding to the voltage component VC

[0075] 2. Second Embodiment Hereinafter, regarding the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description similar to that in the first embodiment is omitted or simplified, and mainly the content different from that in the first embodiment will be described.

[0076] Since the structure of the oscillator 1 in the second embodiment is the same as that in FIGS. 1 to 4, the illustration and description thereof are omitted.

[0077] FIG. 12 is a functional block diagram of the oscillator 1 in the second embodiment. As shown in FIG. 12, in the oscillator 1 of the second embodiment, in the control IC 4, the CPU 10 functions as a failure detection circuit 13 and a filter circuit 14 by executing the failure detection program transferred to the memory 15.

[0078] Similar to the first embodiment, the failure detection circuit 13 calculates the frequency control voltage data DVCX corresponding to the voltage component VC due to aging excluding the voltage component VC that changes according to temperature from the frequency control voltage VC. T The filter circuit 14 performs a filter process on the frequency control voltage data DVCX. This filter process is a process for attenuating short-term fluctuations of the frequency control voltage data DVCX, and may be, for example, a low-pass filter process or a Kalman filter process. A The failure detection circuit 13 may approximate the data obtained by filtering the frequency control voltage data DVCX by the filter circuit 14 with a polynomial with respect to time, and predict the timing at which the frequency control voltage VC deviates from a predetermined voltage range based on the polynomial.

[0079] Since the other configurations of the oscillator 1 in the second embodiment are the same as those in the first embodiment, the description thereof is omitted.

[0080] According to the oscillator 1 of the second embodiment described above, the same effects as those of the oscillator 1 of the first embodiment are achieved.

[0081]

[0082] ​Furthermore, according to the oscillator 1 of the second embodiment, in the control IC 4, since the filter circuit 14 can attenuate unnecessary signal components such as short-term fluctuations by filtering the frequency control voltage data DVCX, the failure detection circuit 13 can accurately predict the timing at which the PLL circuit 46 fails.

[0083] 3. Modification The present invention is not limited to this embodiment, and various modifications can be made within the scope of the gist of the present invention.

[0084] In each of the above embodiments, the failure detection circuit 13 monitors the frequency control voltage VC and detects whether the frequency control voltage VC may deviate from a predetermined voltage range in which the oscillation circuit 124 can operate normally. On the other hand, the failure detection circuit 13 may monitor the output voltage of the low-pass filter 113 included in the fractional N-PLL circuit 45 as the frequency control voltage, and detect whether the frequency control voltage may deviate from a predetermined voltage range in which the voltage-controlled oscillator circuit 114 can operate normally. In this case, the oscillation circuit 81 included in the oscillation IC 8 is an example of the "first oscillation circuit", and the oscillation signal OSCO is an example of the "first clock signal". Also, the voltage-controlled oscillator circuit 114 included in the fractional N-PLL circuit 45 is an example of the "second oscillation circuit", and the clock signal CK1 is an example of the "second clock signal".

[0085] Also, in each of the above embodiments, the temperature control element 71 and the temperature sensor 72 are built in the heat-generating IC 7, but the temperature control element 71 and the temperature sensor 72 may be provided separately. Also, in the above embodiment, the temperature sensor 82 is built in the oscillation IC 8, but the temperature sensor 82 and the oscillation IC 8 may be provided separately. Also, in each of the above embodiments, the temperature sensor 42 is built in the control IC 4, but the temperature sensor 42 and the control IC 4 may be provided separately. In these cases, for example, the temperature sensors 72, 82, 42 may be thermistors or platinum resistors.

[0086] In addition, in each of the above embodiments, the control IC 4 includes one temperature sensor 42, but it may include a plurality of temperature sensors. In this case, for example, the A / D conversion circuit 43 converts a plurality of temperature detection signals output from the plurality of temperature sensors into a plurality of temperature codes, and the microcontroller 40 may perform temperature control and temperature compensation based on the plurality of temperature codes. For example, the microcontroller 40 may perform temperature control and temperature compensation using the average value of the plurality of temperature codes as the temperature code DTS3.

[0087] In addition, in each of the above embodiments, temperature compensation is performed by controlling the division ratio of the fractional N-PLL circuit 45 based on the division ratio control signal DIVC output by the microcontroller 40, but the method of temperature compensation is not limited to this. For example, the oscillation circuit 81 built in the oscillation IC 8 has a capacitor array, and temperature compensation may be performed by selecting the capacitance value of the capacitor array based on the temperature compensation code DCMP calculated by the microcontroller 40. Also, for example, the oscillation circuit 81 has a variable capacitor element for adjusting the frequency, and the D / A conversion circuit converts the temperature compensation code DCMP calculated by the microcontroller 40 into an analog signal, and temperature compensation may be performed by controlling the capacitance value of the variable capacitor element based on the analog signal.

[0088] In addition, in each of the above embodiments, one A / D conversion circuit 43 converts the voltages of the temperature detection signals TS1, TS2, TS3 and the frequency control voltage VC into the temperature codes DTS1, DTS2, DTS3 and the frequency control code DVC in a time-division manner, respectively. However, for example, the control IC 4 may include a plurality of A / D conversion circuits, and the plurality of A / D conversion circuits may convert the voltages of the temperature detection signals TS1, TS2, TS3 and the frequency control voltage VC into the temperature codes DTS1, DTS2, DTS3 and the frequency control code DVC, respectively.

[0089] Further, in each of the above embodiments, the temperature control element 71 is a heat generating element such as a CMOS transistor. However, the temperature control element 71 may be any element that can control the temperature of the vibration element 6. Depending on the relationship between the set temperature that is the target temperature of the temperature of the vibration element 6 and the outside air temperature, it may be a heat absorbing element such as a Peltier element.

[0090] The above-described embodiments and modified examples are merely examples and are not necessarily limited thereto. For example, it is also possible to appropriately combine each of the embodiments and each of the modified examples.

[0091] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations having the same functions, methods, and results, or configurations having the same objectives and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that exhibit the same operational effects as the configurations described in the embodiments or configurations that can achieve the same objectives. The present invention also includes configurations in which known techniques are added to the configurations described in the embodiments.

[0092] The following content is derived from the above-described embodiments and modified examples.

[0093] One aspect of the circuit device is a first oscillation circuit that generates a first clock signal, a second oscillation circuit that generates a second clock signal, and a frequency control voltage generation circuit that generates a frequency control voltage for controlling the frequency of the second clock signal, and a PLL circuit that phase-aligns the second clock signal with the first clock signal, and a failure detection circuit that monitors the frequency control voltage and detects whether the frequency control voltage may deviate from a predetermined voltage range in which the second oscillation circuit can operate normally.

[0094] According to this circuit device, by monitoring the frequency control voltage that changes over time, it is possible to predict in advance a failure of the PLL circuit due to aging of the voltage-controlled second oscillation circuit.

[0095] One aspect of the circuit device is equipped with an A / D conversion circuit that A / D-converts the frequency control voltage and the temperature detection voltage, The failure detection circuit calculates frequency control voltage data obtained by removing a voltage component that changes according to temperature from the frequency control voltage based on the A / D conversion result of the frequency control voltage and the A / D conversion result of the temperature detection voltage, and may predict the timing at which the frequency control voltage deviates from the predetermined voltage range based on the frequency control voltage data.

[0096] According to this circuit device, it is possible to accurately predict the timing at which the PLL circuit fails based on the frequency control voltage data corresponding to the voltage component that changes due to aging, excluding the voltage component that changes according to temperature, from the frequency control voltage.

[0097] In one aspect of the circuit device, the failure detection circuit may approximate the frequency control voltage data by a linear equation with respect to time and predict the timing based on the linear equation.

[0098] In one aspect of the circuit device, the failure detection circuit may approximate the frequency control voltage data by a polynomial with respect to time and predict the timing based on the polynomial.

[0099] One aspect of the circuit device is equipped with a filter circuit that filters the frequency control voltage data, the failure detection circuit may approximate the data obtained by filtering the frequency control voltage data by the filter circuit by a polynomial with respect to time and predict the timing based on the polynomial.

[0100] According to this circuit device, by filtering the frequency control voltage data, unnecessary signal components can be attenuated, so that the timing at which the PLL circuit fails can be accurately predicted.

[0101] In one aspect of the circuit device, the filter processing may be low-pass filter processing.

[0102] According to this circuit device, by performing low-pass filter processing on the frequency control voltage data, short-term fluctuations can be attenuated, so that the timing at which the PLL circuit fails can be accurately predicted.

[0103] In one aspect of the circuit device, the second oscillation circuit may be connected to the oscillator and oscillate the oscillator to generate the second clock signal.

[0104] One aspect of the oscillator according to the present invention includes one aspect of the circuit device.

Description of Reference Numerals

[0105] 1... Oscillator, 2... Outer package, 3... Inner package, 4... Control IC, 5... Oscillator, 6... Vibration element, 7... Heat-generating IC, 8... Oscillation IC, 9... Voltage-controlled oscillator, 10... CPU, 11... Temperature control circuit, 12... Temperature compensation circuit, 13... Fault detection circuit, 14... Filter circuit, 15... Memory, 21... Outer base, 21a... Upper surface, 21b... Lower surface, 22... Outer lid, 23... Sealing member, 25... Internal wiring, 27... Substrate, 28... Wall portion, 29... Leg portion, 31... Inner base, 31a... Upper surface, 31b... Lower surface, 32... Inner lid, 33... Sealing member, 40... Microcontroller, 41... Selector, 42... Temperature sensor, 43... A / D conversion circuit, 44... D / A conversion circuit, 45... Fractional N-PLL circuit, 46... PLL circuit, 47... Switch circuit, 48... Power supply circuit, 49... Interface circuit, 51... Package, 52... Base, 52a... Upper surface, 52b... Lower surface, 53... Lid, 54... Sealing member, 55... Vibration element, 71... Temperature control element, 72... Temperature sensor, 81... Oscillation circuit, 82... Temperature sensor, 90... Memory, 91... Temperature control data, 92... Temperature compensation data, 94... Register, 100... External device, 111... Phase comparator, 112... Charge pump, 113... Low-pass filter, 114... Voltage-controlled oscillation circuit, 115... Divider circuit, 120... Frequency control voltage generation circuit, 121... Phase comparator, 122... Charge pump, 123... Low-pass filter, 124... Oscillation circuit, 211... Upper recess, 211a... First upper recess, 211b... Second upper recess, 211c... Third upper recess, 212... Lower recess, 241... Internal terminal, 242... Internal terminal, 243... Internal terminal, 244... External terminal, 245... Side terminal, 311... Recess, 311a... First recess, 311b... Second recess, 311c... Third recess, 341... Internal terminal, 342... Internal terminal, 343... Internal terminal, 344... External terminal, 521... Recess, 561... Internal terminal, 564... External terminal, B1... Bonding member, B2... Bonding member, B3... Bonding member, B4... Bonding member, BW1... Bonding wire, BW2... Bonding wire, BW3... Bonding wire, BW4... Bonding wire, BW5... Bonding wire, H... Solder, S2... Outer accommodation space, S3... Inner accommodation space, S5... Accommodation space

Claims

1. A first oscillation circuit that generates a first clock signal, a second oscillation circuit that generates a second clock signal, and a frequency control voltage generation circuit that generates a frequency control voltage for controlling the frequency of the second clock signal, and a PLL circuit that phase-locks the second clock signal to the first clock signal, a failure detection circuit that monitors the frequency control voltage and detects whether the frequency control voltage may deviate from a predetermined voltage range in which the second oscillation circuit can operate normally. A circuit device comprising:

2. In claim 1, an A / D conversion circuit that A / D-converts the frequency control voltage and the temperature detection voltage, the failure detection circuit calculates frequency control voltage data excluding a voltage component that changes according to temperature from the frequency control voltage based on the A / D conversion result of the frequency control voltage and the A / D conversion result of the temperature detection voltage, and based on the frequency control voltage data, predicts the timing at which the frequency control voltage deviates from the predetermined voltage range. A circuit device.

3. In claim 2, the failure detection circuit approximates the frequency control voltage data by a linear equation with respect to time and predicts the timing based on the linear equation. A circuit device.

4. In claim 2, the failure detection circuit approximates the frequency control voltage data by a polynomial with respect to time and predicts the timing based on the polynomial. A circuit device.

5. In claim 2, a filter circuit that performs filter processing on the frequency control voltage data, the failure detection circuit approximates the data obtained by subjecting the frequency control voltage data to filter processing by the filter circuit by a polynomial with respect to time and predicts the timing based on the polynomial. A circuit device.

6. In claim 5, the filter processing is low-pass filter processing. A circuit device.

7. In any one of claims 1 to 6, the second oscillation circuit is connected to an oscillator and oscillates the oscillator to generate the second clock signal. A circuit device.

8. An oscillator comprising the circuit device according to claim 1.

Images