Amplifier and motor device

Abstract

To provide an amplifier capable of reducing output noise.SOLUTION: An amplifier (1) includes a switched capacitor amplifier (2) configured to alternately repeat a reference acquisition phase and a signal propagation phase, a sample-hold circuit (3) configured to sample and hold the output of the switched capacitor amplifier, and a controller (4) configured to control the sample-hold circuit. The controller is configured to cause the sample-hold circuit to skip the sampling if the timing of the sampling and the edge timing of a pulse signal overlap.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to an amplifier and a motor device.

Background Art

[0002] Conventionally, as a method for detecting the current flowing through a motor, a method is known in which the current flowing through the motor is detected by a shunt resistor, and the potential difference across the shunt resistor is amplified by an amplifier (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] However, large noise is generated at the edge timing of the PWM (Pulse Width Modulation) signal used in the motor driver that drives the motor, and this noise affects the output of the amplifier. As a result, the output noise of the amplifier increases, and the detection accuracy of the current decreases.

[0005] The amplifier according to the present disclosure includes a switched-capacitor amplifier configured to alternately repeat a reference acquisition phase and a signal propagation phase, a sample-and-hold circuit configured to sample and hold the output of the switched-capacitor amplifier, and a controller configured to control the sample-and-hold circuit, and the controller is configured to skip the sampling in the sample-and-hold circuit when the timing of the sampling overlaps with the edge timing of the pulse signal.

[0006] The motor device according to the present disclosure includes a motor, a motor driver configured to drive the motor, a shunt resistor configured to detect a current flowing through the motor, and the amplifier configured to amplify a potential difference between both ends of the shunt resistor.

Brief Description of Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

[0008] [Detailed Description] <Schematic Configuration of Amplifier According to Embodiment> FIG. 1 is a block diagram showing a configuration of an amplifier 1 (hereinafter abbreviated as "amplifier 1") according to an embodiment. The amplifier 1 includes a positive input terminal INP, a negative input terminal INM, a switched-capacitor amplifier 2, a sample-and-hold circuit 3, a controller 4, an output amplifier 5, a positive output terminal OUTP, and a negative output terminal OUTM.

[0009] The positive input terminal INP is connected to a positive input end of the switched-capacitor amplifier 2. The positive input terminal INP is a terminal configured to receive a positive input voltage VINP.

[0010] The negative input terminal INM is connected to the negative input terminal of the switched capacitor amplifier 2. The negative input terminal INM is a terminal configured to receive the negative input voltage VINM.

[0011] The sample and hold circuit 3 samples and holds the output of the switched capacitor amplifier 2.

[0012] The controller 4 controls the sample and hold circuit 3. More specifically, the controller 4 controls the switch in the sample and hold circuit 3. The controller 4 further controls the switched capacitor amplifier 2. More specifically, the controller 4 controls the switch in the switched capacitor amplifier 2. As the controller 4, for example, an embedded computing module, a DSP (digital signal processor), a microcontroller, a microprocessor, an FPGA (field-programmable gate array), an ASIC (application specific integrated circuit), etc. can be used. Details of the control content of the controller 4 will be described later.

[0013] The output amplifier 5 amplifies the output of the sample and hold circuit 3 and supplies it to the positive output terminal OUTP and the negative output terminal OUTM. Note that if a desired gain can be obtained by the switched capacitor amplifier 2, the amplifier 1 may be configured without the output amplifier 5. The positive output terminal OUTP is a terminal configured to output the positive output voltage VOUT to the outside of the amplifier 1. The negative output terminal OUTM is a terminal configured to output the negative output voltage REF to the outside of the amplifier 1.

[0014] <Configuration Example of Switched Capacitor Amplifier, Sample and Hold Circuit, and Output Amplifier> FIG. 2 is a diagram showing a configuration example of the switched capacitor amplifier 2, the sample and hold circuit 3, and the output amplifier 5.

[0015] The switch capacitor amplifier 2 in the configuration example shown in FIG. 2 includes diodes D1 and D2, resistors R1 and R2, a clamp circuit CL1, switches SW1b, SW2a, SW3a, SW4b, SW5a, SW6a, SW7b, SW8b, SW9a, and SW10a, capacitors C0p, C0n, C1p, and C1n, a fully differential amplifier FDA1, and a terminal T1.

[0016] The anode of diode D1 is connected to the first end of resistor R1. The cathode of diode D1 is connected to the ground potential. The connection node between the anode of diode D1 and the first end of resistor R1 becomes the positive input terminal of switch capacitor amplifier 2.

[0017] The anode of diode D2 is connected to the first end of resistor R2. The cathode of diode D2 is connected to the ground potential. The connection node between the anode of diode D2 and the first end of resistor R2 becomes the negative input terminal of switch capacitor amplifier 2.

[0018] The second end of resistor R1 is connected to the first end of clamp circuit CL1 and the first ends of switches SW1b and SW2a. The second end of resistor R2 is connected to the second end of clamp circuit CL1 and the first ends of switches SW3a and SW4b. Clamp circuit CL1 is a circuit that clamps the voltage between the second end of resistor R1 and the second end of resistor R2.

[0019] The second ends of switches SW1b and SW3a are connected to the first end of capacitor C0p. The second ends of switches SW2a and SW4b are connected to the first end of capacitor C0n.

[0020] The second terminal of capacitor C0p is connected to the positive input terminal of the fully differential amplifier FDA1, the first terminal of switch SW5a, and the first terminal of capacitor C1p. The second terminal of capacitor C1p is connected to the first terminals of switches SW7b and SW9a. The second terminals of switches SW5a and SW7b are connected to the positive output terminal of the fully differential amplifier FDA1. The connection node between the second terminals of switches SW5a and SW7b and the positive output terminal of the fully differential amplifier FDA1 becomes the positive output terminal of the switch-capacitor amplifier 2.

[0021] The second terminal of capacitor C0n is connected to the negative input terminal of the fully differential amplifier FDA1, the first terminal of switch SW6a, and the first terminal of capacitor C1n. The second terminal of capacitor C1n is connected to the first terminals of switches SW8b and SW10a. The second terminals of switches SW6a and SW8b are connected to the negative output terminal of the fully differential amplifier FDA1. The connection node between the second terminals of switches SW6a and SW8b and the negative output terminal of the fully differential amplifier FDA1 becomes the negative output terminal of the switch-capacitor amplifier 2.

[0022] The first terminals of switches SW9a and SW10a are connected to terminal T1. Terminal T1 is a terminal configured to receive the reference voltage VREF. In the configuration example shown in FIG. 2, in order to make the gain of the switch-capacitor amplifier 2 adjustable, capacitors C1p and C1n are variable capacitors (capacitors with adjustable capacitance values), but capacitors C1p and C1n may also be fixed capacitors (capacitors with fixed capacitance values).

[0023] The switch-capacitor amplifier 2 alternately repeats the reference acquisition phase and the signal propagation phase under the control of the controller 4.

[0024] In the switch-capacitor amplifier 2 during the reference acquisition phase, switches SW2a, SW3a, SW5a, SW6a, SW9a, and SW10a are in the on state (conducting state), and switches SW1b, SW4b, SW7b, and SW8b are in the off state (blocking state).

[0025] In the switch capacitor amplifier 2 during the signal propagation phase, switches SW2a, SW3a, SW5a, SW6a, SW9a, and SW10a are in the off state (open state), and switches SW1b, SW4b, SW7b, and SW8b are in the on state (conducting state). The switch capacitor amplifier 2 during the signal propagation phase outputs a voltage proportional to the common-mode input signal (VINP - VINM).

[0026] The common-mode input signal (VINP - VINM) is applied between the positive input terminal INP and the negative input terminal INM under various conditions. Therefore, the circuit before the switch capacitor amplifier 2, that is, the circuit including diodes D1 and D2, resistors R1 and R2, clamp circuit CL1, switches SW1b, SW2a, SW3a, and SW4b, and capacitors C0p and C0n, operates with the common-mode input signal (VINP - VINM), so it is composed of a high breakdown voltage (for example, 40V breakdown voltage) circuit.

[0027] On the other hand, the circuit after the switch capacitor amplifier 2, that is, the circuit including the fully differential amplifier FDA1, switches SW5a, SW6a, SW7b, SW8b, SW9a, and SW10a, and capacitors C1p and C1n, and terminal T1, operates with the power supply voltage, so it is composed of a low breakdown voltage (for example, 6V breakdown voltage) circuit.

[0028] The sample and hold circuit 3 in the configuration example shown in FIG. 2 includes switches SW11 and SW12 and capacitor C2.

[0029] The first terminal of switch SW11 becomes the positive input terminal of the sample and hold circuit 3. The first terminal of switch SW12 becomes the negative input terminal of the sample and hold circuit 3.

[0030] The second terminal of switch SW11 is connected to the first terminal of capacitor C2. The connection node between the second terminal of switch SW11 and the first terminal of capacitor C2 becomes the positive output terminal of the sample-and-hold circuit 3. The second terminal of switch SW12 is connected to the second terminal of capacitor C2. The connection node between the second terminal of switch SW12 and the second terminal of capacitor C2 becomes the negative output terminal of the sample-and-hold circuit 3.

[0031] The output amplifier 5 in the configuration example shown in Fig. 2 includes differential amplifiers A1 to A3 and resistors R3 to R6.

[0032] The non-inverting input terminal of differential amplifier A1 becomes the positive input terminal of output amplifier 5. The non-inverting input terminal of differential amplifier A2 becomes the negative input terminal of output amplifier 5. The inverting input terminal and the output terminal of differential amplifier A1 are connected to the first terminal of resistor R3. The inverting input terminal and the output terminal of differential amplifier A2 are connected to the first terminal of resistor R4.

[0033] The second terminal of resistor R3 is connected to the non-inverting input terminal of differential amplifier A3 and the first terminal of resistor R5. The second terminal of resistor R4 is connected to the inverting input terminal of differential amplifier A3 and the first terminal of resistor R6.

[0034] The second terminal of resistor R5 is connected to the output terminal of differential amplifier A3. The connection node between the second terminal of resistor R5 and the output terminal of differential amplifier A3 becomes the positive output terminal of output amplifier 5. The second terminal of resistor R6 becomes the negative output terminal of output amplifier 5. In the configuration example shown in Fig. 2, in order to make the gain of output amplifier 5 adjustable, resistors R5 and R6 are variable resistors (resistors with adjustable resistance values), but resistors R5 and R6 may also be fixed resistors (resistors with fixed resistance values).

[0035] <Control content of the controller> FIG. 3 is a timing chart showing the state of the amplifier 1. The controller 4 acquires the edge timing TM1 of the PWM signal, and when the sampling timing of the sample hold circuit 3 (the on-periods of the switches SW11 and SW12) overlaps with the edge timing TM1 of the PWM signal, the controller 4 causes the sample hold circuit 3 to skip sampling so that the switches SW11 and SW12 do not turn on. Thereby, large noise generated at the edge timing TM1 of the PWM signal does not affect the output of the amplifier 1. Thereby, the output noise of the amplifier 1 can be reduced. In FIG. 3, the edge timing TM1 of the PWM signal is a falling edge timing, but the edge timing TM1 of the PWM signal includes both a rising edge timing and a falling edge timing.

[0036] The controller 4 may acquire the edge timing TM1 of the PWM signal by acquiring the PWM signal itself generated outside the amplifier 1, or may acquire the edge timing TM1 of the PWM signal by acquiring a signal indicating the edge timing TM1 of the PWM signal generated outside the amplifier 1.

[0037] The PWM signal is a signal synchronized with the positive input voltage VINP and the negative input voltage VINM. Therefore, at the edge timing of the PWM signal, edges also appear in the positive input voltage VINP and the negative input voltage VINM, and the differential input signal (VINP - VINM) will contain large noise. In this embodiment, the controller 4 is configured to acquire the edge timing TM1 of the PWM signal. However, it may also be configured to acquire the edge timing 1 of a pulse signal synchronized with the positive input voltage VINP and the negative input voltage VINM other than the PWM signal. Also, different from this embodiment, components of the amplifier 1 (for example, the controller 4) may generate a pulse signal synchronized with the positive input voltage VINP and the negative input voltage VINM. In this variant, the pulse signal generated by the components of the amplifier 1 may or may not be a PWM signal. Also, in this variant, the pulse signal generated by the components of the amplifier 1 is output outside the amplifier 1 and used outside the amplifier 1. Also, in this variant, when the sampling timing of the sample and hold circuit 3 (the on-periods of the switches SW11 and SW12) overlaps with the edge timing TM1 of the pulse signal generated by the components of the amplifier 1, the controller 4 causes the switches SW11 and SW12 not to turn on to skip the sampling of the sample and hold circuit 3.

[0038] Figure 4 is a flowchart showing a first operation example of the sample and hold control of the controller 4.

[0039] When the amplifier 1 is activated, the controller 4 that executes the first operation example shown in Figure 4 starts the flow operation shown in Figure 4.

[0040] The controller 4 determines whether the sampling timing of the sample and hold circuit 3 (immediately before transitioning to the reference acquisition phase) has arrived (step S10). If the sampling timing of the sample and hold circuit 3 has not arrived, the process of step S10 is repeated.

[0041] If the sampling timing of the sample hold circuit 3 has arrived, the controller 4 determines whether the edge timing TM1 of the PWM signal coincides with the sampling timing of the sample hold circuit 3 (step S20).

[0042] If the edge timing TM1 of the PWM signal coincides with the sampling timing of the sample hold circuit 3, the controller 4 skips the sampling in the sample hold circuit 3 (step S30), and then returns to the process of step S10. On the other hand, if the edge timing TM1 of the PWM signal does not coincide with the sampling timing of the sample hold circuit 3, the controller 4 causes the sample hold circuit 3 to perform sampling (step S40), and then returns to the process of step S10.

[0043] FIG. 5 is a flowchart showing a second operation example of the sample hold control of the controller 4.

[0044] In the flowchart of FIG. 5, step S21 is added to the flowchart of FIG. 4. Step S21 is a step of determining whether the frequency of the PWM signal is equal to or higher than a threshold value. If the frequency of the PWM signal is not equal to or higher than the threshold value, the process proceeds to step S30. If the frequency of the PWM signal is equal to or higher than the threshold value, the process returns to step S10. Thereby, it is possible to avoid a situation where the sample hold circuit 3 of the amplifier 1 does not perform any sampling.

[0045] FIG. 6 is a flowchart showing a third operation example of the sample hold control of the controller 4.

[0046] In the flowchart of FIG. 6, step S22 is added to the flowchart of FIG. 4. Step S22 is a step for determining whether or not the control to skip sampling has continued for a predetermined number of times. If the control to skip sampling has not continued for the predetermined number of times, the process proceeds to step S30. If the control to skip sampling has continued for the predetermined number of times, the process returns to step S10. Thereby, it is possible to avoid a situation where the sample hold circuit 3 of the amplifier 1 does not perform any sampling at all.

[0047] In the flowcharts of FIGS. 5 and 6, it is determined each time whether or not to avoid step S30. However, once step S30 is avoided, it may be avoided always thereafter, or it may be avoided a predetermined number of times once step S30 is avoided.

[0048] <Application Example> The amplifier 1 is incorporated in, for example, a motor device. However, the application destination of the amplifier 1 is not limited to the motor device. FIG. 7 is a diagram showing a configuration example of the motor device.

[0049] The motor device 10 shown in FIG. 7 includes a motor 11, a motor driver 12 configured to drive the motor 11, a shunt resistor SR1, and an amplifier 1 that amplifies the potential difference across both ends of the shunt resistor SR1.

[0050] The motor driver 12 includes an inverter and an inverter control circuit that controls the inverter. The amplifier 1 detects the current drawn by the inverter from the motor 11 based on the potential difference across both ends of one shunt resistor SR1. The inverter control circuit controls the inverter using the detection result of the amplifier 1. The signal supplied from the inverter control circuit to each switching element of the inverter becomes a PWM signal.

[0051] Note that, different from the configuration shown in FIG. 7, shunt resistors may be provided for each phase of the motor 11. In this case, the amplifier 1 is also provided for each phase of the motor 11, and the controller 4 may acquire the edge timing of the PWM signal of the corresponding phase.

[0052] <Others> The above embodiments should be considered as illustrative in all respects and not restrictive. The technical scope of the present disclosure is shown not by the description of the above embodiments but by the claims, and it should be understood that all modifications belonging to the meaning and scope equivalent to the claims are included.

[0053] <Supplementary Note> A supplementary note is provided for the present disclosure in which specific configuration examples are shown in the above embodiments.

[0054] The amplifier (1) of the present disclosure includes a switched-capacitor amplifier (2) configured to alternately repeat a reference acquisition phase and a signal propagation phase, a sample-and-hold circuit (3) configured to sample and hold the output of the switched-capacitor amplifier, and a controller (4) configured to control the sample-and-hold circuit. The controller is configured such that when the timing of the sampling and the edge timing of the pulse signal overlap, the sampling is skipped in the sample-and-hold circuit (a first configuration).

[0055] According to the amplifier of the first configuration, when the sampling timing in the sample-and-hold circuit and the edge timing of the pulse signal overlap, the sample-and-hold circuit skips the sampling, so that large noise generated at the edge timing of the pulse signal does not affect the output of the amplifier. Thereby, the output noise of the amplifier can be reduced.

[0056] In the amplifier of the first configuration, a configuration (a second configuration) may be provided that includes an output amplifier (5) configured to amplify the output of the sample-and-hold circuit.

[0057] In the amplifier of the above-described first or second configuration, the controller may be configured to disable the control for skipping the sampling in the sample-and-hold circuit when the frequency of the pulse signal is equal to or higher than a threshold value (third configuration).

[0058] In the amplifier of the above-described first or second configuration, the controller may be configured to disable the control for skipping the sampling in the sample-and-hold circuit when the control for skipping the sampling in the sample-and-hold circuit continues for a predetermined number of times (fourth configuration).

[0059] In the amplifier of the above-described fourth configuration, the pulse signal may be a PWM signal (fifth configuration).

[0060] The motor device (10) of the present disclosure includes a motor (11), a motor driver (12) configured to drive the motor, a shunt resistor (SR1), and an amplifier (A1) of any one of the above-described first to seventh configurations configured to amplify the potential difference across both ends of the shunt resistor (sixth configuration).

Description of Reference Numerals

[0061] 1 Amplifier according to the embodiment 2 Switch capacitor amplifier 3 Sample-and-hold circuit 4 Controller 5 Output amplifier 10 Motor device 11 Motor 12 Motor driver A1 to A3 Differential amplifier FDA1 Fully differential amplifier C0n, C0p, C1n, C1p, C2 Capacitor CL1 Clamp circuit D1, D2 Diode R1 to R6 Resistor SR1 Shunt resistor SW1b, SW2a, SW3a, SW4b, SW5a, SW6a, SW7b, SW8b, SW9a, SW10a, SW11, SW12 switches INP positive input terminal INM negative input terminal OUTP positive output terminal OUTM negative output terminal T1 terminal

Claims

1. A switched capacitor amplifier configured to alternately repeat a reference acquisition phase and a signal propagation phase; A sample and hold circuit configured to sample and hold the output of the switched capacitor amplifier; A controller configured to control the sample and hold circuit; Comprising: The controller is configured to cause the sample and hold circuit to skip the sampling when the timing of the sampling overlaps with the edge timing of the pulse signal. An amplifier.

2. The amplifier according to claim 1, further comprising an output amplifier configured to amplify the output of the sample and hold circuit.

3. The controller of the amplifier according to claim 1 is configured to disable the control for causing the sample and hold circuit to skip the sampling when the frequency of the pulse signal is equal to or higher than a threshold value.

4. The controller of the amplifier according to claim 1 is configured to disable the control for causing the sample and hold circuit to skip the sampling when the control for causing the sample and hold circuit to skip the sampling continues for a predetermined number of times.

5. The amplifier according to claim 1, wherein the pulse signal is a PWM signal.

6. A motor; A motor driver configured to drive the motor; A shunt resistor; The amplifier according to any one of claims 1 to 5, configured to amplify the potential difference across both ends of the shunt resistor; A motor device comprising:

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