Semiconductor device and method for manufacturing the same

Abstract

To reduce the size of a semiconductor device with a ferroelectric memory cell.SOLUTION: A semiconductor device has a ferroelectric memory cell, and the ferroelectric memory cell has a selection transistor and a memory transistor. A gate insulating film of the selection transistor has a ferroelectric film, and a gate insulating film of the memory transistor has a ferroelectric film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. The present invention relates to a technique effective when applied to, for example, a semiconductor device having a ferroelectric memory and a method for manufacturing the same.

Background Art

[0002] In recent years, ferroelectric memory cells having a ferroelectric film have been developed. In a ferroelectric memory cell, the state of the ferroelectric memory cell changes between a write state and an erase state by controlling the direction of polarization of the ferroelectric film. A ferroelectric memory cell can be driven at a lower voltage than a non-volatile memory cell having a charge storage film such as a silicon nitride film, for example.

[0003] Patent Document 1 discloses a ferroelectric memory cell formed on a semiconductor substrate. This ferroelectric memory cell has a ferroelectric film. The ferroelectric film has a plurality of grains that function as crystal nuclei.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Ferroelectric memory cells having a selection transistor and a memory transistor are known. The selection transistor selects a memory cell to be operated on, and the memory transistor stores information. The selection transistor is formed adjacent to the memory transistor. In a method for manufacturing a ferroelectric memory cell, first, an insulating film is formed on a semiconductor substrate. Next, a ferroelectric film is formed on the semiconductor substrate. The ferroelectric film is disposed adjacent to the insulating film. Next, a control gate electrode is formed on the insulating film, and a memory gate electrode is formed on the ferroelectric film. Thereafter, using the control gate electrode and the memory gate electrode as masks, the insulating film and the ferroelectric film are processed to form a first gate insulating film including the insulating film and a second gate insulating film including the ferroelectric film. Thereafter, through other manufacturing processes, a selection transistor having the first gate insulating film and the control gate electrode is formed, and a memory transistor having the second gate insulating film and the memory gate electrode is formed.

[0006] As described above, before forming the control gate electrode and the memory gate electrode, the insulating film and the ferroelectric film are processed. The insulating film and the ferroelectric film are processed using different masks for each. Therefore, there is a risk that misalignment of the masks may cause defective formation of the insulating film, the ferroelectric film, the control gate electrode, and the memory gate electrode. In order to prevent these defective formations, it is conceivable to secure a processing margin for the insulating film, the ferroelectric film, the control gate electrode, and the memory gate electrode. That is, it is conceivable to increase the intervals between the insulating film, the ferroelectric film, the control gate electrode, and the memory gate electrode. However, in this case, the size of the ferroelectric memory cell becomes large, and the size of the semiconductor chip becomes large.

[0007] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0008] In one embodiment of the present application, the semiconductor device has ferroelectric memory cells. The ferroelectric memory cell has a control gate electrode, a memory gate electrode, a first gate insulating film, a second gate insulating film, a source region, and a drain region. The first gate insulating film includes a ferroelectric film, and the second gate insulating film includes a ferroelectric film.

[0009] In another embodiment of the present application, a method for manufacturing a semiconductor device includes a step of forming a ferroelectric film on a semiconductor substrate, a step of forming a control gate electrode and a memory gate electrode on the ferroelectric film, and a step of processing the ferroelectric film to form a first gate insulating film and a second gate insulating film.

Advantages of the Invention

[0010] The technology of the present application can miniaturize the semiconductor device.

Brief Description of the Drawings

[0011]

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DETAILED DESCRIPTION OF THE INVENTION

[0012] In the following embodiments, for convenience, when necessary, the description will be divided into multiple sections or embodiments. However, unless otherwise explicitly stated, they are not unrelated to each other. One is a modification, detail, supplementary explanation, etc. of a part or all of the other. Also, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise explicitly stated or limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise explicitly stated or considered to be essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, unless otherwise explicitly stated or considered not to be so in principle, it includes those that are substantially approximated or similar to the shape, etc. This also applies to the above numerical values and ranges.

[0013] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary. In addition, in the drawings used in the embodiments, hatching may be omitted for easy viewing of the drawings.

[0014] (Embodiment 1) <Structure of the semiconductor device> As shown in FIG. 1, the semiconductor device includes a semiconductor substrate SS, a well region WR, an element isolation structure EIS, a source region SR1, a drain region DR1, an impurity region IR, a gate insulating film GDF1, a gate insulating film GDF2, a metal film MF1, a metal film MF2, a gate electrode GE1, a gate electrode GE2, sidewall insulating films SDF1 and SDF2, an interlayer insulating film IDF, and a plurality of contact plugs. The semiconductor device has ferroelectric memory cells, and each ferroelectric memory cell has a select transistor and a memory transistor. The ferroelectric memory cell is formed on the semiconductor substrate SS and has at least a source region SR1, a drain region DR1, a gate insulating film GDF1, a gate insulating film GDF2, a metal film MF1, a metal film MF2, a gate electrode GE1, and a gate electrode GE2. The select transistor has at least a source region SR1, a drain region DR1, a gate insulating film GDF1, a metal film MF1, and a gate electrode GE1. The memory transistor has at least a source region SR1, a drain region DR1, a gate insulating film GDF2, a metal film MF2, and a gate electrode GE2. Other semiconductor elements other than the ferroelectric memory cells may be formed on the semiconductor substrate SS.

[0015] The semiconductor substrate SS is made of, for example, p-type single crystal silicon (Si) having a specific resistance of about 1 to 10 Ωcm. The semiconductor substrate SS has an upper surface and a lower surface. The semiconductor substrate SS has a well region WR and an element isolation structure EIS. The well region WR is formed within the semiconductor substrate SS. The conductivity type of the well region WR is, for example, p-type. The well region WR has a predetermined impurity concentration. The element isolation structure EIS is formed within the semiconductor substrate SS. The element isolation structure EIS is disposed on the upper surface of the semiconductor substrate SS. Specifically, the element isolation structure EIS is formed within the well region WR so as to surround the upper part of the well region WR. The element isolation structure EIS includes a groove and an insulating film embedded in the groove. The element isolation structure EIS has a function of electrically separating adjacent semiconductor elements from each other. The upper part of the well region WR is surrounded by the element isolation structure EIS in plan view.

[0016] The source region SR1 is formed within the semiconductor substrate SS and within the well region WR, and is disposed on the upper surface of the semiconductor substrate SS. The depth of the source region SR1 is smaller than the depth of the well region WR. The impurity concentration of the source region SR1 is greater than the impurity concentration of the well region WR. The conductivity type of the source region SR1 is, for example, n-type. The source region SR1 may have an LDD structure. The source region SR1 contains, for example, arsenic or phosphorus. The drain region DR1 is formed within the semiconductor substrate SS and within the well region WR, and is disposed on the upper surface of the semiconductor substrate SS. The depth of the drain region DR1 is smaller than the depth of the well region WR. The impurity concentration of the drain region DR1 is greater than the impurity concentration of the well region WR. The drain region DR1 may have an LDD structure. The drain region DR1 is separated from the source region SR1. The drain region DR1 and the source region SR1 are surrounded by the element isolation structure EIS in a plan view. A silicide layer may be formed on the drain region DR1 and on the source region SR1.

[0017] The impurity region IR is formed within the semiconductor substrate SS and within the well region WR, and is disposed on the upper surface of the semiconductor substrate SS. The depth of the impurity region IR is smaller than the depth of the well region WR. The conductivity type of the impurity region IR is, for example, n-type. The impurity concentration of the impurity region IR is greater than the impurity concentration of the well region WR. The impurity region IR is disposed between the drain region DR1 and the source region SR1 in a plan view. The impurity region IR is arranged so as not to be connected to the wiring and the plug, and is in an electrically floating state. The impurity region IR is formed to connect the channel of the select transistor and the channel of the memory transistor.

[0018] The gate insulating film GDF1 is formed on the semiconductor substrate SS, the metal film MF1 is formed on the gate insulating film GDF1, and the gate electrode GE1 is formed on the metal film MF1. Specifically, the gate insulating film GDF1 is formed on a part of the semiconductor substrate SS located between the drain region DR1 and the impurity region IR in a plan view. The gate insulating film GDF1 has an insulating film DF1 and a ferroelectric film FF1. The insulating film DF1 is formed on the semiconductor substrate SS, and the ferroelectric film FF1 is formed on the insulating film DF1 such that the insulating film DF1 is disposed between the semiconductor substrate SS and the ferroelectric film FF1. The insulating film DF1 is formed of a normal dielectric film, for example, a silicon oxide film. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the insulating film DF1 is, for example, 1 nm or more and 3 nm or less. The ferroelectric film FF1 disposed between the insulating film DF1 and the gate electrode GE1 is formed of, for example, a metal oxide film and is formed of a high dielectric constant film having a higher dielectric constant than a silicon nitride film. The ferroelectric film FF1 contains, for example, hafnium, oxygen, and zirconium. The ferroelectric film FF1 may contain at least one of silicon, germanium, yttrium, lanthanum, and ytterbium instead of zirconium. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the ferroelectric film FF1 is, for example, 6 nm or more and 20 nm or less.

[0019] The metal film MF1 formed on the gate insulating film GDF1 is disposed between the ferroelectric film FF1 and the gate electrode GE1. The metal film MF1 is formed of, for example, a titanium nitride film, a tantalum nitride film, or a tungsten film. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the metal film MF1 is, for example, 2 nm or more and 20 nm or less. The metal film MF1 is used to efficiently crystallize the ferroelectric film FF1. Therefore, if the ferroelectric film FF1 can be efficiently crystallized without forming the metal film MF1, the metal film MF1 may not be formed. The metal film MF1 and the gate electrode GE1 function as a control gate electrode of a select transistor.

[0020] The gate electrode GE1 is formed on the gate insulating film GDF1. Specifically, when the metal film MF1 is formed on the gate insulating film GDF1, the gate electrode GE1 is formed on the metal film MF1. The gate electrode GE1 is formed, for example, from a polycrystalline silicon film into which n-type impurities have been introduced. The gate electrode GE1 may be formed from a titanium nitride film, an aluminum film, or a tungsten film. Further, the gate electrode GE1 may be formed from a laminated film including two or more conductive films.

[0021] The sidewall insulating film SDF1 is formed on the semiconductor substrate SS and on the side surfaces of the gate electrode GE1. The sidewall insulating film SDF1 is formed, for example, from a laminated film including a silicon oxide film and a silicon nitride film.

[0022] The gate insulating film GDF2 is formed on the semiconductor substrate SS, the metal film MF2 is formed on the gate insulating film GDF2, and the gate electrode GE2 is formed on the metal film MF2. Specifically, the gate insulating film GDF2 is formed on a part of the semiconductor substrate SS located between the source region SR1 and the impurity region IR in a plan view. The gate insulating film GDF2 has an insulating film DF2 and a ferroelectric film FF2. The insulating film DF2 is formed on the semiconductor substrate SS, and the ferroelectric film FF2 is formed on the insulating film DF2 such that the insulating film DF2 is disposed between the semiconductor substrate SS and the ferroelectric film FF2. The insulating film DF2 is formed of a paraelectric film, for example, a silicon oxide film. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the insulating film DF2 is, for example, 1 nm or more and 3 nm or less. The ferroelectric film FF2 disposed between the insulating film DF2 and the gate electrode GE2 is formed of, for example, a metal oxide film and is formed of a high-k film having a higher dielectric constant than a silicon nitride film. The ferroelectric film FF2 contains, for example, hafnium, oxygen, and zirconium. The ferroelectric film FF2 may contain at least one of silicon, germanium, yttrium, lanthanum, and ytterbium instead of zirconium. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the ferroelectric film FF2 is, for example, 6 nm or more and 20 nm or less. The thickness of the ferroelectric film FF2 is the same as the thickness of the ferroelectric film FF1.

[0023] The metal film MF2 formed on the gate insulating film GDF2 is disposed between the ferroelectric film FF2 and the gate electrode GE2. The metal film MF2 is formed of, for example, a titanium nitride film, a tantalum nitride film, or a tungsten film. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the metal film MF2 is, for example, 2 nm or more and 20 nm or less. The metal film MF2 is used to efficiently crystallize the ferroelectric film FF2. Therefore, if the ferroelectric film FF2 can be efficiently crystallized without forming the metal film MF2, the metal film MF2 may not be formed. The metal film MF2 and the gate electrode GE2 function as a memory gate electrode of the memory transistor.

[0024] The gate electrode GE2 is formed on the gate insulating film GDF2. Specifically, when the metal film MF2 is formed on the gate insulating film GDF2, the gate electrode GE2 is formed on the metal film MF2. The gate electrode GE2 is formed of, for example, a polycrystalline silicon film into which n-type impurities are introduced. The gate electrode GE2 may be formed of a titanium nitride film, an aluminum film, or a tungsten film. Further, the gate electrode GE2 may be formed of a laminated film including two or more conductive films.

[0025] The sidewall insulating film SDF2 is formed on the semiconductor substrate SS and on the side surfaces of the gate electrode GE2. The sidewall insulating film SDF2 is formed of, for example, a laminated film including a silicon oxide film and a silicon nitride film.

[0026] The interlayer insulating film IDF is formed on the semiconductor substrate SS. Specifically, the interlayer insulating film IDF is formed on the semiconductor substrate SS so as to cover the ferroelectric memory cell. The interlayer insulating film IDF is formed of, for example, a silicon oxide film. A plurality of contact plugs are formed in the interlayer insulating film IDF. Each of the plurality of contact plugs is formed of a barrier metal film and a conductive film. The barrier metal film is formed of a titanium film, a titanium nitride film, or a laminated film thereof, and the conductive film is formed of a tungsten film. The plurality of contact plugs include a contact plug CP1 and a contact plug CP2. The contact plug CP1 is connected to the drain region DR1, and the contact plug CP2 is connected to the source region SR1. Although not shown, the semiconductor device has a contact plug disposed on the gate electrode GE1 and a contact plug disposed on the gate electrode GE2.

[0027] Although not shown, a multilayer wiring layer is disposed on the interlayer insulating film. The multilayer wiring layer has a plurality of wirings and a plurality of interlayer insulating films, and each of the plurality of wirings is connected to each of the plurality of contact plugs.

[0028] <Method of manufacturing a semiconductor device> As shown in FIG. 2, a semiconductor substrate SS is prepared. Next, a groove is formed in the semiconductor substrate SS by photolithography technology and etching process. Next, an insulating film is formed on the semiconductor substrate SS so as to be embedded in the groove. Thereafter, by using the CMP (Chemical Mechanical Polishing) method to remove the insulating film formed outside the groove, an element isolation structure EIS is formed. Next, impurities are introduced into the semiconductor substrate SS by using photolithography technology and ion implantation method, whereby a well region WR is formed in the semiconductor substrate SS.

[0029] Next, as shown in FIG. 3, by performing a heat treatment on the upper surface of the semiconductor substrate SS, an insulating film DF3 is formed on the semiconductor substrate SS. The heat treatment for forming the insulating film DF3 is performed in an atmosphere containing oxygen. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the insulating film DF3 is, for example, 1 nm or more and 3 nm or less.

[0030] Next, as shown in FIG. 4, for example, by the ALD (Atomic Layer Deposition) method, an amorphous film AF1 is formed on the insulating film DF3. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the amorphous film AF1 is, for example, 6 nm or more and 20 nm. The amorphous film AF1 contains, for example, hafnium, oxygen, and zirconium. The amorphous film AF1 may contain at least one of silicon, germanium, yttrium, lanthanum, and ytterbium instead of zirconium.

[0031] Next, as shown in FIG. 5, for example, by the CVD (Chemical Vapor Deposition) method or the sputtering method, a metal film MF3 is formed on the amorphous film AF1. The metal film MF3 is formed of, for example, a titanium nitride film, a tantalum nitride film, or a tungsten film. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the metal film MF3 is, for example, 2 nm or more and 20 nm or less. The metal film MF3 is formed to apply stress to the amorphous film AF1.

[0032] Next, as shown in FIG. 6, the amorphous film AF1 is crystallized by subjecting the amorphous film AF1 to a heat treatment, thereby forming a ferroelectric film FF3 on the semiconductor substrate SS. The heat treatment for crystallizing the amorphous film AF1 is performed in a state where the metal film MF3 is formed on the amorphous film AF1. The heat treatment for crystallizing the amorphous film AF1 is performed, for example, by the RTA (Rapid Thermal Annealing) method or an annealing method using microwaves. The stress from the metal film MF3 controls the crystal orientation of the ferroelectric film FF3. When the amorphous film AF1 is crystallized into the ferroelectric film FF3, the metal film MF3 has a function of orienting the crystal phase of the ferroelectric film FF3 into a cubic crystal.

[0033] Next, as shown in FIG. 7, a conductive film CF1 is formed on the metal film MF3 by, for example, the CVD method. The conductive film CF1 is formed from, for example, polycrystalline silicon into which an n-type impurity has been introduced. When the metal film MF3 is not formed on the ferroelectric film FF3, the conductive film CF1 is formed on the ferroelectric film FF3.

[0034] Next, as shown in FIG. 8, a gate electrode GE1, a gate electrode GE2, a gate insulating film GDF1, and a gate insulating film GDF2 are formed. First, a mask film is formed on the conductive film CF1 by a known method. Next, the conductive film CF1 is processed by an anisotropic etching method using the mask film to form the gate electrode GE1 and the gate electrode GE2. Next, the metal film MF3, the ferroelectric film FF3, and the insulating film DF3 are processed using the gate electrode GE1 and the gate electrode GE2 as masks, thereby forming a metal film MF1, a ferroelectric film FF1, and an insulating film DF1 under the gate electrode GE1, and forming a metal film MF2, a ferroelectric film FF2, and an insulating film DF2 under the gate electrode GE2.

[0035] Next, by a known method, a drain region DR1, a source region SR1, an impurity region IR, sidewall insulating films SDF1 and SDF2, an interlayer insulating film IDF, and a plurality of contact plugs are formed. Thus, a semiconductor device having the structure shown in FIG. 1 is formed.

[0036] <Operation of the Semiconductor Device> Specifically, FIG. 9 shows an example of the voltages applied to each part in the write operation, the erase operation, and the read operation. Each voltage shown in FIG. 9 is applied to the selected memory cell that is the operation target and is not applied to the non-selected memory cell that is not the operation target. A voltage different from the voltage shown in FIG. 9 is applied to the non-selected memory cell. In FIG. 9, in each of the write operation, the erase operation, and the read operation, the voltage Vd applied to the drain region DR1 of the ferroelectric memory cell, the voltage Vcg applied to the gate electrode GE1, the voltage Vmg applied to the gate electrode GE2, the voltage Vs applied to the source region SR1, and the voltage Vb applied to the well region WR are described. Note that the applied voltages shown in FIG. 9 are merely examples.

[0037] Note that in Embodiment 1, a state in which the polarization of the ferroelectric film FF2 is upward and the threshold voltage of the memory transistor is relatively high is defined as the write state. Also, a state in which the polarization of the ferroelectric film FF2 is downward and the threshold voltage of the memory transistor is relatively low is defined as the erase state.

[0038] In the write operation, for example, the voltages shown in the “Write” row of FIG. 9 are applied to each part of the selected memory cell that is the operation target. As a result, the polarization in the ferroelectric film FF2 becomes upward, the threshold voltage of the memory transistor increases, and the ferroelectric film FF2 enters the write state. Even when the voltages shown in the “Write” row of FIG. 9 are no longer applied, the polarization in the ferroelectric film FF2 remains held until an erase operation is performed on the selected memory cell.

[0039] In the erasing operation, for example, the voltage shown in the "Erase" row of FIG. 9 is applied to each part of the selected memory cell targeted for the erasing operation. As a result, the polarization in the ferroelectric film FF2 becomes downward, the threshold voltage of the memory transistor decreases, and the ferroelectric film FF2 enters the erased state. Even when the voltage shown in the "Erase" row of FIG. 9 is no longer applied, the polarization in the ferroelectric film FF2 remains held until a writing operation is performed on the selected memory cell.

[0040] In the reading operation, for example, the voltage shown in the "Read" row of FIG. 9 is applied to each part of the selected memory cell targeted for the reading operation. The voltage Vmg applied to the gate electrode GE2 is set to a value between the threshold voltage of the memory transistor in the written state and the threshold voltage of the memory transistor in the erased state. Therefore, the magnitude of the current flowing through the memory transistor in the written state is different from the magnitude of the current flowing through the memory transistor in the erased state. By detecting the magnitude of the current flowing through the ferroelectric memory cell in the reading operation, the state of the ferroelectric memory cell can be determined.

[0041] The selection transistor has the role of selecting a memory transistor to be operated. If the threshold voltage of the selection transistor fluctuates, the performance of the ferroelectric memory cell fluctuates. For example, there may be a case where the selection transistor cannot select the memory transistor to be operated. Therefore, it is preferable that the fluctuation of the threshold voltage of the selection transistor is small. However, in Embodiment 1, the selection transistor has a ferroelectric film FF1, and the selection transistor may operate as a memory cell. When a write operation or an erase operation is performed on the selection transistor, the threshold voltage of the selection transistor may fluctuate. In order to suppress the fluctuation of the threshold voltage of the selection transistor, a write operation may be performed on the selection transistor after the selection transistor is formed. For example, a voltage of 5V is applied to the gate electrode GE1, and a voltage of 0V is applied to the drain region DR1, the source region SR1, and the well region WR. Thereby, the selection transistor becomes an erased state, and the selection transistor has a relatively low threshold voltage. For example, the threshold voltage of the selection transistor is set lower than the positive voltage applied to the gate electrode GE1 during the operation of the selection transistor. Thereby, it is possible to suppress the positive voltage applied to the gate electrode GE1 during the operation of the selection transistor from fluctuating the threshold voltage of the selection transistor.

[0042] <Main features and effects of Embodiment 1> Compared with the manufacturing method of the semiconductor device according to the comparative example, the main features and effects of the manufacturing method of the semiconductor device and the structure of the semiconductor device according to Embodiment 1 are described.

[0043] In the method for manufacturing a semiconductor device according to the comparative example, as in the first embodiment, referring back to FIG. 2, a semiconductor substrate SS is prepared, and a well region WR and an element isolation structure EIS are formed in the semiconductor substrate SS. Next, in the comparative example, as shown in FIG. 10, an insulating film DFC and a protective film PFC are formed on the semiconductor substrate SS. First, for example, by subjecting the semiconductor substrate SS to a heat treatment, an insulating film DFC is formed on the semiconductor substrate SS. Next, for example, by the CVD method, a protective film PFC is formed on the insulating film DFC. Thereafter, by the CVD method or photolithography technology, a mask film MKC1 is formed on the protective film PFC. Thereafter, the protective film PFC is processed by an etching process to remove the protective film PFC exposed from the mask film MKC1. The processed protective film PFC covers at least a part of the upper surface of the semiconductor substrate SS where the gate insulating film GDFC1 is formed, and exposes a part of the upper surface of the semiconductor substrate SS where the gate insulating film GDFC2 is formed. Next, as shown in FIG. 11, a mask film MKC2 is formed on the protective film PFC and on the insulating film DFC by the CVD method or photolithography technology. The mask film MKC2 is formed on the insulating film DFC so as to cover the protective film PFC. Thereafter, the insulating film DFC is processed by an etching process to remove the insulating film DFC exposed from the mask film MKC2. As a result, the upper surface of the semiconductor substrate SS where the gate insulating film GDFC2 is formed is exposed. Thereafter, although not shown, an insulating film is formed adjacent to the processed insulating film DFC and on the upper surface of the semiconductor substrate SS.

[0044] Next, as shown in FIG. 12, a ferroelectric film FFC1 and a metal film MFC1 are formed on the semiconductor substrate SS. First, for example, by the ALD method, an amorphous film is formed on the semiconductor substrate SS. The amorphous film is formed so as to cover the insulating film DFC and the protective film PFC. Next, for example, by the CVD method or sputtering method, a metal film MFC1 is formed on the amorphous film. The metal film MFC1 is formed so as to cover the insulating film DFC and the protective film PFC. Next, the amorphous film is crystallized by subjecting the amorphous film to a heat treatment to form a ferroelectric film FFC1.

[0045] Next, as shown in FIG. 13, the metal film MFC1 and the ferroelectric film FFC1 are processed. First, a mask film MKC3 is formed on the metal film MFC1. Next, the metal film MFC1 and the ferroelectric film FFC1 are processed by an etching process, and the metal film MFC1 and the ferroelectric film FFC1 exposed from the mask film MKC3 are removed. As a result, the side surfaces of the processed metal film MFC1 and the processed ferroelectric film FFC1 are located on the insulating film DFC, while not on the protective film PFC. That is, the side surfaces of the processed metal film MFC1 and the processed ferroelectric film FFC1 are located on the insulating film DFC exposed from the protective film PFC.

[0046] Next, as shown in FIG. 14, the protective film PFC is removed by an etching method. Next, a conductive film CF3 is formed on the semiconductor substrate SS. Specifically, the conductive film CF3 is formed on the insulating film DFC and on the metal film MFC1. When the metal film MFC1 is not formed on the ferroelectric film FFC1, the conductive film CF3 is formed on the ferroelectric film FFC1.

[0047] Next, as shown in FIG. 15, a mask film is formed on the conductive film CF3 by a known method. Next, the conductive film CF3 is processed by an etching process using the mask film. Thereby, the gate electrode GEC1 and the gate electrode GEC2 are formed.

[0048] Next, as shown in FIG. 16, the metal film MFC1 and the ferroelectric film FFC1 are processed using the gate electrode GEC2 as a mask, thereby forming a metal film MFC2 and a ferroelectric film FFC2 under the gate electrode GEC2.

[0049] Next, as shown in FIG. 17, a drain region DR1, a source region SR1, an impurity region IR, sidewall insulating films SDF1, SDF2, an interlayer insulating film IDF, contact plugs CP1 and CP2 are formed by a known method. Thus, the semiconductor device according to the comparative example is manufactured.

[0050] FIG. 18 shows the formation positions of the mask film MKC1, the mask film MKC2, and the mask film MKC3. Specifically, in FIG. 18, the dotted line A indicates the formation position of the end portion of the mask film MKC1 for processing the protective film PFC shown in FIG. 10. The dotted line B indicates the formation position of the end portion of the mask film MKC2 for processing the insulating film DFC shown in FIG. 11. The dotted line C indicates the formation position of the end portion of the mask film MKC3 for processing the ferroelectric film FFC1 shown in FIG. 13.

[0051] In the comparative example, while the gate insulating film GDFC2 of the memory transistor has the ferroelectric film FFC2, the gate insulating film GDFC1 of the selection transistor does not have a ferroelectric film. Therefore, as referred back to FIGS. 10 to 13, the manufacturing method of the semiconductor device according to the comparative example includes a step of processing the protective film PFC, a step of processing the insulating film DFC, and a step of processing the ferroelectric film FFC1. Therefore, in order to manufacture the semiconductor device according to the comparative example, it is necessary to form at least the mask film MKC1, the mask film MKC2, and the mask film MKC3. The mask film MKC1, the mask film MKC2, and the mask film MKC3 are formed by a CVD method, photolithography technology, etching treatment, and the like. Therefore, manufacturing variations affect the formation positions of the mask film MKC1, the mask film MKC2, and the mask film MKC3. The formation position of the structure formed on the semiconductor substrate SS varies in the planar direction due to manufacturing variations.

[0052] For example, in the comparative example, the formation position of the mask film MKC1 may vary such that the distance between the mask film MKC1 and the mask film MKC3 decreases. Similarly, the formation position of the mask film MKC3 may vary such that the distance between the mask film MKC1 and the mask film MKC3 decreases. If the formation position of the mask film MKC1 is closer to the formation position of the mask film MKC3 than the formation position of the mask film MKC1 shown in FIG. 18, the end of the mask film MKC1 shown in FIG. 18 and the end of the mask film MKC3 shown in FIG. 18 may be interchanged. In that case, for example, a defective formation of the ferroelectric film FFC1 processed using the mask film MKC3 may occur. Therefore, the formation position of one mask film affects the formation position of another mask film, and there is a risk that the protective film PFC, the insulating film DFC, and the ferroelectric film FFC2 cannot be formed at desired positions. In order to form the protective film PFC, the insulating film DFC, and the ferroelectric film FFC2 at desired positions, it is necessary to ensure a sufficient distance between the formation position of one mask film and the formation position of another mask film. Furthermore, in order to prevent a defective formation of the gate electrode GEC1, it is necessary to ensure a sufficient distance between the formation position of the end of the mask film MKC1 and the formation position of the gate electrode GEC1. Also, in order to prevent a defective formation of the gate electrode GEC2, it is necessary to ensure a sufficient distance between the formation position of the end of the mask film MKC2 and the formation position of the gate electrode GEC2.

[0053] Thus, when a sufficient distance is ensured between the formation positions of the mask film MKC1, the mask film MKC2, the mask film MKC3, the gate electrode GEC1, and the gate electrode GEC2, the distance between the gate electrode GEC1 and the gate electrode GEC2 increases. The increase in the distance between the gate electrode GEC1 and the gate electrode GEC2 results in an increase in the size of the ferroelectric memory cell. As a result, the size of the semiconductor chip on which the ferroelectric memory is mounted becomes large.

[0054] In Embodiment 1, the gate insulating film GDF1 has the ferroelectric film FF1, and the gate insulating film GDF2 has the ferroelectric film FF2. Referring back to FIG. 8, in Embodiment 1, the ferroelectric films FF1 and FF2 are formed by processing the ferroelectric film FF3.

[0055] As shown in FIG. 8, by processing the metal film MF3, the ferroelectric film FF3, and the insulating film DF3 using the gate electrodes GE1 and GE2 as masks, the gate insulating film GDF1 and the gate insulating film GDF2 are formed. Therefore, in Embodiment 1, there is no need to form the mask film MKC1 for processing the protective film PFC, the mask film MKC2 for processing the insulating film DFC, and the mask film MKC3 for processing the ferroelectric film FFC1 as required in the comparative example. Therefore, in Embodiment 1, there is no need to secure a sufficient interval between the formation positions of the mask film MKC1, the mask film MKC2, and the mask film MKC3. In Embodiment 1, it is sufficient that a sufficient interval is secured between the formation positions of the gate electrode GE1 and the gate electrode GE2. The interval between the gate electrode GE1 and the gate electrode GE2 in Embodiment 1 can be made smaller than the interval between the gate electrode GEC1 and the gate electrode GEC2 in the comparative example. Therefore, the semiconductor device according to Embodiment 1 can be miniaturized compared with the semiconductor device according to the comparative example.

[0056] Further, in Embodiment 1, not only does the memory transistor have the ferroelectric film FF2, but the selection transistor also has the ferroelectric film FF1. The ferroelectric film FF1 is formed from a high-k dielectric film. Therefore, even if the physical thickness of the insulating film DFC of the selection transistor according to the comparative example is the same as the physical thickness of the gate insulating film GDF1 of the selection transistor according to Embodiment 1, the equivalent oxide thickness (EOT) of the gate insulating film GDF1 can be made smaller than the equivalent oxide thickness of the insulating film DFC. Therefore, the performance can be improved while maintaining the reliability of the semiconductor device according to Embodiment 1 compared with the semiconductor device according to the comparative example.

[0057] (Modification Example 1) <Structure of Semiconductor Device> Modification Example 1 is a modification of Embodiment 1. As shown in FIG. 19, the semiconductor device according to Modification Example 1 has the same configuration as that of the semiconductor device according to Embodiment 1 except for the thickness of the insulating film DF1 and the thickness of the insulating film DF2. In Modification Example 1, the thickness of the insulating film DF1 is greater than the thickness of the insulating film DF2. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the insulating film DF1 is, for example, 4 nm or more and 8 nm or less. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the insulating film DF2 is, for example, 1 nm or more and 3 nm or less.

[0058] <Method for Manufacturing Semiconductor Device> In the method for manufacturing a semiconductor device according to Modification Example 1, as shown in FIG. 2, a semiconductor substrate SS is prepared, and a well region WR and an element isolation structure EIS are formed in the semiconductor substrate SS. Next, as shown in FIG. 20, an insulating film DFM1 is formed on the semiconductor substrate SS. The insulating film DFM1 is formed, for example, by a thermal oxidation method or an ISSG oxidation method. Next, the insulating film DFM1 is processed by photolithography technology and an etching method to remove a part of the insulating film DFM1. As a result, the insulating film DFM1 located on a part of the upper surface of the semiconductor substrate SS where the gate insulating film GDFM2 is formed is removed, and the insulating film DFM1 located on a part of the upper surface of the semiconductor substrate SS where the gate insulating film GDFM1 is formed is not removed. Next, an insulating film DFM2 is formed on a part of the semiconductor substrate SS exposed from the insulating film DFM1. The insulating film DFM2 is formed, for example, by a thermal oxidation method or an ISSG oxidation method. The thickness of the insulating film DFM1 is greater than the thickness of the insulating film DFM2.

[0059] Next, as shown in FIG. 21, an amorphous film AF3 is formed on the insulating film DFM1 and the insulating film DFM2. The formation method and configuration of the amorphous film AF3 in Modification 1 are the same as those of the amorphous film AF1 in Embodiment 1. Next, a metal film MFM1 is formed on the amorphous film AF3. The formation method and configuration of the metal film MFM1 in Modification 1 are the same as those of the metal film MF3 in Embodiment 1. Next, a ferroelectric film FFM1 is formed by crystallizing the amorphous film AF3. The crystallization method of the amorphous film AF3 in Modification 1 is the same as that of the amorphous film AF1 in Embodiment 1. Next, a gate electrode GEM1 and a gate electrode GEM2 are formed on the metal film MFM1. The formation method of the gate electrode GEM1 and the formation method of the gate electrode GEM2 in Modification 1 are the same as those of the gate electrode GE1 and the gate electrode GE2 in Embodiment 1.

[0060] Next, the metal film MFM1 and the ferroelectric film FFM1 are processed using the gate electrode GEM1 and the gate electrode GEM2 as masks. As a result, as shown in FIG. 19, a gate insulating film GDFM1 including a metal film MFM2, a ferroelectric film FFM2, and an insulating film DFM1 and a gate insulating film GDFM2 including a metal film MFM3, a ferroelectric film FFM3, and an insulating film DFM2 are formed. Thereafter, a drain region DR1, a source region SR1, an impurity region IR, sidewall insulating films SDF1 and SDF2, an interlayer insulating film IDF, and a plurality of contact plugs are formed by a known method. Thus, the semiconductor device shown in FIG. 19 is manufactured.

[0061] <Main features and effects of Modification 1> If the thickness of the insulating film DF1 is insufficient, the performance of the selection transistor may deteriorate. When the selection transistor operates, a positive voltage is applied to the gate electrode GE1 of the selection transistor. If the thickness of the insulating film DF1 is insufficient, electrons flowing in the semiconductor substrate SS are injected through the insulating film DF1 to the interface between the insulating film DF1 and the ferroelectric film FF1. Since electrons exist at the interface between the insulating film DF1 and the ferroelectric film FF1, the strength of the electric field applied to the ferroelectric film FF1 increases, and the selection transistor operates as a memory cell. In this case, the operation of the selection transistor as a memory cell means that a write operation is performed on the selection transistor. As a result, the threshold voltage of the selection transistor increases, and there is a possibility that no current flows through the selection transistor. As a result, there is a possibility that the ferroelectric memory cell does not operate normally.

[0062] In Modification 1, the thickness of the insulating film DFM1 is larger than the thickness of the insulating film DFM2. Therefore, when the selection transistor operates, electrons flowing in the semiconductor substrate SS are less likely to be injected through the insulating film DFM1 to the interface between the insulating film DFM1 and the ferroelectric film FFM2. Therefore, it is difficult for the selection transistor to operate as a memory cell, and the ferroelectric memory cell can operate normally. Also in Modification 1, as shown in FIG. 21, by processing the ferroelectric film FFM1, the ferroelectric film FFM2 and the ferroelectric film FFM3 are formed. Thereby, a gate insulating film GDFM1 having the ferroelectric film FFM2 is formed, and a gate insulating film GDFM2 having the ferroelectric film FFM3 is formed. Therefore, similar to the first embodiment, the semiconductor device can be miniaturized.

[0063] (Second Embodiment) <Structure of Semiconductor Device> As shown in FIG. 22, the semiconductor device of Embodiment 2 has a ferroelectric memory cell and a MISFET (Metal Insulator Semiconductor Field Effect Transistor). The ferroelectric memory cell and the MISFET do not have to be arranged adjacent to each other. Other semiconductor elements, dummy patterns, etc. may be arranged between the ferroelectric memory cell and the MISFET. The configuration of the ferroelectric memory cell according to Embodiment 2 is the same as the configuration of the ferroelectric memory cell according to Embodiment 1. The MISFET has at least a source region SR2, a drain region DR2, a gate insulating film GDFS, a metal film MFS1, and a gate electrode GES.

[0064] The source region SR2 is formed in the semiconductor substrate SS and in the well region WR, and is disposed on the upper surface of the semiconductor substrate SS. The depth of the source region SR2 is smaller than the depth of the well region WR. The impurity concentration of the source region SR2 is higher than the impurity concentration of the well region WR. The conductivity type of the source region SR2 is, for example, n-type. The source region SR2 may have an LDD structure. The source region SR2 contains, for example, arsenic or phosphorus. The drain region DR2 is formed in the semiconductor substrate SS and in the well region WR, and is disposed on the upper surface of the semiconductor substrate SS. The depth of the drain region DR2 is smaller than the depth of the well region WR. The impurity concentration of the drain region DR2 is higher than the impurity concentration of the well region WR. The drain region DR2 may have an LDD structure. The drain region DR2 is separated from the source region SR2. The drain region DR2 and the source region SR2 are surrounded by an element isolation structure EIS in plan view. A silicide layer may be formed on the drain region DR2 and on the source region SR2.

[0065] The gate insulating film GDFS is formed on the semiconductor substrate SS, the metal film MFS1 is formed on the gate insulating film GDFS, and the gate electrode GES is formed on the metal film MFS1. Specifically, the gate insulating film GDFS is formed on a part of the semiconductor substrate SS located between the drain region DR2 and the source region SR2 in plan view. Specifically, the gate insulating film GDFS has an insulating film DFS1 and a ferroelectric film FFS1. The insulating film DFS1 is formed on the semiconductor substrate SS, and the ferroelectric film FFS1 is formed on the insulating film DFS1 such that the insulating film DFS1 is disposed between the semiconductor substrate SS and the ferroelectric film FFS1. The insulating film DFS1 is formed of a paraelectric film, for example, a silicon oxide film. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the insulating film DFS1 is, for example, 1 nm or more and 3 nm or less. The insulating film DFS1 has a function of suppressing electrons from entering the ferroelectric film FFS1 from the semiconductor substrate SS when a voltage is applied to the gate electrode GES. If electrons can be suppressed from entering the ferroelectric film FFS1 without the insulating film DFS1, or if it is not necessary to consider the influence of electrons entering the ferroelectric film FFS1, the insulating film DFS1 may not be formed. The ferroelectric film FFS1 disposed between the insulating film DFS1 and the gate electrode GES is formed of, for example, a metal oxide film, and is formed of a high dielectric constant film having a higher dielectric constant than a silicon nitride film. The ferroelectric film FFS1 contains, for example, hafnium, oxygen, and zirconium. The ferroelectric film FFS1 may contain at least one of silicon, germanium, yttrium, lanthanum, and ytterbium instead of zirconium. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the ferroelectric film FFS1 is, for example, 6 nm or more and 20 nm or less.

[0066] The metal film MFS1 is formed on the gate insulating film GDFS and is disposed between the gate insulating film GDFS and the gate electrode GES. The metal film MFS1 is formed of, for example, a titanium nitride film, a tantalum nitride film, or a tungsten film. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the metal film MFS1 is, for example, 2 nm or more and 20 nm or less. The metal film MFS1 is used to efficiently crystallize the ferroelectric film FFS1. Therefore, if the ferroelectric film FFS1 can be efficiently crystallized without forming the metal film MFS1, the metal film MFS1 may not be formed. The metal film MFS1 and the gate electrode GES function as the gate electrode of the MISFET.

[0067] The gate electrode GES is formed on the gate insulating film GDFS. Specifically, when the metal film MFS1 is formed on the gate insulating film GDFS, the gate electrode GES is formed on the metal film MFS1. The gate electrode GES is formed of, for example, a polycrystalline silicon film into which n-type impurities are introduced. The gate electrode GES may be formed of a titanium nitride film, an aluminum film, or a tungsten film. Further, the gate electrode GES may be formed of a laminated film including two or more conductive films.

[0068] The sidewall insulating film SDF3 is formed on the semiconductor substrate SS and on the side surfaces of the gate electrode GES. The sidewall insulating film SDF3 is formed of, for example, a laminated film including a silicon oxide film and a silicon nitride film.

[0069] The interlayer insulating film IDF is formed on the semiconductor substrate SS so as to cover the ferroelectric memory cell and the MISFET. The plurality of contact plugs include contact plugs CP3 and CP4 in addition to the contact plugs CP1 and CP2. The contact plug CP3 is disposed on the drain region DR2, and the contact plug CP4 is disposed on the source region SR2. Although not shown, the semiconductor device has a contact plug disposed on the gate electrode GES.

[0070] <Method of manufacturing semiconductor device> As shown in FIG. 23, an insulating film DFS2 is formed on a semiconductor substrate SS by performing a heat treatment on the upper surface of the semiconductor substrate SS. The insulating film DFS2 is formed on a part of the semiconductor substrate SS where ferroelectric memory cells are formed and a part of the semiconductor substrate SS where MISFETs are formed. The heat treatment for forming the insulating film DFS2 is performed in an atmosphere containing oxygen. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the insulating film DFS2 is, for example, 1 nm or more and 3 nm or less. Next, an amorphous film AF2 is formed on the insulating film DFS2 by, for example, ALD method. The amorphous film AF2 is formed on a part of the semiconductor substrate SS where ferroelectric memory cells are formed and a part of the semiconductor substrate SS where MISFETs are formed. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the amorphous film AF2 is, for example, 6 nm or more and 20 nm. The amorphous film AF2 contains, for example, hafnium, oxygen, and zirconium. The amorphous film AF2 may contain at least one of silicon, germanium, yttrium, lanthanum, and ytterbium instead of zirconium.

[0071] Next, a metal film MFS2 is formed on the amorphous film AF2 by, for example, CVD method or sputtering method. The metal film MFS2 is formed on a part of the semiconductor substrate SS where ferroelectric memory cells are formed and a part of the semiconductor substrate SS where MISFETs are formed. The metal film MFS2 is formed of, for example, titanium nitride, tantalum nitride, or tungsten. In a direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the metal film MFS2 is, for example, 2 nm or more and 20 nm or less. The metal film MFS2 is formed to apply stress to the amorphous film AF2. Next, the amorphous film AF2 is crystallized by performing a heat treatment on the amorphous film AF2 to form a ferroelectric film FFS2. The method of crystallizing the amorphous film AF2 is the same as the method of crystallizing the amorphous film AF1 in Embodiment 1.

[0072] Next, as shown in FIG. 24, a conductive film CF2 is formed on the metal film MFS2, for example, by CVD method. The conductive film CF2 is formed of, for example, polycrystalline silicon into which n-type impurities are introduced. When the metal film MFS2 is not formed on the ferroelectric film FFS2, the conductive film CF2 is formed on the ferroelectric film FFS2. Next, the conductive film CF2 is processed by an anisotropic etching method to form a gate electrode GE1, a gate electrode GE2, and a gate electrode GES.

[0073] Next, as shown in FIG. 25, the metal film MFS2, the ferroelectric film FFS2, and the insulating film DFS2 are processed by an anisotropic etching method using the gate electrode GE1, the gate electrode GE2, and the gate electrode GES as masks. Thereby, a metal film MF1, a metal film MF2, a metal film MFS1, a ferroelectric film FF1, a ferroelectric film FF2, a ferroelectric film FFS1, an insulating film DF1, an insulating film DF2, and an insulating film DFS1 are formed.

[0074] Next, a drain region DR1, a drain region DR2, a source region SR1, a source region SR2, an impurity region IR, sidewall insulating films SDF1, SDF2, SDF3, an interlayer insulating film IDF, and a plurality of contact plugs are formed by a known method. Thus, a semiconductor device having the structure shown in FIG. 22 is formed.

[0075] <Main Features and Effects of Embodiment 2> Various types of semiconductor elements are formed on a semiconductor substrate SS. For example, the semiconductor elements include a ferroelectric memory cell, a low-voltage MISFET, a high-voltage MISFET, and the like. The operating voltages and functions of the ferroelectric memory cell, the low-voltage MISFET, and the high-voltage MISFET are different from each other. Therefore, the structures of the gate insulating films of the ferroelectric memory cell, the low-voltage MISFET, and the high-voltage MISFET are also different from each other. For example, the gate insulating films of the low-voltage MISFET and the high-voltage MISFET are formed of silicon oxide. In the direction perpendicular to the upper surface of the semiconductor substrate SS, the thickness of the gate insulating film of the high-voltage MISFET is larger than the thickness of the gate insulating film of the low-voltage MISFET.

[0076] Referring back to FIG. 17, in the ferroelectric memory cell according to the comparative example, the structure of the gate insulating film GDFC1 of the selection transistor is different from the structure of the gate insulating film GDFC2 of the memory transistor. Therefore, as referring back to FIGS. 10 to 13, it is necessary to process the insulating film DFC, the ferroelectric film FFC1, and the metal film MFC1 so that the insulating film DFC, the ferroelectric film FFC1, and the metal film MFC1 are formed at desired positions. Therefore, the number of manufacturing steps increases in the comparative example. Similarly, the structure of the gate insulating film of the MISFET is different from the structure of the gate insulating film GDFC1 of the selection transistor and the structure of the gate insulating film GDFC2 of the memory transistor. Therefore, a step of processing the gate insulating film of the MISFET is performed so that the gate insulating film of the MISFET is formed at a desired position. Therefore, the number of manufacturing steps increases.

[0077] In Embodiment 2, as shown in FIG. 22, the gate insulating film GDF1 has a ferroelectric film FF1, the gate insulating film GDF2 has a ferroelectric film FF2, and the gate insulating film GDFS has a ferroelectric film FFS1. Then, as shown in FIG. 25, by processing the ferroelectric film FFS2, the ferroelectric film FF1, the ferroelectric film FF2, and the ferroelectric film FFS1 are formed.

[0078] As shown in FIG. 25, by using the gate electrodes GE1, GE2, and GES as masks to process the metal film MFS2, the ferroelectric film FFS2, and the insulating film DFS2, the gate insulating film GDF1, the gate insulating film GDF2, and the gate insulating film GDFS are formed. In Embodiment 2, not only is it unnecessary to form the mask films MKC1, MKC2, and MKC3, but it is also unnecessary to form a mask film for processing the gate insulating film GDFS. In Embodiment 2, since it is not necessary to perform the step of processing the gate insulating film GDFS, the number of manufacturing steps can be reduced and the manufacturing process can be simplified. Compared with the semiconductor device according to the comparative example, the semiconductor device according to Embodiment 2 can be miniaturized in the same manner as Embodiment 1.

[0079] In Modification 1 of Embodiment 1, the technology described can be applied to the technology described in Embodiment 2. That is, in the structure shown in FIG. 22, the thickness of the insulating film DF1 may be greater than the thickness of the insulating film DF2. Also, in order to optimize the performance of the MISFET, the thickness of the insulating film DFS1 may be different from the thicknesses of the insulating film DF1 and the insulating film DF2.

[0080] As described above, the invention made by the inventor of the present application has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0081] AF1, AF2, AF3 Amorphous film CF1, CF2, CF3 Conductive film CP1, CP2, CP3, CP4 Contact plug DF1, DF2, DF3 Insulating film DFC Insulating film DFM1, DFM2 Insulating film DFS1, DFS2 Insulating film DR1, DR2 Drain region EIS Element isolation structure FF1, FF2, FF3 Ferroelectric film FFC1, FFC2 Ferroelectric film FFM1, FFM2, FFM3 Ferroelectric film FFS1, FFS2 Ferroelectric film GDF1, GDF2 Gate insulating film GDFC1, GDFC2 Gate insulating film GDFM1, GDFM2 Gate insulating film GDFS Gate insulating film GE1, GE2 Gate electrode GEC1, GEC2 Gate electrode GEM1, GEM2 Gate electrode GES Gate electrode IDF Interlayer insulating film IR impurity region MF1, MF2, MF3 metal films MFC1, MFC2 metal films MFM1, MFM2, MFM3 metal films MFS1, MFS2 metal films MKC1, MKC2, MKC3 mask films PFC protective film SDF1, SDF2, SDF3 sidewall insulating films SR1, SR2 source regions SS semiconductor substrate WR well region

Claims

1. A semiconductor substrate, A ferroelectric memory cell formed on the semiconductor substrate, And having, The ferroelectric memory cell includes, A first gate insulating film formed on the semiconductor substrate, A first gate electrode formed on the first gate insulating film, A second gate insulating film formed on the semiconductor substrate, A second gate electrode formed on the second gate insulating film, A source region formed in the semiconductor substrate, A drain region formed in the semiconductor substrate, And having, The first gate insulating film has a first ferroelectric film, The second gate insulating film has a second ferroelectric film, a semiconductor device.

2. In the semiconductor device according to Claim 1, The semiconductor substrate has an upper surface, The first gate insulating film has a first insulating film disposed between the semiconductor substrate and the first ferroelectric film, The second gate insulating film has a second insulating film disposed between the semiconductor substrate and the second ferroelectric film, a semiconductor device.

3. In the semiconductor device according to Claim 2, In a direction perpendicular to the upper surface of the semiconductor substrate, the thickness of the first insulating film is greater than the thickness of the second insulating film, a semiconductor device.

4. In the semiconductor device according to Claim 1, The semiconductor substrate has an upper surface, In a direction perpendicular to the upper surface of the semiconductor substrate, the thickness of the first ferroelectric film is the same as the thickness of the second ferroelectric film, a semiconductor device.

5. In the semiconductor device according to Claim 2, The first insulating film is formed of a silicon oxide film, The second insulating film is formed of a silicon oxide film, a semiconductor device.

6. In the semiconductor device according to Claim 1, The first ferroelectric film contains hafnium and oxygen, The second ferroelectric film contains hafnium and oxygen, a semiconductor device.

7. In the semiconductor device according to Claim 1, An impurity region formed in the semiconductor substrate, And further having, The impurity region is disposed between the source region and the drain region, a semiconductor device.

8. In the semiconductor device according to Claim 7, The first gate insulating film is formed on a part of the semiconductor substrate located between the drain region and the impurity region, The second gate insulating film is formed on a part of the semiconductor substrate located between the source region and the impurity region, a semiconductor device.

9. In the semiconductor device according to Claim 1, The ferroelectric memory cell is a first metal film disposed between the first ferroelectric film and the first gate electrode, a second metal film disposed between the second ferroelectric film and the second gate electrode, and further includes a semiconductor device.

10. In the semiconductor device according to claim 1, an interlayer insulating film formed on the semiconductor substrate so as to cover the ferroelectric memory cell, a first contact plug formed in the interlayer insulating film and connected to the drain region, a second contact plug formed in the interlayer insulating film and connected to the source region, and further includes a semiconductor device.

11. (a) a step of preparing a semiconductor substrate, (b) a step of forming a ferroelectric film on the semiconductor substrate, (c) a step of forming a conductive film on the ferroelectric film, (d) a step of forming a first gate electrode and a second gate electrode by processing the conductive film, (e) after the step (d), by processing the ferroelectric film, a first ferroelectric film is formed between the first gate electrode and the semiconductor substrate, and a second ferroelectric film is formed between the second gate electrode and the semiconductor substrate. step, (f) a step of forming a source region and a drain region in the semiconductor substrate, including The first gate electrode, the second gate electrode, the first ferroelectric film, the second ferroelectric film, the source region, and the drain region constitute a ferroelectric memory cell, a method for manufacturing a semiconductor device.

12. In the method for manufacturing a semiconductor device according to claim 11, (g1) a step of forming an insulating film on the semiconductor substrate before the step (b), further including In the step (b), the ferroelectric film is formed on the insulating film, In the step (e), by processing the insulating film, a first insulating film is formed between the semiconductor substrate and the first ferroelectric film, and a second insulating film is formed between the semiconductor substrate and the second ferroelectric film. A method for manufacturing a semiconductor device.

13. In the method for manufacturing a semiconductor device according to claim 11, (g1) a step of forming a first insulating film on the semiconductor substrate before the step (b), (g2) a step of removing a part of the first insulating film after the step (g1) and before the step (b), (g3) a step of forming a second insulating film on the semiconductor substrate after the step (g2) and before the step (b), further including In the step (b), the ferroelectric film is formed on the first insulating film and on the second insulating film. In the step (e), by processing the first insulating film and the second insulating film, the first insulating film is disposed between the semiconductor substrate and the first ferroelectric film, and the second insulating film is disposed between the semiconductor substrate and the second ferroelectric film. A method of manufacturing a semiconductor device, wherein in a direction perpendicular to the upper surface of the semiconductor substrate, the thickness of the first insulating film is greater than the thickness of the second insulating film.

14. In the method of manufacturing a semiconductor device according to claim 12, the first insulating film is formed of a silicon oxide film, A method of manufacturing a semiconductor device, wherein the second insulating film is formed of a silicon oxide film.

15. In the method of manufacturing a semiconductor device according to claim 11, the first ferroelectric film contains hafnium and oxygen, A method of manufacturing a semiconductor device, wherein the second ferroelectric film contains hafnium and oxygen.

16. In the method of manufacturing a semiconductor device according to claim 11, in the step (f), an impurity region is formed in the semiconductor substrate, A method of manufacturing a semiconductor device, wherein the impurity region is disposed between the source region and the drain region.

17. In the method of manufacturing a semiconductor device according to claim 16, the first ferroelectric film is formed on a part of the semiconductor substrate located between the drain region and the impurity region, A method of manufacturing a semiconductor device, wherein the second ferroelectric film is formed on a part of the semiconductor substrate located between the source region and the impurity region.

18. In the method of manufacturing a semiconductor device according to claim 11, (h) A step of forming a metal film on the ferroelectric film after the step (b) and before the step (c), further comprising, In the step (e), by processing the metal film, a first metal film is formed between the first gate electrode and the first ferroelectric film, and a second metal film is formed between the second gate electrode and the second ferroelectric film. A method of manufacturing a semiconductor device.

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