Method for producing trench capacitor structure and trench capacitor

Abstract

To provide a concept for devices having dielectric, e.g., trench capacitors or RC snubbers or for dielectric layer structures for increasing a breakdown voltage with constant or increased integration density (capacitance).SOLUTION: A method for producing a trench capacitor structure includes the steps of: preparing a silicon substrate with a trench structure, the trench structure comprising a plurality of recesses in a main surface of the silicon substrate; forming a first silicon dioxide layer at least in the recesses of the silicon substrate; depositing a first silicon nitride layer on the first silicon dioxide layer; depositing a second silicon dioxide layer on the first silicon nitride layer by depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer; and depositing a second silicon nitride layer on the second silicon dioxide layer.SELECTED DRAWING: Figure 1a

Description

Technical Field

[0001] Embodiments according to the present invention relate to a method for manufacturing a trench capacitor structure and a trench capacitor, or a method for manufacturing a dielectric layer stack and a trench capacitor having a dielectric layer stack.

Background Art

[0002] The dielectric layer stack is preferably a dielectric (ON) stack (x≧2) for, for example, a Si-RC snubber device, where the silicon dioxide layer is denoted by O and the silicon nitride layer is denoted by N. x stack (x≧2), the silicon dioxide layer is denoted by O, and the silicon nitride layer is denoted by N. Different concepts are known for reducing the bending of the substrate when manufacturing an integrated capacitor. German Patent No. 102019204503 discloses, for example, the introduction of a stress-free nitride layer to increase the peak voltage strength to 1200V and reduce the bending of the disk. However, in such a design, it is almost impossible to further increase the voltage strength without sacrificing the integration density (e.g., due to a thicker dielectric layer) or significantly increasing the wafer bending (e.g., a thicker dielectric layer with a simultaneous increase in the surface due to deeper hole structuring). In view of this, concepts are needed for devices having a dielectric, such as trench capacitors or RC snubbers, or dielectric layer structures, to take into account the bending of the disk due to thermomechanical stress during / after deposition of the dielectric layer and increase the breakdown voltage at a constant or increased integration density (capacitance). This object is solved by the subject matter of the independent claims. Developments of the invention are defined in the dependent claims.

Summary of the Invention

[0003] According to one aspect of the present invention, the inventors recognized that the problem in the manufacture of trench capacitor structures is that it is difficult to increase the voltage strength without sacrificing the integration density and without significantly increasing the bending of the silicon substrate. According to one aspect of the present invention, this difficulty is overcome by providing a dielectric layer stack of at least two silicon dioxide layers and at least two silicon nitride layers in the trench structure of the silicon substrate, with the silicon dioxide layers and the silicon nitride layers arranged alternately up and down, and a higher capacitance density can be achieved with a trench capacitor compared to a planar capacitor. At the same time, in particular, the coating of the trench structure, for example in relation to a uniform layer thickness and substrate bending, has to withstand different problems than the coating of a flat surface, so it must be considered that the manufacturing mechanism for planar capacitors cannot simply be applied to trench capacitors. In this context, the inventors recognized that by alternately forming silicon dioxide layers and silicon nitride layers in the trench structure, not only can the substrate bending be controlled during the formation of the layer stack, but it is also possible to increase the hole depth and thus the surface expansion of the capacitor. In particular, it has been found that the layer stack formed in the trench structure must comprise at least two silicon dioxide layers and at least two silicon nitride layers in order to keep the substrate bending as low as possible with a large hole depth. Furthermore, in connection with the trench structure, it has been observed that the silicon dioxide layer can be formed particularly advantageously on the silicon nitride layer when the polycrystalline silicon layer is deposited and oxidized, i.e., with high quality such as a uniform structure, a uniform layer thickness and / or a low defect pattern. Thereby, a trench capacitor structure having a dielectric layer stack with a high dielectric breakdown strength can be obtained.

[0004] Accordingly, one embodiment relates to a method for manufacturing a trench capacitor structure. The method includes providing a silicon substrate with a trench structure, the trench structure comprising a plurality of recesses in a main surface of the silicon substrate. Further, the method includes forming a first silicon dioxide layer in the recesses of the silicon substrate, depositing a first silicon nitride layer on the first silicon dioxide layer, depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer to deposit a second silicon dioxide layer on the first silicon nitride layer, and depositing a second silicon nitride layer on the second silicon dioxide layer. The first silicon dioxide layer is formed at least in the recesses of the silicon substrate. Optionally, the first silicon dioxide layer may be further formed on at least a part of the main surface of the silicon substrate or on the entire main surface of the silicon substrate. The first silicon dioxide layer is further formed, for example, on a portion of the main surface of the silicon substrate connecting the recesses. Thus, at least in the recesses of the silicon substrate, optionally further on the main surface of the silicon substrate, (ON) x A stack (x≥2) is formed, where the silicon dioxide layer is denoted by O and the silicon nitride layer is denoted by N. The index x indicates how many ON layer pairs are arranged on top of each other.

[0005] According to one embodiment, an oxynitride layer is formed between the first silicon nitride layer and the second silicon dioxide layer during the oxidation of the polycrystalline silicon layer. This results in a clean interface between the silicon nitride layer and the silicon dioxide layer. The formation of the oxynitride layer reduces possible defects between the silicon nitride layer and the silicon dioxide layer and improves the dielectric breakdown strength.

[0006] According to one embodiment, during the oxidation of the polycrystalline silicon layer, the polycrystalline silicon layer is completely converted into a second silicon dioxide layer. The inventors have found that even if only a thin polycrystalline silicon layer remains, an unpredictable electrical process may occur in the trench capacitor structure, achieving only a low breakdown strength. This is based on the finding that the polycrystalline silicon layer is a semiconductor layer. However, a stack of alternately arranged silicon dioxide layers and silicon nitride layers functions as a dielectric in the trench capacitor structure, so even a thin semiconductor layer between the layers with an insulating material reduces the breakdown strength of the layer stack.

[0007] Optionally, after the polycrystalline silicon layer is completely converted into the second silicon dioxide layer, oxidation is continued to partially oxidize the first silicon nitride layer to form an oxynitride layer between the first silicon nitride layer and the second silicon dioxide layer. As a result, a clean interface between the silicon nitride layer and the silicon dioxide layer and a high electrical breakdown strength are achieved. The oxidation is continued, for example, over a period of at least 5 minutes, 20 minutes or 1 hour. The period is, for example, in the range of 5 minutes to 5 hours, 20 minutes to 5 hours or 1 hour to 5 hours, preferably in the range of 5 minutes to 1 hour. In a preferred embodiment, the oxidation is continued for about 20 minutes or about 1 hour.

[0008] According to one embodiment, the polycrystalline silicon layer is not doped. This is based on the finding that, as a result, a high-quality silicon dioxide layer can be formed within the trench capacitor structure. The inventors have found, in particular, that as a result, a very pure silicon dioxide layer with low leakage current can be realized. This improves the electrical characteristics of the trench capacitor structure.

[0009] According to one embodiment, the polycrystalline silicon layer is deposited on the first silicon nitride layer by low-pressure vapor deposition, that is, using the LPCVD method. Directly depositing a silicon oxide layer on the silicon nitride layer by the LPCVD method results in an interface with many defects and a low dielectric breakdown strength, but it has been recognized that LPCVD deposition of polycrystalline silicon and subsequent oxidation of the polycrystalline silicon result in a clean interface and a high dielectric breakdown strength.

[0010] According to one embodiment, the first silicon dioxide layer, the first silicon nitride layer, the second silicon dioxide layer and / or the second silicon nitride layer are deposited with respective layer thicknesses in the range of 100 nm to 1000 nm or 330 nm to 530 nm. The individual layers can have different layer thicknesses. It has been further found that a series of several thin silicon dioxide layers and silicon nitride layers achieve lower substrate bending and higher dielectric breakdown strength than a series of not-so-thick silicon dioxide layers and silicon nitride layers.

[0011] According to one embodiment, the first silicon dioxide layer is formed in the recess of the silicon substrate by thermal growth, the first silicon nitride layer is deposited on the first silicon dioxide layer by low-pressure vapor deposition, that is, the LPCVD method, and the second silicon nitride layer is deposited on the second silicon dioxide layer by low-pressure vapor deposition, that is, the LPCVD method.

[0012] According to one embodiment, the silicon nitride layer forms a layer pair with the silicon dioxide layer, and the silicon nitride layer is disposed, for example, on the silicon dioxide layer when viewed from the silicon substrate in the stacking direction. In other words, the silicon dioxide layer and the silicon nitride layer on the silicon dioxide layer can be referred to as a layer pair. The layer pair may also be referred to herein as a layer stack unit. The first silicon dioxide layer and the first silicon nitride layer form, for example, the first layer pair, and the second silicon dioxide layer and the second silicon nitride layer form, for example, the second layer pair. At least one additional layer pair including a silicon dioxide layer and a silicon nitride layer, i.e., can be deposited on the second layer pair when viewed from the silicon substrate in the stacking direction. In this case, for example, the silicon dioxide layer of each additional layer pair is deposited on the silicon nitride layer of the layer pair preceding each. The deposition of the layer pair including the silicon dioxide layer and the silicon nitride layer is repeated several times. Thus, at least in the recess of the silicon substrate, optionally further on the main surface of the silicon substrate, (ON) x A stack is formed (x≥3), the silicon dioxide layer is indicated by O, and the silicon nitride layer is indicated by N. At least one additional layer pair is deposited, for example, on the second layer pair so that a layer structure in which the silicon dioxide layer and the silicon nitride layer are alternately arranged is formed. Starting from the second layer pair, the silicon dioxide layer of each layer pair is deposited by depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer. The inventors have recognized that an overall dielectric stack layer that is thicker, i.e., in which more silicon dioxide layers and silicon nitride layers are alternately arranged vertically, can achieve or even increase the integration density. By alternately stacking the silicon dioxide layer and the silicon nitride layer vertically, substrate bending can be kept low, and at the same time, it has been found that a layer stack having a large overall thickness of, for example, at least 1600 nm, 2000 nm or 3000 nm can be realized in the recess of the silicon substrate. As a result, a layer stack having a high breakdown strength of, for example, at least 1200 V, 1400 V or 1500 V is achieved. Further, it is particularly advantageous if an oxynitride layer is formed between each individual layer pair.

[0013] According to one embodiment, the polycrystalline silicon layer described herein is oxidized by dry chemical oxidation or wet chemical oxidation. In other words, the silicon dioxide layer described herein is thermally grown. Dry chemical or wet chemical oxidation may also be referred to herein as dry chemical or wet chemical re-oxidation or up-oxidation. Wet chemical oxidation may also be referred to herein as wet chemical oxidation. The inventors have recognized that the formation of a silicon dioxide layer by dry chemical or wet chemical oxidation of polycrystalline silicon results in a cleaner interface and higher dielectric breakdown strength than when the silicon dioxide layer is directly deposited by LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition). As a result, a high-quality silicon dioxide layer is produced, improving the electrical characteristics of the trench capacitor structure. Wet chemical oxidation has the advantage of being able to form the silicon dioxide layer more quickly than dry chemical oxidation, and dry chemical oxidation has the advantage over wet chemical oxidation of being able to achieve a higher dielectric breakdown strength for the layer stack formed within the recesses of the silicon substrate.

[0014] According to one embodiment, an RC snubber element is formed or manufactured by the method described herein.

[0015] A further embodiment relates to a trench capacitor comprising a dielectric layer structure comprising a first silicon dioxide layer, a first silicon nitride layer, a second silicon dioxide layer, and a second silicon nitride layer. The trench capacitor includes, for example, a silicon substrate with a trench structure having a plurality of recesses on a main surface of the silicon substrate. The dielectric layer structure is disposed, for example, in the recesses of the silicon substrate. The first silicon dioxide layer, the first silicon nitride layer, the second silicon dioxide layer, and the second silicon nitride layer are arranged in this order. The layers can be directly adjacent to each other. Optionally, an oxynitride layer is disposed between the first silicon nitride layer and the second silicon dioxide layer, and the oxynitride layer can also be regarded as part of the first silicon nitride layer. The second silicon dioxide layer can be an oxidized polycrystalline silicon layer.

[0016] The trench capacitor is based on the same considerations as the method described above. The trench capacitor can be complemented with all the features and functions described for this method. Also, at least a part of the trench capacitor can be manufactured by the method described in this specification.

Brief Description of the Drawings

[0017] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

Figure 1a

Figure 1b

Figure 2

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Figure 7

Embodiments for Carrying Out the Invention

[0018] Detailed Description of Embodiments Related to the Drawings Before the embodiments of the present invention are described in more detail below with reference to the drawings, it should be noted that the same, functionally identical, or equal elements, objects, and / or structures are assigned the same or similar reference numerals in different drawings, and thus, the descriptions of these elements shown in different embodiments are interchangeable or compatible. To facilitate the description of various embodiments, some of the figures include a Cartesian coordinate system x, y, z, where the x-y plane corresponds to the first main surface region of the substrate (= reference plane = x-y plane), i.e., is parallel to the first main surface region, the direction perpendicular upward with respect to the reference plane (x-y plane) corresponds to the “+z” direction, and the direction perpendicular downward with respect to the reference plane (x-y plane) corresponds to the “-z” direction. In the following description, the term “lateral direction” means a direction parallel to the x direction and / or the y direction, i.e., a direction parallel to the x-y plane, and the term “perpendicular” means a direction parallel to the z direction.

[0019] FIG. 1a and FIG. 1b show a trench capacitor structure 200 or a method 100 for manufacturing a trench capacitor. Method 100 includes a step 110 of preparing a silicon (Si) substrate 210 with a trench structure. The trench structure includes a plurality of recesses 212 on the main surface 214 of the silicon substrate 210. The silicon substrate 210 can be, for example, a silicon wafer. In method 100, for example, a pre-manufactured silicon substrate 210 with an already integrated trench structure can be used. Alternatively, step 110 of preparing a silicon substrate 210 with a trench structure can include forming a trench structure on the main surface 214 of the silicon substrate 210. The trench structure is formed, for example, by patterning the silicon substrate. Forming a trench structure on the main surface 214 of the silicon substrate 210 can include one or more lithography steps and one or more etching steps.

[0020] A further step of method 100 relates to forming a first silicon dioxide (Si) layer 2201 at least within the recesses 212 of the silicon substrate 210 (step 120). In FIG. 1b, the first silicon dioxide layer 2201 is also formed, illustratively, on the main surface 214 of the silicon substrate 210. The first silicon dioxide layer 2201 is formed, illustratively, by thermal growth or thermal oxidation. For this purpose, for example, the silicon substrate 210 is oxidized dry-chemically or wet-chemically, in which case dry-chemical oxidation is preferred. For example, the surfaces within the plurality of recesses 212 and optionally the main surface 214 or a part of the main surface 214 are oxidized to form the first silicon dioxide layer 2201. The first silicon dioxide layer 2201 contains, for example, a SiO2 material or a thermal oxide. The thickness of the first silicon dioxide layer 2201 is in the range of, for example, 100 nm to 1000 nm, preferably in the range of 100 nm to 450 nm, for example 330 nm.

[0021] The first silicon nitride layer 2301 is deposited on the first silicon dioxide layer 2201 (step 130). The first silicon nitride layer 2301 is deposited, for example, by low-pressure vapor deposition, that is, using the LPCVD method. The first silicon nitride layer 2301 contains, for example, a Si3N4 material. The thickness of the first silicon nitride layer 2301 is within the range of, for example, 100 nm to 1000 nm, preferably within the range of 100 nm to 550 nm, for example 460 nm, etc. The second silicon dioxide layer 2202 is deposited on the first silicon nitride layer 2301 (step 140). Here, a polycrystalline silicon layer 222, that is, polysilicon, is deposited on the first silicon nitride layer 2301 (step 142) and oxidized (step 144). The polycrystalline silicon layer 222 is not doped, for example. The polycrystalline silicon layer 222 is deposited, for example, by low-pressure vapor deposition, that is, using the LPCVD method. The oxidation 144 of the polycrystalline silicon layer 222 is performed, for example, dry-chemically or wet-chemically, in which case dry-chemical oxidation is preferred. The thickness of the second silicon dioxide layer 2202 is in the range of, for example, 100 nm to 1000 nm, preferably in the range of 100 nm to 450 nm, for example 330 nm.

[0022] Method 100 further includes step 150 of depositing a second silicon nitride layer 2302 on the second silicon dioxide layer 2202. The second silicon nitride layer 2302 is deposited, for example, by low-pressure vapor deposition, i.e., using the LPCVD method. The second silicon nitride layer 2302 includes, for example, a Si3N4 material. The thickness of the second silicon nitride layer 2302 is, for example, within the range of 100 nm to 1000 nm, preferably within the range of 100 nm to 550 nm, such as 530 nm.

[0023] Therefore, referring to the trench capacitor structure 200, a dielectric layer structure 240 is formed or provided in the trench capacitor. The dielectric layer structure 240 includes a first silicon dioxide layer 2201, a first silicon nitride layer 2301, a second silicon dioxide layer 2202, and a second silicon nitride layer 2302. Optionally, the dielectric layer structure 240 can include additional silicon dioxide and silicon nitride layers. For this, refer to, for example, FIGS. 3 and 4. The dielectric layer structure 240 is disposed, for example, on the surfaces of at least a plurality of recesses 212, such as within the plurality of recesses 212. Optionally, the dielectric layer structure 240 is further disposed on the main surface 214 of the silicon substrate 210 or a part of the main surface 214 of the silicon substrate 210.

[0024] The first silicon dioxide layer 2201, the first silicon nitride layer 2301, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 are disposed adjacent to each other in this order, for example. The dielectric layer structure 240 can also be considered as a layer stack having a dielectric layer. For this, refer to layers 2201, 2202, 2301, and 2302. The first silicon dioxide layer 2201 is disposed directly on the substrate 210 of the trench capacitor, and the first silicon nitride layer 2301, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 are disposed on the first silicon dioxide layer 2201 in this order, for example. The order of the dielectric layers of the dielectric layer structure 240 is indicated, for example, in the stacking direction from the silicon substrate 210. Optionally, method 100 can include additional steps as described in connection with FIG. 2. Similarly, the trench capacitor structure 200 can include additional layers as described, for example, in connection with FIG. 2. The first silicon nitride layer 2301 can include, for example, an oxynitride layer 232 described in connection with FIG. 2. The oxynitride layer 232 of the first silicon nitride layer 2301 is disposed, for example, at the interface between the first silicon nitride layer 2301 and the second silicon dioxide layer 2202.

[0025] FIG. 2 illustratively shows method 100 with respect to a cross-section of a trench capacitor structure 200 formed by the above method. In other words, one of the plurality of recesses of the trench structure in the silicon substrate 210, recess 212, and the layers deposited therein are schematically shown in detail. That is, FIG. 2 shows the method steps in detail with respect to one of the plurality of recesses of the trench structure. Even if FIG. 2 shows the method steps only with respect to one of the plurality of recesses, recess 212, it is clear that the method steps can also be applied to the remaining recesses of the plurality of recesses.

[0026] The method 100 in FIG. 2, similar to the method 100 in FIGS. 1a and 1b, includes a step 110 of providing a silicon substrate 210, a step 120 of forming a first silicon dioxide layer 2201 in a recess 212 of the silicon substrate 210, a step 130 of depositing a first silicon nitride layer 2301 on the first silicon dioxide layer 2201, a step 140 of depositing a second silicon dioxide layer 2202 on the first silicon nitride layer 2301, and a step 150 of depositing a second silicon nitride layer 2302 on the second silicon dioxide layer 2202.

[0027] As described in connection with FIGS. 1a and 1b, step 140 of depositing a second silicon dioxide layer 2202 on a first silicon nitride layer 2301 includes step 142 of depositing a polycrystalline silicon layer 222 and step 144 of oxidizing the polycrystalline silicon layer 222. The oxidizing step 144 can be performed, for example, dry chemically or wet chemically. During the oxidizing step 144 of the polycrystalline silicon layer 222, an oxynitride layer 232 is optionally formed between the first silicon nitride layer 2301 and the second silicon dioxide layer 2202 or in the first silicon nitride layer 2301 at the interface between the first silicon nitride layer 2301 and the second silicon dioxide layer 2202. The polycrystalline silicon layer 222 is, for example, completely converted to the second silicon dioxide layer 2202, i.e., completely oxidized, and optionally, thereafter, the first silicon nitride layer 2301 is partially oxidized to form the oxynitride layer 232 in the first silicon nitride layer 2301 or at the interface between the first silicon nitride layer 2301 and the second silicon dioxide layer 2202, and the oxidizing step 144 is continued. The nitride surface of the first silicon nitride layer 2301 is oxidized, for example, to a depth of several nm by continuing the oxidizing step 144 longer than required for complete consumption of the polycrystalline silicon. This step is optional and is particularly intended to optimize the interface between the oxide and the nitride / make the interface between the oxide and the nitride less defective. The first silicon nitride layer 2301 functions, for example, as an oxidation stop. The oxidation period of the oxidizing step 144 is, for example, in the range of 5 hours to 72 hours, 5 hours to 48 hours or 5 hours to 32 hours, for example, 9, 75 hours or 10 hours. The oxidizing step 144 is performed, for example, for at least 5 hours, 9 hours or 24 hours depending on the thickness of the second silicon dioxide layer 2202 to be formed so that the polycrystalline silicon layer 222 is completely converted to the second silicon dioxide layer 2202 and the oxynitride layer 232 is formed. The thicker the second silicon dioxide layer 2202 to be formed or the polycrystalline silicon layer 222 to be oxidized, the longer the oxidizing step 144 should be performed.

[0028] The oxynitride layer 232 contains, for example, a thermal oxide. The thickness of the oxynitride layer 232 is, for example, in the range of 1 nm to 12 nm or 1 nm to 11 nm. The maximum thickness of the oxynitride layer 232 is preferably 11 nm. The first silicon dioxide layer 2201, the first silicon nitride layer 2301, the oxynitride layer 232, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 form, for example, a dielectric layer structure 240.

[0029] Optionally, a layer 250 with a doped polysilicon material can be deposited on the second silicon nitride layer 2302 (step 160). The layer 250 with a doped polysilicon material is deposited, for example, such that at least the recesses 212 where the silicon dioxide and silicon nitride layers are disposed are filled with the doped polysilicon material (step 160). The layer 250 with a doped polysilicon material completes, for example, the plurality of recesses 212. The layer 250 with a doped polysilicon material can be further deposited on the surface of the second silicon nitride layer 2302 facing away from the main surface of the silicon substrate 210 (the side opposite to the main surface of the silicon substrate 210) (step 160). The layer 250 with a doped polysilicon material is deposited, for example, such that a surface parallel to the main surface 214 of the silicon substrate 210 faces away from the dielectric layer structure 240 (the side opposite to the dielectric layer structure 240) (step 160). The layer 250 with a doped polysilicon material is deposited, for example, by low-pressure vapor deposition, that is, using the LPCVD method. The doped polysilicon material is, for example, an in situ doped polycrystalline silicon material. The layer 250 with a doped polysilicon material forms, for example, an electrode such as a front electrode of the RC snubber element (device) 300.

[0030] Optionally, further, an aluminum layer (see 2601 and 2602) can be deposited respectively on the layer 250 with the doped polysilicon material and on the side of the silicon substrate 210 facing away from the dielectric layer structure 240 (the side opposite to the dielectric layer structure 240) (step 170). The aluminum layers 2601 and 2602 are, for example, the metallizations before and after the RC snubber element (device) 300.

[0031] The trench capacitor or RC snubber element 300 includes, for example, a silicon substrate 210 with a trench structure having a plurality of recesses 212, and a dielectric layer structure 240 at least within the recesses 212 of the silicon substrate 210. The first silicon dioxide layer 2201 of the dielectric layer structure 240 is, for example, directly disposed on the substrate 210 of the trench capacitor, and the first silicon nitride layer 2301 with the oxynitride layer 232, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 are, for example, disposed on the first silicon dioxide layer 2201 in this order. The order of the dielectric layers of the dielectric layer structure 240 is indicated, for example, in the stacking direction from the silicon substrate 210. Optionally, the trench capacitor includes a doped polycrystalline silicon layer (see layer 250) on the surface of the dielectric layer structure 240 facing away from the silicon substrate 210 (the side opposite to the silicon substrate 210). Further, the trench capacitor can, for example, include a first aluminum layer 2601 on the surface of the silicon substrate 210 opposite to the main surface 214, and can include a second aluminum layer 2602 on the surface of the doped polycrystalline silicon layer facing away from the main surface 214 (the side opposite to the main surface 214).

[0032] Figures 1a - 2 are (ON) at x = 2 xShows the snubber process. However, methods 100 or trench capacitor structures 200 for trench capacitors or RC snubber elements 300 having more ON layer pairs, i.e., silicon dioxide - silicon nitride layer pairs, are also possible. FIG. 3 exemplarily shows a trench capacitor structure 200 with x ≧ 5, and FIG. 4 exemplarily shows a trench capacitor structure 200 with x = 3. The silicon dioxide layers described herein may also be referred to as oxide layers or denoted by the letter O. The silicon nitride layers described herein may also be referred to as nitride layers or denoted by the letter N.

[0033] As shown in FIGS. 3 and 4, the dielectric layer structure 240 described herein can comprise three or more silicon dioxide - silicon nitride layer pairs, i.e., ON layer pairs 242, for which reference may be made, for example, to 242 in FIG. 3 1-5 and 242 in FIG. 4 1-3 The silicon dioxide layer 220 and the silicon nitride layer 230 together form the ON layer pair 242. When viewed in the stacking direction from the silicon substrate 210, i.e., in the direction of the dielectric layer structure 240, for example within the ON layer pair 242, each silicon nitride layer 230 is disposed on top of each silicon dioxide layer 220.

[0034] The ON layer pairs 242 are arranged one above the other in the stacking direction. Starting from the second layer pair 2422, each silicon dioxide layer 220 is disposed on top of the silicon nitride layer 230 of the respective preceding layer pair 242. The dielectric layer structure 240 comprises, for example, a layer stack in which silicon dioxide layers and silicon nitride layers are alternately arranged. Starting from the second layer pair 2422, each silicon dioxide layer 220 is deposited by depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer. Optionally, after each polycrystalline silicon layer has been completely converted into each silicon dioxide layer 220, the oxidation step can be continued to oxidize the nitride surface of each silicon nitride layer 2301 on which each silicon dioxide layer 220 is disposed to form each oxynitride layer 232.

[0035] In the dielectric layer structure 240 with the xON layer pair 242, as exemplarily shown in FIG. 4, the first silicon nitride layers 230 up to the (x - 1)-th silicon nitride layer 230 can each include an oxynitride layer 232, where x ≥ 3. The oxynitride layers are each disposed, for example, at the interface with the subsequent layer pair 242. That is, when a new layer pair 242 is formed on the preceding layer pair 242, the nitride surface of the silicon nitride layer 230 of the preceding layer pair is oxidized, for example, to a depth of several nm to form the oxynitride layer 232. In this case, the nitride surface is disposed facing the new layer pair 242.

[0036] According to one embodiment, the oxynitride layer 232 can alternatively be considered as an independent layer each disposed between two consecutive ON layer pairs 242. Optionally, the trench capacitor structure 200 shown in FIGS. 3 and 4 can further include the doped polycrystalline silicon layer 250 and / or the aluminum layers 1601 and 2602 described in connection with FIG. 2.

[0037] As in the German Patent No. 102019204503 described at the beginning of this application, instead of relying on stress-free nitride, silicon dioxide (thermally grown) and silicon nitride (deposited via LPCVD) (see German Patent Application Publication No. 102014223904) are repeatedly produced more than twice with layer thicknesses of 100 nm to 1000 nm each on the underlying dielectric layer (silicon dioxide under silicon nitride). Thus, opposite material voltages continue to be used to reduce or control wafer bending, and the breakdown voltage is significantly increased in the process. Due to the mechanical voltages acting on each other, the hole depth, and thus the expansion of the capacitor surface, can be increased. Even if the entire dielectric stack layer is thicker, the integration density can be obtained or even increased.

[0038] To maximize the quality of the silicon dioxide layer 220, the silicon dioxide layer is produced by thermal oxidation. Thus, the first silicon dioxide layer 2201 is thermally grown on the silicon substrate 210, and further silicon dioxide layers 2202 to 220x For (x≥3), each layer of undoped polycrystalline silicon (100 - 1000 nm) is deposited on x-1 x-1 (x≥3) and thermally fully dry - chemically oxidized or re - oxidized. After each polycrystalline silicon layer 222 is completely converted to silicon dioxide 220, the polycrystalline silicon layer is further oxidized for a certain period of time. As a result, the silicon nitride 230 is also somewhat oxidized, and a silicon oxynitride layer 232 is formed. This results in a clean interface between the silicon nitride layer 230 and the silicon dioxide layer 220. The silicon nitride here functions pseudo - as a "growth stopper" and is slightly oxidized due to the very low dry oxidation rate of the silicon nitride itself (R.L.Guldi et al., 1989 J.Electrochem.Soc. 136 3815, DOI 10.1149 / 1.2096555) and the partially thick silicon dioxide layer 220 (formerly polycrystalline silicon 222) on it, which slows down the diffusion of oxygen into the silicon nitride. Due to a certain compensation of the mechanical voltage caused by the opposite pressures of silicon nitride and silicon oxide, wafer bending is kept as low as possible, thereby increasing the hole depth and at the same time increasing the thickness of the entire dielectric stack, and thus the breakdown strength, so that the integration density can be further increased.

[0039] Using the materials and methods known heretofore, an increase in breakdown strength could be achieved only by increasing the total layer thickness. This, on the one hand, results in an increase in wafer bending and, on the other hand, results in a decrease in integration density. If one wants to increase the integration density, deeper holes have to be generated, which increases the wafer bending. As a solution, the mutual mechanical pressure of the dielectrics used herein, i.e., the silicon dioxide layer 220 and the silicon nitride layer 230, is used, i.e., by alternately arranging at least two silicon dioxide layers 220 and at least two silicon nitride layers 230 one above the other. In order to combine this with the best possible electrical properties, instead of the LPCVD or PECVD method, dry chemical oxidation or oxidation or up-oxidation or re-oxidation of polysilicon is used to form the silicon dioxide layer 220 to generate the layer stack.

[0040] By directly depositing a silicon dioxide layer on a silicon nitride layer, a basically similar stack can be generated, for example, by the LPCVD or PECVD method. However, when the LPCVD method or the PECVD method is used, the interface has more defects and the electrical breakdown strength is significantly lower (see FIG. 5). FIG. 5 shows a first characteristic curve 400 of a device having an equivalent oxide thickness of about 1175 nm, manufactured according to FIG. 2. The silicon dioxide layer of the device on which the characteristic curve 400 is based is deposited by dry chemical oxidation. Further, FIG. 5 shows a second characteristic curve 500 of an identically configured device, but the silicon dioxide layer is deposited by LPCVD deposition instead of dry chemical oxidation of the polysilicon layer.

[0041] In addition, polycrystalline silicon can be re-oxidized wet chemically rather than dry chemically, which also functions more rapidly from the perspective of process technology but also has a lower dielectric breakdown strength (see FIG. 6). FIG. 6 shows a first characteristic curve 400 of a device having an equivalent oxide thickness of approximately 1175 nm, manufactured according to FIG. 2. The silicon dioxide layer of the device on which the characteristic curve 400 is based is deposited by dry chemical oxidation. Further, FIG. 6 shows a second characteristic curve 600 in a device also manufactured according to FIG. 2, where the silicon dioxide layer (e.g., the silicon dioxide layer starting from at least the second silicon dioxide layer 2202) is deposited by wet chemical or wet chemical oxidation of the polysilicon layer rather than dry chemical oxidation of the polysilicon layer.

[0042] Furthermore, the device according to FIG. 2 has a higher dielectric breakdown strength compared to a device with a stress-free nitride layer, as known from the specification of German Patent No. 102019204503. FIG. 7 shows a first characteristic curve 400 of a device having an equivalent oxide thickness of approximately 1175 nm, manufactured according to FIG. 2. The silicon dioxide layer of the device on which the characteristic curve 400 is based is deposited by dry chemical oxidation. Further, FIG. 7 shows a second characteristic curve 700 for a device having a dielectric layer structure with 330 nm of SiO2, 550 nm of Si3N4, 500 nm of Si x N y and 500 nm of Si3N4 and having an equivalent oxide thickness of approximately 1085 nm.

[0043] In the method 100 described herein, devices having a voltage class of at least 1000 V, 1200 V, or even at least 1500 V, such as RC snubber elements, can be provided. For example, a device according to FIG. 2 having a total oxide thickness of 680 nm and a total nitride thickness of 1000 nm can achieve a dielectric breakdown voltage of 1500 V at 10 mA. Whether a Si-RC snubber device was manufactured by one of the methods 100 described herein can be found by FIB cross-section analysis (focused ion beam with SEM imaging). The behavior of the leakage current at the nominal voltage can indicate the quality of the oxide used, i.e., the silicon dioxide layer 220, where a rough distinction can be made between PECVD, wet chemically grown oxide and dry chemically grown oxide (leakage current decreases from PECVD to wet oxide to dry oxide). Further, TEM analysis can be used to examine the formation (deposition vs. growth) of the oxide layer used. A further possibility is to examine the etching rate differences of the generated oxide layers.

[0044] By the method described herein, a snubber device for overvoltage attenuation can be manufactured in a power module. Using a snubber device, for example, a silicon carbide transistor in a conventional power module can be switched more quickly without module-induced inductance that can potentially be harmful to all devices in the module, which brings high voltage peaks. Here, the capacitor absorbs energy (in a few cycles), and through an integrated resistor, this energy is converted to heat and dissipated. Possible application areas for such modules are, for example, vehicle electronics (in the charging module or power train of e-mobility) or renewable energy (such as wind turbines). Due to the possibility of faster switching, the overall efficiency of the power module can be increased because less power loss is generated.

[0045] Although several aspects have been described in relation to an apparatus, it is understood that these aspects also represent a description of corresponding methods, and thus, a block or device of the apparatus should also be understood as a corresponding method step or as a feature of a method step. Similarly, aspects described in relation to a method step or as a method step also represent a description of a corresponding block or detail or feature of a corresponding apparatus. Some or all of the method steps can be performed by (or using) a hardware device such as, for example, a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or a plurality of the most important method steps can be performed by such a device.

[0046] The foregoing embodiments represent merely illustrative examples of the principles of the present invention. It is to be understood that modifications and variations of the configurations and details described herein will be apparent to those skilled in the art. Accordingly, it is intended that the present invention be limited only by the following claims and not by the specific details presented herein based on the description of the specification text and the embodiments.

Claims

1. A method (100) for manufacturing a trench capacitor structure (200), comprising: A step (110) of providing a silicon substrate (210) with a trench structure, wherein the trench structure includes a plurality of recesses (212) on a main surface (214) of the silicon substrate (210); Forming a first silicon dioxide layer (220 １ ), in at least the recess (212) of the silicon substrate (210); The step of depositing the first silicon nitride layer (230 １ on the first silicon dioxide layer (220 １ ), step (130); Depositing a polycrystalline silicon layer (222) (142) and oxidizing the polycrystalline silicon layer (222) (144) to form a second silicon dioxide layer (220 １ on the first silicon nitride layer (230 ２ ), and a step (140) of depositing The step (150) of depositing a second silicon nitride layer (230 ２ on the second silicon dioxide layer (220 ２ ), and a method (100) including the same.

2. Before oxidizing (144) the polycrystalline silicon layer (222), an oxynitride layer (232) is formed between the first silicon nitride layer (230 １ ), and the second silicon dioxide layer (220 ２ ), the method (100) according to claim 1.

3. Before oxidizing (144) the polycrystalline silicon layer (222), the polycrystalline silicon layer (222) is completely converted into the second silicon dioxide layer (220 ２ ) in the method (100) according to claim 1.

4. After the polycrystalline silicon layer (222) is completely converted into the second silicon dioxide layer (220 ２ ), the first silicon nitride layer (230 １ ) is partially oxidized and oxidation (144) is continued to form a silicon oxynitride layer (232) between the first silicon nitride layer (230 １ ) and the second silicon dioxide layer (220 ２ ), the method (100) according to claim 3.

5. The method (100) according to any one of claims 1 to 4, wherein the polycrystalline silicon layer (222) is not doped.

6. The polycrystalline silicon layer (222) is deposited on the first silicon nitride layer (230 １ ) by low-pressure vapor deposition, the method (100) according to any one of claims 1 to 5.

7. The first silicon dioxide layer (220 １ ), the first silicon nitride layer (230 １ ), the second silicon dioxide layer (220 ２ ), and the second silicon nitride layer (230 ２ ) are deposited with respective layer thicknesses within the range of 100 nm to 1000 nm, the method (100) according to any one of claims 1 to 6.

8. The step (120) of forming the first silicon dioxide layer (220) at least within the recess (212) of the silicon substrate (210) is performed by thermal growth, １ and is executed by thermal growth, The step (130) of depositing the first silicon nitride layer (230 １ ) on the first silicon dioxide layer (220 １ ) is performed by low-pressure vapor deposition, The step (150) of depositing the second silicon nitride layer (230 ２ ) on the second silicon dioxide layer (220 ２ ) is performed by low-pressure vapor deposition, the method (100) according to any one of claims 1 to 7.

9. A silicon nitride layer (230) on a silicon dioxide layer (220) forms a layer pair (242); the first silicon dioxide layer (220 １ ) and the first silicon nitride layer (230 １ ) form a first layer pair (242 １ ), and the second silicon dioxide layer (220 ２ ) and the second silicon nitride layer (230 ２ ) form a second layer pair (242 ２ ), At least one additional layer pair (242) is deposited on said second layer pair (242 ２ ). starting from said second layer pair (242 ２ ), the method (100) according to any one of claims 1 to 8, wherein each of said silicon dioxide layers (220) is deposited by depositing (142) said polycrystalline silicon layer (222) and oxidizing (144) said polycrystalline silicon layer (222).

10. The at least one further layer pair (242) is deposited on the second layer pair (242 ２ ) such that a layer structure in which a silicon dioxide layer and a silicon nitride layer are alternately arranged is formed, the method (100) according to claim 9.

11. The method (100) according to any one of claims 1 to 10, wherein the oxidizing (144) of the polycrystalline silicon layer (222) is performed by dry chemical oxidation or wet chemical oxidation.

12. The method (100) according to any one of claims 1 to 11 for forming an RC snubber element (300).

13. The first silicon dioxide layer (220 １ ), the first silicon nitride layer (230 １ ), the second silicon dioxide layer (220 ２ ), and the second silicon nitride layer (230 ２ ), and includes a dielectric layer structure (240) including The first silicon dioxide layer (220 １ ), the first silicon nitride layer (230 １ ), the second silicon dioxide layer (220 ２ ), and the second silicon nitride layer (230 ２ ) are adjacent to each other in this order, a trench capacitor.

14. The layer thickness of the first silicon dioxide layer (220 １ ), the first silicon nitride layer (230 １ ), the second silicon dioxide layer (220 ２ ), and the second silicon nitride layer (230 ２ ) is within the range of 100 nm to 1000 nm. The trench capacitor according to claim 13.

15. The trench capacitor according to claim 13 or 14, wherein the trench capacitor is manufactured by the method (100) according to any one of claims 1 to 12.

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