Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a parasitic capacitance.SOLUTION: A transistor 10 includes: a first insulation layer 110; a semiconductor layer 120 on the first insulation layer; a source electrode layer 130 and a drain electrode layer 140 on the semiconductor layer; a second insulation layer 173 on the first insulation layer; a second insulation layer; a third insulation layer 175 on the source electrode layer and the drain electrode layer; a gate insulation layer 150 on the semiconductor layer; a gate electrode layer 160 on the gate insulation layer; and a fourth insulation layer 170 on the third insulation layer, the gate insulation layer, and the gate electrode layer. The second insulation layer includes a region contacted to the semiconductor layer, the source electrode layer, and the drain electrode layer on a side surface. An upper surface of the second insulation layer is on a flat surface that is similar to the source electrode layer and the drain electrode layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine , a manufacture, or a composition of matter. In particular , the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, and their driving methods, or their manufacturing methods. In particular, one aspect of the present invention relates to a semiconductor device or a method for manufacturing the same.

[0002] Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics . A transistor and a semiconductor circuit are an aspect of the semiconductor device. In addition, a storage device, a display device, and an electronic device may include a semiconductor device.

Background Art

[0003] Techniques for constructing a transistor using a semiconductor film formed on a substrate having an insulating surface have been attracting attention . Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices) . As a semiconductor thin film applicable to a transistor, silicon-based semiconductor materials are widely known, but oxide semiconductors are attracting attention as other materials .

[0004] For example, Patent Document 1 discloses a transistor using an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) as an active layer of the transistor .

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Special Publication No. 11-505377 Summary of the Invention [Problem to be solved by the invention]

[0006] As semiconductor elements become smaller, parasitic capacitance near transistors becomes a major problem.

[0007] In transistor operation, the area near the channel (for example, between the source electrode and the drain electrode) If parasitic capacitance is present, it takes time for the parasitic capacitance to charge, which slows down the transistor response. This reduces the performance and thus the response of the semiconductor device.

[0008] In addition, the various processes for forming transistors (especially film formation, processing, etc.) It is becoming increasingly difficult to control this, and variations in the manufacturing process can affect transistor characteristics, and even has a significant impact on reliability.

[0009] In addition, with the trend towards finer processing, the precision required for processing is becoming more stringent, and the difficulty of processing is increasing. It's coming soon.

[0010] Therefore, one aspect of the present invention has an object to reduce parasitic capacitance in the vicinity of a transistor. Another object is to provide a semiconductor device having good electrical characteristics. Another object of the present invention is to provide a highly reliable semiconductor device. One of the objectives of the present invention is to reduce the variation in characteristics of a semiconductor device or a semiconductor device caused by the manufacturing process. Another object is to stabilize the manufacturing process of a transistor. An object of the present invention is to provide a semiconductor device including an oxide semiconductor layer with few oxygen vacancies. To provide a semiconductor device that can be formed by a simple process. Or, one of the objects is to provide a semiconductor device having a configuration capable of reducing interface levels in the vicinity of an oxide semiconductor layer. Or, one of the objects is to provide a semiconductor device with low power consumption. Or, one of the objects is to provide a novel semiconductor device or the like. Or, one of the objects is to provide a method for manufacturing the above semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011]

[0012] The side surfaces of the oxide layer, source electrode layer, drain electrode layer, second insulating layer, and third insulating layer A semiconductor device characterized by having a region in contact therewith.

[0013] Another aspect of the present invention is to form a first insulating layer, form a first oxide film on the first insulating layer then form a semiconductor film on the first oxide film, form a first conductive film on the semiconductor film, and form a first mask on the first conductive film, and etch a part of the first conductive film using the first mask to form the first conductive layer in an island shape, and etch a part of the first oxide film and the semiconductor film using the first mask and the first conductive layer as a mask, thereby forming the first oxide layer and the semiconductor layer in an island shape, form a second insulating film on the first insulating layer and the first conductive layer, and perform chemical mechanical polishing on the second insulating film until the first conductive layer is exposed to form the second insulating layer, form a third insulating film on the first conductive layer and the second insulating layer, form a second mask on the third insulating film, and etch a part of the third insulating film using the second mask to form the source electrode layer, the drain electrode layer, and the third insulating layer, form a second oxide film on the third insulating layer and the semiconductor layer, form a fourth insulating film on the second oxide film, form a second conductive film on the fourth insulating film, and perform chemical mechanical polishing on the second conductive film, the fourth insulating film, and the second oxide film to form the second oxide layer, the gate insulating layer, and the gate electrode layer. A method for manufacturing a semiconductor device is characterized by this Also, perform a first heat treatment after forming the semiconductor film, form a fourth insulating layer containing oxygen on the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer. When forming the fourth insulating layer insulating layer, source electrode layer, drain electrode layer, and third insulating layer, and form a second oxide film on the third insulating layer and the semiconductor layer, form a fourth insulating film on the second oxide film, form a second conductive film on the fourth insulating film, and perform chemical mechanical polishing on the second conductive film, the fourth insulating film, and the second oxide film to form the second oxide layer, the gate insulating layer, and the gate electrode layer. A method for manufacturing a semiconductor device is characterized by this 4 insulating film, and second oxide film to form the second oxide layer, gate insulating layer, and gate electrode layer. A method for manufacturing a semiconductor device is characterized by this A method for manufacturing a semiconductor device, characterized by forming a second oxide layer, a gate insulating layer, and a gate electrode layer .

[0014] Also, perform a first heat treatment after forming the semiconductor film, and form a fourth insulating layer containing oxygen on the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer. When forming the fourth insulating layer Form a mixed layer of the third insulating layer and the fourth insulating layer, and at the same time, add oxygen to the mixed layer or the first insulating layer It is preferable to perform a second heat treatment to diffuse oxygen into the semiconductor layer .

[0015] In addition, the third insulating film is an insulating film containing oxygen, and the fourth insulating layer is preferably formed by a sputtering method using oxygen gas .

[0016] In addition, the third insulating film is a silicon oxide film, and the fourth insulating layer is preferably formed by a sputtering method using 50% by volume or more of oxygen gas and using an aluminum oxide target .

[0017] In addition, it is preferable to perform the second heat treatment at 300°C or higher and 450°C or lower

[0018] Another aspect of the present invention is to form a first insulating layer, form a first oxide film on the first insulating layer , form a semiconductor film on the first oxide film, form a first conductive film on the semiconductor film, form a second insulating film on the first conductive film, form a first mask on the second insulating film, use the first mask to etch a part of the second insulating film and the first conductive film, form a first conductive layer and a second insulating layer, form a second mask on the second insulating layer and the semiconductor film, use the second mask to etch a part of the second insulating layer, the first conductive layer, the first oxide film, and the semiconductor film to form a first oxide layer, a semiconductor layer, a source electrode layer, a drain electrode layer, and a third insulating layer, form a second oxide film on the first insulating layer, the third insulating layer, and the semiconductor layer , form a third insulating film on the second oxide film, and form the third insulating film ​Form a second conductive film thereon, form a third mask on the second conductive film, and use the third mask to etch a part of the second oxide film, the third insulating film, and the second conductive film to form a second oxide layer, a gate insulating layer, and a gate electrode layer, which is a characteristic of a semiconductor device manufacturing method.

[0019] Also, perform a first heat treatment after forming the semiconductor film, form a fourth insulating layer having oxygen on the first insulating layer, the third insulating layer, and the gate electrode layer, and when forming the fourth insulating layer, have a first mixed layer between the first insulating layer and the fourth insulating layer, and a second mixed layer between the third insulating layer and the fourth insulating layer, and at the same time, add oxygen to the first mixed layer, the second mixed layer, the first insulating layer, or the second insulating layer, perform a second heat treatment, and preferably diffuse oxygen into the semiconductor layer.

[0020] Also, the first insulating film and the second insulating film are insulating films having oxygen, and the fourth insulating layer is preferably formed by a sputtering method using oxygen gas.

[0021] Also, the first insulating film and the second insulating film are silicon oxide films, and the fourth insulating layer is preferably formed by a sputtering method using 50% by volume or more of oxygen gas and using an aluminum oxide target.

[0022] Also, it is preferable to perform the second heat treatment at 300°C or higher and 450°C or lower.

[0023] Another aspect of the present invention is to form a first insulating layer, form a first oxide film on the first insulating layer form a semiconductor film on the first oxide film, form a first conductive film on the semiconductor film, and the first ​​​​Form a second insulating film on the conductive film, form a third insulating film on the second insulating film, and form a first mask on the third insulating film. Using the first mask, etch a part of the third insulating film, the second insulating film, the first conductive film, the semiconductor film, and the first oxide film. As a result, form the first oxide layer, the semiconductor layer, the second insulating layer, and the third insulating layer in an island shape. Form a fourth insulating film on the first insulating layer and the third insulating layer, and perform a chemical mechanical polishing process on the fourth insulating film until the third insulating layer is exposed to form the fourth insulating layer. Form a second mask on the fourth insulating layer and the third insulating layer, and use the second mask to form the source electrode layer, the drain electrode layer, the fifth insulating layer, and the sixth insulating layer. Form a second oxide film on the fourth insulating layer, the sixth insulating layer, and the semiconductor layer, form a fifth insulating film on the second oxide film, and form a second conductive film on the fifth insulating film. Perform a chemical mechanical polishing process on the second conductive film, the fifth insulating film, and the second oxide film to form the second oxide layer, the gate insulating layer, and the gate electrode layer. A method for manufacturing a semiconductor device is characterized by the above steps. Also, perform a first heat treatment after forming the semiconductor film. When forming the third insulating film, form a mixed layer between the second insulating film and the third insulating film, and at the same time add oxygen to the mixed layer or the second insulating film. Form a seventh insulating layer on the fourth insulating layer, the sixth insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer. When forming the seventh insulating layer, form a mixed layer between the fourth insulating layer and the seventh insulating layer, and at the same time add oxygen to the mixed layer or the fourth insulating layer. Perform a second heat treatment to diffuse oxygen into the semiconductor layer, which is preferable.

[0024]

[0025]

[0025]

[0025]

[0025] In addition, the second insulating film and the fourth insulating film are insulating films containing oxygen, and are the same as the third insulating film The seventh insulating layer is preferably formed by a sputtering method using oxygen gas.

[0026] In addition, the second insulating film and the fourth insulating film are silicon oxide films, and are the same as the third insulating film The seventh insulating layer is preferably formed by a sputtering method using 50% by volume or more of oxygen gas and using an aluminum oxide target. It is preferably formed by a sputtering method using an aluminum oxide target.

[0027] In addition, it is preferable to perform the second heat treatment at 300°C or higher and 450°C or lower.

[0028] In addition, a configuration using a semiconductor device, a microphone, a speaker, and a housing can be adopted.

Advantages of the Invention

[0029] By using one aspect of the present invention, the parasitic capacitance in the vicinity of the transistor can be reduced . Alternatively, a semiconductor device with good electrical characteristics can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, variations in characteristics caused by the manufacturing process of the transistor or semiconductor device can be reduced. Alternatively, the manufacturing process of the transistor can be stabilized. Alternatively, a semiconductor device having an oxide semiconductor layer with less oxygen deficiency can be provided. Alternatively, a semiconductor device that can be formed by a simple process can be provided. Alternatively, a semiconductor device having a configuration capable of reducing the interface states in the vicinity of the oxide semiconductor layer can be provided. Alternatively, a low-power consumption semiconductor device can be provided . Alternatively, a novel semiconductor device or the like can be provided. Alternatively, a method for manufacturing the above semiconductor device can be provided. . Alternatively, a semiconductor device having a configuration capable of reducing the interface states in the vicinity of the oxide semiconductor layer can be provided. Alternatively, a low-power consumption semiconductor device can be provided . Alternatively, a novel semiconductor device or the like can be provided. Alternatively, a method for manufacturing the above semiconductor device can be provided. . Alternatively, a method for manufacturing the above semiconductor device can be provided.

[0030] Note that the description of these effects does not preclude the existence of other effects. In one aspect of the present invention, it is not necessarily required to have all of these effects. Other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0031]

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Embodiments for Carrying Out the Invention

[0032] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0033] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0034] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0035] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, and X and Y are connected without an element (e.g., switch, transistor, capacitor element, inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables an electrical connection between them. This is the case where X and Y are connected.

[0036] As an example of the case where X and Y are electrically connected, an element (e.g., switch, transistor, capacitor element, inductor, resistor, diode, display element, light-emitting element, load, etc.) that enables an electrical connection between X and Y can be connected between X and Y in one or more numbers. Note that the switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or the switch has a function of selecting and switching the path through which the current flows. Note that when X and Y are electrically connected, it includes the case where X and Y are directly connected.

[0037] As an example of the case where X and Y are functionally connected, a circuit (e.g., logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, buck circuit, etc.), level shifter circuit that changes the potential level of a signal, etc.), voltage source, current source, switching circuit, amplification circuit (circuit that can increase the signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) can be connected between X and Y in one or more numbers. That is, for example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y shall be regarded as being functionally connected. Note that when X and Y are functionally connected, it shall include the case where X and Y are directly connected and the case where X and Y are electrically connected.

[0038] Note that when it is explicitly described that X and Y are electrically connected, the case where X and Y are electrically connected (that is, the case where another element or another circuit is interposed between X and Y), the case where X and Y are functionally connected (that is, the case where another circuit is interposed between X and Y and they are functionally connected), and the case where X and Y are directly connected (that is, the case where they are connected without interposing another element or another circuit between X and Y) shall be disclosed in this specification and the like. That is, when it is explicitly described that they are electrically connected, it shall be the same as the case where it is only explicitly described that they are connected, and the same content shall be

[0039] disclosed in this specification and the like. Note that, for example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X with or without passing through Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y with or without passing through Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows.

[0040] For example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and they are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." By using the same expression methods as these examples to define the connection order in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Or, as another expression method, for example, "The source (or the first terminal, etc.) of the transistor is electrically connected to X via at least the first connection path, and the first connection path does not have a second connection path, and the second connection path is the path between the source (or the first terminal, etc.) of the transistor and the drain

[0041] (or the second terminal, etc.) of the transistor." and the second connection path is the path between the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor and does not pass through the first connection path. (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor." , the first connection path is the path through Z1, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y through at least the third connection path, and the third connection path does not have the second connection path, and the third connection path is the path through Z2 . It can be expressed as. Or, "The source of the transistor (or the first terminal, etc.) is electrically connected to X through Z1 by at least the first connection path, and the first connection path does not have the second connection path, and the second connection path has a connection path through the transistor, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y through Z2 by at least the third connection path, and the third connection path does not have the second connection path." It can be expressed as. Also . "The source of the transistor (or the first terminal, etc.) is electrically connected to X through Z1 by at least the first electrical path, and the first electrical path does not have the second electrical path, and the second electrical path is an electrical path from the source of the transistor (or the first terminal, etc.) to the drain of the transistor (or the second terminal, etc.), and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y through Z2 by at least the third electrical path, and the third electrical path does not have the fourth electrical path, and the fourth electrical path is an electrical path from the drain of the transistor (or the second terminal, etc.) to the source of the transistor (or the first terminal, etc.)." It can be expressed as . By using an expression method similar to these examples to define the connection paths in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be connected to X and Y respectively through Z1 and Z2, and the connection paths between them can be clearly defined. This helps to accurately describe the electrical connection relationship in the circuit, which is very important for understanding and analyzing the circuit performance. In addition, when designing or debugging a circuit, a clear understanding of these connection paths can help to quickly locate and solve problems. For example, if there is a problem with the electrical connection between the source and the drain of the transistor, it can be determined whether the problem lies in the first, second, or third connection path according to the defined connection relationship. This provides a basis for circuit design and maintenance. the second terminal, etc.) of the transistor can be connected to X and Y respectively through Z1 and Z2, and the connection paths between them can be clearly defined. This helps to accurately describe the electrical connection relationship in the circuit, which is very important for understanding and analyzing the circuit performance. In addition, when designing or debugging a circuit, a clear understanding of these connection paths can help to quickly locate and solve problems. For example, if there is a problem with the electrical connection between the source and the drain of the transistor, it can be determined whether the problem lies in the first, second, or third connection path according to the defined connection relationship. This provides a basis for circuit design and maintenance. the second terminal, etc.) of the transistor can be connected to X and Y respectively through Z1 and Z2, and the connection paths between them can be clearly defined. This helps to accurately describe the electrical connection relationship in the circuit, which is very important for understanding and analyzing the circuit performance. In addition, when designing or debugging a circuit, a clear understanding of these connection paths can help to quickly locate and solve problems. For example, if there is a problem with the electrical connection between the source and the drain of the transistor, it can be determined whether the problem lies in the first, second, or third connection path according to the defined connection relationship. This provides a basis for circuit design and maintenance. the second terminal, etc.) of the transistor can be connected to X and Y respectively through Z1 and Z2, and the connection paths between them can be clearly defined. This helps to accurately describe the electrical connection relationship in the circuit, which is very important for understanding and analyzing the circuit performance. In addition, when designing or debugging a circuit, a clear understanding of these connection paths can help to quickly locate and solve problems. For example, if there is a problem with the electrical connection between the source and the drain of the transistor, it can be determined whether the problem lies in the first, second, or third connection path according to the defined connection relationship. This provides a basis for circuit design and maintenance. the second terminal, etc.) of the transistor can be connected to X and Y respectively through Z1 and Z2, and the connection paths between them can be clearly defined. This helps to accurately describe the electrical connection relationship in the circuit, which is very important for understanding and analyzing the circuit performance. In addition, when designing or debugging a circuit, a clear understanding of these connection paths can help to quickly locate and solve problems. For example, if there is a problem with the electrical connection between the source and the drain of the transistor, it can be determined whether the problem lies in the first, second, or third connection path according to the defined connection relationship. This provides a basis for circuit design and maintenance. the second terminal, etc.) of the transistor can be connected to X and Y respectively through Z1 and Z2, and the connection paths between them can be clearly defined. This helps to accurately describe the electrical connection relationship in the circuit, which is very important for understanding and analyzing the circuit performance. In addition, when designing or debugging a circuit, a clear understanding of these connection paths can help to quickly locate and solve problems. For example, if there is a problem with the electrical connection between the source and the drain of the transistor, it can be determined whether the problem lies in the first, second, or third connection path according to the defined connection relationship. This provides a basis for circuit design and maintenance. the second terminal, etc.) of the transistor can be connected to X and Y respectively through Z1 and Z2, and the connection paths between them can be clearly defined. This helps to accurately describe the electrical connection relationship in the circuit, which is very important for understanding and analyzing the circuit performance. In addition, when designing or debugging a circuit, a clear understanding of these connection paths can help to quickly locate and solve problems. For example, if there is a problem with the electrical connection between the source and the drain of the transistor, it can be determined whether the problem lies in the first, second, or third connection path according to the defined connection relationship. This provides a basis for circuit design and maintenance. the second terminal, etc.) of the transistor can be connected to X and Y respectively through Z1 and Z2, and the connection paths between them can be clearly defined. This helps to accurately describe the electrical connection relationship in the circuit, which is very important for understanding and analyzing the circuit performance. In addition, when designing or debugging a circuit, a clear understanding of these connection paths can help to quickly locate and solve problems. For example, if there is a problem with the electrical connection between the source and the drain of the transistor, it can be determined whether the problem lies in the first, second, or third connection path according to the defined connection relationship. This provides a basis for circuit design and maintenance. the second terminal, etc.) of the transistor can be connected to X and Y respectively through Z1 and Z2, and the connection paths between them can be clearly defined. This helps to accurately describe the electrical connection relationship in the circuit, which is very important for understanding and analyzing the circuit performance. In addition, when designing or debugging a circuit, a clear understanding of these connection paths can help to quickly locate and solve problems. For example, if there is a problem with the electrical connection between the source and the drain of the transistor, it can be determined whether the problem lies in the first, second, or third connection path according to the defined connection relationship. This provides a basis for circuit design and maintenance. It is possible to determine the technical scope by distinguishing (such as the second terminal, etc.).

[0042] Note that these expression methods are just examples and are not limited to these expression methods. Here, X , Y, Z1, and Z2 are assumed to be objects (such as devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0043] Note that even when components that are independent on the circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of multiple components combined. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of multiple components combined within its scope. There may be a case where one component has the functions of multiple components combined. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of multiple components combined within its scope. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of multiple components combined within its scope. electrode. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of multiple components combined within its scope. electrical connection includes such a case where one conductive film has the functions of multiple components combined within its scope. within its scope.

[0044] <Appendix regarding the description of the drawings> In this specification, terms indicating arrangements such as "above" and "below" are used for convenience to explain the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation. reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation. reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0045] Also, the terms "above" and "below" do not limit that the positional relationship of the components is directly above or directly below and in direct contact. For example, in the expression "electrode B above the insulating layer A", it is not necessary for electrode B to be directly formed in contact above the insulating layer A, and those including other components between the insulating layer A and the electrode B are not excluded. it is not necessary for electrode B to be directly formed in contact above the insulating layer A, and those including other components between the insulating layer A and the electrode B are not excluded. are not excluded.

[0046] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Further, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0047] In addition, in this specification, when the crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

[0048] Also, in the drawings, the size, layer thickness, or area is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to that scale. Note that the drawings are shown schematically for clarity and are not limited to the shapes or values shown in the drawings.

[0049] Also, in the drawings, in the top view (also called a plan view or layout view) or perspective view, etc., for the sake of clarity of the drawings, the description of some components may be omitted.

[0050] Also, "identical" may have the same area or the same shape. Also, it may be at the same height in the vertical direction from the base plate surface. The same height can be rephrased as the same plane. Also, due to the relationship of the manufacturing process, it is assumed that it may not be completely the same shape, the same plane, or the same height. Therefore, even if it is substantially the same, it can be rephrased as being the same.

[0051] <Supplementary Note Regarding Replaceable Descriptions> In this specification and the like, when explaining the connection relationship of transistors, one of the source and the drain is denoted as "one of the source or the drain" (or the first electrode, or the first terminal), and the other of the source and the drain is denoted as "the other of the source or the drain" (or the second electrode, or the second terminal). This is because the source and the drain of a transistor change depending on the structure or operating conditions of the transistor. Regarding the naming of the source and the drain of a transistor, it can be appropriately rephrased according to the situation, such as the source (drain) terminal, the source (drain) electrode, etc.

[0052] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0053] Also, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And there is a channel region between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and current can flow through the drain, the channel region, and the source.

[0054] Here, since the source and the drain change depending on the structure or operating conditions of the transistor, it is difficult to limit which one is the source or the drain. Therefore, the source and ​​​​​​The portions that function as the source and the portions that function as the drain are not called the source or the drain, one of the source and the drain may be denoted as the first electrode, and the other of the source and the drain may be denoted as the second electrode.

[0055] Note that the ordinal numbers "first", "second", and "third" used in this specification are added to avoid confusion of components, and it is noted that they are not numerically limiting.

[0056] Also, in this specification and the like, a display device may refer to a device in which, for example, an FPC (Flexible Printed Circuits) or a TCP (Tape Carrier Package) is attached to the substrate of the display panel, or a device in which an IC (integrated circuit) is directly mounted on the substrate by the COG (Chip On Glass) method.

[0057] Also, the terms "film" and "layer" may be interchangeable depending on the case or the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer" in some cases.

[0058] <Supplementary Note on Definition of Terms> Hereinafter, the definitions of each term in this specification and the like will be described.

[0059] In this specification, when the terms "trench" or "groove" are used, they refer to a narrow strip-shaped depression.

[0060] Also, in this specification, when indicating silicon oxynitride as a film, it is represented as SiOxNy. It may be described. At this time, x and y may be natural numbers or numbers with a decimal point. It may also be.

[0061] <Regarding connection> In this specification, when it is said that A and B are connected, it means that not only A and B are directly connected, but also those that are electrically connected are included. Here, when it is said that A and B are electrically connected, it means that when there is an object having some electrical action between A and B, it enables the exchange of electrical signals between A and B.

[0062] Note that the content described in one embodiment (even some of the content) can be applied, combined, or replaced with the other content described in that embodiment (even some of the content), and / or the content described in one or more other embodiments (even some of the content). It can be done.

[0063] Note that the content described in the embodiments refers to the content described using various figures in each embodiment, or the content described using the text described in the specification.

[0064] Note that the figure (even a part) described in one embodiment can be combined with another part of that figure, another figure (even a part) described in that embodiment, and / or the figure (even a part) described in one or more other embodiments to form more figures. It can be done.

[0065] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention and a method for manufacturing the same will be described with reference to the drawings. It will be described.

[0066] Figures 1(A), 1(B), and 1(C) are top views and cross-sectional views of the transistor 10 according to one aspect of the present invention. Figure 1(A) is a top view, Figure 1(B) is a cross-sectional view taken along the dashed line A1 - A2 shown in Figure 1(A), and Figure 1(C) is a cross-sectional view taken along A3 - A4. In Figure 1(A), some elements are enlarged, reduced, or omitted for clarity. Also, the dashed line in the A1 - A2 direction is sometimes referred to as the channel length direction, and the dashed line in the A3 - A4 direction is sometimes referred to as the channel width direction.

[0067] The transistor 10 includes a substrate 100, an insulating layer 110, an insulator 121, a semiconductor layer 122, an insulator 123, a source electrode layer 130, a drain electrode layer 140, a gate insulating layer 1 50, a gate electrode layer 160, an insulating layer 175, an insulating layer 173, and an insulating layer 170. The transistor 10 has the insulating layer 110 on the substrate 100. The transistor 10 has the insulator 121 on the insulating layer 110. The transistor 10 has the semiconductor layer 122 on the insulator 121. The transistor 10 has the source electrode layer 130 and the drain electrode layer 140 on the semiconductor layer 122 and is electrically connected to the semiconductor layer 122. The transistor 1 0 has the insulating layer 173, and the insulating layer 173 has a region in contact with the side surfaces of the insulator 121, the semiconductor layer 122, the insulator 12 3, the source electrode layer 130, and the drain electrode layer 140. The transistor 10 has the insulating layer 175 on the insulating layer 173, the source electrode layer 130, and the drain electrode layer 140, and the insulating layer 175 has a region in contact with the side surface of the insulator 123. The transistor 10 has the insulator 123 on the semiconductor layer 122, and the insulator 123 has a region in contact with the side surfaces of the insulator 121, the insulating layer 173, and the insulating layer 175 as shown in Figure 1(C). Also, the insulator 12 ​​​​​​ As shown in FIG. 1(B), 3 has a region in contact with the lower surface of the insulating layer 170, the insulating layer 175, the source electrode layer 130, and the side surfaces of the drain electrode layer 140. The transistor 10 has a gate insulating layer 150 on the insulator 123. The transistor 10 has a gate electrode layer 160 on the gate insulating layer 150.

[0068] <Regarding the insulator> Note that an insulator (for example, insulator 121, insulator 123) basically has insulating properties and allows current to flow near the interface with the semiconductor layer when the gate electric field or the drain electric field becomes strong.

[0069] Also, in the above-described structure, since the semiconductor layer 122 has regions in contact with the source electrode layer 130 and the drain electrode layer 140, and the insulator 123 has regions in contact with the source electrode layer 130 and the drain electrode layer 140, when the transistor 10 operates, the insulators 121, semiconductor layer 122, and insulator 123 have a high heat dissipation effect with respect to the heat generated therein.

[0070] In addition, when forming the insulating layer 170, the transistor 10 forms a mixed layer having the material of the insulating layer 175 and the material of the insulating layer 170, or a gas used during the formation of the insulating layer 170, etc. at the interface with the insulating layer 175, and oxygen (excess oxygen, referred to as exO) is added to the mixed layer or the insulating layer 175. Further, by performing a heat treatment, the oxygen diffuses to the semiconductor layer 122 and can fill the oxygen vacancies present in the insulator 121 and the semiconductor layer 122. This can improve transistor characteristics (for example, threshold value, reliability, etc.).

[0071] Note that the excess oxygen added during the formation of the insulating layer 170 exists in various states, such as oxygen radicals, oxygen ions, or oxygen atoms, due to the influence of factors such as the voltage, power, plasma, or substrate temperature applied during film formation by, for example, sputtering method. At this time, the excess oxygen has more energy than in a stable state and can enter the insulating layer 175. Note that the method of adding oxygen is not limited to the above method, and the insulating layer 110 may contain the excess oxygen during film formation, or another method (for example, ion implantation method, ion plasma immersion method, etc.) may be used after film formation. As shown in the cross-sectional view between the dashed-dotted lines A3 - A4 in Fig. 1(C), in the channel width direction, the gate electrode layer 160 faces the side surfaces of the insulator 121, the semiconductor layer 122, and the insulator 123 through the gate insulating layer 150. That is, when a voltage is applied to the gate electrode layer 160, the insulator 121, the semiconductor layer 122, and the insulator 123 are surrounded by the electric field of the gate electrode layer 160 in the channel width direction. The structure of the transistor in which the semiconductor layer 122 is surrounded by the electric field of the gate electrode layer 160 is called a surrounded channel (s-channel) structure. Also, since the transistor 10 can form the gate electrode layer, the source electrode layer, and the drain electrode layer in self-alignment using a groove, the alignment accuracy is relaxed, and it becomes possible to easily fabricate a fine transistor. Note that such a structure shown in this embodiment is called a self-align s-channel FET (Self Align s-channel FET, SA s-channel FET) structure, or a trench

[0072]

[0073] ​ Trench gate s-channel FET ), or a TGSA s-channel FET (Trench Gat e Self Align FET), or a GLSA s-channel FE T (Gate Last Self Align FET).

[0074] Here, when the insulator 121, the semiconductor layer 122, and the insulator 123 are combined to form the semiconductor layer 120 in a transistor with a TGSA structure, in the on state, a channel is formed in the entire semiconductor layer 120 (bulk), so the on-current increases. On the other hand, in the off state, since the entire channel region formed in the semiconductor layer 120 can be depleted the off-current can be further reduced.

[0075] In addition, since the transistor 10 has a TGSA structure, the parasitic capacitance generated between the gate electrode and the source electrode, or between the gate electrode and the drain electrode is reduced, and the cut-off frequency characteristics of the transistor 10 are improved, etc., making it possible to make the transistor 10 respond at high speed.

[0076] In addition, in this embodiment, as will be described later, after performing a planarization process until the source electrode layer 130 and the drain electrode layer 140 are exposed for the second insulating film that becomes the insulating layer 175, when forming the third insulating film that becomes the insulating layer 173, it is preferable that the upper surface of the insulating layer 173, the upper surfaces of the source electrode layer 130 and the drain electrode layer 140 are in the same plane parallel to the substrate surface. Thereby the insulating layer 173 on the source electrode layer 130 and the drain electrode layer 140 can be uniformly formed within the substrate surface, and the formation process of the groove portion 174 (for example, the etching treatment time, etc.) can be stabilized ​ can be achieved. As a result, the transistor 10 can be stably manufactured. This enables the shape of the transistor to be stabilized and variation in transistor characteristics to be suppressed.

[0077] Note that the position of the upper surface of the source electrode layer 130 or the drain electrode layer 140 may be lower than, the same as, or higher than the position of the bottom surface of the gate electrode layer 160.

[0078] Also, for the transistor 10, the upper surface of the gate electrode layer 160 may be below the upper surface of the insulating layer 175. Further, the transistor 10 may have a shape in which the source electrode layer 130 and the drain electrode layer 14 0 are shorter than the semiconductor layer 122 in the channel length direction, or may have a longer shape in the channel length direction.

[0079] <Regarding the channel length> Note that the channel length is, for example, in a top view of the transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined to be one value. Therefore, in this specification the channel length is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed.

[0080] <Regarding the channel width> ​​​​​The channel width refers to, for example, the length of the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) overlaps with the gate electrode. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Note that depending on the structure of the transistor, there may be a difference between the actual channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor containing a fine and three-dimensional channel, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the actual effective channel width where the channel is formed is larger than the apparent channel width shown in the top view. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Note that depending on the structure of the transistor, there may be a difference between the actual channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor containing a fine and three-dimensional channel, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the actual effective channel width where the channel is formed is larger than the apparent channel width shown in the top view. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

[0081] Note that depending on the structure of the transistor, there may be a difference between the actual channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor containing a fine and three-dimensional channel, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the actual effective channel width where the channel is formed is larger than the apparent channel width shown in the top view. Note that depending on the structure of the transistor, there may be a difference between the actual channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor containing a fine and three-dimensional channel, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the actual effective channel width where the channel is formed is larger than the apparent channel width shown in the top view. Note that depending on the structure of the transistor, there may be a difference between the actual channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor containing a fine and three-dimensional channel, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the actual effective channel width where the channel is formed is larger than the apparent channel width shown in the top view. Note that depending on the structure of the transistor, there may be a difference between the actual channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor containing a fine and three-dimensional channel, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the actual effective channel width where the channel is formed is larger than the apparent channel width shown in the top view. Note that depending on the structure of the transistor, there may be a difference between the actual channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor containing a fine and three-dimensional channel, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the actual effective channel width where the channel is formed is larger than the apparent channel width shown in the top view. Note that depending on the structure of the transistor, there may be a difference between the actual channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor containing a fine and three-dimensional channel, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the actual effective channel width where the channel is formed is larger than the apparent channel width shown in the top view. Note that depending on the structure of the transistor, there may be a difference between the actual channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor containing a fine and three-dimensional channel, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the actual effective channel width where the channel is formed is larger than the apparent channel width shown in the top view. Note that depending on the structure of the transistor, there may be a difference between the actual channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor containing a fine and three-dimensional channel, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the actual effective channel width where the channel is formed is larger than the apparent channel width shown in the top view. Note that depending on the structure of the transistor, there may be a difference between the actual channel width (hereinafter referred to as the effective channel width) in the region where the channel is actually formed and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor containing a fine and three-dimensional channel, the ratio of the channel region formed on the side surface of the semiconductor may increase. In that case, the actual effective channel width where the channel is formed is larger than the apparent channel width shown in the top view.

[0082] By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0083] <SCWについて> Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel width in the region is called the Surrounding Channel Width (SCW). In this specification, it is simply called When channel width is mentioned, it refers to enclosed channel width or apparent channel width. In this specification, when the term "channel width" is used, it means an effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, etc. The width of the upper channel and the width of the enclosed channel are obtained by taking a cross-sectional TEM image. The value can be determined, such as by analysis.

[0084] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0085] <Improvement of characteristics through miniaturization> In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width shrinks. When the ON current is reduced, the ON current decreases.

[0086] However, in the transistor according to one embodiment of the present invention shown in FIG. An insulator 123 is formed so as to cover the semiconductor layer 122 in which the channel is formed. The channel formation layer and the gate insulating layer are not in contact with each other. Scattering of carriers generated at the interface with the insulating layer can be suppressed, and the on-current of the transistor can be increased significantly. It can be increased.

[0087] In addition, in the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction with respect to the semiconductor layer 12 2, a gate electric field from the side direction is applied. That is, since the gate electric field is applied to the entire semiconductor layer 122, and the current flows through the entire semiconductor layer 122, the on-current can be further increased. That is, the gate electric field is applied to the entire semiconductor layer 122, and the current flows through the entire semiconductor layer 122, so that the on-current can be further increased. Since it becomes like this, the on-current can be further increased.

[0088] Further, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface levels by forming the insulator 123 on the insulator 121 and the semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by using the semiconductor layer 122 as an intermediate layer. Therefore, in addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized, and the S value (subthreshold coefficient) can be made small. Therefore, Icut (the current when the gate voltage VG is 0V) can be lowered, and the power consumption can be reduced. And, in addition to the above-described improvement in the on-current of the transistor, the threshold voltage can be stabilized, and the S value (subthreshold coefficient) can be made small. Therefore, Icut (the current when the gate voltage VG is 0V) can be lowered, and the power consumption can be reduced. In addition, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. value (subthreshold coefficient) can be made small. Therefore, Icut (the current when the gate voltage VG is 0V) can be lowered, and the power consumption can be reduced. That is, Icut (the current when the gate voltage VG is 0V) can be lowered, and the power consumption can be reduced. In addition, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. It can be improved.

[0089] Note that, in the present embodiment, an example in the case where the semiconductor layer 120 (such as the semiconductor layer 122 ) is used for the channel or the like has been shown, but one aspect of the embodiment of the present invention is not limited thereto. For example, the channel, its vicinity, the source region, the drain region, etc. may be, depending on the case, not limited to this. For example, the channel, its vicinity, the source region, the drain region, etc. may be, depending on the case, Alternatively, depending on the situation, it may be formed of a material having silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like. ium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like. It may be formed of a material having silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like.

[0090] <Configuration of Transistor> The configuration of the transistor according to this embodiment will be described below.

[0091] <<Substrate 100>> For the substrate 100, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Also, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI (Silicon n On Insulator) substrate, or the like can also be used, and a substrate on which a semiconductor element is provided may be used. The substrate 100 is not limited to a mere support material, and may be a substrate on which other devices such as other transistors are formed. In this case, at least one of the gate electrode layer 160, the source electrode layer 130, and the drain electrode layer 140 of the transistor may be electrically connected to the above-mentioned other devices. Also, a flexible substrate may be used as the substrate 100. As a method of providing a transistor on the flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to the substrate 100 which is a flexible substrate. In that case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Note that, as the substrate 100, a sheet, film, or foil woven with fibers may be used. Also, the substrate 100 may have stretchability.

[0092] Alternatively, a flexible substrate may be used as the substrate 100. As a method of providing a transistor on the flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to the substrate 100 which is a flexible substrate. In that case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Note that, as the substrate 100, a sheet, film, or foil woven with fibers may be used. Also, the substrate 100 may have stretchability. and transferring it to the substrate 100 which is a flexible substrate. In that case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Note that, as the substrate 100, a sheet, film, or foil woven with fibers may be used. Also, the substrate 100 may have stretchability. This may be the case. Further, when the bending and pulling are stopped, the substrate 100 may have the property of returning to its original shape. Or it may have a property of not returning to its original shape. The thickness of the substrate 100 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. Making the substrate 100 thinner can reduce the weight of the semiconductor device. Also, by making the substrate 100 thinner, in some cases where it has stretchability even when using glass or the like, or when it has the property of returning to its original shape when bending and pulling are stopped. Therefore, impacts applied to the semiconductor device on the substrate 100 due to dropping or the like can be mitigated. That is, a robust semiconductor device can be provided. As the substrate 100 which is a flexible substrate, for example, metal, alloy, resin, or glass, or fibers thereof can be used. The substrate 100 which is a flexible substrate preferably has less deformation due to the environment as the linear expansion coefficient is lower. As the substrate 100 which is a flexible substrate,

[0093] for example, a material with a linear expansion coefficient of 1×10 / K or less, 5×10 / K or less, or 1×10 / K or less can be used. Examples of the resin include polyester, polyolefin, -3 amide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, -5 polytetrafluoroethylene (PTFE), etc. In particular, aramid has a low linear expansion coefficient and is thus suitable as the substrate 100 which is a flexible substrate. -5 / K or less. As the resin, for example, there are polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, polytetrafluoroethylene (PTFE), etc. In particular, aramid is suitable as the substrate 100 which is a flexible substrate because it has a low linear expansion coefficient.

[0094] 《Insulating layer 110》 The insulating layer 110 has the role of preventing the diffusion of impurities from the substrate 100 and, in addition, the semiconductor layer It can play a role in supplying oxygen to 120 (semiconductor layer 122). Therefore, the insulating layer 110 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, by the TDS method, the oxygen release amount in terms of oxygen atoms is set to be a film of 1.0×10 atoms / cm3 or more. Note that the surface temperature of the film during the above TDS analysis 19 is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 500 °C or less. Also, as described above, when the substrate 100 is a substrate on which other devices are formed, the insulating layer 110 also has a function as an interlayer insulating film. In that case, it is preferable to perform a planarization process by a method such as CMP (Chemical Mechanical Polishin g) so that the surface becomes flat.

[0095] 《Insulators 121, 123, Semiconductor Layer 122》 The oxides that can be used as the insulator 121, the semiconductor layer 122, and the insulator 123 are preferably contain at least indium (In) or zinc (Zn). Or, it is preferably contain both In and Zn. Also, in order to reduce the variation in the electrical characteristics of the transistors using the oxide as a semiconductor, it is preferably contain a stabilizer together with them. Typically, there are In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn- Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, C e, Mg, or Nd).

[0096] Examples of the stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), al uminum (Al), or zirconium (Zr), etc. Also, other stabilizers and include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium ( Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium ( Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc. .

[0097] When the insulator 123 is an In-M-Zn oxide, the atomic ratio of In and M when the sum of In and M is 100 at omic% is preferably such that In is 25 atomic % or more and M is less than 75 atomic%, more preferably In is 34 atomic % or more and M is less than 66 atomic%.

[0098] The content of indium, gallium, etc. in the insulator 123 can be compared by time-of-flight secondary ion mass spectrometry (TOF-SIMS), X-ray photoelectron spectroscopy (XPS), ICP mass spectrometry (ICP-MS ).

[0099] Since the semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more, the off-current of the transistor 10 can be reduced .

[0100] The thickness of the semiconductor layer 122 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 50 nm or less.

[0101] The insulator 121 and the insulator 123 are oxide films composed of one or more of the elements constituting the semiconductor layer 122. Therefore, the semiconductor layer 122 and the insulator 121, and the insulator 12 3 At the interface with 3, interface scattering is unlikely to occur. Therefore, at this interface, the movement of carriers is not inhibited, and the field-effect mobility of the transistor 10 is increased.

[0102] The insulators 121 and 123 are typically In-Ga oxide, In-Zn oxide, In-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), and the energy level of the lower end of the conduction band is closer to the vacuum level than that of the semiconductor layer 122. Typically, the difference between the energy level of the lower end of the conduction band of the insulators 121 and 123 and the energy level of the lower end of the conduction band of the semiconductor layer 122 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the insulators 121 and 123 and the electron affinity of the semiconductor layer 122 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Note that the electron affinity indicates the difference between the vacuum level and the energy level of the lower end of the conduction band.

[0103] When the insulators 121 and 123 have Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd at an atomic ratio higher than that of In, the following effects may occur. (1) Increase the energy gap between the insulators 121, the semiconductor layer 122, and the insulators 123. (2) Reduce the electron affinity of the insulators 121 and 123. (3) Shield impurities from the outside. (4) Increase the insulation property compared to the semiconductor layer 122. (5) ​​​​​​​​​​​​​​​ Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd is a metal element with a strong binding force with oxygen. Therefore, by having Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd at an atomic ratio higher than that of In, oxygen deficiency is less likely to occur.

[0104] Note that since the insulators 121 and 123 have higher insulation properties compared to the semiconductor layer 122, they have the same function as a gate insulating layer.

[0105] When the insulators 121 and 123 are In-M-Zn oxides, the atomic ratio of In and M excluding Zn and O is preferably less than 50 atomic% for In and 50 atomic% or more for M, and more preferably less than 25 atomic% for In and 75 atomic% or more for M.

[0106] Also, when the insulators 121 and 123 are In-M-Zn oxides (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), compared to the semiconductor layer 122, the atomic ratio of M (Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) contained in the insulators 121 and 123 is high. Typically, it is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more higher than the atomic ratio of the above-mentioned atoms contained in the semiconductor layer 122. Since the elements represented by M above bind more strongly with oxygen than indium, they have the function of suppressing the occurrence of oxygen deficiency in the insulators 121 and 123. That is, the insulators 121 and 123 are oxide films in which oxygen deficiency is less likely to occur than in the semiconductor layer 122.

[0107] Also, the semiconductor layer 122 has a higher indium content than the insulators 121 and 123. This is preferable. As for the semiconductor, mainly the s orbitals of heavy metals contribute to carrier conduction, and by increasing the In content, more s orbitals overlap. Therefore, an oxide having a composition in which In is more than M has a higher mobility compared to an oxide having a composition in which In is equal to or less than M. Therefore, by using an oxide having a high indium content for the semiconductor layer 122, a transistor with high field-effect mobility can be realized.

[0108] Also, when the semiconductor layer 122 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), in the target used to form the semiconductor layer 122, if the atomic ratio of the metal elements is In:M:Zn = x1:y1:z1, x1 / y1 is 1 / 3 or more and 6 or less, and further preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, and further preferably 1 or more and 6 or less. By setting z1 / y1 to 1 or more and 6 or less, a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film is likely to be formed as the semiconductor layer 122. Representative examples of the atomic ratio of the metal elements in the target include In:M:Zn = 1 :1:1, 1:1:1.2, 2:1:1.5, 2:1:2.3, 2:1:3, 3:1:2 :4:2:3, 4:2:4.1, etc.

[0109] Also, when the insulator 121 and the insulator 123 are In-M-Zn oxides (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), in the target used to form the insulator 121 and the insulator 123, if the atomic ratio of the metal elements is In:M:Zn = x Assuming 2:y2:z2, then x2 / y2 < x1 / y1, and z2 / y2 is preferably 1 / 3 or more 6 or less, more preferably 1 or more and 6 or less. Note that setting z2 / y2 to 1 or more and 6 or less makes it easier to form the CAAC-OS film as the insulator 121 and the insulator 123. Typical examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:2, 1:3:4, 1:3:6, 1:3:8, 1:4:4, 1:4:5, 1:4:6, 1:4: 7, 1:4:8, 1:5:5, 1:5:6, 1:5:7, 1:5:8, 1:6:8, 1: 6:4, 1:9:6, etc.

[0110] Note that the atomic ratios of the insulator 121 and the insulator 123 each include a variation of plus or minus 40% of the above atomic ratio as an error.

[0111] In addition, the insulator 123 can be replaced with a metal oxide, such as aluminum oxide (AlOx), gallium oxide (GaOx), hafnium oxide (HfOx), silicon oxide (SiOx), germanium oxide (GeOx), or zirconia (ZrOx), or the insulator 123 can have the metal oxide on it.

[0112] Note that the atomic ratio is not limited to these, and an appropriate atomic ratio can be used according to the required semiconductor characteristics.

[0113] In addition, the insulator 121 and the insulator 123 may have the same composition. For example, as the insulator 121 and the insulator 123, an In-Ga-Zn oxide with an atomic ratio of the metal elements of the target used in the sputtering method of In:Ga :Zn = 1:3:2, 1:3:4, or 1:4:5 may be used.

[0114] Alternatively, the insulators 121 and 123 may have different compositions. For example, when using an In-Ga-Zn oxide with an atomic ratio of metal elements in the target used in the sputtering method of In:Ga:Zn = 1:3:4 for the insulator 121, an In-Ga-Zn oxide with an atomic ratio of metal elements in the target of In:Ga:Zn = 1:3:2 may be used for the insulator 123.

[0115] The thicknesses of the insulator 121, the semiconductor layer 122, and the insulator 123 are preferably 3 nm or more and 100 nm or less, or 3 nm or more and 50 nm or less.

[0116] Here, the thickness of the semiconductor layer 122 may be formed thinner, the same, or thicker than at least the insulator 121. For example, when the semiconductor layer 122 is thickened, the on-current of the transistor can be increased. Also, the insulator 121 may have a thickness such that the effect of suppressing the generation of interface levels of the semiconductor layer 122 is not lost. For example, the thickness of the semiconductor layer 122 can be greater than 1 times, or 2 times or more, or 4 times or more, or 6 times or more the thickness of the insulator 121. Also, when it is not necessary to increase the on-current of the transistor, the thickness of the insulator 121 may be equal to or greater than the thickness of the semiconductor layer 122. For example, when the insulating layer 110, the insulating layer 170, the insulating layer 173, or the insulating layer 175 has an excessive amount of oxygen, by heat treatment, the oxygen diffuses, and the amount of oxygen deficiency contained in the semiconductor layer 122 can be reduced, and the electrical characteristics of the semiconductor device can be stabilized. For example, when the insulating layer 110, the insulating layer 170, the insulating layer 173, or the insulating layer 175 has an excessive amount of oxygen, by heat treatment, the oxygen diffuses, and the amount of oxygen deficiency contained in the semiconductor layer 122 can be reduced, and the electrical characteristics of the semiconductor device can be stabilized.

[0117] Also, similar to the insulator 121, the insulator 123 also suppresses the generation of interface levels of the semiconductor layer 122. It suffices that the thickness is such that the effect is not lost. For example, the thickness may be equal to or less than that of the insulator 121. If the insulator 123 is thick, there is a risk that the electric field by the gate electrode layer 160 will hardly reach the semiconductor layer 122. Therefore, it is preferable that the insulator 123 be formed thin. In addition, since oxygen contained in the insulator 123 may diffuse into the source electrode layer 130 and the drain electrode layer 140 and prevent the source electrode layer 130 and the drain electrode layer 140 from being oxidized, it is preferable that the film thickness of the insulator 123 be thin. For example, the insulator 123 may be thinner than the thickness of the semiconductor layer 122. Note that the thickness of the insulator 123 is not limited to this, and may be appropriately set according to the voltage for driving the transistor in consideration of the breakdown voltage of the gate insulating layer 150. When the compositions of the insulator 121, the semiconductor layer 122, and the insulator 123 are different, the interface may be observable using a scanning transmission electron microscope (STEM). <Regarding hydrogen concentration> Hydrogen contained in the insulator 121, the semiconductor layer 122, and the insulator 123 reacts with oxygen that binds to metal atoms to form water, and at the same time, oxygen vacancies are formed in the lattice (or the portion where oxygen has desorbed) from which oxygen has desorbed. When hydrogen enters the oxygen vacancies, carriers, i.e., electrons, may be generated. In addition, when a part of hydrogen binds to oxygen that binds to metal atoms, carriers, i.e., electrons, may be generated. Therefore, a transistor using an oxide containing hydrogen as a semiconductor tends to have normally-on characteristics.

[0118]

[0119]

[0120] ​​​​​​​​​​​​Therefore, at the insulator 121, semiconductor layer 122, insulator 123, and their respective interfaces, it is preferable that hydrogen is reduced as much as possible along with oxygen deficiency. For example, at the insulator 121, semiconductor layer 122, insulator 123, and their respective interfaces, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry ) is 1×10 16 atoms / cm 3 or more and 2×10 20 ato ms / cm 3 or less, preferably 1×10 16 atoms / cm 3 or more and 5×10 19 ato ms / cm 3 or less, more preferably 1×10 16 atoms / cm 3 or more and 1×10 19 a toms / cm 3 or less, even more preferably 1×10 16 atoms / cm 3 or more and 5×10 18 atoms / cm 3 or less. As a result, the transistor 10 can have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

[0121] <Regarding carbon and silicon concentrations> In addition, if silicon or carbon, which is one of the Group 14 elements, is contained at the insulator 121, semiconductor layer 122, insulator 123, and their respective interfaces, oxygen deficiency increases in the insulator 121, semiconductor layer 122, and insulator 123, and an n-type region is formed. Therefore, the silicon at the insulator 121, semiconductor layer 122, insulator 123, and their respective interfaces ​​​The concentration of the con and carbon is desirably reduced. For example, insulator 121, semiconductor layer 1 22, insulator 123, and the concentration of silicon and carbon obtained by SIMS at each interface is 1×10 16 atoms / cm 3 or more and 1×10 19 atoms / cm 3 or less, preferably 1×10 atoms / cm 16 or more and 5×10 3 atoms / cm 18 or less, more preferably 1×10 3 atoms / cm or more and 2×10 16 atoms / cm 3 or less and 2×10 18 atoms / c m 3 or less. As a result, the transistor 10 has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

[0122] <Regarding the concentration of alkali metal or alkaline earth metal> In addition, alkali metals and alkaline earth metals may generate carriers when combined with oxides, and the off-current of the transistor may increase. For this reason, it is preferable to reduce the concentration of alkali metals or alkaline earth metals at the interfaces of insulator 1 21, semiconductor layer 122, insulator 123, respectively. For example, at the interfaces of insulator 121, semiconductor layer 122, insulator 123, and each interface, the concentration of alkali metals or alkaline earth metals obtained by SIMS is 1×10 atoms / cm or less, preferably 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less. As a result, the transistor ​The stage 10 has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. It has.

[0123] <Regarding nitrogen concentration> Also, when nitrogen is contained in the insulator 121, the semiconductor layer 122, the insulator 123, and their respective interfaces, carriers, i.e., electrons, are generated, the carrier density increases, and an n-type region is formed. As a result, a transistor using an oxide containing nitrogen tends to have normally-on characteristics. Therefore, at the insulator 121, the semiconductor layer 122, the insulator 123, and their respective interfaces, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration obtained by SIMS at the insulator 121, the semiconductor layer 122, the insulator 123, and their respective interfaces is 5×10 atoms / cm or more and 5×10 atoms / cm or less, preferably 1×10 15 atoms / cm 3 or more and 5×10 19 atoms / cm 3 or less, more preferably 1×10 15 atoms / cm 3 or more and 5×10 18 atoms / cm 3 or less, even more preferably 1×10 15 atoms / cm 3 or more and 1×10 18 atoms / cm 3 or less, still more preferably 1×10 15 atoms / cm 3 or more and 5×10 17 ato ms / cm 3 or less. As a result, the transistor 10 has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. It has.

[0124] <Regarding carrier density> By reducing the impurities in the insulator 121, the semiconductor layer 122, and the insulator 123, the carrier density of the insulator 121, the semiconductor layer 122, and the insulator 123 can be reduced. Therefore, the insulator 121, the semiconductor layer 122, and the insulator 123 have a carrier density of 1× 10 15 per cm 3 or less, preferably 1×10 13 per cm 3 or less, more preferably 8 ×10 11 per cm 3 less, even more preferably 1×10 11 per cm 3 less, most preferably is 1×10 10 per cm 3 less, and 1×10 -9 per cm 3 or more.

[0125] As the insulator 121, the semiconductor layer 122, and the insulator 123, by using an oxide film with a low impurity concentration and a low density of defect levels, a transistor with even better electrical characteristics can be fabricated. Here, an oxide with a low impurity concentration and a low density of defect levels (with few oxygen deficiencies) is called highly pure intrinsic or substantially highly pure intrinsic. Since an oxide that is highly pure intrinsic or substantially highly pure intrinsic has few carrier generation sources, it may be possible to reduce the carrier density. Therefore, a transistor in which a channel region is formed in the oxide film is likely to have electrical characteristics (also called normally-off characteristics) in which the threshold voltage is positive. Moreover, since an oxide film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the trap level density may also be low. Also, a transistor using an oxide film that is highly pure intrinsic or substantially highly pure intrinsic has an extremely small off-current, and the source electrode and the drain has few oxygen deficiencies) is called highly pure intrinsic or substantially highly pure intrinsic. Since an oxide that is highly pure intrinsic or substantially highly pure intrinsic has few carrier generation sources, it may be possible to reduce the carrier density. Therefore, a transistor in which a channel region is formed in the oxide film is likely to have electrical characteristics (also called normally-off characteristics) in which the threshold voltage is positive. is less likely to have carrier generation sources, so the carrier density can be reduced. Therefore, a transistor in which a channel region is formed in the oxide film is likely to have electrical characteristics (also called normally-off characteristics) in which the threshold voltage is positive. Therefore, a transistor in which a channel region is formed in the oxide film is likely to have electrical characteristics (also called normally-off characteristics) in which the threshold voltage is positive. characteristics (also called normally-off characteristics) in which the threshold voltage is positive. In addition, since an oxide film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the trap level density may also be low. Also, a transistor using an oxide film that is highly pure intrinsic or substantially highly pure intrinsic has an extremely small off-current, and the source electrode and the drain Using an oxide film that is highly pure intrinsic or substantially highly pure intrinsic, the off-current of the transistor is extremely small, and the source electrode and the drain When the voltage between the in electrodes (drain voltage) is in the range of 1 V to 10 V, the off-current is below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 A or less, and such characteristics can be obtained. Therefore, a transistor in which a channel region is formed in the oxide film may be a transistor with small fluctuations in electrical characteristics and high reliability. -13 A or less, and such characteristics can be obtained. Therefore, a transistor in which a channel region is formed in the oxide film may be a transistor with small fluctuations in electrical characteristics and high reliability. Furthermore, the off-current of a transistor using the oxide film highly purified as described above for the channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current normalized by the channel width of the transistor can be reduced to several y A / μm to several zA / μm.

[0126] Also, the insulator 121, the semiconductor layer 122, and the insulator 123 may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS, polycrystalline structure, microcrystalline structure, or amorphous structure, which will be described later. In the non-single crystal structure, the amorphous structure has the highest density of defect levels, and CAAC C-OS has the lowest density of defect levels. The insulator 121, the semiconductor layer 122, and the insulator 123 may have, for example, a microcrystalline structure. The insulator 121, the semiconductor layer 122, and the insulator 123 having a microcrystalline structure contain, for example, microcrystals with a size of 1 nm or more and less than 10 nm in the film. Or, the oxide film having a microcrystalline structure is, for example,

[0127] a mixed-phase structure having a crystal part of 1 nm or more and less than 10 nm in the amorphous phase. The insulator 121, the semiconductor layer 122, and the insulator 123 may have, for example, an amorphous structure. The amorphous structure has the highest density of defect levels among them, and CAAC C-OS has the lowest density of defect levels.

[0128] The insulator 121, the semiconductor layer 122, and the insulator 123 may have, for example, a microcrystalline structure. The insulator 121, the semiconductor layer 122, and the insulator 123 having a microcrystalline structure contain, for example, microcrystals with a size of 1 nm or more and less than 10 nm in the film. Or, the oxide film having a microcrystalline structure is, for example, a mixed-phase structure having a crystal part of 1 nm or more and less than 10 nm in the amorphous phase. a mixed-phase structure having a crystal part of 1 nm or more and less than 10 nm in the amorphous phase. a mixed-phase structure having a crystal part of 1 nm or more and less than 10 nm in the amorphous phase.

[0129] The insulator 121, the semiconductor layer 122, and the insulator 123 may have, for example, an amorphous structure. The insulator 121, semiconductor layer 122, and insulator 123 of a crystalline structure, for example, have an atomic arrangement that is disordered and has no crystal component. Alternatively, an oxide film having an amorphous structure, for example, has a completely amorphous structure and has no crystal part.

[0130] Note that the insulator 121, semiconductor layer 122, and insulator 123 may be a mixed film having regions of two or more structures of CAAC-OS, microcrystalline structure, and amorphous structure. As the mixed film, for example, there is a single-layer structure having an amorphous structure region, a microcrystalline structure region, and a CAAC-OS region. Alternatively, as the mixed film, for example, there is a laminated structure of an amorphous structure region, a microcrystalline structure region, and a CAAC-OS region.

[0131] Note that the insulator 121, semiconductor layer 122, and insulator 123 may, for example, have a single-crystalline structure

[0132] By providing an oxide film that is less likely to cause oxygen deficiency in contact with the upper and lower sides of the semiconductor layer 122 compared to the semiconductor layer 122, oxygen deficiency in the semiconductor layer 122 can be reduced. Further, since the semiconductor layer 122 is in contact with the insulator 121 and the insulator 123 having one or more of the metal elements constituting the semiconductor layer 122, the interface level density at the interface between the insulator 121 and the semiconductor layer 122 and at the interface between the semiconductor layer 122 and the insulator 123 is extremely low. For example, after adding oxygen to the insulating layer 110 and performing a heat treatment, the oxygen moves to the semiconductor layer 122 via the insulator 121, but at this time, the oxygen is hardly trapped at the interface level, and the oxygen contained in the insulator 121 can be efficiently moved to the semiconductor layer 122. As a result, the semiconductor layer ​​​​​​​​In addition, oxygen vacancies in the insulator 121 can be reduced. Since oxygen is added, it is possible to reduce oxygen vacancies in the insulator 121. Furthermore, the localized state density of the semiconductor layer 122 can be reduced.

[0133] In addition, the semiconductor layer 122 may be an insulating film having a different constituent element (for example, a gate insulating film including a silicon oxide film). When the semiconductor comes into contact with a semiconductor insulating layer, an interface state is formed, and the interface state can form a channel. In such a case, a second transistor with a different threshold voltage appears, However, the semiconductor layer 122 may have a large apparent threshold voltage. The insulator 121 and the insulator 123 each containing one or more metal elements are in contact with the semiconductor layer 122. Therefore, the interface between the insulator 121 and the semiconductor layer 122 and the interface between the insulator 123 and the semiconductor layer 122 are The interface state is less likely to be formed at the interface.

[0134] The insulators 121 and 123 are components of the insulating layer 110 and the gate insulating layer 150, respectively. In order to prevent the formation of impurity levels due to the incorporation of chemical elements into the semiconductor layer 122, It also functions as a barrier film for

[0135] For example, the insulating layer 110 or the gate insulating layer 150 may be an insulating film containing silicon. In this case, the silicon in the gate insulating layer 150 or the insulating layer 110 and the gate insulating layer 150 Carbon that may be mixed into the insulator 121 or the insulator 123 penetrates into the insulator 121 or 123 up to a depth of several nm from the interface. When impurities such as silicon and carbon enter the semiconductor layer 122, the impurity level In some cases, the impurity level acts as a donor and generates electrons, making the material n-type.

[0136] However, if the film thicknesses of the insulators 121 and 123 are thicker than several nanometers, the impurities such as silicon and carbon will not reach the semiconductor layer 122, so the influence of impurity levels is reduced.

[0137] Therefore, by providing the insulators 121 and 123, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced.

[0138] Also, when the gate insulating layer 150 is in contact with the semiconductor layer 122 and a channel is formed at the interface, interface scattering occurs at the interface, and the field-effect mobility of the transistor decreases. However, since the insulators 121 and 123 containing one or more metal elements constituting the semiconductor layer 122 are provided in contact with the semiconductor layer 122, carrier scattering hardly occurs at the interface between the semiconductor layer 122 and the insulators 121 and 123, and the field-effect mobility of the transistor can be increased. This is possible.

[0139] In this embodiment, it is possible to reduce the oxygen deficiency amount of the semiconductor layer 122 and further the oxygen deficiency amounts of the insulators 121 and 123 in contact with the semiconductor layer 122, and the localized state density of the semiconductor layer 12 2 can be reduced. As a result, the transistor 10 shown in this embodiment can have characteristics with little variation in the threshold voltage and high reliability. Also, the transistor 10 shown in this embodiment has excellent electrical characteristics.

[0140] Note that as the gate insulating layer of the transistor, an insulating film containing silicon is often used. Therefore, for the above reasons, the region serving as the channel of the oxide layer is that of the transistor of one aspect of the present invention. It can be said that a structure that does not contact the gate insulating layer is preferable. Also, when a channel is formed at the interface between the gate insulating layer and the oxide layer, carrier scattering occurs at the interface, and the field-effect mobility of the transistor may decrease. From this perspective as well, it can be said that the region that becomes the channel of the oxide layer is preferably separated from the gate insulating layer. Therefore, by forming the semiconductor layer 120 into a stacked structure of insulator 121, semiconductor layer 122, and insulator 123

[0141] a channel can be formed in the semiconductor layer 122, and a transistor having high field-effect mobility and stable electrical characteristics can be formed. Note that the semiconductor layer does not necessarily have to be three layers, and it may have a single-layer, two-layer, four-layer, or even five-layer or more

[0142] configuration. In the case of a single layer, the layer corresponding to the semiconductor layer 122 shown in this embodiment may be used.

[0143] <Band diagram> Here, the band diagram will be described. The band diagram shows the energy (Ec) of the lower end of the conduction band of the insulating layer 110, insulator 121, semiconductor layer 122, insulator 123, and gate insulating layer 150 for easy understanding.

[0144] As shown in FIGS. 3(A) and 3(B), in the insulator 121, semiconductor layer 122, and insulator 123, the energy of the lower end of the conduction band changes continuously. This can also be understood from the fact that since the elements constituting the insulator 121, semiconductor layer 122, and insulator 123 are common, oxygen diffuses easily among them. Therefore, although the insulator 121, semiconductor layer 122, and insulator 123 are a laminate of films with different compositions, it can also be said that they are physically continuous. ​​​

[0145] The oxide films laminated with common main components are not simply laminated but continuously joined (here In particular, a U-shaped well (U Shape Well) structure is formed in which the energy at the lower end of the conduction band changes continuously between layers. That is, the lamination structure is formed so that there are no impurities that form defect levels such as trap centers or recombination centers at the interfaces of the respective layers. If impurities are mixed between the layers of the laminated multilayer film, the continuity of the energy band is lost, and carriers disappear due to trapping or recombination at the interface.

[0146] In addition, in Fig. 3(B), the case where the Ec of the insulator 121 and the insulator 123 is the same is shown, but they may be different from each other.

[0147] From Fig. 3(B), it can be seen that the semiconductor layer 122 becomes a well, and in the transistor 10, a channel is formed in the semiconductor layer 122. In addition, a channel having a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously with the semiconductor layer 122 as the bottom can also be called an embedded channel.

[0148] Near the interfaces of the insulator 121 and the insulator 123 and an insulating film such as a silicon oxide film, trap levels caused by impurities or defects can be formed. Due to the presence of the insulator 121 and the insulator 123, the semiconductor layer 122 and the trap level can be separated. However, when the energy difference between the Ec of the insulator 121 or the insulator 123 and the Ec of the semiconductor layer 122 is small, electrons in the semiconductor layer 122 reach the trap level beyond the energy difference. ​​​​​​​This can occur. When electrons with a negative charge are trapped in the trap level, negative fixed charges are generated at the interface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction. Furthermore, in the long-term storage test of the transistor, there is a concern that the traps are not fixed and cause fluctuations in the characteristics. Therefore, in order to reduce the fluctuation of the threshold voltage of the transistor, it is necessary to provide an energy difference between the Ec of the insulator 121 and the insulator 123 and the Ec of the semiconductor layer 122.

[0149] Each of these energy differences is preferably 0.1 eV or more, more preferably 0.2 eV or more. It should be noted that the insulator 121, the semiconductor layer 122, and the insulator 123 preferably contain crystal parts. In particular, by using a crystal oriented along the c-axis, stable electrical characteristics can be imparted to the transistor. Moreover, in the band diagram as shown in Fig. 3(B), without providing the insulator 123, an In-Ga oxide (for example, an In-Ga oxide with an atomic ratio of In:Ga = 7

[0150] :93) may be provided between the semiconductor layer 122 and the gate insulating layer 150, or gallium oxide may be provided. Alternatively, with the insulator 123 present, an In-Ga oxide may be provided between the insulator 123 and the gate insulating layer 150, or gallium oxide may be provided. The semiconductor layer 122 uses an oxide with a larger electron affinity than the insulator 121 and the insulator 123.

[0151] For example, as the semiconductor layer 122, the electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, higher than that of the insulator 121 and the insulator 123.

[0152] than that of the insulator 121 and the insulator 123. More preferably, an oxide having a larger value of 0.2 eV or more and 0.4 eV or less can be used.

[0153] The transistor shown in this embodiment includes one or more metal elements constituting the semiconductor layer 122 and has the insulators 121 and 123. Therefore, it is difficult to form interface levels at the interface between the insulator 121 and the semiconductor layer 122 and at the interface between the insulator 123 and the semiconductor layer 122. Therefore, by providing the insulators 121 and 123, variations and fluctuations in any electrical characteristics such as the threshold voltage of the transistor can be reduced.

[0154] 《Source electrode layer 130, Drain electrode layer 140》 The source electrode layer 130 and the drain electrode layer 140 are made of a single substance, an alloy, or a compound containing oxygen, nitrogen, fluorine, silicon, etc. having these as main components, such as copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr), etc. It is preferable to use a single layer or a stacked layer of a conductive layer. For example, when stacking, the lower conductive layer in contact with the semiconductor layer 122 has a material that easily binds to oxygen, and the upper conductive layer has a material with strong oxidation resistance. It is also preferable to use high melting point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity. It is also preferable to form it with a low resistance conductive material such as aluminum or copper. Furthermore, when using a Cu-Mn alloy, oxidation at the interface with an oxygen-containing insulator can be prevented. It is preferable to form manganese because manganese oxide has the function of suppressing the diffusion of Cu. Also when tantalum nitride is used, it has the effect of suppressing the diffusion of hydrogen and oxygen (barrier property), and also tantalum nitride itself has the effect of being difficult to oxidize, which is preferable.

[0155] Also, when a conductive material that easily binds to oxygen is brought into contact with the oxide semiconductor layer, oxygen in the oxide semiconductor layer diffuses to the side of the conductive material that easily binds to oxygen. Oxygen deficiency occurs in the region near the contact with the source electrode layer or drain electrode layer of the oxide semiconductor layer, and hydrogen contained slightly in the film enters the oxygen deficiency, causing the region to be significantly n-type. Therefore the n-type region can be used as the source or drain of the transistor. Thus .

[0156] For example, by using W as the lower conductive layer and Pt as the upper conductive layer to form a stacked structure while making the contacted oxide semiconductor n-type, oxidation of the conductive layer due to contact with the insulating layer 175 can be suppressed.

[0157] 《Gate Insulating Layer 150》 The gate insulating layer 150 can contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al ), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge ), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd) , hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy) , silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx ), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (La Ox), neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide ( TaOx) can be used. Also, the gate insulating layer 150 may be a stack of the above mentioned materials. Note that the gate insulating layer 150 may contain lanthanum (La), nitrogen, zirconium (Zr), etc. as impurities.

[0158] Next, an example of the stacked structure of the gate insulating layer 150 will be described. The gate insulating layer 150 has, for example, oxygen, nitrogen, silicon, hafnium, etc. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride.

[0159] Hafnium oxide has a higher relative permittivity than silicon oxide and silicon oxynitride. Therefore, compared with the case of using silicon oxide, the film thickness of the gate insulating layer 150 can be increased, so that the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative permittivity than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited to these.

[0160] By the way, the surface to be formed of hafnium oxide having a crystal structure has interface levels caused by defects. There are cases where it occurs. The interface level may function as a trap center. Therefore, When hafnium oxide is disposed close to the channel region of the transistor, the interface level may cause the electrical characteristics of the transistor to deteriorate. Therefore, in order to reduce the influence of the interface level it may be preferable to dispose another film between the channel region of the transistor and hafnium oxide to separate them from each other. This film has a buffer function . The film having the buffer function may be a film included in the gate insulating layer 150, or may be a film included in the oxide semiconductor film. That is, as the film having the buffer function, silicon oxide , silicon oxynitride, an oxide semiconductor, etc. can be used. Note that for the film having the buffer function a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region, for example, is used . Or, for the film having the buffer function, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region, for example, is used . Or, for the film having the buffer function, a semiconductor or insulator having a larger ionization energy than the semiconductor that becomes the channel region, for example, is used .

[0161] On the other hand, there are cases where the threshold voltage of the transistor can be controlled by trapping charges in the interface level (trap center) on the formed surface of hafnium oxide having the crystal structure described above . In order for the charge to exist stably, for example, an insulator having a larger energy gap than hafnium oxide may be disposed between the channel region and hafnium oxide . Or, a semiconductor or insulator having a smaller electron affinity than hafnium oxide may be disposed . Or, for the film having the buffer function, an insulator having a larger ionization energy than hafnium oxide may be disposed. Or, a semiconductor or insulator having a smaller electron affinity than hafnium oxide may be disposed . Or, for the film having the buffer function, an insulator having a larger ionization energy than hafnium oxide A semiconductor or insulator may be disposed. By using such an insulator, it becomes difficult for the charges trapped at the interface levels to be released, and the charges can be retained over a long period of time. This can be achieved.

[0162] Examples of such an insulator include silicon oxide and silicon oxynitride. In order to trap charges at the interface levels in the gate insulating layer 150, electrons may be moved from the oxide semiconductor film toward the gate electrode layer 160. As a specific example, at a high temperature (for example, 125 °C or higher and 450 °C or lower, typically 150 °C or higher and 300 °C or lower), the potential of the gate electrode layer 160 is set higher than the potentials of the source electrode layer 130 and the drain electrode layer 140 and maintained for 1 second or longer, typically 1 minute or longer.

[0163] In the transistor in which a desired amount of electrons are trapped at the interface levels such as the gate insulating layer 150 in this way, the threshold voltage shifts to the positive side. By adjusting the voltage of the gate electrode layer 160 and the time for applying the voltage, the amount of electrons trapped (the amount of variation in the threshold voltage) can be controlled. Note that even if it is not within the gate insulating layer 150, as long as charges can be trapped, it does not matter. A laminated film having a similar structure may be used for other insulating layers.

[0164] 《Gate Electrode Layer 160》 For the gate electrode layer 160, for example, conductive films such as aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), and tungsten (W) can be used. Also, the gate electrode ​ The polar layer 160 can be laminated. Also, a conductive film containing nitrogen, such as a nitride of the above material, may be used. Further, when tantalum nitride is used, it has an effect of suppressing the diffusion of hydrogen and oxygen (barrier property), and tantalum nitride itself has an effect of being difficult to oxidize, so it is preferable.

[0165] 《Insulating layer 170》 The insulating layer 170 can contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example, an insulating film containing one or more of aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx) can be used. Also, the insulating layer 170 may be a laminate of the above materials.

[0166] Also, for the insulating layer 170, an oxide containing In or Zn may be used. Typically, In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) are available.

[0167] ​​​​​​​​​​​​​​​The insulating layer 170 preferably includes an aluminum oxide film. The aluminum oxide film is Has a barrier effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the membrane Therefore, the aluminum oxide film can be used during and after the manufacturing process of the transistor. After manufacturing, the insulation of impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of transistors Preventing contamination of the semiconductor layer 122 with oxygen, which is the main component material, The insulating layer 110 is provided with a protective layer 122 to prevent unnecessary release of oxygen. It is suitable for use as a protective film.

[0168] In addition, the insulating layer 170 is preferably a film having an oxygen supplying ability. When the insulating film 170a is formed, a mixed layer of the insulating layer 170 and the insulating layer 175 is formed. The mixed layer or insulating layer 175 is doped with oxygen, and the oxygen is then converted into The oxygen diffuses into the oxide semiconductor and can compensate for oxygen vacancies in the oxide semiconductor. This makes it possible to improve the transistor characteristics (eg, threshold value, reliability, etc.).

[0169] In addition, another insulating layer may be provided above or below the insulating layer 170. For example, an oxide Magnesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, oxide Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, An insulating film containing one or more of neodymium oxide, hafnium oxide, and tantalum oxide may be used. Oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), Silicon (Si), Gallium (Ga), Germanium (Ge), Yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (H f), tantalum (Ta), titanium (Ti), etc. can be included. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), silicon nitride ( SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx) can be used as an insulating film containing one or more. Also, the insulating layer may be a laminate of the above materials . The insulating layer preferably has more oxygen than the stoichiometric composition. Oxygen released from the insulating layer can be diffused through the gate insulating layer 150 into the channel formation region of the semiconductor layer 120. Therefore, oxygen can fill the oxygen vacancies formed in the channel formation region. Thus, stable electrical characteristics of the transistor can be obtained.

[0170] 《Insulating layer 173 and insulating layer 175》 The insulating layer 173 and the insulating layer 175 can contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example, magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNx), silicon nitride oxide (SiNxOx), silicon nitride (S iNx), etc. can be included. iNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), tantalum oxide (TaOx), aluminum oxide (AlOx), an insulating film containing one or more of these can be used. Also, the insulating layer 17 3 and the insulating layer 175 may be a laminate of the above materials. The insulating layer preferably has more oxygen than the stoichiometric composition.

[0171] Alternatively, the insulating layer 173 and the insulating layer 175 may be made of a low dielectric constant material (Low-k material). For example, silicon oxide with a few percent of fluorine (F) introduced (SiOF), silicon oxide with a few percent of carbon (C) introduced (SiOC), fluorinated silicate glass (FSG), organic silicate glass (OSG), hydrogenated silsesquioxane (HSQ), methylsilsesquioxane (MSQ), organic polymers, polyimide, fluororesin (such as polytetrafluoroethylene), amorphous carbon with fluorine added, etc. can be used to form them. By using a Low-k material for the insulating layer 173 and the insulating layer 175, the capacitance related to the transistor 10 can be further reduced.

[0172] <Conductive layer 165> In addition, the transistor 10 can have a conductive layer 165 under the insulating layer 110 as shown in FIG. 2, and the conductive layer 165 can function as a bottom gate. The conductive layer can be given the same potential as the gate electrode layer 160 as shown in FIG. 2(B), or a different potential as shown in FIG. 2( D). For the conductive layer 165, for example, copper (C u), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (C r), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), a single substance made of materials such as platinum (Pt), iridium (Ir), strontium (Sr), or an alloy, or a single layer or a laminate of a conductive layer containing compounds such as oxygen, nitrogen, fluorine, silicon, etc. having these as main components is preferably used. For example, the conductive layer 166 can have a material with strong oxidation resistance. Also, for the conductive layer 167, it is preferable to use a high melting point material such as tungsten or molybdenum that can achieve both heat resistance and conductivity. Further, it is preferably formed of a low resistance conductive material such as aluminum or copper.

[0173] <Method for manufacturing a transistor> Next, the manufacturing method of the semiconductor device of this embodiment will be described with reference to FIGS. 6 to 14. Note that parts overlapping with the parts described in the configuration of the above transistor will be omitted. Also, the direction A1 - A2 shown in FIGS. 6 to 14 may be referred to as the channel length direction shown in FIGS. 1(A) and 1(B). Further, the direction A3 - A4 shown in FIGS. 6 to 14 may be referred to as the channel width direction shown in FIGS. 1(A ) and 1(C).

[0174] In this embodiment, each layer (insulating layer, oxide semiconductor layer, conductive layer, etc.) constituting the transistor can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method. Alternatively, it can be formed by a coating method or a printing method. As the film formation method, a sputtering method, a plasma enhanced chemical vapor deposition (PECVD ​ ) Although the [method] is representative, the thermal CVD method may also be used. As an example of the thermal CVD method, MOCVD (metal-organic chemical vapor deposition) method or ALD (atomic layer deposition) method may be used.

[0175] <Thermal CVD method> Since the thermal CVD method is a film-forming method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0176] Also, in the thermal CVD method, a source gas and an oxidizing agent are simultaneously fed into the chamber, and the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the reaction is carried out near or on the substrate to deposit a film on the substrate. Film formation may be performed.

[0177] Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described so far. For example, when forming an In -Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In (CH3)3. Also, the chemical formula of trimethylgallium is Ga(CH3)3. . Also, the chemical formula of dimethylzinc is Zn(CH3)2. Also, these combinations are not limited thereto, and triethylgallium (chemical formula Ga(C2H5 )3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5 )2) can be used instead of dimethylzinc.

[0178] <ALD method> A film-forming apparatus using a conventional CVD method, during film formation, a source gas (precursor) for the reaction One or more of them are simultaneously supplied to the chamber. The film forming apparatus using the ALD method is Precursors for the reaction are sequentially introduced into the chamber, and the order of gas introduction is repeated to form a film. For example, each switching valve (also called a high-speed valve) is switched to supply two or more types of precursors to the chamber in order, and an inert gas (such as argon or nitrogen) etc. is introduced after the first precursor so that the plurality of types of precursors are not mixed and the second precursor is introduced. Also, instead of introducing an inert gas, after exhausting the first precursor by vacuum evacuation, the second precursor can be introduced.

[0179] Figs. 4(A), (B), (C), and (D) show the film forming process of the ALD method. The first precursor 6 01 adsorbs on the surface of the substrate (see Fig. 4(A)), and the first single layer is formed (see Fig. 4(B ). At this time, metal atoms etc. contained in the precursor can combine with the hydroxyl groups present on the substrate surface. The metal atoms may have alkyl groups such as methyl groups or ethyl groups bonded thereto. After exhausting the first precursor 601, it reacts with the second precursor 602 introduced (see Fig. 4(C)), and the second single layer is laminated on the first single layer to form a thin film (see Fig. 4(D)). For example, when the second precursor contains an oxidizing agent, a chemical reaction occurs between the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms and the oxidizing agent, and an oxide film can be formed. Also, if a gas having hydrogen is used as the second precursor, a metal film can be formed by a reduction reaction.

[0180] ​​The ALD method is a film formation method based on surface chemical reactions. The precursor adsorbs onto the surface of the film to be formed, and a single layer is formed by the action of the self-limiting mechanism. For example, a precursor such as trimethylaluminum reacts with the hydroxyl groups (OH groups) present on the surface of the film to be formed. At this time, since only surface reactions by heat occur, the precursor can come into contact with the surface of the film to be formed, and metal atoms, etc. in the precursor can adsorb onto the surface of the film to be formed via thermal energy. In addition, the precursor has a high vapor pressure, is thermally stable and does not self-decompose at the stage before film formation, and has characteristics such as fast chemisorption onto the substrate. Moreover, since the precursor is introduced as a gas, if there is sufficient time for the precursors introduced alternately to diffuse, even in a region with high aspect ratio irregularities, a film can be formed with good coverage. Furthermore, in the ALD method, by controlling the gas introduction order and repeating a plurality of times until the desired thickness is reached, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetitions,

[0181] precise film thickness adjustment is possible. Also, by increasing the evacuation capacity, the film formation rate can be increased, and furthermore, the impurity concentration in the film can be reduced. Moreover, in the ALD method, there are an ALD method using heat (thermal ALD method) and an ALD method using plasma ( plasma ALD method). In the thermal ALD method, the reaction of the precursor is carried out using thermal energy, and in the plasma ALD method, the reaction of the precursor is carried out in a radical state.

[0182] The ALD method can form extremely thin films with high precision. Even for a surface with irregularities, surface coverage is good, and a film can be formed with high uniformity. is good, and a film can be formed with high uniformity. is good, and a film can be formed with high uniformity.

[0183] The ALD method can form extremely thin films with high precision. Even for a surface with irregularities, surface coverage It has a high rate and a high film density.

[0184] <Plasma ALD> In addition, by forming a film by the plasma ALD method, compared with the ALD method using heat (thermal ALD method) it is possible to form a film at a lower temperature. The plasma ALD method can, for example, form a film even at 100°C or lower without reducing the film formation rate. Also, in the plasma ALD method, N2 can be radicalized by plasma, so it is possible to form not only oxides but also nitrides.

[0185] Also, in plasma ALD, the oxidizing power of the oxidant can be enhanced. As a result, when forming a film by ALD, the precursors remaining in the film or the organic components desorbed from the precursors can be reduced, and carbon, chlorine, hydrogen, etc. in the film can be reduced, and a film with a low impurity concentration can be obtained.

[0186] Also, when performing plasma ALD, radical species can be generated, and plasma can be generated in a state separated from the substrate, such as ICP (Inductively Coupled Plasma), and plasma damage to the substrate or the film on which the protective film is to be formed can be suppressed.

[0187] From the above, by using the plasma ALD method, compared with other film formation methods, the process temperature can be lowered, and the surface coverage rate can be increased, and the film can be formed. As a result, the intrusion of water and hydrogen from the outside can be suppressed. Therefore, the reliability of transistor characteristics can be improved.

[0188] <Explanation of the ALD apparatus> Fig. 5(A) shows an example of a film forming apparatus using the ALD method. The film forming apparatus using the ALD method includes a film forming chamber (chamber 1701), a raw material supply section 1711a, a raw material supply section 1711b, high-speed valves 1712a and 1712b which are flow controllers, a raw material inlet 1713 a, a raw material inlet 1713b, a raw material discharge port 1714, and an exhaust device 1715. The raw material inlets 1713a and 1713b installed in the chamber 1701 are respectively connected to the raw material supply sections 1711a and 1711b via supply pipes and valves, and the raw material discharge port 1714 is connected to the exhaust device 1715 via a discharge pipe, a valve, and a pressure regulator.

[0189] Inside the chamber, there is a substrate holder 1716 equipped with a heater, and the film forming substrate 1700 is placed on the substrate holder.

[0190] In the raw material supply sections 1711a and 1711b, raw material gas is formed from solid raw materials or liquid raw materials by means of vaporizers and heating means. Alternatively, the raw material supply sections 1711a and 1711b may be configured to supply raw material gas.

[0191] Also, although an example of providing two raw material supply sections 1711a and 1711b is shown, it is not particularly limited, and three or more may be provided. Also, the high-speed valves 1712a and 1712b can be precisely controlled by time, and are configured to supply either raw material gas or inert gas. The high-speed valves 1712a and 1712b are flow controllers for raw material gas, and can also be said to be flow controllers for inert gas.

[0192] In the film forming apparatus shown in Fig. 5(A), the film forming substrate 1700 is carried into the substrate holder 1716, After sealing the chamber 1701, the substrate to be film - formed is heated by the heater of the substrate holder 1716 to raise the substrate 1700 to a desired temperature (e.g., 100 °C or higher or 150 °C or higher), and a thin film is formed on the substrate surface by repeating the supply of the source gas , evacuation by the evacuation device 1715, supply of an inert gas, and evacuation by the evacuation device 1715.

[0193] In the film - forming apparatus shown in Fig. 5(A), by appropriately selecting the sources (such as volatile organometallic compounds) prepared in the source supply section 1711a and the source supply section 1711b, an insulating layer composed of an oxide (including composite oxides) containing one or more elements selected from hafnium (Hf), aluminum (Al), tantalum (Ta), zirconium (Zr), etc. can be formed. Specifically, an insulating layer composed of hafnium oxide, an insulating layer composed of aluminum oxide, an insulating layer composed of hafnium silicate, or an insulating layer composed of aluminum silicate can be formed. Also, by appropriately selecting the sources (such as volatile organometallic compounds) prepared in the source supply section 1711a and the source supply section 1711b, thin films such as a tungsten layer, a titanium layer and other metal layers, and a nitride layer such as a titanium nitride layer can also be formed.

[0194] For example, when forming a hafnium oxide layer by a film - forming apparatus using the ALD method, two types of gases, a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (such as hafnium alkoxide or hafnium amide such as tetrakis - dimethylamido hafnium (TDMAH)), and ozone (O3) as an oxidizing agent are used. In this case, either the source supply section 1711a or The first source gas supplied is TDMAH, and the second source gas supplied from the source gas supply unit 1711b is ozone. The chemical formula of tetrakis(dimethylamide)hafnium is Hf [N(CH3)2]4. As other materials, there are tetrakis(ethylmethylamine d)hafnium and the like. Note that nitrogen has a function of eliminating charge trapping levels. Therefore, by including nitrogen in the source gas, hafnium oxide with a low charge trapping level density can be formed into a film .

[0195] For example, when forming an aluminum oxide layer by a film forming apparatus using the ALD method, a source gas obtained by vaporizing a liquid (such as TMA) containing a solvent and an aluminum precursor compound and two types of gases, H2O as an oxidizing agent, are used. In this case, the first source gas supplied from the source gas supply unit 1711a is TMA, and the second source gas supplied from the source gas supply unit 1711b is H 2O. The chemical formula of trimethylaluminum is Al(CH3)3. Also, as other material liquids, there are tris(dimethylamide)aluminum, triisobutylaluminum um, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionato ) and the like.

[0196]

[0197] For example, when forming a silicon oxide film by a film forming apparatus using ALD, hexachlorosilane is adsorbed on the film forming surface, chlorine contained in the adsorbed material is removed, and radicals of an oxidizing gas (O2 , nitrous oxide) are supplied to react with the adsorbed material.

[0197] For example, when forming a tungsten film by a film forming apparatus using ALD, WF6 gas and B2H6 gas are sequentially introduced repeatedly to form an initial tungsten film, and then WF6 Tungsten films are formed by sequentially and repeatedly introducing gas and H2 gas. Note that B2H6 gas may be replaced with SiH4 gas.

[0198] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film-forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In- O layer, and then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer. Further, thereafter, Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, these gases may be mixed to form a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer as well. Note that H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH 3)3 gas, In(C2H5)3 gas may be used. Further, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used. used.

[0199] 《Multi-chamber film-forming apparatus》 Further, an example of a multi-chamber manufacturing apparatus having at least one film-forming apparatus shown in Fig. 5(A) is shown in Fig. 5(B). shown in Fig. 5(B).

[0200] The manufacturing apparatus shown in Fig. 5(B) can continuously form a laminated film without exposing it to the atmosphere, aiming to prevent the inclusion of impurities and improve throughput.

[0201] The manufacturing apparatus shown in Fig. 5(B) includes a load chamber 1702, a transfer chamber 1720, a pretreatment chamber 1703, It has at least chamber 1701 which is a film formation chamber and unload chamber 1706. Note that the chambers of the manufacturing apparatus (including load chamber, processing chamber, transfer chamber, film formation chamber, unload chamber, etc.) are preferably filled with an inert gas (such as nitrogen gas) with a controlled dew point to prevent adhesion of moisture, etc., and desirably maintain a reduced pressure.

[0202] Also, chambers 1704 and 1705 may be film formation apparatuses using the same ALD method as chamber 1701, or may be film formation apparatuses using the plasma CVD method, or may be film formation apparatuses using the sputtering method, or may be film formation apparatuses using the metalorganic chemical vapor deposition (MOCVD: Metal Organic Chemical Vapor Deposition) method.

[0203] For example, a film formation apparatus using the plasma CVD method is used as chamber 1704, and a film formation apparatus using the MOCVD method is used as chamber 1705, and an example of forming a laminated film is shown below.

[0204] In FIG. 5(B), a top view of the transfer chamber 1720 shows an example of a hexagon, but depending on the number of layers of the laminated film, it may be a manufacturing apparatus connected to more chambers as a polygon with more sides. Also, in FIG. 5(B), the top surface shape of the substrate is shown as a rectangle, but it is not particularly limited. Also, in FIG. 5(B), a single-wafer type example is shown, but it may also be a batch-type film formation apparatus for forming a film on a plurality of substrates at once.

[0205] <Formation of insulating layer 110> First, an insulating layer 110 is formed on the substrate 100. The insulating layer 110 is formed by the plasma CVD method, thermal ​​​By means of CVD method (MOCVD method, ALD method), sputtering method, etc., for example, aluminum oxide neodymium, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium magnesium, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium nium and tantalum oxide and other oxide insulating films, silicon nitride, silicon oxynitride, nitrogen aluminum nitride, aluminum oxynitride and other nitride insulating films, or a mixed material thereof can be used to form. Also, a laminate of the above materials may be used, and the upper layer of the laminate in contact with the first insulator film that will later become the insulator 121 can be a source of oxygen supply to the semiconductor layer 122 and is preferably formed of a material containing excessive oxygen .

[0206] For example, a silicon oxynitride film with a thickness of 100 nm can be used as the insulating layer 110 by plasma CVD method .

[0207] Next, a first heat treatment may be performed to desorb water, hydrogen, etc. contained in the insulating layer 110 . As a result, it is possible to reduce the concentration of water, hydrogen, etc. contained in the insulating layer 110, and by the heat treatment , it is possible to reduce the diffusion amount of water, hydrogen, etc. to the first oxide semiconductor film formed later .

[0208] <Formation of the first insulator film and semiconductor film> Subsequently, a first insulator film that will later become the insulator 121 and a semiconductor film that will later become the semiconductor layer 122 are formed on the insulating layer 110 . The first insulator film and the semiconductor film can be formed by sputtering method, MOCVD method, PLD method, etc., and it is more preferable to form by using the sputtering method . As the sputtering method, RF sputtering method, DC sputtering method, AC sputtering method, etc. can be used It is possible. Also, in the sputtering method, by forming using the facing target method (also called the facing electrode method, the gas phase sputtering method, the VDSP (Vapor Deposition Spattering) method), it is possible to reduce plasma damage during film formation. tering method, the VDSP (Vapor Deposition Spattering) method) can reduce plasma damage during film formation. tering method, the VDSP (Vapor Deposition Spattering) method) can reduce plasma damage during film formation. It is possible.

[0209] For example, when forming the first insulator film by the sputtering method, each chamber number in the sputtering apparatus should be evacuated to a high vacuum (5×10 Pa to 1×10 Pa) using an adsorption type vacuum exhaust pump such as a cryopump to remove impurities such as water that can become impurities for the oxide semiconductor as much as possible, and the substrate to be film-formed can be heated to 100°C or higher, preferably 40 -7 Pa to 1×10 -4 Pa or so), and it is preferable that the substrate to be film-formed can be heated to 100°C or higher, preferably 40 0°C or higher. Or, it is preferable to combine a turbo molecular pump and a cold trap so that gas containing carbon components, moisture, etc. does not flow back into the chamber from the exhaust system. Also, an exhaust system combining a turbo molecular pump and a cryopump may be used. tering method, the VDSP (Vapor Deposition Spattering) method) can reduce plasma damage during film formation. tering method, the VDSP (Vapor Deposition Spattering) method) can reduce plasma damage during film formation. tering method, the VDSP (Vapor Deposition Spattering) method) can reduce plasma damage during film formation.

[0210] To obtain a high-purity intrinsic oxide semiconductor, not only the chamber should be evacuated to a high vacuum, but also the sputtering gas should be made highly pure. The oxygen gas or argon gas used as the sputtering gas should be a gas with a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower. tering method, the VDSP (Vapor Deposition Spattering) method) can reduce plasma damage during film formation. tering method, the VDSP (Vapor Deposition Spattering) method) can reduce plasma damage during film formation. tering method, the VDSP (Vapor Deposition Spattering) method) can reduce plasma damage during film formation. tering method, the VDSP (Vapor Deposition Spattering) method) can reduce plasma damage during film formation.

[0211] The sputtering gas is appropriately selected from noble gases (typically argon), oxygen gas, and a mixed gas of noble gas and oxygen gas. In the case of a mixed gas of noble gas and oxygen gas, with respect to the noble gas, tering method, the VDSP (Vapor Deposition Spattering) method) can reduce plasma damage during film formation. It is preferable to increase the gas ratio of oxygen.

[0212] When forming the oxide semiconductor film, for example, when using the sputtering method, the substrate temperature is 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, more preferably 200°C or higher and 420°C or lower, and by forming the oxide semiconductor film, a CAAC-OS film can be formed.

[0213] The first insulator film can be selected such that its electron affinity is smaller than that of the semiconductor film. It is possible.

[0214] Also, the semiconductor film may have a higher indium content than the first insulator film and the second insulator film. In an oxide semiconductor, mainly the s orbitals of heavy metals contribute to carrier conduction. By increasing the In content, more s orbitals overlap. Therefore, an oxide with a higher In content than Ga has a higher mobility compared to an oxide with an In content equal to or less than that of Ga. For this reason, by using an oxide with a high indium content for the semiconductor layer 122, a transistor with high mobility can be realized.

[0215] Also, in the first insulator film and the semiconductor film, for example, when forming the film by sputtering, by using a sputtering apparatus of a multi-chamber type, the first insulator film and the semiconductor film can be continuously formed without being exposed to the atmosphere. In that case, it is possible to suppress the entry of unnecessary impurities and the like into the interface between the first insulator film and the semiconductor film, and it is possible to reduce the interface level. As a result, the electrical characteristics of the transistor, especially the characteristics in the reliability test, can be stabilized. ​

[0216] In addition, when there is damage in the semiconductor film, the presence of the first insulator film can move the semiconductor film that becomes a main conduction path away from the damaged part, and as a result, the electrical characteristics of the transistor, particularly the characteristics in the reliability test, can be stabilized. For example, as the first insulator film, an oxide semiconductor film formed to a thickness of 20 nm using a target of In:Ga:Zn = 1:3:4 (atomic ratio) by sputtering can be used. Also, as the semiconductor film, an oxide semiconductor film formed to a thickness of 15 nm using a target of In:Ga:Zn = 1:1:1 (atomic ratio) by sputtering can be used.

[0217] For example, as the first insulator film, an oxide semiconductor film formed to a thickness of 20 nm using a target of In:Ga:Zn = 1:3: 4 (atomic ratio) by sputtering can be used. Also, as the semiconductor film, an oxide semiconductor film formed to a thickness of 15 nm using a target of In:Ga:Zn = 1:1 :1 (atomic ratio) by sputtering can be used. :1 (atomic ratio) by sputtering can be used. It is also possible.

[0218] In addition, it is preferable to perform a second heat treatment after forming the first insulator film and the semiconductor film. By performing the second heat treatment, the amount of oxygen deficiency in the semiconductor film can be reduced. By performing the second heat treatment, the amount of oxygen deficiency in the semiconductor film can be reduced.

[0219] The temperature of the second heat treatment is 250 °C or higher and less than the substrate distortion point, preferably 300 °C or higher and 650 °C or lower, more preferably 350 °C or higher and 550 °C or lower. The temperature of the second heat treatment is 250 °C or higher and less than the substrate distortion point, preferably 300 °C or higher and 650 °C or lower, more preferably 350 °C or higher and 550 °C or lower.

[0220] The second heat treatment is performed in an inert gas atmosphere containing a noble gas such as helium, neon, argon, xenon, krypton, or nitrogen. Or, after heating in an inert gas atmosphere, it may be heated in an oxygen atmosphere or a dry air (air with a dew point of -80 °C or lower, preferably -100 °C or lower, preferably - 120 °C or lower). Or it may be performed under reduced pressure. Note that, in addition to the above dry air, it is preferable that the inert gas and the oxygen gas do not contain hydrogen, water, etc. 120 °C or lower). Or it may be performed under reduced pressure. Note that, in addition to the above dry air, it is preferable that the inert gas and the oxygen gas do not contain hydrogen, water, etc. 120 °C or lower). Or it may be performed under reduced pressure. Note that, in addition to the above dry air, it is preferable that the inert gas and the oxygen gas do not contain hydrogen, water, etc. , in addition to the above dry air, it is preferable that the inert gas and the oxygen gas do not contain hydrogen, water, etc. Typically, the dew point is -80°C or less, preferably -100°C or less. Treatment times range from 3 minutes to 24 hours.

[0221] In the second heat treatment, the heat transfer from a heating element such as a resistance heating element is used instead of an electric furnace. A device that heats the workpiece by induction or thermal radiation may be used. For example, the GRTA ( Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Ra RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device uses halogen lamps, metal Halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps The workpiece is heated by the radiation of light (electromagnetic waves) emitted from a lamp such as a high-pressure mercury lamp. The GRTA device is a device that performs the second heat treatment using high-temperature gas. The hot gas is an inert gas, such as nitrogen or a noble gas, such as argon. .

[0222] Note that the second heat treatment is performed after etching to form an insulator 121 and a semiconductor layer 122, which will be described later. may be performed after

[0223] For example, after heat treatment at 450°C for 1 hour in a nitrogen atmosphere, Heat treatment can be performed at 450° C. for 1 hour.

[0224] The above steps reduce oxygen vacancies in the semiconductor film and impurities such as hydrogen and water. In addition, a semiconductor film with a reduced localized level density can be formed.

[0225] <Formation of the first conductive film> Next, a first conductive film serving as the source electrode layer 130 and the drain electrode layer 140 is formed on the semiconductor film. The first conductive film can be formed by a sputtering method, a chemical vapor deposition (CVD) method (including a metalorganic chemical vapor deposition (MOCVD) method, a metal chemical vapor deposition method, an atomic layer deposition (ALD) method, or a plasma enhanced chemical vapor deposition (PECVD) method), a vapor deposition method, a pulsed laser deposition (PLD) method, etc. The first conductive film can be formed by using a sputtering method, a chemical vapor deposition (CVD) method (including a metalorganic chemical vapor deposition (MOCVD) method, a metal chemical vapor deposition method, an atomic layer deposition (ALD) method, or a plasma enhanced chemical vapor deposition (PECVD) method), a vapor deposition method, a pulsed laser deposition (PLD) method, etc. The first conductive film can be formed by using a sputtering method, a chemical vapor deposition (CVD) method (including a metalorganic chemical vapor deposition (MOCVD) method, a metal chemical vapor deposition method, an atomic layer deposition (ALD) method, or a plasma enhanced chemical vapor deposition (PECVD) method), a vapor deposition method, a pulsed laser deposition (PLD) method, etc. The first conductive film can be formed by using a sputtering method, a chemical vapor deposition (CVD) method (including a metalorganic chemical vapor deposition (MOCVD) method, a metal chemical vapor deposition method, an atomic layer deposition (ALD) method, or a plasma enhanced chemical vapor deposition (PECVD) method), a vapor deposition method, a pulsed laser deposition (PLD) method, etc.

[0226] The material of the first conductive film is preferably a single substance, an alloy, or a compound mainly composed of these materials, such as copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr), etc., which form a single layer or a laminate of the conductive film. For example, when laminating, the lower conductive layer in contact with the semiconductor layer 122 has a material that easily binds to oxygen, and the upper conductive layer can have a material with strong oxidation resistance. Also, it is preferable to use a high melting point material such as tungsten (W) or molybdenum (Mo) that achieves both heat resistance and conductivity. Further, it is preferable to form it with a low resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu. The material of the first conductive film is preferably a single substance, an alloy, or a compound mainly composed of these materials, such as copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr), etc., which form a single layer or a laminate of the conductive film. For example, when laminating, the lower conductive layer in contact with the semiconductor layer 122 has a material that easily binds to oxygen, and the upper conductive layer can have a material with strong oxidation resistance. Also, it is preferable to use a high melting point material such as tungsten (W) or molybdenum (Mo) that achieves both heat resistance and conductivity. Further, it is preferable to form it with a low resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu. The material of the first conductive film is preferably a single substance, an alloy, or a compound mainly composed of these materials, such as copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr), etc., which form a single layer or a laminate of the conductive film. For example, when laminating, the lower conductive layer in contact with the semiconductor layer 122 has a material that easily binds to oxygen, and the upper conductive layer can have a material with strong oxidation resistance. Also, it is preferable to use a high melting point material such as tungsten (W) or molybdenum (Mo) that achieves both heat resistance and conductivity. Further, it is preferable to form it with a low resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu. The material of the first conductive film is preferably a single substance, an alloy, or a compound mainly composed of these materials, such as copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr), etc., which form a single layer or a laminate of the conductive film. For example, when laminating, the lower conductive layer in contact with the semiconductor layer 122 has a material that easily binds to oxygen, and the upper conductive layer can have a material with strong oxidation resistance. Also, it is preferable to use a high melting point material such as tungsten (W) or molybdenum (Mo) that achieves both heat resistance and conductivity. Further, it is preferable to form it with a low resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu. The material of the first conductive film is preferably a single substance, an alloy, or a compound mainly composed of these materials, such as copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr), etc., which form a single layer or a laminate of the conductive film. For example, when laminating, the lower conductive layer in contact with the semiconductor layer 122 has a material that easily binds to oxygen, and the upper conductive layer can have a material with strong oxidation resistance. Also, it is preferable to use a high melting point material such as tungsten (W) or molybdenum (Mo) that achieves both heat resistance and conductivity. Further, it is preferable to form it with a low resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu. For example, when laminating, the lower conductive layer in contact with the semiconductor layer 122 has a material that easily binds to oxygen, and the upper conductive layer can have a material with strong oxidation resistance. Also, it is preferable to use a high melting point material such as tungsten (W) or molybdenum (Mo) that achieves both heat resistance and conductivity. Further, it is preferable to form it with a low resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu. For example, when laminating, the lower conductive layer in contact with the semiconductor layer 122 has a material that easily binds to oxygen, and the upper conductive layer can have a material with strong oxidation resistance. Also, it is preferable to use a high melting point material such as tungsten (W) or molybdenum (Mo) that achieves both heat resistance and conductivity. Further, it is preferable to form it with a low resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu. For example, when laminating, the lower conductive layer in contact with the semiconductor layer 122 has a material that easily binds to oxygen, and the upper conductive layer can have a material with strong oxidation resistance. Also, it is preferable to use a high melting point material such as tungsten (W) or molybdenum (Mo) that achieves both heat resistance and conductivity. Further, it is preferable to form it with a low resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu. Also, it is preferable to use a high melting point material such as tungsten (W) or molybdenum (Mo) that achieves both heat resistance and conductivity. Further, it is preferable to form it with a low resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu. Also, it is preferable to use a high melting point material such as tungsten (W) or molybdenum (Mo) that achieves both heat resistance and conductivity. Further, it is preferable to form it with a low resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu. Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu. Furthermore, when using a Cu-Mn alloy, it is preferable because a film containing manganese oxide is formed at the interface with an insulator containing oxygen, and manganese oxide has a function of suppressing the diffusion of Cu.

[0227] For example, a tungsten film with a thickness of 20 to 100 nm can be formed as the first conductive film by a sputtering method. For example, a tungsten film with a thickness of 20 to 100 nm can be formed as the first conductive film by a sputtering method.

[0228] Note that the conductive layer 130b formed by processing the first conductive film in a subsequent process has a function as a hard mask and functions as a source electrode layer and a drain electrode layer in this subsequent process and can eliminate the need for an additional film formation process, thus shortening the semiconductor manufacturing process . .

[0229] <Formation of Insulator 121 and Semiconductor Layer 122> Next, a resist mask is formed by a lithography process, and using the resist mask, the first conductive film is selectively etched in part to form the conductive layer 130b. Subsequently, after removing the resist on the conductive layer 130b, using the conductive layer 130b as a hard mask, the semiconductor film and the first oxide semiconductor film are selectively etched respectively to form the semiconductor layer 122 and the insulator 121 in an island shape (see Fig. 6). Note that as the etching method, a dry etching method can be used. Note that by using the conductive layer 130b as a hard mask to etch the semiconductor film and the first insulator film, the edge roughness of the oxide semiconductor layer after etching can be reduced compared with the case of using only the resist mask . For example, by using methane gas and argon gas as etching gases and selectively etching the first oxide semiconductor film and the semiconductor film using the resist mask and the hard mask , the insulator 121 and the semiconductor layer 122 can be formed. Note that at this time, part of the insulating layer 110 may be etched

[0230] . <Film Formation of Insulating Film> Next, an insulating film 173a that becomes the insulating layer 173 is formed on the insulating layer 110 and the conductive layer 130b .

[0231] ​​(see FIG. 7). The insulating film 173a can be formed by, for example, plasma CVD method, thermal CVD method (MOCVD method, AL D method), sputtering method, spin coating method, etc., such as aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx ), neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (Ta Ox) and other oxide insulating films, silicon nitride (SiNx), silicon oxynitride (SiNxO y), aluminum nitride (AlNx), aluminum oxynitride (AlNxOy) and other nitride insulating films, or a mixed material thereof. Further, a laminate of the above materials may be used.

[0232] Alternatively, the insulating film 173a may be made of a low dielectric constant material (Low-k material). For example , silicon oxide with a few percent of fluorine (F) introduced (SiOF), silicon oxide with a few percent of carbon (C) introduced (SiOC), fluorinated silicate glass (FSG), organic silicate glass (OSG), hydrogenated silsesquioxane (HSQ), methylsilsesquioxane ( MSQ), organic polymer, fluororesin (polytetrafluoroethylene), polyimide, amorphous carbon with fluorine added and the like can be used to form it.

[0233] Note that the second heat treatment may be performed after the formation of the insulating film 173a.

[0234] <Planarization of the second insulating film> Next, a planarization process of the insulating film 173a is performed until the conductive layer 130b is exposed, and the insulating layer 173 is formed (see Fig. 8). The planarization process can be performed using a method such as CMP (Chemical Mechanic al Polishing). Thereby, the film thickness of the insulating film 175a on the conductive layer 130b within the substrate surface described later can be made uniform.

[0235] Note that the second heat treatment may be performed after planarizing the insulating film 173a.

[0236] <Formation of Insulating Film> Next, a third insulating film 175a that becomes the insulating layer 175 is formed on the insulating layer 173 and the conductive layer 130b (see Fig. 9).

[0237] The insulating film 175a can be formed using the same materials and methods as the insulating film 173a.

[0238] <Formation of Groove Portion> Next, a resist mask 176 is formed on the insulating film 175a by a lithography process (see Fig. 10). Note that after applying an organic film on the insulating film 175a, or after applying an organic film on the resist, the lithography process may be performed. The organic film contains propylene gly col monomethyl ether, ethyl lactate, etc., and has a function as an anti-reflection film (BA RC, Bottom Anti Reflective Coating) during exposure, and in addition, can improve the adhesion between the resist and the film and the resolution.

[0239] Note that when forming a transistor with an extremely short channel length, at least in the region where the conductive layer 130b that becomes the source electrode layer 130 and the drain electrode layer 140 is divided, electron beam exposure, immersion exposure, EUV (EUV: Extreme Ultra- violet) exposure A resist mask is processed using a method suitable for fine line processing such as light, and then the etching process is The region can be etched by forming a resist mask by electron beam exposure. In this case, if a positive resist is used as the resist mask, the exposed area can be minimized. This makes it possible to improve the throughput. To form transistors with channel lengths of 100 nm or less, and even 30 nm or less. Alternatively, microfabrication may be performed by exposure technology using X-rays or the like.

[0240] Using the resist mask, the insulating film 175a is partially etched by dry etching. As a result, the insulating layer 175 is formed and the groove portion 174 is formed. is formed.

[0241] Next, the exposed conductive layer 130b is partially etched to separate the source electrode layer 13 0, the drain electrode layer 140 can be formed (see FIG. 11).

[0242] After the source electrode layer 130 and the drain electrode layer 140 are formed, etching residues are removed. In order to prevent this, a cleaning process may be performed. This can prevent short circuits in the drain electrode layer 140. Alkaline solutions such as tetramethylammonium hydroxide This can be done using an acidic solution such as diluted hydrofluoric acid, oxalic acid, or phosphoric acid. Note that the cleaning process etches a part of the semiconductor layer 122, and the semiconductor layer 122 is left untreated. A recess is formed.

[0243] For example, after planarizing the silicon oxynitride film formed as the insulating film 173a, a resist mask is formed on the silicon oxynitride film by lithography, and dry etching is performed using the resist mask and a gas containing carbon and fluorine to perform an opening process on the silicon oxynitride, and the conductive layer 130b is dry etched using a chlorine- and fluorine-based gas, whereby the source electrode layer 130 and the drain electrode layer 140 can be formed. On the silicon oxynitride film, a resist mask is formed by lithography, and dry etching is performed using the resist mask and a gas containing carbon and fluorine. By performing dry etching using the resist mask and a gas containing carbon and fluorine, an opening process for silicon oxynitride is performed, and the conductive layer 130b is dry etched using a chlorine- and fluorine-based gas. By performing dry etching using the resist mask and a gas containing carbon and fluorine, an opening process for silicon oxynitride is performed, and the conductive layer 130b is dry etched using a chlorine- and fluorine-based gas. By performing dry etching using the resist mask and a gas containing carbon and fluorine, an opening process for silicon oxynitride is performed, and the conductive layer 130b is dry etched using a chlorine- and fluorine-based gas, whereby the source electrode layer 130 and the drain electrode layer 140 can be formed.

[0244] <Formation of the second insulator film 123a> Next, a second insulator film 123a used as the insulator 123 is formed on the semiconductor layer 122 and the insulating layer 175. The second insulator film 123a can be formed in the same manner as the first insulator film, and the material of the second insulator film 123a can be selected so that the electron affinity is smaller than that of the semiconductor film. Next, a second insulator film 123a used as the insulator 123 is formed on the semiconductor layer 122 and the insulating layer 175. The second insulator film 123a can be formed in the same manner as the first insulator film, and the material of the second insulator film 123a can be selected so that the electron affinity is smaller than that of the semiconductor film. Next, a second insulator film 123a used as the insulator 123 is formed on the semiconductor layer 122 and the insulating layer 175. The second insulator film 123a can be formed in the same manner as the first insulator film, and the material of the second insulator film 123a can be selected so that the electron affinity is smaller than that of the semiconductor film. Next, a second insulator film 123a used as the insulator 123 is formed on the semiconductor layer 122 and the insulating layer 175. The second insulator film 123a can be formed in the same manner as the first insulator film, and the material of the second insulator film 123a can be selected so that the electron affinity is smaller than that of the semiconductor film.

[0245] For example, as the second insulator film 123a, an oxide semiconductor film formed by sputtering to a thickness of 5 nm using a target of In:Ga:Zn = 1:3:2 (atomic ratio) can be used. For example, as the second insulator film 123a, an oxide semiconductor film formed by sputtering to a thickness of 5 nm using a target of In:Ga:Zn = 1:3:2 (atomic ratio) can be used. For example, as the second insulator film 123a, an oxide semiconductor film formed by sputtering to a thickness of 5 nm using a target of In:Ga:Zn = 1:3:2 (atomic ratio) can be used.

[0246] <Formation of the insulating film 150a> Next, an insulating film 150a that becomes the gate insulating layer 150 is formed on the second insulator film 123a. For the insulating film 150a, for example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. are used. Next, an insulating film 150a that becomes the gate insulating layer 150 is formed on the second insulator film 123a. For the insulating film 150a, for example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. are used. Next, an insulating film 150a that becomes the gate insulating layer 150 is formed on the second insulator film 123a. For the insulating film 150a, for example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. are used. Next, an insulating film 150a that becomes the gate insulating layer 150 is formed on the second insulator film 123a. For the insulating film 150a, for example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. are used. Next, an insulating film 150a that becomes the gate insulating layer 150 is formed on the second insulator film 123a. For the insulating film 150a, for example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. are used. The insulating film 150a may be a laminate of the above materials. 0a is the method of sputtering, CVD (plasma CVD, MOCVD, ALD, etc.), M The insulating film 150a can be formed by using the BE method or the like. An insulating film can be formed by appropriately using a similar method.

[0247] For example, a silicon oxynitride film having a thickness of 10 nm is formed as the insulating film 150a by the plasma CVD method. It is possible.

[0248] <Formation of Conductive Film 160a> Next, a conductive film 160a that will become a gate electrode layer 160 is formed on the insulating film 150a (FIG. 1 The conductive film 160a may be made of, for example, aluminum (Al), titanium (Ti), Chromium (Cr), Cobalt (Co), Nickel (Ni), Copper (Cu), Yttrium (Y ), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), tungsten (W), or a combination of these The conductive film 160a can be formed by a sputtering method or a CVD method. Plasma CVD, MOCVD, ALD, etc.), MBE, vapor deposition, plating, etc. The conductive film 160a can be formed by using a conductive film containing nitrogen. Alternatively, a laminate of the conductive film and a conductive film containing nitrogen may be used. It may be a single layer or a multilayer.

[0249] For example, titanium nitride is formed to a thickness of 10 nm by the ALD method, and tungsten is deposited by metal CVD. A laminated structure formed to a thickness of 150 nm by a method can be used.

[0250] <Flattening process> Next, a planarization process is performed. The planarization process is performed using a method such as CMP or dry etching. The planarization process may be terminated when the insulating film 150a is exposed, or may be terminated after the first step. The step may be terminated when the insulating film 123a of the second insulating film 123 is exposed, or when the insulating layer 175 is exposed. This may result in the gate electrode layer 160, the gate insulating layer 150, and the insulating layer 12. 3 can be formed (see FIG. 13).

[0251] The second insulating film 123a or the insulating film 150a is formed on the planarized insulating layer 175. If the second insulating film 1 has a resist mask, it may be processed using a new resist mask. A resist mask is formed on the insulating film 23a or the insulating film 150a by a lithography process. The mask has an area larger than the upper surface of the gate electrode layer 160. The insulating film 150a and the second insulating film 123a are selectively etched to form a gate insulating layer. 150, an insulator 123 may be formed.

[0252] In the transistor 10, by providing the insulator 123 in which oxygen vacancies are unlikely to occur, The desorption of oxygen from the side surface of the insulator 123 in the channel width direction is suppressed, and the occurrence of oxygen vacancies is prevented. This results in improved electrical characteristics and a highly reliable transistor. This can be realized.

[0253] <Deposition of Insulating Layer 170> Next, the insulating layer 173, the insulator 123, the gate insulating layer 150, and the gate electrode layer 160 are An insulating layer 170 is then formed.

[0254] The insulating layer 170 can be formed by plasma CVD method, thermal CVD method (MOCVD method, ALD method), or sputtering method, etc. For example, oxide insulating films such as aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx), nitride insulating films such as silicon nitride (SiNx), silicon oxynitride (SiNxOy), aluminum nitride (AlNx), aluminum oxynitride (AlNxOy), or a mixed material thereof can be used. Also, a laminate of the above materials may be used. Further, for the insulating layer 170, an oxide containing In or Zn may be used. Typically, there are In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd). For example, the oxygen gas used during the formation of the insulating layer 170 is applied during film formation by sputtering method. When forming the aluminum oxide film, a mixed layer 171 is formed at the interface with the insulating layer 173. It is desirable to form an aluminum oxide film by sputtering method as the insulating layer 170. Also, it is desirable to use aluminum oxide as the sputtering target. Also, it is desirable that the gas used during film formation contains oxygen gas. Moreover, it is preferable to use aluminum oxide as the sputtering target. For the insulating layer 170, it is also possible to use oxides containing In or Zn. Typically, there are In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd). The insulating layer 170 can be formed using oxide insulating films such as aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx), nitride insulating films such as silicon nitride (SiNx), silicon oxynitride (SiNxOy), aluminum nitride (AlNx), aluminum oxynitride (AlNxOy), or a mixed material thereof. Or a laminate of these materials may be used. Also, it is possible to use a laminate of the above materials. For the insulating layer 170, an oxide containing In or Zn may be used. Typically, there are In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd). For example, the insulating layer 170 can be formed by plasma CVD method, thermal CVD method (MOCVD method, ALD method), or sputtering method, etc.

[0255] It is desirable to form an aluminum oxide film by sputtering method as the insulating layer 170. When forming the aluminum oxide film, a mixed layer 171 is formed at the interface with the insulating layer 173. It is also desirable to use aluminum oxide as the sputtering target.

[0256] When forming the aluminum oxide film, a mixed layer 171 is formed at the interface with the insulating layer 173. For example, the oxygen gas used during the formation of the insulating layer 170 is applied during film formation by sputtering method.

[0257] For example, the oxygen gas used during the formation of the insulating layer 170 is applied during film formation by sputtering method. Due to the influence of the applied voltage, power, plasma, substrate temperature, etc., oxygen radicals, oxygen ions, oxygen atoms, etc., exist in various states and have a state with higher energy compared to the stable state. At this time, oxygen (excess oxygen, referred to as exO) 172 is added into the insulating layer 173 or the mixed layer 171.

[0258] <Oxygen addition> In addition, when manufacturing the transistor 10, it is not limited to the above method, and the process of adding oxygen may be performed separately. The process of adding the oxygen may be performed on the insulating layer 110, or on the first oxide semiconductor film or the second insulator film 123a described above. As the oxygen to be added, any one or more of oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. is used. In addition, as the method of adding oxygen, there are an ion doping method, an ion implantation method, a plasma immersion ion implantation method, etc.

[0259] When using the ion implantation method as the method of adding oxygen, oxygen atomic ions may be used, or oxygen molecular ions may be used. When using oxygen molecular ions, it is possible to reduce the damage to the film to which the addition is made. Oxygen molecular ions are separated on the surface of the film to which the oxygen is added and are added as oxygen atomic ions. Since energy is used to separate oxygen molecules into oxygen atoms, when oxygen molecular ions are added to the film to which the oxygen is added, the energy per oxygen atomic ion is lower compared to the case where oxygen atomic ions are added to the film to which the oxygen is added. Therefore, the damage to the film to which the oxygen is added can be reduced.

[0260] In addition, when oxygen molecular ions are implanted, the oxygen is more easily absorbed than when oxygen atomic ions are implanted. The energy per atomic ion is low. Therefore, it is possible to implant oxygen molecular ions. This allows the acceleration voltage to be increased, and the throughput to be improved. In addition, by using oxygen molecular ions, compared to the case of using oxygen atomic ions, It is possible to halve the dose to add the same amount of oxygen atomic ions. As a result, the throughput of the manufacturing process can be increased.

[0261] In addition, when oxygen is added to the film to which the oxygen is added, oxygen atoms are added to the film to which the oxygen is added. The oxygen is added under conditions such that the peak of the concentration profile of the molecular ions is located. It is preferable to add oxygen to the film to be etched. As a result, the film is more resistant to oxygen ion implantation than when oxygen atomic ions are implanted. In addition, the acceleration voltage during implantation can be lowered, reducing damage to the film to which the oxygen is added. That is, the amount of defects in the film to which oxygen is added can be reduced. It is possible to suppress the change in the electrical characteristics of the transistor. This reduces damage to the film that is being processed, and suppresses fluctuations in the electrical characteristics of the transistor. It can be controlled.

[0262] Also, a plasma method is used in which a film to which oxygen is added is exposed to plasma generated in an atmosphere containing oxygen. By plasma immersion ion implantation (PIA), oxygen is added to the film to which the oxygen is added. The oxygen-containing atmosphere may be oxygen, ozone, nitrous oxide, nitrogen dioxide, or the like. The atmosphere contains a chemical gas. By exposing the film to which oxygen is to be added to the plasma, oxygen is added to the film to which oxygen is to be added. It is possible and preferable to increase the dosage. An example of an apparatus for performing such plasma treatment is an ashing apparatus.

[0263] For example, when the acceleration voltage is 5 kV and the dose amount is 1×10 16 / cm 2 of oxygen molecular ions can be added to the first oxide semiconductor film by ion implantation method.

[0264] By combining the above steps and subsequent heat treatment, the oxygen deficiency amount of the semiconductor layer 122 can be reduced. Note that the film with oxygen added has a lower film density compared to the film before oxygen addition.

[0265] Next, a third heat treatment may be performed. The third heat treatment is typically 150 °C or higher and below the glass transition point, preferably 250 °C or higher and 500 °C or lower, more preferably 300 °C or higher and 45 0 °C or lower. By this heat treatment, the added oxygen 172 diffuses and moves to the semiconductor layer 122, and oxygen can be supplied to the oxygen deficiencies present in the semiconductor layer 122 (see FIG. 14).

[0266] For example, by sputtering method, using an aluminum oxide (AlOx) target and containing 50% by volume of oxygen gas as the gas during sputtering, the insulating layer 170 can be formed. The thickness can be 20 nm to 40 nm. Also, as the third heat treatment, heat treatment can be performed at 400 °C for 1 hour in an oxygen atmosphere.

[0267] Through the above steps, the density of localized levels in the semiconductor film is reduced, and a transistor having excellent electrical characteristics A dissta can be fabricated. Also, a transistor with little variation in electrical characteristics over time and under stress tests and high reliability can be fabricated. A transistor with little variation in electrical characteristics over time and under stress tests and high reliability can be fabricated.

[0268] (Embodiment 2) In this embodiment, a method for fabricating transistors 11 and 12 with a structure different from that of transistor 10 described in Embodiment 1 will be described. A method for fabricating transistors 11 and 12 with a structure different from that of transistor 10 described in Embodiment 1 will be described.

[0269] <Modified Example 1 of Transistor 10: Transistor 11> Transistor 11, which has a different shape from transistor 10 shown in Fig. 1, will be described with reference to Fig. 15. A description will be given.

[0270] Figs. 15(A), 15(B), and 15(C) are top views and cross-sectional views of transistor 11. Fig. 15(A) is a top view of transistor 11, Fig. 15(B) is a cross-sectional view between the dashed line A1 - A2 in Fig. 15(A), and Fig. 15(C) is a cross-sectional view between A3 - A4. Figs. 15(A), 15(B), and 15(C) are top views and cross-sectional views of transistor 11.

[0271] Transistor 11 is different from transistor 10 in that the insulating layer 170 has a region in contact with the sides of the insulator 121, semiconductor layer 122, source electrode layer 13 0, drain electrode layer 140, and insulating layer 175. Figs. 15(A), 15(B), and 15(C) are top views and cross-sectional views of transistor 11.

[0272] Also, transistor 11 is different from the manufacturing method of transistor 10 in that the insulator 121, semiconductor layer 122, source electrode layer 130, drain electrode layer 140, and insulating layer 175 are formed in the same process, and no planarization process is performed in each process. Figs. 15(A), 15(B), and 15(C) are top views and cross-sectional views of transistor 11.

[0273] <Method for Fabricating Transistor 11> The method for fabricating transistor 11 will be described with reference to Figs. 16 to 23. Note that in Embodiment 1 For steps similar to those for the transistor 10 described above, the description therefor is incorporated herein by reference.

[0274] As shown in FIG. 16(A) and FIG. 16(B), the first insulating layer 110 and the first insulating material 121 are The insulating film 121a, the semiconductor film 122a which becomes the semiconductor layer 122, the source electrode layer 130, and the drain electrode layer 130 are The conductive film 130a which becomes the rain electrode layer 140 and the insulating film 175a which becomes the insulating layer 175 are formed. A resist mask 176 is formed on the insulating film 175a by using a lithography method.

[0275] Next, the insulating film 175a and the conductive film 130a are partially etched using the resist mask 176. Then, the groove 174, the insulating layer 175b, and the conductive layer 130b are formed (see FIG. 17).

[0276] Next, the insulating layer 175b, the conductive layer 130b, the semiconductor film 122a, and the The insulating film 121a of the first insulating film 121 is partially etched to remove the insulating film 121, the semiconductor layer 122, and the source electrode 123. The layer 130, the drain electrode layer 140, and the insulating layer 175 are formed (see FIG. 18).

[0277] Next, a second insulating film 123a which becomes the insulator 123 and an insulating film 1 which becomes the gate insulating layer 150 are formed. 50a, and a conductive film 160a which will become a gate electrode layer 160 are sequentially formed (see FIG. 19).

[0278] Next, a conductive film 160a and an insulating film 160b are formed using a resist mask formed by lithography. The insulating film 150a and the second insulating film 123a are partially etched, and the insulating film 123 and the A gate insulating layer 150 and a gate electrode layer 160 are formed (see FIG. 20).

[0279] The insulator 123, the gate insulating layer 150, and the gate electrode layer 160 do not have to be formed at the same time. is also acceptable. As shown in FIGS. 21 and 22, the insulator 123 may be formed without etching the insulating film 150a , and the gate electrode layer 160 may be formed. Also, the end of the insulator 123 and the gate insulating layer 1 50 and the end of the gate electrode layer 160 may be formed so as not to overlap.

[0280] Next, the insulating layer 170 is formed, and by performing a heat treatment, oxygen 172 can be diffused to the semiconductor layer 122 to reduce oxygen vacancies in the semiconductor layer 122 (see FIG. 23).

[0281] Through the above steps, the transistor 11 can be fabricated.

[0282] In the method of manufacturing the transistor 11, the insulating film 175a that becomes the insulating layer 175 can be formed before processing the source electrode layer 1 30 and the conductive film 130a that becomes the drain electrode layer 140. Therefore, the film thickness of the insulating film 175a can be made uniform within the substrate surface, and the etching treatment time during the formation of the groove portion 174 can be stabilized. As a result, the transistor 11 can be stably fabricated, and the shape of the transistor can be stabilized. Therefore, the transistor characteristics can be stabilized. fabricated, and the shape of the transistor can be stabilized. Therefore, the transistor characteristics can be stabilized.

[0283] <Modification Example 2 of Transistor 10: Transistor 12> The transistor 12 having a shape different from that of the transistor 10 shown in FIG. 1 will be described with reference to FIG. 24.

[0284] FIGS. 24(A), 24(B), and 24(C) are top views and cross-sectional views of the transistor 12 . FIG. 24(A) is a top view of the transistor 12, and FIG. 24(B) is a cross-sectional view between the dashed line A1 - A2 in FIG. 24(A ), and FIG. 24(C) is a cross-sectional view between A3 - A4.

[0285] ​​​ Transistor 12 differs from transistor 10 in that it has an insulating layer 177 .

[0286] As described later, the first insulating film 121a which becomes the insulator 121, the semiconductor layer 122, the conductive film 110 which is to become the source electrode layer 130 and the drain electrode layer 140; 30a, an insulating film 175a which becomes the insulating layer 175, and an insulating film 177a which becomes the insulating layer 177. This method differs from the method for manufacturing the transistor 10 in that the above films are formed before processing each of the above films.

[0287] <Method of manufacturing transistor 12> A method for manufacturing the transistor 12 will be described with reference to FIGS. For steps similar to those for the transistor 10 described above, the description therefor is incorporated herein by reference.

[0288] A first insulating film 121a which becomes the insulator 121 and a semiconductor layer 122 are formed on the insulating layer 110. Conductive film 122a, conductive film 130a which will become source electrode layer 130 and drain electrode layer 140 , an insulating film 175a which becomes the insulating layer 175, and an insulating film 177a which becomes the insulating layer 177. Before processing, films are formed in sequence (see FIG. 25).

[0289] The insulating layer 177 can be formed of the same material and by the same method as the insulating layer 170. Cut.

[0290] Next, the insulating film 177a, the insulating film 175a, the conductive film 130a, and the semiconductor The insulating film 122a and the first insulating film 121a are partially etched to leave the insulator 121 and the semiconductor layer 122, a conductive layer 130b, an insulating layer 175b, and an insulating layer 171b are formed (see FIG. 26). At this time, the insulating layer 110 may be partially etched.

[0291] Next, an insulating film 173a that will become the insulating layer 173 is formed (see FIG. 27). The insulating film 173a can be formed by a plasma CVD method, a thermal CVD method (MOCVD method, ALD method), a sputtering method, or a spin coating method or the like.

[0292] Next, the insulating film 173a is subjected to a planarization process by CMP until the insulating layer 171b is exposed to form the insulating layer 173 (see FIG. 28). Note that the insulating layer 171b has a low polishing rate under the same CMP processing conditions as the insulating layer 173, that is, it preferably has a function as a stopper. That is, it preferably has a function as a stopper.

[0293] Next, a resist mask is formed on the insulating layer 173 and the insulating layer 171b by a lithography method, and further, using the insulating layer 171b as a hard mask, the conductive layer 130b is partially selectively etched until the semiconductor layer 122 is exposed. Thereby, the source electrode layer 130, the drain electrode layer 140, and the insulating layer 175 are formed (see FIG. 29).

[0294] Next, the second insulator film 123a, the insulating film 150a, and the conductive film 160a are sequentially formed (see FIG. 3 0).

[0295] Next, a planarization process is performed on the conductive film 160a, the insulating film 150a, and the second insulator film 123a to form the insulator 123, the gate insulating layer 150, and the gate electrode layer 160 (see FIG. 31).

[0296] Next, an insulating layer 170 is formed, and by performing a heat treatment, oxygen 172 can be diffused to the semiconductor layer 122 to reduce oxygen deficiency in the semiconductor layer 122 (see FIG. 32).

[0297] ​​​​​​ Through the above process, the transistor 12 can be fabricated.

[0298] In the method of fabricating the transistor 12, the insulating film 175a that becomes the insulating layer 175 can be formed before processing the conductive film 130a that becomes the source electrode layer 1 30 and the drain electrode layer 140. Therefore, the film thickness of the insulating film 175a can be made uniform within the plane of the substrate, and the etching processing time during the formation of the groove portion 174 can be stabilized. As a result, the transistor 12 can be stably fabricated, and the shape of the transistor can be stabilized. Therefore, the transistor characteristics (for example, threshold value, reliability, etc.) can also be stabilized.

[0299] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. .

[0300] (Embodiment 3) <Structure of Oxide Semiconductor> In this embodiment, the structure of the oxide semiconductor will be described.

[0301] The oxide semiconductor can be divided into a single-crystalline oxide semiconductor and other non-single-crystalline oxide semiconductors. Examples of the non-single-crystalline oxide semiconductor include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline Oxide Semicondu ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li ke Oxide Semiconductor), and amorphous oxide semiconductors.

[0302] From another perspective, oxide semiconductors can be divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

[0303] Generally, the definition of an amorphous structure is known to be not fixed in a metastable state, isotropic, and having no heterogeneous structure. It can also be rephrased as a structure with flexible bond angles, having short-range order but no long-range order.

[0304] Conversely, in the case of an essentially stable oxide semiconductor, it cannot be called a completely amorphous (completely amorphous) oxide semiconductor. Also, an anisotropic (for example, having a periodic structure in a micro region) oxide semiconductor cannot be called a completely amorphous oxide semiconductor. However, although a-like OS has a periodic structure in a micro region, it has voids (also called voids) and is an unstable structure. Therefore, it can be said that its physical properties are close to those of an amorphous oxide semiconductor.

[0305] <caac-os> First, CAAC-OS will be described.

[0306] CAAC-OS is one of the oxide semiconductors having a plurality of c-axis oriented crystal parts (also referred to as pellets). conductors.

[0307] Using a transmission electron microscope (TEM: Transmission Electron Micro scope), when observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of CAAC-OS, a plurality of pellets can be confirmed. On the other hand , in a high-resolution TEM image, the boundaries between pellets, that is, grain boundaries (also referred to as grain boundaries ), cannot be clearly confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0308] Hereinafter, CAAC-OS observed by TEM will be described. Fig. 33(A) shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction substantially parallel to the sample surface. High For the observation of a high-resolution TEM image, a spherical aberration correction (Spherical Aberration Corrector) function is used. A high-resolution TEM image using a spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The acquisition of a Cs-corrected high-resolution TEM image can be performed, for example, by using a JEOL JEM-ARM200F atomic-resolution analytical electron microscope manufactured by JEOL Ltd.

[0309] An enlarged Cs-corrected high-resolution TEM image of the region (1) in Fig. 33(A) is shown in Fig. 33(B). From Fig. 33(B), it can be confirmed that in the pellet, metal atoms are arranged in layers. 。The arrangement of each layer of metal atoms reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface on which the CAAC-OS film is formed, and is parallel to the surface to be formed or the upper surface of the CAAC-OS. That is, it is parallel to the surface to be formed or the upper surface of the CAAC-OS, reflecting the unevenness of the surface to be formed or the upper surface.

[0310] As shown in FIG. 33(B), CAAC-OS has a characteristic atomic arrangement. FIG. 33(C) shows the characteristic atomic arrangement indicated by auxiliary lines. From FIGS. 33(B) and 33(C) it can be seen that the size of one pellet is 1 nm or more or 3 nm or more, and the size of the gap formed by the inclination between pellets is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). In addition, CAAC-OS can also be called an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). 。Also, CAAC-OS can be called an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). Here, based on the Cs-corrected high-resolution TEM image, when the arrangement of the pellets 5100 of CAAC-OS on the substrate 5120 is schematically shown, it has a structure like bricks or blocks stacked

[0311] (see FIG. 33(D)). The location where the inclination occurs between the pellets observed in FIG. 33(C) corresponds to the region 5161 shown in FIG. 33(D). That is, it has a structure like bricks or blocks stacked (see FIG. 33(D)). The location where the inclination occurs between the pellets observed in FIG. 33(C) corresponds to the region 5161 shown in FIG. 33(D). Also, FIG. 34(A) shows a Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. The Cs-corrected high-resolution TEM images of the regions (1), (2), and (3) in FIG. 34(A) are respectively shown in FIGS. 34(B), 34(C), and 34(D). From FIGS. 34(B), 34(C), and 34(D), it can be confirmed that

[0312] the metal atoms are arranged in a triangular, square, or hexagonal shape. However, the Cs-corrected high-resolution TEM images of the regions (1), (2), and (3) in FIG. 34(A) are respectively shown in FIGS. 34(B), 34(C), and 34(D). From FIGS. 34(B), 34(C), and 34(D), it can be confirmed that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, From FIGS. 34(B), 34(C), and 34(D), it can be confirmed that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, the metal atoms are arranged in a triangular, square, or hexagonal shape. However, However, there is no regularity in the arrangement of metal atoms among different pellets.

[0313] Next, the CA analyzed by X-ray diffraction (XRD) AC-OS will be described. For example, for CAAC-OS having a crystal of InGaZnO4 when performing a structural analysis by the out-of-plane method, as shown in FIG. 35(A) a peak may appear at around a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the crystal of InGaZnO4, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0314] In the structural analysis of CAAC-OS by the out-of-plane method, in addition to the peak around 2θ of 31° a peak may also appear at around 2θ of 36°. The peak around 2θ of 36° indicates that a part of CAAC-OS contains crystals having no c-axis orientation. More preferable CAAC-OS shows a peak at around 2θ of 31° and does not show a peak at around 2θ of 36° in the structural analysis by the out-of-plane method.

[0315] On the other hand, when performing a structural analysis of CAAC-OS by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak appears at around 2θ of 56°. This peak is attributed to the (110) plane of the crystal of InGaZnO4. In the case of CAAC-OS, even when the analysis ( φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 56° °, as shown in FIG. 35(B), no distinct peak appears. In contrast When the single crystal oxide semiconductor is InGaZnO4 and 2θ is fixed near 56° and φ is scanned, as shown in Fig. 35(C), six peaks attributed to crystal planes equivalent to the (110) plane are observed. Therefore, from the structural analysis using XRD, it can be confirmed that the CAAC-OS has irregular orientations of the a-axis and the b-axis.

[0316] Next, the CAAC-OS analyzed by electron diffraction will be described. For example, for the CAAC-OS having a crystal of InGaZnO4, when an electron beam with a probe diameter of 300 nm is incident parallel to the sample surface, a diffraction pattern as shown in Fig. 36(A) (also referred to as a limited-field transmission electron diffraction pattern) may appear. This diffraction pattern includes spots due to the (009) plane of the InGaZnO4 crystal. Therefore, also by electron diffraction, it can be seen that the pellets included in the CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. On the other hand, Fig. 36(B) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicular to the sample surface for the same sample. From Fig. 36 (B), a ring-shaped diffraction pattern is confirmed. Therefore, also by electron diffraction, it can be seen that the a-axis and the b-axis of the pellets included in the CAAC-OS have no orientation. Note that the first ring in Fig. 36(B) is considered to be due to the (010) plane and the (100) plane of the InGaZnO4 crystal, etc. Also, the second ring in Fig. 36(B) is considered to be due to the (110) plane, etc. As described above, the CAAC-OS is a highly crystalline oxide semiconductor. The crystal of the oxide semiconductor

[0317] of the oxide semiconductor ​​​​​Crystallinity may decrease due to contamination by impurities or generation of defects, so the opposite view is taken. CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0318] Note that impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. Elements such as silicon, which have a stronger bonding force with oxygen than the metal elements constituting the oxide semiconductor, can deprive the oxide semiconductor of oxygen, disrupting the atomic arrangement of the oxide semiconductor and becoming a factor in reducing crystallinity. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a large atomic radius (or molecular radius), so they disrupt the atomic arrangement of the oxide semiconductor and become a factor in reducing crystallinity. When an oxide semiconductor has impurities or defects, its characteristics may vary depending on light, heat, etc. For example, impurities contained in the oxide semiconductor may become carrier traps or carrier generation sources. Also, oxygen vacancies in the oxide semiconductor may become carrier traps or carrier generation sources by capturing hydrogen.

[0319]

[0320] CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with a low carrier density. Specifically, it is less than 8×10 11 / cm 3 preferably less than 1×10 11 / cm 3 even more preferably less than 1×10 10 / cm 3 and can be an oxide semiconductor with a carrier density of 1×10 -9 / cm 3 or more. Such an oxide semiconductor can be a high-purity intrinsic or ​​​​​​​​​​It is substantially called a highly pure and genuine oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics.

[0321] <nc-os> Next, we will explain nc-OS.

[0322] In the high-resolution TEM image, the nc-OS is divided into two groups: one where the crystals can be confirmed, and the other where the crystals can be clearly confirmed. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In addition, the nanocrystals are different from the pellets in CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is called pellets. There may be cases where this happens.

[0323] The nc-OS is a nano-sized area (e.g., an area of 1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be considered to be a-like OS or amorphous oxide semiconductor. For example, for nc-OS, the X-shaped pellets with a diameter larger than that of the pellets may not be distinguishable. When using the line, the peaks showing the crystal planes were not detected by the out-of-plane method. In addition, for nc-OS, a probe diameter larger than the pellet (e.g. 50n When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than that of the pellet. When performing nanobeam electron diffraction using an electron beam with a diameter of ーブ, spots are observed. Also, n When performing nanobeam electron diffraction on c-OS, a region with high brightness may be observed that draws a circle (ring-shaped). Furthermore, multiple spots may be observed within the ring-shaped region. There are cases where this occurs.

[0324] Thus, since the crystal orientations among the pellets (nanocrystals) do not have regularity, nc- OS can also be called an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide semiconductor having NANC (Non-Aligned nanocrystals ).

[0325] nc-OS is an oxide semiconductor with higher regularity than an amorphous oxide semiconductor. Therefore, nc-OS has a lower density of defect levels than a-like OS and amorphous oxide semiconductors. . However, nc-OS does not show regularity in crystal orientation among different pellets. Therefore , nc-OS has a higher density of defect levels than CAAC-OS.

[0326] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.

[0327] Looseness may be observed in the high-resolution TEM image of a-like OS. Also, in the high resolution TEM image, there are regions where the crystal part can be clearly confirmed and regions where the crystal part cannot be confirmed.

[0328] Due to having looseness, a-like OS has an unstable structure. Below, a-like ​​To show that the OS has an unstable structure compared to CAAC-OS and nc-OS , the change in structure due to electron irradiation is shown.

[0329] As samples for electron irradiation, a-like OS (denoted as sample A), nc-OS (denoted as sample B), and CAAC-OS (denoted as sample C) are prepared. All of the samples are In-Ga-Zn oxide.

[0330] First, high-resolution cross-sectional TEM images of each sample are obtained. From the high-resolution cross-sectional TEM images, it can be seen that each sample has a crystalline part.

[0331] Note that the determination of which part is regarded as one crystalline part can be performed as follows. For example, the unit cell of the InGaZnO4 crystal has three In-O layers and six Ga-Zn-O layers, and it is known to have a structure in which a total of nine layers are stacked in the c-axis direction. The distance between these adjacent layers is about the same as the lattice plane spacing of the (009) plane (also called the d value), and from crystal structure analysis, the value is determined to be 0.29 nm. Therefore, a portion where the lattice fringe spacing is between 0.28 nm and 0.30 nm can be regarded as the crystalline part of InGaZnO4. Note that the lattice fringe corresponds to the a-b plane of the InGaZnO4 crystal.

[0332] Figure 37 shows an example of investigating the average size of the crystalline parts (from 22 to 45 locations) of each sample. However, the length of the lattice fringe described above is used as the size of the crystalline part. From Figure 37, it can be seen that the a-like OS has a crystalline part that increases in size according to the cumulative electron irradiation dose. Specifically, as shown by (1) in Figure 37, at the initial stage of observation by TEM, it is about 1.2 nm The crystal part (also referred to as the initial nucleus) with a size of... had grown to a size of about 2.6 nm at a cumulative irradiation dose of 4.2×10 8 e - / nm 2 It can be seen that in... On the other hand, for nc-OS and CAAC-OS, it can be seen that there is no change in the size of the crystal part in the range where the cumulative irradiation dose of electrons is up to 4.2×10 8 e - / nm 2 Specifically, as shown in (2) and (3) of Fig. 37, regardless of the cumulative irradiation dose of electrons, the sizes of the crystal parts of nc-OS and CAAC-OS are about 1.4 nm and about 2.1 nm, respectively It can be seen that there is...

[0333] Thus, a-like OS may show crystal growth by electron irradiation On the other hand, it can be seen that nc-OS and CAAC-OS hardly show crystal growth by electron irradiation That is, it can be seen that a-like OS has an unstable structure compared to nc-OS and CAAC-O S

[0334] Also, because it has looseness, a-like OS has a lower density structure compared to nc-OS and CAAC-OS Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal with the same composition The density of nc-OS and the density of CAAC -OS are 92.3% or more and less than 100% of the density of a single crystal with the same composition. An oxide semiconductor with a density less than 78% of the density of a single crystal is difficult to form a film itself

[0335] For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], rhombic The density of single-crystalline InGaZnO4 having a hexahedral crystal structure is 6.357 g / cm 3 becomes. Therefore in an oxide semiconductor that satisfies, for example, In:Ga:Zn = 1:1:1 [atomic ratio] , the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Also , for example, in an oxide semiconductor that satisfies In:Ga:Zn = 1:1:1 [atomic ratio] , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0336] Note that there may be cases where single crystals of the same composition do not exist. In that case, by combining single crystals with different compositions in any ratio , it is possible to estimate the density corresponding to the single crystal in the desired composition . The density corresponding to the single crystal of the desired composition may be estimated using a weighted average with respect to the ratio of combining single crystals with different compositions . However, it is preferable to estimate the density by combining as few types of single crystals as possible .

[0337] As described above, the oxide semiconductor takes various structures, each having various characteristics. Also , the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS , CAAC-OS

[0338] (Embodiment 4) In this embodiment, an example of a circuit using a transistor according to one aspect of the present invention will be described with reference to the drawings .

[0339] <Cross-sectional structure> FIG. 38(A) shows a cross-sectional view of a semiconductor device according to an aspect of the present invention. In FIG. 38(A), X The 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. In FIG. 38(A) The semiconductor device shown has a transistor 2200 using a first semiconductor material at the lower part, and has a transistor 2100 using a second semiconductor material at the upper part. In FIG. 38(A), As the transistor 2100 using the second semiconductor material, an example in which the transistor exemplified in the previous embodiment is applied is shown. Note that the left side of the dashed line is the cross-section in the channel length direction of the transistor, and the right side is the cross-section in the channel width direction.

[0340] The first semiconductor material and the second semiconductor material are preferably materials having different bandgaps . For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductor, etc.), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor such as single-crystal silicon is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can obtain excellent sub threshold characteristics and can be made into a fine transistor by applying the transistor exemplified in the previous embodiment. Also, since the switching speed is fast, high-speed operation is possible, and since the off-current is low, the leakage current is small.

[0341] The transistor 2200 may be either an n-channel type transistor or a p-channel type transistor, and an appropriate transistor may be used depending on the circuit. Also, acid ​​​​​​​In addition to using a transistor according to one embodiment of the present invention using a nitride semiconductor, other materials and structures are not required. For example, the specific configuration of the semiconductor device is not necessarily limited to that shown here.

[0342] In the configuration shown in FIG. 38A, an insulator 2201 and an insulator The transistor 2100 is connected via the transistor 2207. A plurality of wirings 2202 are provided between the transistor 2100 and the A plurality of plugs 2203 embedded in the substrate are used to connect the wiring provided in the upper and lower layers. The electrodes are electrically connected to an insulator 2204 that covers the transistor 2100. A wiring 2205 is provided on the insulator 2204 .

[0343] In this way, by stacking two types of transistors, the area occupied by the circuit is reduced, Multiple circuits can be arranged at higher density.

[0344] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulator provided near the semiconductor film of the transistor 2200 is a silicon dung. This has the effect of terminating the ring bond and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, the transistor 21 Hydrogen in the insulator provided near the semiconductor film of 00 generates carriers in the oxide semiconductor. This may be one of the factors that reduces the reliability of the transistor 2100. Therefore, the upper layer of the transistor 2200 using a silicon-based semiconductor material is oxidized. When the transistor 2100 using a semiconductor is stacked, hydrogen diffusion between the transistors may occur. Providing the insulator 2207 having the function of preventing this is particularly effective. By confining hydrogen in the lower layer with the insulator 220 7, the reliability of the transistor 2200 is improved, and in addition, since the diffusion of hydrogen from the lower layer to the upper layer is suppressed, the reliability of the transistor 2100 can also be improved simultaneously.

[0345] As the insulator 2207, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0346] Also, so as to cover the transistor 2100 composed of an oxide semiconductor film, it is preferable to form a block film having the function of preventing the diffusion of hydrogen on the transistor 2100. As the block film, the same material as the insulator 2207 can be used, and in particular, it is preferable to apply an aluminum oxide film. The aluminum oxide film has a high blocking effect of not allowing the film to permeate both impurities such as hydrogen and moisture and oxygen. Therefore, by using an aluminum oxide film as the block film covering the transistor 2100, it is possible to prevent the desorption of oxygen from the oxide semiconductor film contained in the transistor 2100 and at the same time prevent the mixing of water and hydrogen into the oxide semiconductor film. Note that the block film may be used by laminating the insulator 2204, or may be provided on the lower side of the insulator 2204. side of the insulator 2204.

[0347] Note that the transistor 2200 is not only a planar-type transistor but also various types of It can be a transistor. For example, it can be a transistor such as a FIN (fin) type, a TRI-GATE (tri-gate) type, etc. An example of a cross-sectional view in that case is shown in Figure 38(D). An insulator 2212 is provided on a semiconductor substrate 2211. The semiconductor substrate 2211 has a thin convex portion (also referred to as a fin) at the tip. Note that an insulator may be provided on the convex portion. The insulator functions as a mask for preventing the semiconductor substrate 2 211 from being etched when forming the convex portion. Note that the tip of the convex portion does not have to be thin. For example, it may be a substantially rectangular parallelepiped convex portion, or a convex portion with a thick tip may be used. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2215 are formed in the semiconductor substrate 2211. Here, an example where the semiconductor substrate 2211 has a convex portion has been shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

[0348] <Circuit configuration example> In the above configuration, various circuits can be configured by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described.

[0349] <CMOS inverter circuit> The circuit diagram shown in Figure 38(B) is a so-called CMOS circuit in which a p-channel type transistor 2200 and an n-channel type transistor 2100 are connected in series and their gates are connected. ​​​​​​It shows the configuration of the S inverter.

[0350] <CMOS analog switch> Also, the circuit diagram shown in Fig. 38(C) shows a configuration in which the respective sources and drains of transistor 2100 and transistor 2200 are connected. By adopting such a configuration, it can function as a so-called CMOS analog switch.

[0351] <Example of a memory device> An example of a semiconductor device (memory device) that uses the transistor which is one aspect of the present invention and can retain the stored content even in a situation where no power is supplied and has no limit on the number of write operations is shown in Fig. 39.

[0352] The semiconductor device shown in Fig. 39(A) has a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor element 3400. Note that as the transistor 3300, the transistors described in Embodiments 1 to 2 can be used.

[0353] Fig. 39(B) shows a cross-sectional view of the semiconductor device shown in Fig. 39(A). In the semiconductor device of the cross-sectional view, a configuration in which a back gate is provided for the transistor 3300 is shown, but a configuration without a back gate may also be used.

[0354] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 3300 has a small off-current, the stored content can be retained over a long period by using it. That is, it can be a semiconductor memory device that does not require a refresh operation or has an extremely low frequency of refresh operations. ​ This makes it possible to sufficiently reduce power consumption.

[0355] In FIG. 39(A), the first wiring 3001 is electrically connected to the source electrode of the transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is electrically connected to either the source electrode or the drain electrode of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate electrode of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the other of the source electrode or the drain electrode of the transistor 3300 and one of the electrodes of the capacitor element 3400. The fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor element 3400.

[0356] In the semiconductor device shown in FIG. 39(A), by taking advantage of the feature that the potential of the gate electrode of the transistor 3200 can be held, writing, holding, and reading of information are possible as follows.

[0357] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, turning on the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and the capacitor element 3400. That is, a predetermined charge is applied to the gate electrode of the transistor 3200 (writing). Here, either one of two different potential level charges (hereinafter referred to as Low level charge and High level charge) is applied. Then, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is in the off state, and the transistor 3300 is turned off, so that the charge applied to the gate electrode of the transistor 3200 is held (held). Since the off-current of the transistor 3300 is extremely small, the charge on the gate of the transistor 3200 is held for a long time. Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the first wiring 3001 and an appropriate potential (read potential) is applied to the fifth wiring 3005, the second wiring 3002 takes different potentials according to the amount of charge held in the gate electrode of the transistor 3200. Generally, when the transistor 3200 is an n-channel type, the apparent threshold value V

[0358] when a high-level charge is applied to the gate electrode of the transistor 3200 is lower than the apparent threshold value V when a low-level charge is applied to the gate electrode of the transistor 3200. Here, the apparent threshold voltage is the potential of the fifth wiring 3005 required to turn the transistor 3200 "on". Therefore, by setting the potential of the fifth wiring 3005 to a potential V0 between V

[0359] and V the charge applied to the gate electrode of the transistor 3200 can be discriminated. For example, in writing, if a high-level charge was applied, when the potential of the fifth wiring 3005 becomes V0 (> V ), the transistor 3200 becomes "on". If a low-level charge was applied, the potential of the fifth wiring 3005 In general, when the transistor 3200 is an n-channel type, the apparent threshold value V when a high-level charge is applied to the gate electrode of the transistor 3200 is lower than the apparent threshold value V th_H when a low-level charge is applied to the gate electrode of the transistor 3200. Here, the apparent threshold voltage is the potential of the fifth wiring 3005 required to turn the transistor 3200 "on". Therefore, by setting the potential of the fifth wiring 3005 to a potential V0 between V and V th_L the charge applied to the gate electrode of the transistor 3200 can be discriminated. For example, in writing, if a high-level charge was applied, when the potential of the fifth wiring 3005 becomes V0 (> V ), the transistor 3200 becomes "on". If a low-level charge was applied, the potential of the fifth wiring 3005 is such that the charge applied to the gate electrode of the transistor 3200 can be discriminated. For example, in writing, if a high-level charge was applied, when the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 becomes "on". If a low-level charge was applied, the potential of the fifth wiring 3005 th_L between and V is set to a potential V0, the charge applied to the gate electrode of the transistor 3200 can be discriminated. For example, in writing, if a high-level charge was applied, when the potential of the fifth wiring 3005 becomes V0 (> V ), the transistor 3200 becomes "on". If a low-level charge was applied, the potential of the fifth wiring 3005 th_H ) and the transistor 3200 becomes "on". If a low-level charge was applied, the potential of the fifth wiring 3005 will cause the transistor 3200 to be in the "on state" when the potential of the fifth wiring 3005 is V0 (> V Even if the potential is V0 (<V th_L ), the transistor 3200 remains in the "off state". Therefore, by determining the potential of the second wiring 3002, the stored information can be read. When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. For example, in a memory cell where information is not read, a potential such that the transistor 3200 becomes in the "off state" regardless of the state of the gate electrode, that is, a potential smaller than V

[0360] is applied to the fifth wiring 3005, so that only the information of the desired memory cell can be read. Alternatively, in a memory cell where information is not read, a potential such that the transistor 3200 becomes in the "on state" regardless of the state of the gate electrode, that is, a potential larger than V is applied to the fifth wiring 3005, so that only the information of the desired memory th_H cell can be read. The semiconductor device shown in FIG. 39(C) is different from FIG. 39(A in that the transistor 3200 is not provided. Also in this case, writing and holding operations of information are possible by the same operation as above. th_L

[0361] Next, reading of information will be described. When the transistor 3300 is turned on, the floating third wiring 3003 and the capacitor element 3400 are conducted, and charge is redistributed between the third wiring 3003 and the capacitor element 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is the potential of one of the electrodes of the capacitor element 3400 ( ) and is possible.

[0362] and the other electrode potential of the capacitor element 3400. depends on the potential of one of the electrodes of the capacitor element 3400 ( Alternatively, it takes different values depending on the charge stored in the capacitive element 3400.

[0363] For example, let the potential of one electrode of the capacitive element 3400 be V, the capacitance of the capacitive element 3400 be C, and the capacitance component of the third wiring 3003 be CB, and the potential of the third wiring 3003 before charge redistribution be VB0. Then, the potential of the third wiring 3003 after charge redistribution is (CB × VB0 + C × V) / (CB + C). Therefore, assuming that the potential of one electrode of the capacitive element 3400 takes two states of V1 and V0 (V1 > V0) as the state of the memory cell, the potential of the third wiring 3003 when holding the potential V1 (=(CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the third wiring 3003 when holding the potential V0 (=(CB × VB0 + C × V0) / (CB + C)). It can be seen that information can be read by comparing the potential of the third wiring 3003 with a predetermined potential. In this case, a transistor to which the above first semiconductor material is applied in a drive circuit for driving the memory cell may be used, and a transistor to which the second semiconductor material is applied may be stacked and provided on the drive circuit as the transistor 3300. In the semiconductor device shown in this embodiment, by applying a transistor with an extremely small off-current using an oxide semiconductor in the channel formation region, it is possible to hold the stored content for an extremely long time. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced.

[0364] And information can be read by comparing the potential of the third wiring 3003 with a predetermined potential. This can be done.

[0365] In this case, a transistor to which the above first semiconductor material is applied in a drive circuit for driving the memory cell may be used, and a transistor to which the second semiconductor material is applied may be stacked and provided on the drive circuit as the transistor 3300. Use a transistor to which the first semiconductor material is applied in the drive circuit for driving the memory cell, and stack and provide a transistor to which the second semiconductor material is applied on the drive circuit as the transistor 3300. It may be configured as follows.

[0366] In the semiconductor device shown in this embodiment, by applying a transistor with an extremely small off-current using an oxide semiconductor in the channel formation region, it is possible to hold the stored content for an extremely long time. That is, it is possible to make the refresh operation unnecessary or to extremely reduce the frequency of the refresh operation, so that the power consumption can be sufficiently reduced. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Since it is possible to make the refresh operation unnecessary or to extremely reduce the frequency of the refresh operation, the power consumption can be sufficiently reduced. This is also the case when there is no power supply (however, it is desirable that the potential be fixed). Even in this case, it is possible to retain the stored content over a long period of time.

[0367] In addition, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of device degradation. For example, unlike conventional non-volatile memories, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written according to the on-state and off-state of the transistor, high-speed operation can be easily realized. In addition, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of device degradation. For example, unlike conventional non-volatile memories, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written according to the on-state and off-state of the transistor, high-speed operation can be easily realized. In addition, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of device degradation. For example, unlike conventional non-volatile memories, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written according to the on-state and off-state of the transistor, high-speed operation can be easily realized. In addition, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of device degradation. For example, unlike conventional non-volatile memories, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written according to the on-state and off-state of the transistor, high-speed operation can be easily realized. In addition, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of device degradation. For example, unlike conventional non-volatile memories, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written according to the on-state and off-state of the transistor, high-speed operation can be easily realized. In addition, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of device degradation. For example, unlike conventional non-volatile memories, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written according to the on-state and off-state of the transistor, high-speed operation can be easily realized. In addition, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of device degradation. For example, unlike conventional non-volatile memories, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written according to the on-state and off-state of the transistor, high-speed operation can be easily realized.

[0368] In this specification and the like, even if the connection destinations of all the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc. are not specified, those skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destinations. And when the content of the specified connection destinations is described in this specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destinations is described in this specification and the like. In particular, when multiple cases are conceivable as the connection destinations of the terminals, it is not necessary to limit the connection destinations of those terminals to specific locations. Therefore, by specifying the connection destinations of only some of the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc., In this specification and the like, even if the connection destinations of all the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc. are not specified, those skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destinations. And when the content of the specified connection destinations is described in this specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destinations is described in this specification and the like. In particular, when multiple cases are conceivable as the connection destinations of the terminals, it is not necessary to limit the connection destinations of those terminals to specific locations. Therefore, by specifying the connection destinations of only some of the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc., In this specification and the like, even if the connection destinations of all the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc. are not specified, those skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destinations. And when the content of the specified connection destinations is described in this specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destinations is described in this specification and the like. In particular, when multiple cases are conceivable as the connection destinations of the terminals, it is not necessary to limit the connection destinations of those terminals to specific locations. Therefore, by specifying the connection destinations of only some of the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc., In this specification and the like, even if the connection destinations of all the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc. are not specified, those skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destinations. And when the content of the specified connection destinations is described in this specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destinations is described in this specification and the like. In particular, when multiple cases are conceivable as the connection destinations of the terminals, it is not necessary to limit the connection destinations of those terminals to specific locations. Therefore, by specifying the connection destinations of only some of the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc., In this specification and the like, even if the connection destinations of all the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc. are not specified, those skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destinations. And when the content of the specified connection destinations is described in this specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destinations is described in this specification and the like. In particular, when multiple cases are conceivable as the connection destinations of the terminals, it is not necessary to limit the connection destinations of those terminals to specific locations. Therefore, by specifying the connection destinations of only some of the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc., In this specification and the like, even if the connection destinations of all the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc. are not specified, those skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destinations. And when the content of the specified connection destinations is described in this specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destinations is described in this specification and the like. In particular, when multiple cases are conceivable as the connection destinations of the terminals, it is not necessary to limit the connection destinations of those terminals to specific locations. Therefore, by specifying the connection destinations of only some of the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc., In this specification and the like, even if the connection destinations of all the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc. are not specified, those skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destinations. And when the content of the specified connection destinations is described in this specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destinations is described in this specification and the like. In particular, when multiple cases are conceivable as the connection destinations of the terminals, it is not necessary to limit the connection destinations of those terminals to specific locations. Therefore, by specifying the connection destinations of only some of the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc., In this specification and the like, even if the connection destinations of all the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc. are not specified, those skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destinations. And when the content of the specified connection destinations is described in this specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destinations is described in this specification and the like. In particular, when multiple cases are conceivable as the connection destinations of the terminals, it is not necessary to limit the connection destinations of those terminals to specific locations. Therefore, by specifying the connection destinations of only some of the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc., In this specification and the like, even if the connection destinations of all the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc. are not specified, those skilled in the art may be able to configure an aspect of the invention. That is, it can be said that an aspect of the invention is clear even without specifying the connection destinations. And when the content of the specified connection destinations is described in this specification and the like, it may be possible to determine that an aspect of the invention without specifying the connection destinations is described in this specification and the like. In particular, when multiple cases are conceivable as the connection destinations of the terminals, it is not necessary to limit the connection destinations of those terminals to specific locations. Therefore, by specifying the connection destinations of only some of the terminals of active elements (such as transistors and diodes), passive elements (such as capacitor elements and resistor elements), etc., This may constitute an aspect of the invention.

[0369] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art that If you are a person who has experience in the field of electronics, you may be able to identify the invention. In some cases, a person skilled in the art can identify an invention by at least specifying the function. In other words, if a function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an embodiment of the invention. and can constitute one embodiment of the invention. For a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an embodiment of the invention.

[0370] In this specification, etc., in a drawing or text described in a certain embodiment, It is possible to extract a part of the invention and use it as an embodiment of the invention. If a figure or text describing a certain part is included, the figure or text of that part is taken out. The above-mentioned contents are disclosed as one aspect of the invention and constitute one aspect of the invention. Therefore, for example, active elements (transistors, diodes, etc.) etc.), wiring, passive elements (capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic Drawings showing one or more of the following: materials, inorganic materials, parts, devices, operating methods, manufacturing methods, etc. Or, in a sentence, a part of it can be taken out and used to constitute one aspect of the invention. It is assumed to be so. For example, having N (N is an integer) circuit elements (transistors, capacitor elements, etc.) From a circuit diagram constituted, it is possible to extract M (M is an integer and M < N) circuit elements (transistors, capacitors elements, etc.) and constitute one aspect of the invention. As another example, From a cross-sectional view constituted of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers and constitute one aspect of the invention. As yet another example, from a flowchart constituted of N (N is an integer) elements, it is possible to extract M (M is an integer and M < N ) elements and constitute one aspect of the invention.

[0371] <Imaging device> Hereinafter, an imaging device according to one aspect of the present invention will be described.

[0372] FIG. 40(A) is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, and peripheral circuits 270, 280, and 290. The pixel unit 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are each connected to a plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211 . Note that, in this specification and the like, all of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be referred to as a "peripheral circuit" or a "driving circuit" in some cases . For example, the peripheral circuit 260 can be said to be a part of the peripheral circuit.

[0373] ​In addition, the imaging device 200 preferably has a light source 291. The light source 291 can emit detection light P 1.

[0374] In addition, the peripheral circuit has at least one of a logic circuit, a switch, a buffer, an amplifier circuit, or a conversion circuit. Further, the peripheral circuit may be formed on the substrate forming the pixel unit 210. Further, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuit. Note that the peripheral circuit may omit any one or more of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290.

[0375] Also, as shown in FIG. 40(B), in the pixel unit 210 included in the imaging device 200, the pixel 211 may be arranged obliquely. By arranging the pixel 211 obliquely, the pixel pitch in the row direction and the column direction can be shortened. Thereby, the imaging quality of the imaging device 200 can be further improved.

[0376] <Example Configuration of Pixel 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and filters (color filters) that transmit light in specific wavelength bands are combined with the respective sub- pixels 212, whereby information for realizing color image display can be acquired.

[0377] FIG. 41(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 41(A) is provided with a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") provided with a color filter that transmits light in the red (R) wavelength band, and light in the green (G) wavelength band is provided with a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a color filter that transmits A sub-pixel 212 provided with a color filter that transmits light in the wavelength bands of red (R), green (G), and blue (B). (hereinafter also referred to as "sub-pixel 212B"). The sub-pixel 212 can function as a photosensor.

[0378] The sub-pixels 212 (sub-pixel 212R, sub-pixel 212G, and sub-pixel 212B) are electrically connected to wiring 231, wiring 247, wiring 248, wiring 249, and wiring 250. Also, the sub-pixels 212R, sub-pixel 212G, and sub-pixel 212B are each connected to independent wiring 253. In this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the n-th row (n is an integer of 1 or more and p or less) are described as wiring 248[n] and wiring 249[n], respectively. Also, for example, the wiring 253 connected to the pixel 211 in the m-th column (m is an integer of 1 or more and q or less) is described as wiring 253[m]. In FIG. 41(A), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the m-th column is described as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is described as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is described as wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring.

[0379] The imaging device 200 has a configuration in which sub-pixels 212 provided with color filters that transmit light in the same wavelength band of adjacent pixels 211 are electrically connected to each other via a switch. FIG. 41(B) shows a connection example of the sub-pixel 212 of the pixel 211 arranged in the n-th row and m-th column and the sub-pixel 212 of the pixel 211 arranged in the (n + 1)-th row and m-th column adjacent to the pixel 211. Well. In FIG. 41(B), the sub-pixel 212R arranged in the n-th row and m-th column and the sub-pixel 212R arranged in the (n + 1)-th row and m-th column are connected via the switch 201. Also, the sub-pixel 212G arranged in the n-th row and m-th column and the sub-pixel 212G arranged in the (n + 1)-th row and m-th column are connected via the switch 202. Also, the sub-pixel 212B arranged in the n-th row and m-th column and the sub-pixel 212B arranged in the (n + 1)-th row and m-th column are connected via the switch 203. Note that the color filter used for the sub-pixel 212 is not limited to red (R), green (G), and blue (B), and color filters that transmit cyan (C), yellow (Y), and magenta (M) light may be used respectively. By providing the sub-pixel 212 that detects light in three different wavelength bands for one pixel 211, a full-color image can be obtained. Or, in addition to the sub-pixel 212 provided with color filters that transmit red (R), green (G), and blue (B) light respectively, a pixel 211 having a sub-pixel 212 provided with a color filter that transmits yellow (Y) light may be used. Or, in addition to the sub-pixel 212 provided with color filters that transmit cyan (C), yellow (Y), and magenta (M) light respectively, a pixel 211 having a sub-pixel 212 provided with a color filter that transmits blue (B) light may be used. By providing the sub-pixel 212 that detects light in four different wavelength bands for one pixel 211, the color reproducibility of the obtained image can be further enhanced. Also, for example, in FIG. 41(A), the pixel number ratio of the sub-pixel 212 that detects the red wavelength band, the sub-pixel 212 that detects the green wavelength band, and the sub-pixel 212 that detects the blue wavelength band

[0380]

[0381]

[0382] ​​​​​​​​​​​​​​ The pixel number ratio (or light-receiving area ratio) does not have to be 1:1:1. For example, the pixel number ratio (light-receiving area ratio ) may be a Bayer array with red:green:blue = 1:2:1. Alternatively, the pixel number ratio (light-receiving area ratio) may be red:green:blue = 1:6:1.

[0383] Note that the number of sub-pixels 212 provided in the pixel 211 may be one, but two or more are preferred. For example , by providing two or more sub-pixels 212 that detect the same wavelength band, redundancy can be increased and the reliability of the imaging device 200 can be enhanced.

[0384] In addition, an IR (IR: Infrared) filter that absorbs or reflects visible light and transmits infrared light can be used to realize the imaging device 200 that detects infrared light.

[0385] Also, by using an ND (ND: Neutral Density) filter (attenuating filter) , it is possible to prevent output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light-receiving element). By combining ND filters with different light attenuation amounts, the dynamic range of the imaging device can be increased. In addition to the filters described above, a lens may be provided in the pixel 211. Here, an arrangement example of the pixel 211, the filter 254, and the lens 255 will be described using the cross-sectional view of FIG. 42. By providing the lens

[0386] 255, the photoelectric conversion element can efficiently receive incident light. Specifically , as shown in FIG. 42(A), the light 256 can be made to enter the photoelectric conversion element 220 through the lens 255 formed in the pixel 211, the filter 25 4 (filter 254R, filter 254G, and filter 254B), and the pixel circuit 2 30 and the like. 4 (filter 254R, filter 254G, and filter 254B), and the pixel circuit 2 30 and the like.

[0387] However, as shown in the region surrounded by the dashed line, part of the light 256 indicated by the arrow may be blocked by part of the wiring 257. Therefore, as shown in FIG. 42(B), it is preferable to arrange the lens 255 and the filter 254 on the side of the photoelectric conversion element 220 so that the photoelectric conversion element 220 can efficiently receive the light 256. By making the light 256 incident on the photoelectric conversion element 220 from the side of the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity can be provided.

[0388] As the photoelectric conversion element 220 shown in FIG. 42, a photoelectric conversion element in which a pn junction or a pin junction is formed may be used.

[0389] Alternatively, the photoelectric conversion element 220 may be formed using a substance having a function of absorbing radiation and generating charges. Examples of substances having a function of absorbing radiation and generating charges include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy, etc.

[0390] For example, when selenium is used for the photoelectric conversion element 220, a photoelectric conversion element 220 having a light absorption coefficient over a wide wavelength band such as visible light, ultraviolet light, infrared light, X-rays, and gamma rays can be realized.

[0391] Here, one pixel 211 included in the imaging device 200 may have a sub-pixel 212 having a first filter in addition to the sub-pixel 212 shown in FIG. 41.

[0392] <Example 2 of pixel configuration> Hereinafter, a transistor using silicon and a transistor using an oxide semiconductor will be ​​​​​​​An example of forming a pixel using the above will be described.

[0393] 43(A) and 43(B) are cross-sectional views of elements constituting the imaging device.

[0394] The imaging device shown in FIG. 43(A) is a silicon-based transistor provided on a silicon substrate 300. A transistor using an oxide semiconductor that is stacked on the transistor 351. A transistor 352 and a transistor 353, and a transistor 354 provided on the silicon substrate 300. Each transistor includes a photodiode 360 having an anode 361 and a cathode 362. The photodiodes 360 are electrically connected to various plugs 370 and wiring 371. The anode 361 of the photodiode 360 has a low resistance region 363. 3 and has an electrical connection with plug 370 via.

[0395] The imaging device includes a transistor 351 and a photodiode 352 disposed on a silicon substrate 300. A layer 310 having an electrode 360 and a layer 371 provided in contact with the layer 310. 20 and in contact with layer 320, and includes transistors 352 and 353. A layer 330 is provided in contact with the layer 330 and has wiring 372 and wiring 373. It has 40.

[0396] In the example of the cross-sectional view of FIG. 43(A), the transistor 3 is formed on the silicon substrate 300. The light receiving surface of the photodiode 360 is disposed on the opposite side to the surface on which the photodiode 51 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. The light-receiving surface of the photosensor 360 can be made the same as the surface on which the transistor 351 is formed.

[0397] When forming pixels using only transistors using an oxide semiconductor, layer 31 0 may be a layer having a transistor using an oxide semiconductor. Or layer 310 may be omitted and pixels may be formed using only transistors using an oxide semiconductor.

[0398] Also, in the cross-sectional view of Fig. 43(A), the photodiode 360 provided in layer 310 and the layer 330 can be formed so as to overlap with the transistor provided therein. Then, the pixel integration density can be increased. That is, the resolution of the imaging device can be increased.

[0399] Also, Fig. 43(B) shows that the imaging device can have a structure in which the photodiode 365 is disposed on the transistor on the layer 340 side. In Fig. 43(B), for example, layer 310 has a transistor 351 using silicon and a transistor 352, layer 320 has wiring 3 71, layer 330 has a transistor 352 using an oxide semiconductor and a transistor 35 3, layer 340 has a photodiode 365, and the photodiode 365 is composed of a semiconductor layer 366, a semiconductor layer 367, and a semiconductor layer 368, and is electrically connected to the wiring 373 and the wiring 374 via the plug 370.

[0400] With the element configuration shown in Fig. 43(B), the aperture ratio can be widened.

[0401] Also, for the photodiode 365, a pin-type diode element using an amorphous silicon film, a microcrystalline silicon film, etc. may be used. The photodiode 365 is an n-type semiconductor A structure in which a layer 368, an i-type semiconductor layer 367, and a p-type semiconductor layer 366 are stacked in this order is provided. It is preferable to use amorphous silicon for the i-type semiconductor layer 367. Also, for the p-type semiconductor layer 366 and the n-type semiconductor layer 368, amorphous silicon or microcrystalline silicon containing dopants for imparting their respective conductivity types can be used. Amorphous silicon photodiode 365 with an amorphous silicon as a photoelectric conversion layer has high sensitivity in the wavelength region of visible light and is easy to detect weak visible light. Moreover, the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0402]

[0403] (Embodiment 5) <RF tag> In this embodiment, the RF tag including the transistor or the memory device described in the previous embodiment will be described with reference to FIG. 44.

[0404] The RF tag in this embodiment has a memory circuit inside, stores information necessary for the memory circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Because of such characteristics, the RF tag can be used in an individual authentication system that identifies an article by reading individual information of the article or the like. Note that extremely high reliability is required for use in these applications.

[0405] The configuration of the RF tag will be described with reference to FIG. 44. FIG. 44 is a block diagram showing a configuration example of the RF tag.

[0406] As shown in FIG. 44, the RF tag 800 includes a communicator 801 (also called an interrogator, a reader / writer, etc.) ​​​​​​​​Antenna 8 that receives the radio signal 803 transmitted from the antenna 802 connected to the communication device 801 04. The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 8 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing the reverse current in the transistor exhibiting the rectifying action included in the demodulation circuit 807, for example, an oxide semiconductor, may be used. As a result, it is possible to suppress a decrease in the rectifying action caused by the reverse current and prevent the output of the demodulation circuit from saturating. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linear. Note that the data transmission format is roughly classified into three types: an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. The RF tag 800 shown in this embodiment can be used in any of these methods. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 8 05 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectifies it, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit that controls so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

[0407] Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 8 05 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectifies it, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit that controls so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. That is, it is a circuit for generating an input potential by smoothing the rectified signal. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit that controls so that when the amplitude of the input AC signal is large and the internally generated voltage is large, power of a certain level or more is not input to the subsequent circuit. That is, it is a circuit for controlling so as not to input power exceeding a certain level to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

[0408] ​ The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from an input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating a reset signal for the logic circuit 809 by utilizing the rising edge of a stable power supply voltage.

[0409] The demodulation circuit 807 is a circuit for demodulating an input AC signal by envelope detection and generating a demodulated signal. In addition, the modulation circuit 808 is a circuit for performing modulation according to data output from the antenna 804.

[0410] The logic circuit 809 is a circuit for analyzing and processing a demodulated signal. The memory circuit 810 is a circuit for holding input information and includes a row decoder, a column decoder, a memory area, and the like. In addition, the ROM 811 is a circuit for storing a unique number (ID) and the like and outputting according to processing.

[0411] Note that each of the above circuits can be appropriately selected or omitted.

[0412] Here, the transistor described in the previous embodiment can be used for the memory circuit 810. Since the transistor according to one aspect of the present invention can hold information even when the power supply is cut off, it can be suitably used for an RF tag. Furthermore, since the power (voltage) required for writing data in the memory circuit according to one aspect of the present invention is significantly smaller than that of a conventional non-volatile memory, it is also possible not to cause a difference in the maximum communication distance between data read and write times. Furthermore, it is possible to suppress the occurrence of malfunction or miswriting due to insufficient power during data writing. ​

[0413] Also, the memory circuit according to one aspect of the present invention can be used as a non-volatile memory, so it can also be applied to the ROM811. In that case, it is preferable to separately prepare a command for the producer to write data into the ROM811 and prevent the user from freely rewriting it. By the producer writing a unique number before shipping and then shipping the product, it is possible to assign unique numbers not to all the manufactured RF tags but only to the good products to be shipped, which makes it possible to avoid the situation where the unique numbers of the products after shipping are discontinuous and facilitates customer management corresponding to the products after shipping.

[0414] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. .

[0415] (Embodiment 6) In this embodiment, a CPU including the memory device described in the previous embodiment will be described.

[0416] FIG. 45 is a block diagram showing a configuration example of a CPU using at least a part of the transistors described in the previous embodiment.

[0417] <cpu> The CPU shown in Fig. 45 has, on the substrate 1190, an ALU 1191 (ALU: Arithmet ic logic unit, arithmetic circuit), an ALU controller 1192, an instr uction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface 1 198, a rewritable ROM 1199, and a ROM interface 1189. The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. The ROM 1 199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in Fig. 45 is merely an example shown with its configuration simplified, and an actual CPU has various configurations depending on its application. For example, a configuration including the CPU or the arithmetic circuit shown in Fig. 45 can be regarded as one core, and a configuration including a plurality of such cores operating in parallel may be adopted. Also, the number of bits that the CPU can handle with its internal arithmetic circuit and data bus can be e.g., 8 bits, 16 bits, 32 bits, 64 bits, etc. Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the inter

[0418] rupt controller 1194, the register controller 1197, and the timing controller 1195. The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions.

[0419] ​​Perform control. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU program according to their priorities and mask states. The register controller 1197 generates addresses for the register 1196 and reads from and writes to the register 1196 according to the state of the CPU. Moreover, the timing controller 1195 generates signals for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the various circuits described above. In the CPU shown in FIG. 45, the register 1196 is provided with memory cells. As the memory cells of the register 1196, the transistors shown in Embodiments 1 to 3 can be used. In the CPU shown in FIG. 45, the register controller 1197 selects the holding operation in the register 1196 according to an instruction from the ALU 1191. That is, in the memory cells included in the register 1196, it is selected whether to hold data by a flip-flop or to hold data by a capacitive element. When holding data by a flip-flop is selected, the supply of the power supply voltage to the memory cells in the register 1196 is performed.

[0420]

[0421]

[0422] When data retention in the capacitance element is selected, data rewriting to the capacitance element is performed, and the supply of the power voltage to the memory cell in the register 1196 can be stopped .

[0423] <Recording circuit> FIG. 46 is an example of a circuit diagram of a memory element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatile when the power supply is cut off, a circuit 1202 in which stored data is non-volatile when the power supply is cut off, a switch 1203, a switch 1204, a logic element 1206, a capacitance element 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitance element 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include other elements such as a diode, a resistance element, and an inductor as necessary.

[0424] Here, the storage device described in the previous embodiment can be used for the circuit 1202. When the supply of the power voltage to the memory element 1200 is stopped, the gate of the transistor 120 9 in the circuit 1202 is configured to receive a ground potential (0 V) or a potential at which the transistor 1209 is turned off continuously. For example, the first gate of the transistor 1209 is grounded through a load such as a resistor .

[0425] The switch 1203 is configured by using a transistor 1213 of one conductivity type (e.g., n-channel type), and the switch 1204 is configured by using a transistor 1214 of a conductivity type opposite to that of the one conductivity type (e.g., p-channel type). Here, the first end of the switch 1203 is shown in an example configured by using a transistor 1214 of a conductivity type opposite to that of the one conductivity type (e.g., p-channel type). Here, the first end of the switch 1203 is shown in an example configured by using a transistor 1214 of a conductivity type opposite to that of the one conductivity type (e.g., p-channel type). Here, the first end of the switch 1203 The child corresponds to one of the source electrode and the drain electrode of the transistor 1213, and the switch 120 The second terminal of 3 corresponds to the other of the source electrode and the drain electrode of the transistor 1213, and the sw The switch 1203 is controlled by the control signal RD input to the gate of the transistor 1213 to make the first The conduction or non-conduction between the first terminal and the second terminal (that is, the on-state or off-state of the transistor 1213) is selected. The first terminal of the switch 1204 corresponds to one of the source electrode and the drain electrode of the transistor 121 4, and the second terminal of the switch 1204 corresponds to the other of the source electrode and the drain electrode of the transistor 121 4. The switch 1204 is controlled by the control signal RD input to the gate of the transistor 1214 to make the conduction or non-conduction between the first terminal and the second terminal (that is, the on-state or off-state of the transistor 1214) Selected. Selected. Selected. Selected.

[0426] One of the source electrode and the drain electrode of the transistor 1209 is electrically connected to one of the pair of electrodes of the capacitor element 1208 and the gate of the transistor 1210. Here Let the connection part be node M2. One of the source electrode and the drain electrode of the transistor 1210 is electrically connected to a wiring (for example, a GND line) that can supply a low power supply potential, And the other is electrically connected to the first terminal of the switch 1203 (one of the source electrode and the drain electrode of the transistor 1213). The second terminal of the switch 1203 (the other of the source electrode and the drain electrode of the transistor 12 13) is electrically connected to the first terminal of the switch 1204 (one of the source electrode and the drain electrode of the transistor 1214). The seco...

Claims

【Claim 1】 A semiconductor device having a first transistor and a second transistor, wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, a first conductive layer having a function as a gate electrode of the first transistor, a first insulating layer having a region located above the first conductive layer, an oxide semiconductor layer having a region above the first insulating layer and having a channel formation region of the second transistor, a second conductive layer having a region above the oxide semiconductor layer and having a function as one of a source electrode or a drain electrode, a second insulating layer having a region in contact with a side surface of the first insulating layer and a region in contact with a side surface of the oxide semiconductor layer, a third insulating layer having a region above the first conductive layer and a region above the second conductive layer and having a groove, a fourth insulating layer having a region above the third insulating layer and having a groove, a fifth insulating layer having a function as a gate insulating layer formed along an inner wall of the groove, a third conductive layer having a region in contact with the fifth insulating layer inside the groove and having a function as a gate electrode, wherein an upper surface of the second insulating layer, an upper surface of the fourth insulating layer, an upper surface of the fifth insulating layer, and an upper surface of the third conductive layer are on the same plane.

Images