Display device

Abstract

To provide a semiconductor device with a high aperture ratio.SOLUTION: A semiconductor device includes a transistor and a capacitor having a pair of electrodes, and a channel formation region of the transistor and one electrode of the capacitor are formed of an oxide semiconductor layer on the same insulating surface, and the other electrode of the capacitor is a light-transmitting conductive film. One electrode of the capacitor is electrically connected to a wiring formed on the same insulating surface as the insulating surface on which a source electrode or a drain electrode of the transistor is formed, and the other electrode of the capacitor is electrically connected to one of the source electrode or the drain electrode of the transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine , a manufacture, or a composition of matter. In particular , the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a driving method thereof, or a method for manufacturing the same . In particular, the present invention relates to, for example, a semiconductor device having an oxide semiconductor , a display device, or a light-emitting device, and a method for manufacturing the same.

Background Art

[0002] In recent years, flat panel displays such as liquid crystal displays (LCDs) have become widely popular . In a display device such as a flat panel display, a transistor as a switching element, a liquid crystal element electrically connected to the transistor, and a capacitive element connected in parallel with the liquid crystal element are provided in pixels arranged in the row direction and the column direction . As a semiconductor material constituting the semiconductor film of the transistor, silicon semiconductors such as amorphous (non-crystalline) silicon or poly (polycrystalline) silicon are widely used .

[0003] In addition, metal oxides exhibiting semiconductor characteristics (hereinafter referred to as oxide semiconductors) are semiconductor materials applicable to the semiconductor film of a transistor. For example, technologies for manufacturing transistors using zinc oxide or In-Ga-Zn-based oxide semiconductors are disclosed (see Patent Document 1 and Patent Document 2) .

[0004] .

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] A capacitive element has a dielectric film provided between a pair of electrodes. Among the pair of electrodes, at least one of the electrodes is formed of the same material as a gate electrode, a source electrode, or a drain electrode that constitutes a transistor, etc. Therefore, it is often formed of a conductive film having light-shielding properties such as metal. many.

[0007] Also, the larger the capacitance value of the capacitive element, the longer the period during which the alignment of the liquid crystal molecules of the liquid crystal element can be kept constant in the situation where an electric field is applied. In a display device capable of displaying a still image, being able to lengthen this period can reduce the number of times of rewriting image data, and reduction of power consumption can be expected. In order to increase the charge capacitance of the capacitive element, there is a means of increasing the occupied area of the capacitive element in the pixel, specifically increasing the area where the pair of electrodes overlap. However, in the above display device, if the area of the conductive film having light-shielding properties is increased in order to increase the area where the pair of electrodes overlap, the aperture ratio of the pixel is reduced and the display quality of the image deteriorates.

[0008]

[0009] decreases.

[0009] Therefore, in view of the above problems, one aspect of the present invention provides a semiconductor device with a high aperture ratio, etc. One of the objectives is to... Or, having a capacitive element capable of increasing the charge capacity One of the objectives is to provide a semiconductor device or the like. Or, a semiconductor device capable of reducing the number of mask sheets in a photolithography process One of the objectives is to provide a semiconductor device or the like. One of the objectives is to provide a semiconductor device or the like having a low off-current. Or, one of the objectives is to provide a semiconductor device or the like with reduced power consumption. Or, one of the objectives is to provide a semiconductor device or the like using a transparent conductive layer. Or, one of the objectives is to provide a highly reliable semiconductor device or the like. Or, one of the objectives is to provide an eye-friendly semiconductor device or the like. Or, one of the objectives is to provide a novel semiconductor device or the like. Or, one of the objectives is to provide a method for manufacturing a novel semiconductor device or the like. Or, one of the objectives is to provide a semiconductor device or the like using a transparent conductive layer. Or, one of the objectives is to provide a highly reliable semiconductor device or the like. Or, one of the objectives is to provide an eye-friendly semiconductor device or the like. Or, one of the objectives is to provide a novel semiconductor device or the like. Or, one of the objectives is to provide a method for manufacturing a novel semiconductor device or the like. Or, one of the objectives is to provide a highly reliable semiconductor device or the like. Or, one of the objectives is to provide an eye-friendly semiconductor device or the like. Or, one of the objectives is to provide a novel semiconductor device or the like. Or, one of the objectives is to provide a method for manufacturing a novel semiconductor device or the like. Or, one of the objectives is to provide an eye-friendly semiconductor device or the like. Or, one of the objectives is to provide a novel semiconductor device or the like. Or, one of the objectives is to provide a method for manufacturing a novel semiconductor device or the like. Or, one of the objectives is to provide a novel semiconductor device or the like. Or, one of the objectives is to provide a method for manufacturing a novel semiconductor device or the like. Or, one of the objectives is to provide a method for manufacturing a novel semiconductor device or the like. One of the objectives is to...

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention relates to a semiconductor device including a capacitive element having translucency, with an oxide semiconductor layer as one electrode and a translucent conductive film as the other electrode. One aspect of the present invention relates to a semiconductor device including a capacitive element having translucency, with an oxide semiconductor layer as one electrode and a translucent conductive film as the other electrode.

[0012] One aspect of the present invention is a semiconductor device having a transistor, formed on a first insulating film The formed first oxide semiconductor layer and second oxide semiconductor layer, the source electrode layer and drain electrode layer electrically connected to the first oxide semiconductor layer, and the wiring electrically connected to the second oxide semiconductor layer, the first insulating film, the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, and the second insulating film formed on the wiring, the gate electrode layer overlapping the first oxide semiconductor layer via the second insulating film, the third insulating film formed on the second insulating film and the gate electrode layer, the fourth insulating film formed on the third insulating film, and the transparent conductive film formed on the fourth insulating film on the second oxide semiconductor layer, which contains a dielectric, has at least a part of the second oxide semiconductor layer as the first electrode, and at least a part of the transparent conductive film as the second electrode, and is a semiconductor device characterized by having a capacitive element. The first oxide semiconductor layer and the second oxide semiconductor layer are preferably formed of the same material. Also, the first oxide semiconductor layer and the second oxide semiconductor layer preferably have an energy gap of 2.0 eV or more. One or more dopants selected from hydrogen, boron, nitrogen, fluorine, aluminum, phosphorus, arsenic, indium, tin, antimony, and noble gas elements may be added to the second oxide semiconductor layer. The dielectric can be formed of the second insulating film, the third insulating film, and the fourth insulating film. Alternatively, the dielectric may be formed of the third insulating film and the fourth insulating film.

[0013]

[0014]

[0015]

[0016]

[0017]

[0018] ​​​​​​​​​​​​ Alternatively, the dielectric may be formed of a fourth insulating film.

[0019] Alternatively, the third insulating film is preferably formed of a single-layer structure or a laminated structure of an insulating oxide material selected from silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, gallium oxide, or a Ga-Zn-based metal oxide.

[0020] Alternatively, the fourth insulating film is preferably formed of a single-layer structure or a laminated structure of a nitride insulating material selected from silicon oxynitride, silicon nitride, aluminum nitride, and aluminum oxynitride.

[0021] Alternatively, a nitride insulating film containing hydrogen may be formed between the first insulating film and the second oxide semiconductor layer.

[0022] Alternatively, the source electrode layer, the drain electrode layer, and the wiring can be formed on the same insulating surface.

[0023] Alternatively, the source electrode layer, the drain electrode layer, and the wiring can be formed of the same material.

[0024] Alternatively, the transparent conductive film can be configured to be electrically connected to one of the source electrode or the drain electrode.

[0025] In another aspect of the present invention, a first oxide semiconductor layer and a second oxide semiconductor layer are formed on the first insulating film, a source electrode layer and a drain electrode layer electrically connected to the first oxide semiconductor layer, and a wiring electrically connected to the second oxide semiconductor layer are formed, and the first insulating film, the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, the drain electrode layer , and form a second insulating film on the wiring, and form a gate electrode layer that overlaps with the first oxide semiconductor layer on the second insulating film , form a third insulating film on the second insulating film and the gate electrode layer , form a fourth insulating film on the third insulating film, and form an opening in the second insulating film, the third insulating film, and the fourth insulating film that communicates with the source electrode layer or the drain electrode layer , and form a transparent conductive film that is electrically connected to the source electrode layer or the drain electrode layer through the opening on the fourth insulating film , and form a transistor, and at least a part of the second oxide semiconductor layer as the first electrode, and at least a part of the transparent conductive film as the second electrode , and a capacitor element having a dielectric layer, and this is a method for manufacturing a semiconductor device characterized by .

[0026] It is preferable that the first oxide semiconductor layer and the second oxide semiconductor layer are formed of the same material .

[0027] Further, the first oxide semiconductor layer and the second oxide semiconductor layer are preferably formed of a material having an energy gap of 2. 0 eV or more.

[0028] Further, one or more dopants selected from hydrogen, boron, nitrogen, fluorine, aluminum, phosphorus, arsenic , indium, tin, antimony, and noble gas elements may be added to the second oxide semiconductor layer .

[0029] The dielectric can be formed of the second insulating film, the third insulating film, and the fourth insulating film.

[0030] Further, the second insulating film on the second oxide semiconductor layer may be etched, and the dielectric may be formed of the third insulating film and the fourth insulating film.

[0031] Further, the second insulating film and the third insulating film on the second oxide semiconductor layer may be etched, and a dielectric body may be formed of the fourth insulating film.

[0032] Further, the third insulating film is preferably formed of a single-layer structure or a stacked structure of an insulating oxide material selected from silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, gallium oxide, or a Ga-Zn-based metal oxide. Further, the fourth insulating film is preferably formed of a single-layer structure or a stacked structure of a nitride insulating material selected from silicon oxynitride, silicon nitride, aluminum nitride, or aluminum oxynitride. Further, a nitride insulating film containing hydrogen may be formed between the first insulating film and the second oxide semiconductor layer.

[0033] Further, it is preferable that the source electrode layer, the drain electrode layer, and the wiring are formed of the same material. Further, it is preferable that the source electrode layer, the drain electrode layer, and the wiring are formed on the same insulating surface.

[0034]

[0035]

[0036]

Advantages of the Invention

[0037] According to one aspect of the present invention, a semiconductor device having a high aperture ratio or the like can be provided. Or, a semiconductor device having a capacitive element capable of increasing the charge capacitance or the like can be provided. Or, a semiconductor device capable of reducing the number of masks in the photolithography process can be provided. Or, a semiconductor device having a low off-current or the like can be provided. Or, a semiconductor device with reduced power consumption or the like can be provided. Or, a transparent ​ A semiconductor device using a light-emitting semiconductor layer can be provided. Or, a highly reliable semiconductor device can be provided. Or, an eye-friendly semiconductor device can be provided. Or, a method for manufacturing a semiconductor device can be provided.

Brief Description of the Drawings

[0038]

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[0039] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0040] In the configuration of the present invention described below, the same parts or parts having similar functions are designated by the same reference numerals. The same reference numerals are used in different drawings, and the repeated explanations are omitted. When referring to a part having a function, the hatch pattern is the same and no symbol is attached. be.

[0041] In each figure described in this specification, the size of each structure, the thickness of the film, or the area is shown for clarity. The figures may be exaggerated for illustrative purposes and are not necessarily limited to that scale.

[0042] In this specification and elsewhere, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of steps or the order of layers. The above does not indicate the specific name of the item.

[0043] Voltage is the potential difference between two points, and potential is the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) of a unit charge in a particle. Generally, the potential difference between the potential at a certain point and a reference potential (e.g., ground potential) is This is simply referred to as potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, potential may be read as voltage, and voltage may also be read as potential.

[0044] In this specification, when an etching process is performed after a photolithography process, the resist mask formed by the photolithography process shall be removed.

[0045] (Embodiment 1) In this embodiment, a semiconductor device, which is an aspect of the present invention, will be described with reference to the drawings. Note that in this embodiment, a semiconductor device, which is an aspect of the present invention, will be described by taking a liquid crystal display device as an example. Note that the semiconductor device, which is an aspect of the present invention, can also be applied to other display devices.

[0046] FIG. 3 is a diagram for explaining a semiconductor device according to an aspect of the present invention. The semiconductor device shown in FIG. 3 includes a pixel portion 100, a first drive circuit 104, a second drive circuit 106, m scanning lines 107 each arranged in parallel or substantially parallel and having their potentials controlled by the first drive circuit 104, and n signal lines 109 each arranged in parallel or substantially parallel and having their potentials controlled by the second drive circuit 106. Further, the pixel portion 100 includes a plurality of pixels 101 arranged in a matrix. The semiconductor device also has capacitance lines 115 (not shown in FIG. 3). The capacitance lines 115 are each arranged in parallel or substantially parallel along the scanning lines 107 or each arranged in parallel or substantially parallel along the signal lines 109.

[0047] Each scanning line 107 is among the pixels 101 arranged in m rows and n columns in the pixel portion 100, It is electrically connected to the n pixels 101 arranged in any row. Also, each signal line 109 Among the pixels 101 arranged in m rows and n columns, it is electrically connected to the m pixels 101 arranged in any one column . Both m and n are integers of 1 or more. Also, each capacitance line 115 Among the pixels 101 arranged in m rows and n columns, it is electrically connected to the n pixels 101 arranged in any one row . When the capacitance lines 115 are arranged in parallel or substantially parallel along the signal lines 109, among the pixels 101 arranged in m rows and n columns, it is electrically connected to the m pixels 101 arranged in any one column .

[0048] Note that the first driving circuit 104 can have a function of supplying a signal for switching the transistor connected to the scanning line 107, for example, a function as a scanning line driving circuit . Also, the second driving circuit 106 can have a function of supplying a video signal to the transistor connected to the signal line 109, for example, a function as a signal line driving circuit. Note that, without being limited to this, the first driving circuit 104 and the second driving circuit 106 can also supply other signals .

[0049] Also, in this embodiment, for the purpose of explaining the liquid crystal display device as an example, for convenience, the wiring connected to the first driving circuit 104 is referred to as the scanning line 107 and the capacitance line 115, and the wiring connected to the second driving circuit 106 is referred to as the signal line 109, but the function is not limited by the name .

[0050] FIG. 1 is a top view for explaining an example of the configuration of the pixel 101 included in the semiconductor device. Note that, in FIG. 1, one of the pair of electrodes of the liquid crystal layer and the liquid crystal element is omitted .​​​​​ 。

[0051] In the pixel 101 shown in FIG. 1, the scanning line 107 is provided to extend in a direction substantially orthogonal to the signal line 109 (row direction) ). The signal line 109 is provided to extend in a direction substantially orthogonal to the scanning line 107 (column direction) ). The capacitance line 115 is provided to extend in a direction parallel to the signal line 109 . Note that the scanning line 107 is electrically connected to the first drive circuit 104 (see FIG. 3), and the signal line 109 is electrically connected to the second drive circuit 106 (see FIG. 3) .

[0052] The transistor 103 is provided in the vicinity of the region where the scanning line 107 and the signal line 109 intersect . The transistor 103 includes at least a semiconductor film 111 having a channel formation region, a gate electrode, a gate insulating film (not shown in FIG. 1), a source electrode, and a drain electrode . Note that in the scanning line 107, the region overlapping with the semiconductor film 111 functions as the gate electrode of the transistor 103 . In the signal line 109, the region overlapping with the semiconductor film 111 functions as one of the source electrode or the drain electrode of the transistor 103 . In the conductive film 11 3, the region overlapping with the semiconductor film 111 functions as the other of the source electrode or the drain electrode of the transistor 103 . Therefore, the gate electrode, the source electrode, and the drain electrode may be respectively indicated as the scanning line 107, the signal line 109, and the conductive film 113 . Also, in FIG. 1, the scanning line 107 has an end portion located outside the end portion of the semiconductor film 111 in the upper surface shape . Therefore, the scanning line 107 functions as a light-shielding film that blocks light from the outside. As a result, the semiconductor film 111 included in the transistor is not irradiated with light, and the electrical characteristics of the transistor do not change . Movement can be suppressed.

[0053] In addition, in one aspect of the present invention, it is preferable to use an oxide semiconductor for the semiconductor film 111. Oxidation For a transistor using an oxide semiconductor, the off-current can be made extremely small by fabricating it under appropriate conditions. Therefore, the power consumption of the semiconductor device can be reduced.

[0054] In one aspect of the present invention, the transistor using an oxide semiconductor is an n-channel transistor. In addition, oxygen deficiencies contained in the oxide semiconductor may generate carriers, which may deteriorate the electrical characteristics and reliability of the transistor. For example, the threshold voltage of the transistor may vary in the negative direction, and a drain current may flow when the gate voltage is 0 V. In this way, when the gate voltage is 0 V, the situation where a drain current flows is called normally-on characteristics. Note that a transistor for which it can be considered that no drain current flows when the gate voltage is 0 V is called normally-off characteristics. In this way, when the gate voltage is 0 V, the situation where a drain current flows is called normally-on characteristics. In this way, when the gate voltage is 0 V, the situation where a drain current flows is called normally-on characteristics. Note that a transistor for which it can be considered that no drain current flows when the gate voltage is 0 V is called normally-off characteristics.

[0055] Therefore, when using an oxide semiconductor for the semiconductor film 111, it is preferable that defects (typically oxygen deficiencies) contained in the oxide semiconductor film that is the semiconductor film 111 are reduced as much as possible. For example, the spin density (corresponding to the defect density contained in the oxide semiconductor film) with g value = 1.93 by the electron spin resonance method in which the direction of the magnetic field is applied parallel to the film surface is preferably reduced to below the detection lower limit of the measuring instrument. By reducing the defects contained in the oxide semiconductor film as much as possible, it is possible to suppress the transistor 103 from having normally-on characteristics, and it is possible to improve the electrical characteristics and reliability of the semiconductor device. .93 of the spin density (corresponding to the defect density contained in the oxide semiconductor film) by the electron spin resonance method in which the direction of the magnetic field is applied parallel to the film surface is preferably reduced to below the detection lower limit of the measuring instrument. By reducing the defects contained in the oxide semiconductor film as much as possible, it is possible to suppress the transistor 103 from having normally-on characteristics, and it is possible to improve the electrical characteristics and reliability of the semiconductor device. By reducing the defects contained in the oxide semiconductor film as much as possible, it is possible to suppress the transistor 103 from having normally-on characteristics, and it is possible to improve the electrical characteristics and reliability of the semiconductor device.

[0056] A negative shift in the threshold voltage of a transistor may be caused not only by oxygen vacancies but also by hydrogen contained in an oxide semiconductor (including hydrogen compounds such as water). Some of the hydrogen contained in the oxide semiconductor contributes to the formation of donor levels and generates electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. Therefore, when using an oxide semiconductor for the semiconductor film 111, it is preferable that the oxide semiconductor film of the semiconductor film 111 has as little hydrogen as possible. Specifically, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is less than 5×10 atoms / cm

[0057] Thus, when using an oxide semiconductor for the semiconductor film 111, it is preferable that the oxide semiconductor film of the semiconductor film 111 has as little hydrogen as possible. Specifically, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is less than 5×10 atoms / cm (SIMS: Secondary Ion Mass Spectrometry) is less than 5×10 18 atoms / cm 3 preferably less than 1×10 18 atoms / cm 3 or less, more preferably less than 5×10 17 atoms / cm 3 or less, and even more preferably less than 1×10 16 atoms / cm 3 or less. The semiconductor film 11 1 is formed to have such a region.

[0058] In addition, it is preferable to form the semiconductor film 111 to have a region where the concentration of an alkali metal or an alkaline earth metal obtained by secondary ion mass spectrometry is 1×10 atoms / cm 18 or less, preferably 2×10 3 atoms / cm 16 or less, and 3 below. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, they may generate carriers, and the transistor This may increase the off-state current of the transistor 103.

[0059] In addition, when nitrogen is contained in the oxide semiconductor film that is the semiconductor film 111, the electron This causes the electrons to be generated, increasing the carrier density and making it easier to become n-type. Transistors using oxide semiconductors tend to be normally-on. In the nitride semiconductor film, it is preferable that the nitrogen is reduced as much as possible. For example, The concentration is 5 x 10 18 atoms / cm 3 The semiconductor film 111 has the following regions: It is preferable to form

[0060] In this way, impurities (hydrogen, nitrogen, alkali metals or alkaline earth metals, etc.) can be removed. The oxide semiconductor film 111 is purified as much as possible to reduce the amount of oxygen contained in the oxide semiconductor film. This can prevent the transistor 103 from becoming normally on, and the off-current of the transistor 103 can be reduced. Therefore, a semiconductor device having good electrical characteristics can be manufactured. In addition, a semiconductor device with improved reliability can be manufactured.

[0061] Note that the off-state current of a transistor using a highly purified oxide semiconductor film is low. This can be proved by various experiments. For example, when the channel width is 1×10 6 The channel length L in μm Even with a 10 μm element, the voltage between the source and drain electrodes (drain voltage) is 1 V. In the range of 10 V to 10 V, the off-state current is below the measurement limit of the semiconductor parameter analyzer. That is, 1 × 10 -13 In this case, the transistor The off-state current, which corresponds to the value obtained by dividing the value by the channel width, is found to be 100 zA / μm or less. In addition, the capacitance element and the transistor are connected to each other, so that current can flow into or out of the capacitance element. The off-state current was measured using a circuit that controls the outflow of charge using the transistor. In the measurement, a highly purified oxide semiconductor film was used for a channel formation region of the transistor. The off-state current of the transistor is measured based on the change in the amount of charge per unit time of the capacitance element. As a result, when the voltage between the source and drain electrodes of the transistor was 3 V, several tens of It was found that an extremely low off-state current of yA / μm was obtained. A transistor using a fluorinated oxide semiconductor film has an extremely small off-state current. can.

[0062] In FIG. 1, the conductive film 113 is formed of a conductive film that transmits light through the opening 117. It is electrically connected to a pixel electrode 121 which is one of the electrodes of the liquid crystal element.

[0063] The capacitor 105 has a semiconductor film 119 formed of a light-transmitting oxide semiconductor. A pixel electrode 121 having a light transmitting property is used as the other electrode. The dielectric film is a light-transmitting insulating film (not shown in FIG. 1). The capacitor 105 has a light-transmitting property. 119 is electrically connected to the capacitance line 115 .

[0064] In this manner, since the capacitor 105 has a light-transmitting property, the capacitor 105 transmits light even in an overlapping region with the liquid crystal element. Therefore, the capacitance element 105 can be made large (large surface area) in the pixel 101. Even if it is formed in the product, the aperture ratio can be increased to, for example, 55% or more, and further 60% or more. Moreover, a semiconductor device with an increased capacitance in the capacitive element can be obtained.

[0065] For example, in a liquid crystal display device with high resolution, the area of the entire pixel is reduced, but in the capacitive element, the necessary capacitance must be ensured, and there is a limit to the reduction of the area. For this reason, in a liquid crystal display device with high resolution, the aperture ratio becomes small. On the other hand, since the capacitive element 105 shown in this embodiment has translucency, by providing the capacitive element in the pixel, it is possible to increase the aperture ratio while obtaining sufficient capacitance in each pixel. Typically, it is preferably used for a high-resolution liquid crystal display device with a pixel density of 200 ppi or more, and further 300 ppi or more. Also, one aspect of the present invention can increase the aperture ratio, so that the light of a light source such as a backlight can be efficiently used, and the power consumption of the display device can be reduced. Moreover, since it is possible to increase the aperture ratio, the light of a light source such as a backlight can be efficiently used, and the power consumption of the display device can be reduced.

[0066] Next, cross-sectional views between the dashed-dotted lines A1 - A2, B1 - B2, and C1 - C2 shown in FIG. 1, and a cross-sectional view of the transistor used in the first drive circuit 104 shown in FIG. 3 are shown in FIG. 2. Note that the top view of the first drive circuit 104 is omitted, and in FIG. 2, the cross-sectional view of the first drive circuit 104 is shown as D1 - D2. Also, the transistor used in the first drive circuit 104 can also be used in the second drive circuit 106. First, the cross-sectional structure between the dashed-dotted lines A1 - A2, B1 - B2, and C1 - C2 of the pixel 101 will be described. First, the cross-sectional structure of the pixel 101 between the dashed-dotted lines A1 - A2, B1 - B2, and C1 - C2 will be described.

[0067] First, the cross-sectional structure between the dashed-dotted lines A1 - A2, B1 - B2, and C1 - C2 of the pixel 101 will be described. First, the cross-sectional structure between the dashed-dotted lines A1 - A2, B1 - B2, and C1 - C2 of the pixel 101 will be described.

[0068] On the substrate 102, an underlying insulating film 110 is provided, and a semiconductor film 111 and a semiconductor conductive film 119 are provided on the underlying insulating film. On the semiconductor film 111, a signal line 109 including one of the source electrode or the drain electrode of the transistor 103, and a conductive film 113 including the other of the source electrode or the drain electrode of the transistor 103 are provided. On the semiconductor film 119, a capacitor line 115 is provided. On the semiconductor film 111, the semiconductor film 119, the signal line 109, the conductive film 113, and the capacitor line 115, a gate insulating film 127 is provided, and a scanning line 107 is provided on the region overlapping with the semiconductor film 111 of the gate insulating film 127. On the gate insulating film 127, on the signal line 109, on the semiconductor film 111, on the conductive film 113, and on the semiconductor film 119, insulating films 129, 131, and 132 functioning as a protective insulating film of the transistor 103 are provided. The insulating films 129, 131, and 132 are provided with an opening 117 (see FIG. 1) reaching the conductive film 113, and a pixel electrode 121 (see FIG. 1) is provided so as to cover the opening.

[0069] In the capacitor element 105 shown in this embodiment, one of the pair of electrodes is a semiconductor film 119 formed in the same manner as the semiconductor film 111 on the underlying insulating film 110, and the other of the pair of electrodes is the pixel electrode 121, and the dielectric film provided between the pair of electrodes is the insulating films 129, 131, and 132.

[0070] Note that a dopant may be added to the semiconductor film 119. When the semiconductor film 119 is an oxide semiconductor, for example, hydrogen, boron, nitrogen, fluorine, aluminum, phosphorus, arsenic, Adding one or more dopants selected from indium, tin, antimony, and noble gas elements can make the oxide semiconductor layer n-type and increase the conductivity. Therefore , the semiconductor film 119 can also be referred to as a conductive film and can act as one electrode of the capacitive element.

[0071] Note that the semiconductor film 119 acting as a conductive film preferably has a higher hydrogen concentration than the semiconductor film 111. In the semiconductor film 119, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Second ary Ion Mass Spectrometry) is 8 ×10 19 atoms / cm 3 or more, preferably 1×10 20 atoms / cm 3 or more, more preferably 5×10 20 atoms / cm 3 or more. In the semiconductor film 111, the hydrogen concentration obtained by secondary ion mass spectrometry is 5×10 19 atoms / cm 3 or less , preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 ato ms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less, even more preferably 1×10 16 atoms / cm 3 or less.

[0072] Also, the semiconductor film 119 acting as a conductive film has a lower resistivity than the semiconductor film 111. The resistivity of the semiconductor film 119 is 1×10 times or more and 1×10 ―8 times or less of the resistivity of the semiconductor film 111. ―1 It is preferably as follows, typically 1×10 ―3 Ωcm or more and less than 1×10 4 Ωcm, and more preferably, the resistivity is 1×10 Ωcm or more and less than 1×10 ―3 Ωcm. ―1 It is good that it is less than .

[0073] Note that the semiconductor film 119 can be formed of a material different from that of the semiconductor film 111 or the semiconductor film 231. That is, the semiconductor film 119 can also be formed using a process different from that of the semiconductor film 111 or the semiconductor conductor film 231.

[0074] Note that a semiconductor film can be formed in the same manner as the semiconductor film 119, and a resistance element can be configured using the semiconductor film. Then, a protection circuit can be configured using the resistance element. By providing a protection circuit, destruction from static electricity or the like can be reduced. .

[0075] Next, the structure of the transistor provided in the first drive circuit 104 will be described.

[0076] A conductive film 241 is provided on the substrate 102, and a base insulating film 110 is provided on the substrate and on the conductive film. In a region overlapping the conductive film 241 on the base insulating film 110, a semi conductor film 231 is provided. On the semiconductor film 231, a wiring 229 including one of the source electrode or the drain electrode of the transistor 223, and a wiring 233 including the other of the source electrode or the drain electrode of the transistor 223 are provided. On the semiconductor film 231, the wiring 22 9, and the wiring 233, a gate insulating film 127 is provided, and a gate electrode 227 is provided on a region of the gate insulating film overlapping the semiconductor film 231. The gate insulating film 127 ​ On the upper gate electrode 227, an insulating film 1 that functions as a protective insulating film for the transistor 223 is provided. 29, an insulating film 131, and an insulating film 132 are provided. Note that the transistors provided in the first driving circuit 10 4 may have a configuration in which the conductive film 241 is not provided.

[0077] In the transistor 223, by providing a conductive film 241 that overlaps with the gate electrode 227 via the semiconductor film 231, the variation in the turn-on current rising gate voltage can be reduced at different drain voltages. Also, on the surface of the semiconductor film 231 facing the conductive film 241, it is possible to control the current flowing between the wiring 229 and the wiring 233, and the variation in electrical characteristics between transistors can be reduced. Also, by providing the conductive film 2 41, the influence of the change in the surrounding electric field on the semiconductor film 231 can be reduced, and the reliability of the transistor can be improved. Furthermore, by setting the potential of the conductive film 241 to the same potential or an equivalent potential as the lowest potential (Vss, for example, the potential of the wiring 229 when the potential of the wiring 229 is used as a reference) of the driving circuit, the variation in the threshold voltage of the transistor can be reduced, and the reliability of the transistor can be enhanced. Note that the gate insulating film 127, the scanning line 107, and the insulating film provided on the gate electrode 227 are not limited to the above-described three-layer configuration, and may be one layer, two layers, or four or more layers.

[0078] In addition, the gate insulating film 127, the scanning line 107, and the insulating film provided on the gate electrode 227 are not limited to the above-described three-layer configuration, and may be one layer, two layers, or four or more layers. not limited to the above-described three-layer configuration, and may be one layer, two layers, or four or more layers.

[0079] Next, the components of the above structure will be described in detail.

[0080] There are no major restrictions on the material of the substrate 102, etc., but at least in the manufacturing process of the semiconductor device, ​It is necessary to have heat resistance to withstand the heat treatment performed. For example, there are glass substrates, ceramic substrates, plastic substrates, etc. As the glass substrate, an alkali-free glass substrate such as barium borosilicate glass, aluminoborosilicate glass or aluminosilicate glass may be used. Also, it is possible to use a substrate that does not have translucency such as a stainless alloy. In that case, it is preferable to provide an insulating film on the substrate surface. Note that as the substrate 102, a quartz substrate, a sapphire substrate, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate, an SOI (Silicon On Insulator) substrate, etc. can also be used. The underlayer insulating film 110 can be formed of an insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or a Ga-Zn based metal oxide, and can be formed in a single layer structure or a laminated structure. The thickness of one region of the underlayer insulating film 110 is 30 nm or more and 500 nm or less, preferably 150 nm or more and 400 nm or less. It is preferable to use an oxide semiconductor film for the semiconductor film 111, the semiconductor film 119, and the semiconductor film 231. The oxide semiconductor film can have an amorphous structure, a single crystal structure, or a polycrystalline structure. Also, the thickness of one region of the semiconductor film 111 is 1 nm or more and 100 nm or less, preferably 1 nm or more and 50 nm or less, more preferably 1 nm or more and 30 nm or less, and most preferably 3 nm or more and 20 nm or less. Note that a light shielding film is provided under the underlayer insulating film 110 so as to hide the channel region of the semiconductor film 111.

[0081]

[0082]

[0083] It is also possible to configure. As the light-shielding film, for example, it may be formed simultaneously with the conductive film 241. Okay.

[0084] As a semiconductor applicable to the semiconductor film 111, the semiconductor film 119, and the semiconductor film 231, an oxide semiconductor having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more, and less than 3.9 eV, preferably less than 3.7 eV, more preferably less than 3.5 eV is exemplified. Thus, by using an oxide semiconductor having a wide energy gap, the off-current of the transistor 103 can be reduced. Further, the oxide semiconductor has a high transmittance to visible light and can be used for one electrode of the capacitor element 105 to form a transparent capacitor element, thereby improving the aperture ratio of pixels in a liquid crystal display device or the like. The energy gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. And less than 3.9 eV, preferably less than 3.7 eV, more preferably less than 3.5 eV. By using an oxide semiconductor having a wide energy gap in this way, the off-current of the transistor 103 can be reduced. Further, the oxide semiconductor has a high transmittance to visible light and can be used for one electrode of the capacitor element 105 to form a transparent capacitor element, thereby improving the aperture ratio of pixels in a liquid crystal display device or the like. The energy gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. And less than 3.9 eV, preferably less than 3.7 eV, more preferably less than 3.5 eV. Can be improved.

[0085] Note that by n-type doping the oxide semiconductor film, the optical band gap of the oxide semiconductor film can be made 2.4 eV or more and 3.1 eV or less, or 2.6 eV or more and 3.0 eV or less. The energy gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. And less than 3.9 eV, preferably less than 3.7 eV, more preferably less than 3.5 eV. Further, for example, when the oxide semiconductor film used as the semiconductor film 119 is an In-Ga-Zn-based metal oxide with an atomic ratio of In:Ga:Zn = 1:1:1, its optical band gap is 3.15 eV. Also, the optical band gap of indium tin oxide used for the pixel electrode 121 or the like is 3.7 eV to 3.9 eV. Therefore, the semiconductor film 119 can absorb light including the wavelength with the highest energy among the visible light rays that will be transmitted through the pixel electrode 121 and ultraviolet light. There is concern about damage to the eyes caused by the light including the wavelength with high energy and ultraviolet light. A semiconductor using the transparent capacitor element 105 is used for the pixel 101. The energy gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. And less than 3.9 eV, preferably less than 3.7 eV, more preferably less than 3.5 eV. The energy gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. And less than 3.9 eV, preferably less than 3.7 eV, more preferably less than 3.5 eV. The energy gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. And less than 3.9 eV, preferably less than 3.7 eV, more preferably less than 3.5 eV. There is concern about damage to the eyes caused by the light including the wavelength with high energy and ultraviolet light. A semiconductor using the transparent capacitor element 105 having translucency is used for the pixel 101. The device can be said to be gentle on the eyes. Note that the capacitive element 105 does not necessarily have to overlap with the entire area of the pixel 101. At least, as long as the capacitive element 105 overlaps with a part of the pixel 101, it is possible to absorb light including wavelengths with high energy and ultraviolet light among visible light. It can be done.

[0086] The oxide semiconductors applicable to the semiconductor film 111, the semiconductor film 119, and the semiconductor film 231 preferably contain at least indium (In) or zinc (Zn). Or, it preferably contains both In and Zn. Also, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have one or more stabilizers together with them.

[0087] Examples of the stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), or zirconium (Zr), etc. Also, examples of other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc.

[0088] Examples of the oxide semiconductors applicable to the semiconductor film 111, the semiconductor film 119, and the semiconductor film 231 include, for example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, which are oxides containing two metals, ​​​​​​​​​​​​Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, oxides containing three kinds of metals, In-Ga-Zn oxides (also denoted as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, A l-Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In -Zr-Zn oxides, In-Ti-Zn oxides, In-Sc-Zn oxides, In- Y-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr -Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu- Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Z n oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn oxides, oxides containing four kinds of metals such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In -Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Z n oxides, In-Hf-Al-Zn oxides can be used.

[0089] Here, the In-Ga-Zn oxide means an oxide mainly composed of In, Ga, and Zn and the ratio of In, Ga, and Zn is not limited. Also, other metal elements may be included.

[0090] Also, as the oxide semiconductor, a material represented by InMO3(ZnO) m (m>0) can be used. Here, M is one metal element selected from Ga, Fe, Mn, and Co or a combination represents a number of metal elements or an element as the above stabilizer.

[0091] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Ga:Z n = 2:2:1 (= 2 / 5:2 / 5:1 / 5), or In:Ga:Zn = 3:1:2 (= 1 / 2:1 / 6:1 / 3) of the atomic ratio of In-Ga-Zn-based metal oxide can be used. Alternatively, In:Sn:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), I n:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8) of the atomic ratio of In-Sn-Zn-based metal oxide can be used. Note that the atomic ratio of the metal oxide includes a plus or minus 20% variation of the above atomic ratio as an error.

[0092] However, it is not limited to these, and those with an appropriate atomic ratio may be used according to the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.). Also, in order to obtain the required semiconductor characteristics, it is preferable to make the carrier density, impurity concentration, defect density, atomic ratio of metal element and oxygen, interatomic distance, density, etc. appropriate. For example, in the In-Sn-Zn-based oxide, relatively high field-effect mobility can be obtained easily. However, in the In-Ga-Zn -based oxide, the field-effect mobility can also be increased by reducing the defect density in the bulk.

[0093] The signal line 109, the conductive film 113, the capacitive line 115, the wiring 229, and the wiring 233 are preferably formed of a metal film with low resistance in order to reduce the resistance loss. For example, molybdenum ( Mo), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al) ​ Metal materials such as copper (Cu), chromium (Cr), neodymium (Nd), scandium (Sc), etc. or alloy materials mainly composed of these can be used to form a single-layer structure or a laminated structure. It is possible.

[0094] As an example of the signal line 109, the conductive film 113, the capacitor line 115, the wiring 229, and the wiring 233, a single-layer structure using aluminum containing silicon, a two-layer structure with titanium laminated on aluminum, a two-layer structure with titanium laminated on titanium nitride, a two-layer structure with tungsten laminated on titanium nitride, a two-layer structure with tungsten laminated on tantalum nitride, a two-layer structure with copper laminated on a copper-magnesium-aluminum alloy, a two-layer structure with copper laminated on titanium nitride and further with tungsten formed thereon, and a three-layer structure, etc. There are

[0095] For example, for the signal line 109, the conductive film 113, the capacitor line 115, the wiring 229, and the wiring 233, it is preferable to use aluminum or copper which is a low-resistance material. By using aluminum or copper, signal delay can be reduced and display quality can be improved. Note that aluminum has low heat resistance and is likely to cause defects due to hillocks, whiskers, or migration. To prevent aluminum migration, it is preferable to laminate a metal material with a melting point higher than that of aluminum, such as molybdenum, titanium, tungsten, etc. on aluminum. Also, when using copper, to prevent defects due to migration and diffusion of copper elements, it is preferable to laminate a metal material with a melting point higher than that of copper, such as molybdenum, titanium, tungsten, etc. is preferable.

[0096] Also, the materials of the signal line 109, the conductive film 113, the capacitor line 115, the wiring 229, and the wiring 233​ As the material, a conductive material having translucency applicable to the pixel electrode 121 can be used. In the case where the semiconductor device according to one aspect of the present invention is a reflective display device, a conductive material having no translucency can be used for the pixel electrode 121 or the substrate 102.

[0097] The gate insulating film 127 can be formed of an insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or a Ga-Zn based metal oxide, etc., and can be formed in a single layer structure or a laminated structure. Note that in order to improve the interface characteristics with the oxide semiconductor film which is the semiconductor film 111, at least the region of the gate insulating film 1 27 in contact with the semiconductor film 111 is preferably formed of an insulating film containing oxygen.

[0098] Further, by using an insulating film having barrier properties against oxygen, hydrogen, water, etc. for the gate insulating film 127, diffusion of oxygen from the oxide semiconductor film which is the semiconductor film 111 to the outside and intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film can be prevented. Examples of the insulating film having barrier properties against oxygen, hydrogen, water, etc. include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, silicon nitride, etc.

[0099] Also, as the gate insulating film 127, hafnium silicate (HfSiO x ), hafnium silicate having nitrogen (HfSi O x y N z ), hafnium aluminate having nitrogen (HfAlx O y N z ) By using high-k materials such as hafnium oxide and yttrium oxide, the gate leakage of transistor 103 can be reduced.

[0100] Further, the gate insulating film 127 preferably has the following laminated structure from the gate electrode side. As the first silicon nitride film, a silicon nitride film with a small amount of defects is provided. On the first silicon nitride film, as the second silicon nitride film, a silicon nitride film with a small amount of hydrogen desorption and ammonia desorption is provided. On the second silicon nitride film, it is preferable to provide any of the insulating films containing oxygen that can be used as the gate insulating film 127.

[0101] As the second silicon nitride film, in the temperature-programmed desorption gas analysis method, the desorption amount of hydrogen molecules is 5× 10 21 molecules / cm 3 less than, preferably 3×10 21 molecules / cm 3 or less, more preferably is 1×10 21 molecules / cm 3 or less, and the desorption amount of ammonia molecules is 1×10 22 molecules / cm 3 less than, preferably 5×10 21 molecules / cm 3 or less, more preferably 1×10 21 molecules / cm 3 or less. It is preferable to use a silicon nitride film with such properties. By using the first silicon nitride film and the second silicon nitride film as part of the gate insulating film 127, a gate insulating film with a small amount of defects and a small amount of hydrogen and ammonia desorption can be formed as the gate insulating film 127. Therefore, the hydrogen contained in the gate insulating film 127 and It becomes possible to reduce the diffusion amount of boron and nitrogen into the semiconductor film 111.

[0102] In a transistor using an oxide semiconductor, at the interface between the oxide semiconductor film and the gate insulating film or when there are trap levels (also referred to as interface levels) in the gate insulating film, the threshold voltage of the transistor tends to vary, typically in the negative direction of the threshold voltage. Also, the trap level causes an increase in the subthreshold coefficient (S value) indicating the gate voltage required for the drain current to change by one digit when the transistor is in the on state. Further, the change in the above electrical characteristics is not uniform, and there is a problem that the electrical characteristics vary from transistor to transistor. Therefore, by using a silicon nitride film with a small amount of defects as the gate insulating film, and by providing an insulating film containing oxygen in the region in contact with the semiconductor film 111, it is possible to reduce the negative shift of the threshold voltage and suppress the increase in the S value. The thickness of one region of the gate insulating film 127 is 5 nm or more and 400 nm or less, more preferably 10 nm or more and 300 nm or less, and still more preferably 50 nm or more and 250 nm or less.

[0103] The scanning line 107, the gate electrode 227, and the conductive film 241 can be formed using materials applicable to the signal line 109, the conductive film 113, the capacitance line 115, the wiring 229, and the wiring 233, and can be formed in a single-layer structure or a

[0104] laminated structure. Furthermore, as part of the materials for the scanning line 107, the gate electrode 227, and the conductive film 241, a metal oxide containing nitrogen, specifically, an In-Ga-Zn-based oxide containing nitrogen or an I containing nitrogen

[0105] ​​​n-Sn oxides, In-Ga oxides containing nitrogen, and In-Zn oxides containing nitrogen Nitrogen-containing Sn-based oxides, nitrogen-containing In-based oxides, and metal nitride films (InN, Sn These materials have a work function of 5 eV (electron volts) or more. When an oxide semiconductor is used for the semiconductor film 111 of the transistor 103, By using a metal oxide containing nitrogen as the gate electrode of the transistor 7 (the gate electrode of the transistor 103), The threshold voltage of the transistor 103 can be changed in the positive direction. For example, a nitrogen-containing In-Ga-Zn oxide can be used to realize a transistor with off-state characteristics. In the case of using an oxide semiconductor film, the nitrogen concentration is at least higher than that of the oxide semiconductor film of the semiconductor film 111. In practice, an In-Ga-Zn oxide having a nitrogen concentration of 7 atomic % or more can be used.

[0106] The insulating film 129 and the insulating film 131 are made of, for example, silicon oxide, silicon oxynitride, or alumina. oxide, hafnium oxide, gallium oxide, or Ga-Zn-based metal oxides The border material can be formed in a single layer or laminated structure.

[0107] The thickness of one region of the insulating film 129 is 5 nm to 150 nm, preferably 5 nm to 50 The thickness of the insulating film 131 is preferably 10 nm or more and 30 nm or less. The thickness of the region is 30 nm to 500 nm, preferably 150 nm to 400 nm. do.

[0108] One or both of the insulating films 129 and 131 are made of oxygen that satisfies the stoichiometric composition. It is preferable that the oxide insulating film contains as much oxygen as possible. Prevent the desorption of oxygen from the oxide semiconductor film, and diffuse the oxygen contained in the oxygen-excess region through the gate oxide insulating film 127 into the oxide semiconductor film to be able to compensate for oxygen deficiencies . For example, the amount of oxygen molecules released during heat treatment at 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower, measured by temperature-programmed desorption gas analysis (hereinafter referred to as TDS analysis) is 1.0×10 18 molecules / cm 3 or more. By using an insulating oxide film with such an amount, the oxygen deficiencies contained in the oxide semiconductor film can be compensated for. Note that in one or both of the insulating films 129 and insulating film 131, an insulating oxide film may partially have a region containing oxygen in excess of the stoichiometric composition (oxygen excess region). Even if such an insulating oxide film exists, as long as an oxygen-excess region exists in at least the region superimposed on the semiconductor film 111, the desorption of oxygen from the oxide semiconductor film can be prevented, and the oxygen contained in the oxygen-excess region can be diffused into the oxide semiconductor film to be able to compensate for oxygen deficiencies.

[0109] When the insulating film 131 is an insulating oxide film containing more oxygen than the oxygen satisfying the stoichiometric composition, the insulating film 129 is preferably an insulating oxide film that permeates oxygen. Note that in the insulating film 1 29, all the oxygen that enters the insulating film 129 from the outside does not diffuse through the insulating film 129 but some oxygen remains in the insulating film 129. Also, there is oxygen that is contained in the insulating film 129 in advance and diffuses from the insulating film 129 to the outside. Therefore, the insulating film 129 is preferably an insulating oxide film with a large oxygen diffusion coefficient.

[0110] Also, one or both of the insulating films 129 and 131 have barrier properties against nitrogen For example, a dense oxide insulating film can provide a barrier against nitrogen. Specifically, the fluoride can be dissolved in 0.5% by weight of hydrofluoric acid at 25°C. It is preferable that the etching rate of the oxide insulating film when used is 10 nm / min or less. .

[0111] One or both of the insulating film 129 and the insulating film 131 may be made of silicon oxynitride or nitride. When using an oxide insulating film containing nitrogen, such as silicon oxide, the nitrogen concentration obtained by SIMS is is 3×10 above the SIMS detection limit 20 atoms / cm 3 Less than 1 x 10 1 8 atoms / cm 3 More than 1×10 20 atoms / cm 3 The following areas are to be included: In this way, the semiconductor included in the transistor 103 is preferably formed This can reduce the amount of nitrogen transferred to the membrane 111. The amount of defects in the nitrogen-containing oxide insulating film itself can be reduced.

[0112] The insulating film 132 is made of, for example, silicon oxynitride, silicon nitride, aluminum nitride, or nitride. The insulating material is a nitride, such as aluminum oxide, and is formed in a single layer or multilayer structure. can be done.

[0113] As the insulating film 132, a nitride insulating film with a low hydrogen content may be provided. For example, the surface temperature of the film is 100° C. or higher and 700° C. or lower, preferably 100° C. or higher and 500° C. or lower. The amount of hydrogen molecules released, as measured by TDS analysis performed at a temperature below 500°C, .0×10 21 molecules / cm3 is less than, preferably 3.0×10 21 molecules / cm 3 less than and more preferably 1.0×10 21 molecules / cm 3 and use a nitride insulating film that is less than can be.

[0114] One region of the insulating film 132 preferably has a thickness that can function to suppress the intrusion of impurities such as hydrogen and water from the outside. For example, it is 50 nm or more and 200 nm or less, preferably 50 nm or more and 150 nm or less, and more preferably 50 nm or more and 100 nm or less. By providing the insulating film 132, impurities such as carbon are blocked by the insulating film 132, and the movement of impurities from the outside to the semiconductor films 111 and 231 of the transistor 103 and the transistor 223 is reduced, so that the variation in the electrical characteristics of the transistor can be reduced. 132, impurities such as carbon are blocked by the insulating film 132, and the movement of impurities from the outside to the semiconductor films 111 and 231 of the transistor 103 and the transistor 223 is reduced, so that the variation in the electrical characteristics of the transistor can be reduced. 132, impurities such as carbon are blocked by the insulating film 132, and the movement of impurities from the outside to the semiconductor films 111 and 231 of the transistor 103 and the transistor 223 is reduced, so that the variation in the electrical characteristics of the transistor can be reduced. 132, impurities such as carbon are blocked by the insulating film 132, and the movement of impurities from the outside to the semiconductor films 111 and 231 of the transistor 103 and the transistor 223 is reduced, so that the variation in the electrical characteristics of the transistor can be reduced. is possible.

[0115] In addition, when the insulating film provided on the gate insulating film 127, the scanning line 107, and the gate electrode 227 is a single layer, it is preferable to provide the insulating film 131. Also, when the insulating film is two layers it is preferably provided in the order of the insulating film 131 and the insulating film 132 from the semiconductor film side.

[0116] In addition, between the gate insulating film 127, the scanning line 107, the gate electrode 227, and the pixel electrode 121, the conductive film 241 and the wiring and the like that can be formed simultaneously therewith, the insulating film formed by a CVD method (chemical vapor deposition method) using an organic silane gas, typically a silicon oxide film, may be included. by a CVD method (chemical vapor deposition method) using an organic silane gas, typically a silicon oxide film, may be included.

[0117] The silicon oxide film can be provided with a thickness of 300 nm or more and 600 nm or less. Organosilane As the gas, silicon-containing compounds such as tetraethyl orthosilicate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TM CTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), tris(dimethylamino)silane (SiH(N(CH3)2)3) can be used.

[0118] By forming the silicon oxide film by a CVD method using an organosilane gas, it is possible to improve the flatness of the surface of the element portion formed on the substrate 10 2. As a result, it is possible to reduce the alignment disorder of the liquid crystal and reduce the light leakage without providing a planarization film formed of an organic resin, and at the same time, it is possible to enhance the contrast. Of course, an organic resin may be used instead of the silicon oxide film, or a laminate including the silicon oxide film and an organic resin may be used.

[0119] The pixel electrode 121 can be formed of a conductive material having translucency such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide.

[0120] Next, each component included in the pixel 101 shown in this embodiment will be described.

[0121] FIG. 4(A) is an example of the circuit diagram of the pixel 101 described above. The pixel 101 has a transistor 103, a capacitive element 105, and a liquid crystal element 108. The gate electrode of the transistor 103 is electrically connected to the scanning line 107, and one of the source electrode or the drain electrode is electrically connected to the signal line 109, and the other of the source electrode or the drain electrode is electrically connected to one electrode of the capacitive element 105 and one electrode (pixel electrode) of the liquid crystal element 108. Also, the other electrode of the capacitive element 105 is electrically connected to the capacitance line 115, and the other electrode (opposing electrode) of the liquid crystal element 108 is electrically connected to a wiring that supplies an opposing potential to the opposing electrode.

[0122] The liquid crystal element 108 is an element that controls the transmission or non - transmission of light by the optical modulation action of the liquid crystal sandwiched between a substrate on which the transistor 103 and the pixel electrode are formed and an opposing substrate (for example, a substrate on which the opposing electrode is formed). The optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a vertical electric field or an oblique electric field). When the pixel electrode and the opposing electrode (also called a common electrode) are formed on one substrate side, the electric field applied to the liquid crystal is a horizontal electric field. Note that the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a vertical electric field or an oblique electric field). When the pixel electrode and the opposing electrode (also called a common electrode) are formed on one substrate side, the electric field applied to the liquid crystal is a horizontal electric field. Note that the electric field applied to the liquid crystal is a horizontal electric field. Note that when the pixel electrode and the opposing electrode (also called a common electrode) are formed on one substrate side, the electric field applied to the liquid crystal is a horizontal electric field. The electric field applied to the liquid crystal is a horizontal electric field.

[0123] Also, FIG. 4(B) is an example of a detailed circuit diagram of the pixel 101. As shown in FIG. 4(B) and FIG. 2, the transistor 103 has a scanning line 107 including a gate electrode, a signal line 109 including one of the source electrode or the drain electrode, and a conductive film 113 including the other of the source electrode or the drain electrode. In the capacitive element 105, a semiconductor film 119 connected to the capacitance line 115 serves as one electrode. has.

[0124] In the capacitive element 105, a semiconductor film 119 connected to the capacitance line 115 serves as one electrode. It functions. Also, the pixel electrode 121 connected to the conductive film 113 including the other of the source electrode or the drain electrode functions as the other electrode. Also, the insulating films 129, 131, and 132 provided between the semiconductor film 119 and the pixel electrode 121 function as a dielectric film. The pixel electrode 121 functions as the other electrode. Also, the insulating films 129, 131, and 132 provided between the semiconductor film 119 and the pixel electrode 121 function as a dielectric film. The insulating films 129, 131, and 132 provided between the semiconductor film 119 and the pixel electrode 121 function as a dielectric film. It functions.

[0125] The liquid crystal element 108 is composed of a pixel electrode 121, a counter electrode 154, and a liquid crystal layer provided between the pixel electrode 121 and the counter electrode 154. The liquid crystal element 108 is composed of a pixel electrode 121, a counter electrode 154, and a liquid crystal layer provided between the pixel electrode 121 and the counter electrode 154.

[0126] In the capacitor element 105, the semiconductor film 119 functions as an electrode of the capacitor element even if it has a high resistance similar to the semiconductor film 111. This is because it is possible to make the pixel electrode 121 function as a gate electrode, the insulating films 129, 131, and 132 function as a gate insulating film, and the capacitor line 115 function as a source electrode or a drain electrode. As a result, the capacitor element 105 can be operated in the same manner as a transistor, and the semiconductor film 119 can be made conductive. In the capacitor element 105, the semiconductor film 119 functions as an electrode of the capacitor element even if it has a high resistance similar to the semiconductor film 111. This is because it is possible to make the pixel electrode 121 function as a gate electrode, the insulating films 129, 131, and 132 function as a gate insulating film, and the capacitor line 115 function as a source electrode or a drain electrode. As a result, the capacitor element 105 can be operated in the same manner as a transistor, and the semiconductor film 119 can be made conductive. In the capacitor element 105, the semiconductor film 119 functions as an electrode of the capacitor element even if it has a high resistance similar to the semiconductor film 111. This is because it is possible to make the pixel electrode 121 function as a gate electrode, the insulating films 129, 131, and 132 function as a gate insulating film, and the capacitor line 115 function as a source electrode or a drain electrode. As a result, the capacitor element 105 can be operated in the same manner as a transistor, and the semiconductor film 119 can be made conductive. In the capacitor element 105, the semiconductor film 119 functions as an electrode of the capacitor element even if it has a high resistance similar to the semiconductor film 111. This is because it is possible to make the pixel electrode 121 function as a gate electrode, the insulating films 129, 131, and 132 function as a gate insulating film, and the capacitor line 115 function as a source electrode or a drain electrode. As a result, the capacitor element 105 can be operated in the same manner as a transistor, and the semiconductor film 119 can be made conductive. Therefore, the semiconductor film 119 can function as one electrode of the capacitor element 105. Therefore, the semiconductor film 119 can function as one electrode of the capacitor element 105. It can function.

[0127] Next, the manufacturing method of the semiconductor device shown in FIGS. 1 and 2 will be described with reference to FIGS. 5 and 6. It will be described.

[0128] First, a conductive film 241 is formed on the substrate 102, and an underlying insulating film 110 is formed so as to cover the conductive film. It is formed.

[0129] The conductive film 241 can be formed by forming a conductive film using the above-described materials, forming a mask on the conductive film, and processing using the mask. The conductive film can be formed by a vapor deposition method, a CVD method, etc. The conductive film 241 can be formed by forming a conductive film using the above-described materials, forming a mask on the conductive film, and processing using the mask. The conductive film can be formed by a vapor deposition method, a CVD method, etc. , various film formation methods such as sputtering method and spin coating method can be used. Note that the thickness of the conductive film is not particularly limited and can be determined in consideration of the formation time, desired resistivity, etc. This can be done. The mask can be, for example, a resist mask formed by a photolithography process. Also, the processing of the conductive film can be performed by one or both of dry etching and wet etching.

[0130] The underlying insulating film 110 can be formed using the materials described above. The underlying insulating film can be formed using various film formation methods such as vapor deposition method, CVD method, sputtering method, and spin coating method.

[0131] Next, a semiconductor film 111, a semiconductor film 119, and a semiconductor film 231 are formed (see FIG. 1). The semiconductor film 111, the semiconductor film 119, and the semiconductor film 231 are formed by forming an oxide semiconductor film using the oxide semiconductor described above, forming a mask on the oxide semiconductor film, and processing using the mask. The oxide semiconductor film can be formed using a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, etc. By using the printing method, the element-isolated semiconductor films 111 and 119 can be directly formed on the underlying insulating film 110. When the oxide semiconductor film is formed by the sputtering method, a power supply device for generating plasma can be appropriately used, such as an RF power supply device, an AC power supply device, or a DC power supply device. As the sputtering gas, a rare gas (typically argon), oxygen, a mixed gas of a rare gas and oxygen can be appropriately used. In the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen with respect to the rare gas. Also, ​ The target may be appropriately selected according to the composition of the oxide semiconductor film to be formed. Note that the mask can be, for example, a resist mask formed by a photolithography process. Also, the processing of the oxide semiconductor film can be performed by one or both of dry etching and wet etching. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that etching can be performed into a desired shape. Also, the above oxide semiconductor film may be formed by a CVD method. As the CVD method, thermal CVD methods such as MOCVD (Metal Organic Chemical Vapor Deposition) method and ALD (Atomic Layer Deposition) method may be used. Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0132] VD(Metal Organic Chemical Vapor Depositi on) method and ALD (Atomic Layer Deposition) method and other thermal CVD methods may be used.

[0133] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage. The thermal CVD method may be performed by simultaneously feeding a source gas and an oxidizing agent into the chamber, setting the inside of the chamber at atmospheric pressure or under reduced pressure, and reacting them near or on the substrate to deposit a film on the substrate.

[0134] Also, in the ALD method, the inside of the chamber may be set at atmospheric pressure or under reduced pressure, and the source gases for the reaction may be sequentially introduced into the chamber, and the film may be formed by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more types of source gases are sequentially supplied to the chamber so that the first source gas does not mix with the plurality of types of source gases.

[0135] of source gases are sequentially supplied to the chamber, and the film is formed by repeating the order of gas introduction. An inert gas (such as argon or nitrogen) etc. is introduced simultaneously with or after the source gas, and the source gas of No. 2 is introduced. When introducing the inert gas simultaneously, the inert gas becomes a carrier gas, and an inert gas may also be introduced simultaneously when introducing the second source gas. Alternatively, after discharging the first source gas by vacuum exhaust instead of introducing the inert gas, the second source gas may be introduced. The first source gas adsorbs on the surface of the substrate to form the first layer, and reacts with the subsequently introduced second source gas, and the second layer is laminated on the first layer to form a thin film. By repeating this gas introduction sequence a plurality of times until the desired thickness is reached while controlling the gas introduction sequence, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, which is suitable for manufacturing fine transistors. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethyl

[0136] gallium, and dimethylzinc are used. The chemical formula of trimethylindium is I n(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3 . The chemical formula of dimethylzinc is Zn(CH3)2. Also, these combinations are not limited thereto, and triethylgallium (chemical formula Ga(C2H5 )3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5 )2) can be used instead of dimethylzinc. When forming an In-Ga-Zn-O film by ALD method, In(CH3)3 gas and O3 gas

[0137] ​Sequentially introduce the [chemical name] repeatedly to form an InO2 layer, and then simultaneously introduce Ga(CH3)3 gas and O3 gas to form a GaO layer, and further subsequently simultaneously introduce Zn(CH3)2 and O3 gas to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, these gases can be mixed to form mixed compound layers such as In-Ga-O layer, In-Zn-O layer, Ga-In-O layer, Zn-In -O layer, Ga-Zn-O layer, etc. Note that instead of O3 gas, H2O gas obtained by bubbling with an inert gas such as Ar can be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2 H5)3 gas can be used. Also, instead of Ga(CH3)3 gas, Ga(C2H5) 3 gas can be used. Also, instead of In(CH3)3 gas, In(C2H5)3 gas can be used. Also, Zn(CH3)2 gas can be used. After forming the semiconductor films 111, 119, and 231, heat treatment is performed,

[0138] and dehydrogenation or dehydration of the oxide semiconductor films that are the semiconductor films 111, 119, and 231 is preferably performed. The temperature of the heat treatment is typically 150°C or higher and less than the substrate distortion point, preferably 200°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower. Note that the heat treatment may be performed on the oxide semiconductor film before processing into the semiconductor films 111, 119, and 231. In the heat treatment, the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction or heat radiation of a medium such as heated gas. For example, it may be an apparatus that heats the object to be treated by heat conduction or heat radiation of a medium such as heated gas. For example, it may be an apparatus that heats the object to be treated by heat conduction or heat radiation of a medium such as heated gas. For example,

[0139] in the heat treatment, the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction or heat radiation of a medium such as heated gas. For example, it may be an apparatus that heats the object to be treated by heat conduction or heat radiation of a medium such as heated gas. For example, GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (La mp Rapid Thermal Anneal) equipment, etc., of RTA (Rapid Th ermal Anneal) equipment can be used. The LRTA equipment is a device that heats the object to be processed by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA equipment is a device that performs heat treatment using high-temperature gas. The heat treatment can be carried out in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (argon, helium, etc. ). It is preferable that the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain hydrogen, water, etc. After heating in an inert gas atmosphere, it may be heated in an oxygen atmosphere. The treatment time is preferably 3 minutes to 24 hours.

[0140] Here, a dopant may be added to the semiconductor film 119. The method of adding a dopant to the semiconductor film 119 is to provide a mask in a region other than the semiconductor film 119, and use the mask to add one or more dopants selected from hydrogen, boron, nitrogen, fluorine, aluminum, phosphorus, arsenic, indium, tin, antimony and noble gas elements by ion implantation method or ion doping method . etc. Also, instead of the ion implantation method or the ion doping method, the semiconductor film 119 can be exposed to a plasma containing the dopant to add the dopant . After adding the dopant, heat treatment may be performed. The heat treatment is as described above.

[0141] Here, a dopant may be added to the semiconductor film 119. The method of adding a dopant to the semiconductor film 119 is to provide a mask in a region other than the semiconductor film 119, and use the mask to add one or more dopants selected from hydrogen, boron, nitrogen, fluorine, aluminum, phosphorus, arsenic, indium, tin, antimony and noble gas elements by ion implantation method or ion doping method . etc. Also, instead of the ion implantation method or the ion doping method, the semiconductor film 119 can be exposed to a plasma containing the dopant to add the dopant . etc. Also, instead of the ion implantation method or the ion doping method, the semiconductor film 119 can be exposed to a plasma containing the dopant to add the dopant . etc. Also, instead of the ion implantation method or the ion doping method, the semiconductor film 119 can be exposed to a plasma containing the dopant to add the dopant . Also, after adding the dopant, heat treatment may be performed. The heat treatment is as described above. Details of the heat treatment for dehydrogenation or dehydration of the semiconductor film 111 and the semiconductor film 119 can be appropriately carried out with reference to it.

[0142] Next, the signal line 109, the conductive film 113, the capacitance line 115, the wiring 229, and the wiring 233 are formed. The signal line 109, the conductive film 113, the capacitance line 115, the wiring 229, and the wiring 233 can be formed by forming a conductive film using the above-described materials, forming a mask on the conductive film, and processing using the mask. The mask and the processing can be carried out in the same manner as the conductive film 241.

[0143] Next, a gate insulating film 127 is formed so as to cover the base insulating film 110, the semiconductor film 111, the semiconductor film 119, the semiconductor film 231, the signal line 1 09, the conductive film 113, the capacitance line 115, the wiring 229, and the wiring 233.

[0144] The gate insulating film 127 can be formed using various film formation methods such as CVD method or sputtering method using the above-described materials. When applying gallium oxide to the gate insulating film 127, it can be formed using the MOCVD (Metal Organic Chemical Va por Deposition) method.

[0145] Next, a scanning line 107 is formed in a region overlapping the semiconductor film 111 on the gate insulating film 127, and a gate electrode 227 is formed in a region overlapping the semiconductor film 231 (see FIG. 5(B)).

[0146] The scanning line 107 and the gate electrode 227 can be formed by forming a conductive film using the above-described materials, forming a mask on the conductive film, and processing using the mask. The mask ​​​​​​ Scratching and the said processing can be carried out in the same manner as the conductive film 241.

[0147] Next, an insulating film 129, an insulating film 131, and an insulating film 132 are formed on the gate insulating film 127, the scanning line 107, and the gate electrode 227 (see Fig. 6(A)). Note that the insulating film 129 , the insulating film 131, and the insulating film 132 are preferably formed continuously. By forming them continuously, it is possible to suppress the mixing of impurities at the respective interfaces of the insulating film 129, the insulating film 131, and the insulating film 132.

[0148] The insulating film 129, the insulating film 131, and the insulating film 132 can be formed by various film-forming methods such as the CVD method or the sputtering method using the materials described above.

[0149] The insulating film 129 can be formed, for example, using the insulating film described above. Here, the case of forming a silicon oxide film or a silicon oxynitride film as the insulating film will be described. The formation conditions are as follows: The substrate placed in the evacuated processing chamber of the plasma CVD apparatus is held at 180°C or higher and 400°C or lower, more preferably 200°C or higher and 370°C or lower. The deposition gas containing silicon and the oxidizing gas of the raw material gas are introduced into the processing chamber, and the pressure in the processing chamber is set to 20 Pa or higher and 250 Pa or lower, more preferably 40 Pa or higher and 20 0 Pa or lower, and high-frequency power is supplied to the electrode provided in the processing chamber.

[0150] Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc.

[0151] In addition, by increasing the amount of oxidizing gas to 100 times the amount of deposition gas containing silicon, It is possible to reduce the hydrogen content in the insulating film 129 and to prevent the hydrogen content in the insulating film 129 from being increased. The oxygen diffused from the insulating film 131 can be reduced by Since the insulating film 129 may capture the dangling bonds, When the dangling bonds contained in the insulating film 129 are reduced, the oxygen contained in the insulating film 131 is efficiently diffused into the semiconductor film 111 and the semiconductor film 231 through the gate insulating film 127. The oxygen vacancies in the oxide semiconductor films, which are the semiconductor film 111 and the semiconductor film 231, are filled. As a result, the amount of hydrogen entering the oxide semiconductor film can be reduced. In both cases, oxygen vacancies in the oxide semiconductor film can be reduced.

[0152] The insulating film 131 is an oxide insulating film including the oxygen excess region or an oxygen insulating film having a stoichiometric composition. In the case of forming an oxide insulating film containing more oxygen than Note that the oxide insulating film here is a silicon oxide film or a silicon oxynitride film. The formation of the film will be described below. The formation conditions are as follows: The substrate placed in the evacuated processing chamber is heated to 180° C. or higher and 260° C. or lower, more preferably 1 The temperature is kept between 80°C and 230°C, and the raw material gas is introduced into the treatment chamber to adjust the pressure in the treatment chamber. 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less, 0.17 W / cm2 on the electrode installed in the treatment chamber 2 More than 0.5W / cm 2 The following are more preferred Or 0.25W / cm 2Above 0.35 W / cm 2 The conditions for supplying the following high-frequency power are taken as one example.

[0153] The source gas for the insulating film 131 can be the source gas applicable to the insulating film 129.

[0154] As the formation conditions of the insulating film 131, by supplying the high-frequency power with the above power density in the reaction chamber at the above pressure the decomposition efficiency of the source gas in the plasma increases, the oxygen radicals increase, and the oxidation of the source gas proceeds, so the oxygen content in the insulating film 131 becomes more than the stoichiometric composition. However, when the substrate temperature is the temperature of the above formation conditions, since the bonding force between silicon and oxygen is weak, a part of the oxygen desorbs by heating. As a result, it is possible to form an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition and having a part of the oxygen desorbed by heating. and the oxidation of the source gas proceeds, so the oxygen content in the insulating film 131 becomes more than the stoichiometric composition. However, when the substrate temperature is the temperature of the above formation conditions, since the bonding force between silicon and oxygen is weak, a part of the oxygen desorbs by heating. As a result, it is possible to form an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition and having a part of the oxygen desorbed by heating. and the oxidation of the source gas proceeds, so the oxygen content in the insulating film 131 becomes more than the stoichiometric composition. However, when the substrate temperature is the temperature of the above formation conditions, since the bonding force between silicon and oxygen is weak, a part of the oxygen desorbs by heating. As a result, it is possible to form an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition and having a part of the oxygen desorbed by heating. and the oxidation of the source gas proceeds, so the oxygen content in the insulating film 131 becomes more than the stoichiometric composition. However, when the substrate temperature is the temperature of the above formation conditions, since the bonding force between silicon and oxygen is weak, a part of the oxygen desorbs by heating. As a result, it is possible to form an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition and having a part of the oxygen desorbed by heating. can be achieved.

[0155] In addition, since the insulating film 131 can increase the amount of oxygen desorbed by heating by increasing the film thickness, it is preferable to provide the insulating film 131 thicker than the insulating film 129. Even when the insulating film 131 is provided thicker by providing the insulating film 129, the covering property can be improved. In addition, since the insulating film 131 can increase the amount of oxygen desorbed by heating by increasing the film thickness, it is preferable to provide the insulating film 131 thicker than the insulating film 129. Even when the insulating film 131 is provided thicker by providing the insulating film 129, the covering property can be improved. In addition, since the insulating film 131 can increase the amount of oxygen desorbed by heating by increasing the film thickness, it is preferable to provide the insulating film 131 thicker than the insulating film 129. Even when the insulating film 131 is provided thicker by providing the insulating film 129, the covering property can be improved. can be achieved.

[0156] When the insulating film 132 is provided as a nitride insulating film with a low hydrogen content, it can be formed using the following formation conditions. Here, the case of forming a silicon nitride film is described as the nitride insulating film. As an example of the formation conditions, a substrate placed in a vacuum-exhausted processing chamber of a plasma CVD apparatus is held at 80°C or higher and 400°C or lower, more preferably 200°C or higher and 370°C or lower, and a source gas is introduced into the processing chamber to set the pressure in the processing chamber to 100 Pa or higher and 25 Here, the case of forming a silicon nitride film is described as the nitride insulating film. As an example of the formation conditions, a substrate placed in a vacuum-exhausted processing chamber of a plasma CVD apparatus is held at 80°C or higher and 400°C or lower, more preferably 200°C or higher and 370°C or lower, and a source gas is introduced into the processing chamber to set the pressure in the processing chamber to 100 Pa or higher and 25 Pa or lower. It is set to 0 Pa or less, preferably 100 Pa or more and 200 Pa or less, and the conditions for supplying high-frequency power to the electrode provided in the processing chamber are mentioned.

[0157] As the raw material gas for the insulating film 132, a depositable gas containing silicon, nitrogen, and ammonia are preferably used. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Also, the flow rate of nitrogen is 5 times or more and 50 times or less, preferably 10 times or more and 50 times or less with respect to the flow rate of ammonia. Note that by using ammonia as the raw material gas, the decomposition of the depositable gas containing silicon and nitrogen can be promoted. This is because ammonia dissociates by plasma energy or thermal energy, and the energy generated by the dissociation contributes to the decomposition of the bonds of the depositable gas molecules containing silicon and the bonds of nitrogen molecules. By doing so, a silicon nitride film with a low hydrogen content and capable of suppressing the intrusion of impurities such as hydrogen and water from the outside can be formed. After forming at least the insulating film 131, a heat treatment is performed, and the excess oxygen contained in the insulating film 129 or the insulating film 13 1 is diffused through the gate insulating film 127 into the semiconductor film 111 and the semiconductor film 23 1 to compensate for the oxygen deficiency of the oxide semiconductor films that are the semiconductor film 111 and the semiconductor film 231. Note that the heat treatment can be appropriately performed with reference to the details of the heat treatment for dehydrogenation or dehydration of the semiconductor film 111 and the semiconductor film 231.

[0158] Next, the region where the conductive film 113 of the insulating film 129, the insulating film 131, and the insulating film 132 overlap is provided. 1 to compensate for the oxygen deficiency of the oxide semiconductor films that are the semiconductor film 111 and the semiconductor film 231. Note that the heat treatment can be appropriately performed with reference to the details of the heat treatment for dehydrogenation or dehydration of the semiconductor film 111 and the semiconductor film 231. 1 to compensate for the oxygen deficiency of the oxide semiconductor films that are the semiconductor film 111 and the semiconductor film 231. Note that the heat treatment can be appropriately performed with reference to the details of the heat treatment for dehydrogenation or dehydration of the semiconductor film 111 and the semiconductor film 231. 1 to compensate for the oxygen deficiency of the oxide semiconductor films that are the semiconductor film 111 and the semiconductor film 231. Note that the heat treatment can be appropriately performed with reference to the details of the heat treatment for dehydrogenation or dehydration of the semiconductor film 111 and the semiconductor film 231.

[0159] Next, the region that overlaps with the conductive film 113 of the insulating film 129, the insulating film 131, and the insulating film 132 An opening 117 (see FIG. 1) reaching the conductive film 113 is formed.

[0160] Next, by forming the pixel electrode 121, the semiconductor device shown in FIGS. 1 and 2 can be manufactured (see FIG. 6(B)). The pixel electrode 121 can be formed by using the above-described material to form a conductive film in contact with the conductive film 113 through the opening 117, forming a mask on the conductive film, and processing using the mask. Note that the mask and the processing can be performed in the same manner as the conductive film 24 1. In addition, in the semiconductor device which is one aspect of the present invention, the configuration of the capacitor element can be appropriately changed. For example, as shown in the cross-sectional view of the capacitor element 105 in FIG. 7(A), the gate insulating film 127 may be removed from the dielectric portion of the capacitor element 105. By doing so, the thickness of the dielectric portion can be reduced, and the charge capacitance of the capacitor element 105 can be improved.

[0161] Note that, in order to partially remove the gate insulating film 127, a mask may be formed on the gate insulating film and processed using the mask. Note that the mask and the processing can be performed in the same manner as the conductive film 241. In addition, when forming the gate electrode 227 using a halftone mask, a part of the gate insulating film 127 may be removed. In this case, the photolithography process can be reduced. In addition, either the insulating film 1 29 or the insulating film 131 may be removed.

[0162]

[0162] Alternatively, as shown in the cross-sectional view of the capacitor element 105 in FIG. 7(B), the gate insulating film 127, the insulating film 129, and the insulating film 131 may be removed from the dielectric portion of the capacitor element 105. By doing so, the film thickness of the dielectric portion can be further reduced, and the charge capacitance of the capacitor element 105 can be improved. It can be made upward.

[0163] Also, in the capacitor element 105 shown in FIG. 7(B), the semiconductor film 119 and the insulating film 132 are in contact with each other. The insulating film 132 is preferably a nitride insulating film as described above. The nitride insulating film contains a large amount of nitrogen and hydrogen, and they can be diffused into the semiconductor film 119. When an oxide semiconductor is used as the semiconductor film 119, a part of the nitrogen and hydrogen incorporated into the oxide semiconductor contributes to the formation of donor levels that generate carriers, so that the oxide semiconductor layer can be made n-type. Therefore, the conductivity of the semiconductor film 119 can be improved, and a process of doping impurities into the semiconductor film 119 can be omitted. Also, as shown in FIG. 8, a configuration in which a nitride insulating film 118 is provided between the semiconductor film 119, which is one electrode of the capacitor element 105, and the underlying insulating film 110 may be employed. In such a configuration, similar to FIG. 7(B), nitrogen and hydrogen can be diffused from the nitride insulating film 118 into the semiconductor film 119, and the conductivity of the semiconductor film 119 can be improved. To form the nitride insulating film 118, a film applicable as the insulating film 132 can be formed, a mask can be formed on the film, and the mask can be used for processing to form it. The mask and the processing

[0164] can be performed in the same manner as the conductive film 241. Also, the configuration of the capacitor element shown in FIG. 7(A) or (B) may be combined with the capacitor element. Furthermore, in the semiconductor device according to one aspect of the present invention, the transistor provided in the pixel In the same manner as in FIG. 7(B), nitrogen and hydrogen can be diffused from the nitride insulating film 118 into the semiconductor film 119, and the conductivity of the semiconductor film 119 can be improved. Note that, to form the nitride insulating film 118, a film applicable as the insulating film 132 is formed, a mask is formed on the film, and the mask is used for processing to form it. The mask and the processing can be performed in the same manner as the conductive film 241. Also, the configuration of the capacitor element shown in FIG. 7(A) or (B) may be combined with the capacitor element. That is, the mask and the processing can be performed in the same manner as the conductive film 241. Also, the configuration of the capacitor element shown in FIG. 7(A) or (B) may be combined with the capacitor element. Moreover, the mask and the processing can be performed in the same manner as the conductive film 241. Also, the configuration of the capacitor element shown in FIG. 7(A) or (B) may be combined with the capacitor element. Moreover, in the semiconductor device which is one aspect of this invention, about the transistor provided in a pixel

[0165] Moreover, in the semiconductor device which is one aspect of the present invention, regarding the transistor provided in the pixel The shape is not limited to the shape of the transistor shown in FIGS. 1 and 2, and can be changed as appropriate. For example, in a transistor, one of the source electrode or the drain electrode included in the signal line 109 is U-shaped (C-shaped, U-shaped, or horseshoe-shaped), and a transistor having a shape that surrounds a conductive film including the other of the source electrode or the drain electrode may be used. By adopting such a shape, even if the area of the transistor is small, it is possible to secure a sufficient channel width, and it is possible to increase the amount of drain current (also referred to as on-current) flowing when the transistor is conducting.

[0166] Also, in the pixel 101 shown above, a transistor having one gate electrode is shown as the transistor, but a transistor having two gate electrodes facing each other via the semiconductor film 111 can be used. Note that, as the configuration of the transistor having two gate electrodes, for example, reference can be made to the transistor used in the first driving circuit 104 having the gate electrode 227 and the conductive film 241 shown in FIG. 2.

[0167] The transistor having two gate electrodes has a conductive film under the base insulating film 110 of the transistor 103 described in this embodiment. The conductive film overlaps at least the channel formation region of the semiconductor film 111. By providing the conductive film at a position overlapping the channel formation region of the semiconductor film 111, the potential of the conductive film is preferably set to the lowest potential of the video signal input to the signal line 109. As a result, it is possible to control the current flowing between the source electrode and the drain electrode on the surface of the semiconductor film 111 facing the conductive film, and the transistor The variation in electrical characteristics can be reduced. Also, by providing the conductive film, the influence of changes in the surrounding electric field on the semiconductor film 111 can be reduced, and the reliability of the transistor can be improved.

[0168] Note that the conductive film can be formed by the same materials and methods as the conductive film 241, the scanning line 107, the signal line 109, the pixel electrode 121, etc.

[0169] From the above, by using a semiconductor film formed in the same manufacturing process as the semiconductor film included in the transistor as one electrode of the capacitive element, a semiconductor device having a capacitive element with an increased aperture ratio and an increased charge capacitance can be manufactured while increasing the charge capacitance. As a result, a semiconductor device with excellent display quality can be obtained.

[0170] Also, by using a semiconductor film formed in the same manufacturing process as the semiconductor film included in the transistor as one electrode of the capacitive element, a semiconductor device having a capacitive element with a high aperture ratio and a large charge capacitance can be manufactured without increasing the number of masks required in the photolithography process.

[0171] In addition, since the oxide semiconductor film, which is the semiconductor film included in the transistor, has a reduced oxygen deficiency and reduced impurities such as hydrogen, the semiconductor device according to one aspect of the present invention is a semiconductor device having good electrical characteristics.

[0172] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0173] (Embodiment 2) In this embodiment, the transistor included in the semiconductor device described in the above embodiment and​​​​​​​​​​ One aspect applicable to an oxide semiconductor film used as a semiconductor film in a capacitive element will be described. will be described.

[0174] The oxide semiconductor may have a non-single crystal. The non-single crystal has, for example, CAAC (C Axi s Aligned Crystal), polycrystal, microcrystal, and an amorphous part.

[0175] The oxide semiconductor may have CAAC. Note that an oxide semiconductor having CAAC is referred to as C AAC-OS (C Axis Aligned Crystalline Oxide Semiconductor).

[0176] CAAC-OS can sometimes confirm crystal parts in an observation image by a transmission electron microscope (TEM). ron Microscope). In many cases, the crystal parts included in CAAC-OS have a size that can be accommodated within a cube with a side length of 100 nm in the observation image by TEM. Also, in the observation image by TEM, CAAC-OS may not be able to clearly confirm the boundary between crystal parts. Also, in the observation image by TEM, CAAC-OS may not be able to clearly confirm a grain boundary (also referred to as a grain boundary). Since CAAC-OS does not have a clear grain boundary, segregation of impurities is less likely to occur. Also, since CAAC-OS does not have a clear grain boundary, the density of defect levels is less likely to increase. Also, since CAAC-OS does not have a clear grain boundary, the decrease in electron mobility is small.

[0177] CAAC-OS has a plurality of crystal parts, and in the plurality of crystal parts, the c-axis is perpendicular to the normal of the formation surface. They may be aligned in a direction parallel to the line vector or the normal vector of the surface. Therefore, CAAC-OS uses an X-ray diffraction (XRD) apparatus When performing analysis by the out-of-plane method, a peak may appear at around 2θ = 31°. If the peak at around 2θ = 31° is due to the crystal of InGaZnO4, it indicates that it is oriented in the (00 9) plane. Also, CAAC-OS may show a peak at around 2θ = 36°. If the peak at around 2θ = 36° is due to the crystal of ZnGa2O4, it indicates that it is oriented in the ( 222) plane. Preferably, for CAAC-OS, a peak appears at around 2θ = 31°, and no peak appears at around 2θ = 36°.

[0178] Also, between different crystal parts of CAAC-OS, the directions of the a-axis and the b-axis may not be aligned. For CAAC-OS having the crystal of InGaZnO4, when performing analysis by the in-plane method in which X-rays are incident from a direction perpendicular to the c-axis using an XRD apparatus a peak may appear at around 2θ = 56°. The peak at around 2θ = 56° indicates the (110) plane of the crystal of InG aZnO4. Here, when fixing 2θ in the vicinity of 56° and performing analysis (φ scan) by rotating the sample with the surface normal vector as the axis (φ-axis), six symmetric peaks appear in the case of a single crystal oxide semiconductor in which the directions of the a-axis and the b-axis are aligned However, no distinct peak appears in the case of CAAC-OS.

[0179] Thus, CAAC-OS may be c-axis oriented, and the a-axis and / or the b-axis may not be macroscopically aligned.

[0180] In addition, when spots (bright spots) are observed in the electron diffraction pattern of CAAC-OS, this may occur. In particular, an electron diffraction pattern obtained using an electron beam with a beam diameter of 10 nmφ or less, or 5 nmφ or less, is called an ultramicro electron diffraction pattern.

[0181] Figure 10(A) is an example of the ultramicro electron diffraction pattern of a sample having CAAC-OS. Here, the sample is cut in a direction perpendicular to the formation surface of CAAC-OS and thinned to a thickness of about 40 nm. Here, an electron beam with a beam diameter of 1 nmφ is incident from a direction perpendicular to the cross-section of the sample. From Figure 10(A), it can be seen that spots are observed in the ultramicro electron diffraction pattern of CAAC-OS.

[0182] The crystal parts included in CAAC-OS are aligned such that the c-axis is parallel to the normal vector of the formation surface or the surface of CAAC-OS, and when viewed from a direction perpendicular to the ab-plane, the metal atoms are arranged in a triangular or hexagonal shape, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in a layered shape or the metal atoms and oxygen atoms are arranged in a layered manner. Note that the directions of the a-axis and b-axis may be different between different crystal parts. In this specification, when simply described as perpendicular, the range of 80° or more and 100° or less, preferably 85° or more and 95° or less is also included. When simply described as parallel, the range of -10° or more and 10° or less, preferably -5° or more and 5° or less is also included.

[0183] Since the c-axes of the crystal parts included in CAAC-OS are aligned in a direction parallel to the normal vector of the formation surface or the surface of CAAC-OS, the shape of CAAC-OS (the formed surface) ​​​​​​Depending on the cross-sectional shape of the forming surface or the cross-sectional shape of the surface, they may face in different directions. In addition, the crystallization process such as heat treatment was performed when the film was formed or after it was formed. Therefore, the c-axis of the crystal part is the same as the shape of the CAAC-OS when it is formed. The vectors are aligned to be parallel to the normal vector of the resulting surface or the normal vector of the surface.

[0184] In some cases, the CAAC-OS can be formed by reducing the impurity concentration. Impurities are hydrogen, carbon, silicon, transition metal elements, and other elements that are not the main components of oxide semiconductors. In particular, elements such as silicon have a higher oxygen content than metal elements that make up oxide semiconductors. Therefore, when the element removes oxygen from the oxide semiconductor, This can disrupt the atomic arrangement of the conductor and reduce its crystallinity. Metals, argon, and carbon dioxide have large atomic (or molecular) radii, so they are oxide semiconductors. This can disrupt the atomic arrangement of the conductor and reduce the crystallinity of the oxide semiconductor. The AAC-OS is an oxide semiconductor with a low impurity concentration. Impurities may act as a carrier generation source.

[0185] In the CAAC-OS, the distribution of the crystal parts may not be uniform. In the process of forming the -OS, when crystal growth is performed from the surface side of the oxide semiconductor, The proportion of crystalline parts may be higher near the surface than near the surface. When impurities are mixed into the OS, the crystallinity of the crystalline part in the region where the impurities are mixed decreases. There are times when I do.

[0186] In addition, CAAC-OS can be formed by reducing the density of defect levels. In an oxide semiconductor, oxygen vacancies are defect levels. Oxygen vacancies may become trap levels or may become carrier generation sources by capturing hydrogen. In order to form CAAC-OS, it is important not to generate oxygen vacancies in the oxide semiconductor. Therefore, CAAC-OS is an oxide semiconductor with a low density of defect levels. Or, CAAC-OS is an oxide semiconductor with few oxygen vacancies. In an oxide semiconductor, oxygen deficiency is a defect level. Oxygen deficiency may become a trap level or may become a carrier generation source by capturing hydrogen. In order to form CAAC-OS, it is important not to generate oxygen vacancies in the oxide semiconductor. Therefore, CAAC-OS is an oxide semiconductor with a low density of defect levels. Or, CAAC-OS is an oxide semiconductor with few oxygen vacancies. An oxide semiconductor with a low impurity concentration and a low density of defect levels (few oxygen vacancies) is called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor that is high-purity intrinsic or substantially high-purity intrinsic may be able to reduce the carrier density because there are few carrier generation sources. Therefore, a transistor using such an oxide semiconductor in the channel formation region may rarely have an electrical characteristic (also called normally-on) in which the threshold voltage becomes negative.

[0187] In addition, an oxide semiconductor that is high-purity intrinsic or substantially high-purity intrinsic may have a low trap level density because of its low defect level density. Therefore, a transistor using such an oxide semiconductor in the channel formation region may be a transistor with small fluctuations in electrical characteristics and high reliability. Note that the time required for the charge trapped in the trap level of the oxide semiconductor to disappear may be long, and it may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor with a high trap level density in the channel formation region may have unstable electrical characteristics. In addition, a transistor using CAAC-OS that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so it may be able to reduce the carrier density. Therefore, a transistor using such an oxide semiconductor in the channel formation region may rarely have an electrical characteristic (also called normally-on) in which the threshold voltage becomes negative. In addition, an oxide semiconductor that is high-purity intrinsic or substantially high-purity intrinsic may have a low trap level density because of its low defect level density. Therefore, a transistor using such an oxide semiconductor in the channel formation region may be a transistor with small fluctuations in electrical characteristics and high reliability. Note that the time required for the charge trapped in the trap level of the oxide semiconductor to disappear may be long, and it may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor with a high trap level density in the channel formation region may have unstable electrical characteristics. In addition, a transistor using CAAC-OS that is high-purity intrinsic or substantially high-purity intrinsic

[0188] In addition, a transistor using CAAC-OS that is high-purity intrinsic or substantially high-purity intrinsic It has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0189] CAAC-OS can be formed, for example, by a sputtering method using a DC power supply. It is possible.

[0190] The oxide semiconductor may have polycrystals. An oxide semiconductor having polycrystals is referred to as a polycrystalline oxide semiconductor. The polycrystalline oxide semiconductor includes a plurality of crystal grains. It is possible to confirm crystal grains in the observation image by TEM for the polycrystalline oxide semiconductor. The crystal grains included in the polycrystalline oxide semiconductor often have a particle size of 2 nm or more and 300 nm or less, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less in the observation image by TEM. Also, it may be possible to confirm the boundary between crystal grains in the observation image by TEM for the polycrystalline oxide semiconductor. Also, for the polycrystalline oxide semiconductor, for example, it may be possible to confirm grain boundaries in the observation image by TEM.

[0191] The polycrystalline oxide semiconductor may have a plurality of crystal grains, and the orientations may be different in the plurality of crystal grains. Also, when the polycrystalline oxide semiconductor is analyzed by the out-of-plane method using an XRD apparatus, a peak with 2θ indicating orientation near 31° or peaks indicating a plurality of types of orientation may appear. Also, spots may be observed in the electron diffraction pattern for the polycrystalline oxide semiconductor. Since the polycrystalline oxide semiconductor has high crystallinity, it may have high electron mobility. Therefore, a transistor using the polycrystalline oxide semiconductor in the channel formation region has a high electric field. It is possible to confirm crystal grains in the observation image by TEM for the polycrystalline oxide semiconductor. The crystal grains included in the polycrystalline oxide semiconductor often have a particle size of 2 nm or more and 300 nm or less, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less in the observation image by TEM. Also, it may be possible to confirm the boundary between crystal grains in the observation image by TEM for the polycrystalline oxide semiconductor. Also, for the polycrystalline oxide semiconductor, for example, it may be possible to confirm grain boundaries in the observation image by TEM. The polycrystalline oxide semiconductor may have a plurality of crystal grains, and the orientations may be different in the plurality of crystal grains. Also, when the polycrystalline oxide semiconductor is analyzed by the out-of-plane method using an XRD apparatus, a peak with 2θ indicating orientation near 31° or peaks indicating a plurality of types of orientation may appear. Also, spots may be observed in the electron diffraction pattern for the polycrystalline oxide semiconductor. Since the polycrystalline oxide semiconductor has high crystallinity, it may have high electron mobility.

[0192] The polycrystalline oxide semiconductor has a plurality of crystal grains, and the orientations may be different in the plurality of crystal grains. Also, when the polycrystalline oxide semiconductor is analyzed by the out-of-plane method using an XRD apparatus, a peak with 2θ indicating orientation near 31° or peaks indicating a plurality of types of orientation may appear. Also, spots may be observed in the electron diffraction pattern for the polycrystalline oxide semiconductor. Since the polycrystalline oxide semiconductor has high crystallinity, it may have high electron mobility. Therefore, a transistor using the polycrystalline oxide semiconductor in the channel formation region has a high electric field.

[0193] Since the polycrystalline oxide semiconductor has high crystallinity, it may have high electron mobility. Therefore, a transistor using the polycrystalline oxide semiconductor in the channel formation region has a high electric field. It has an effective mobility. However, impurities may segregate at the grain boundaries in a polycrystalline oxide semiconductor. In addition, the grain boundaries in a polycrystalline oxide semiconductor become defect levels. Since the grain boundaries in a polycrystalline oxide semiconductor may become carrier generation sources and trap levels, a transistor using a polycrystalline oxide semiconductor in a channel formation region may have larger fluctuations in electrical characteristics and lower reliability than a transistor using CAAC-OS in the channel formation region.

[0194] A polycrystalline oxide semiconductor can be formed by heat treatment at a high temperature or laser light treatment.

[0195] An oxide semiconductor may have microcrystals. Note that an oxide semiconductor having microcrystals is called a microcrystalline oxide semiconductor.

[0196] In an observation image by TEM, it may not be possible to clearly confirm the crystal part in a microcrystalline oxide semiconductor. The crystal parts included in a microcrystalline oxide semiconductor often have a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, microcrystals of 1 nm or more and 10 nm or less are called nanocrystals (nc: nanocrystal). An oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline Oxide Semiconductor). In addition, in an observation image by TEM, it may not be possible to clearly confirm the boundary between crystal parts in nc-OS. In addition, since nc-OS does not have clear grain boundaries, impurities are less likely to segregate. In addition, since nc-OS does not have clear grain boundaries, the density of defect levels is less likely to increase. In addition, since nc-OS does not have clear grain boundaries, the decrease in electron mobility is small. ​​​​​​​​​​​​​​

[0197] nc-OS may have periodic atomic arrangements in a minute region (for example, a region of 1 nm or more and 10 nm or less). Also, since there is no regularity between crystal parts in nc-OS, macroscopically, there may be cases where no periodicity is observed in the atomic arrangement or no long-range order is observed. Therefore, depending on the analysis method, nc-OS may not be distinguishable from an amorphous oxide semiconductor. For example, when nc-OS is analyzed by the out-of-plane method using X-rays with a beam diameter larger than that of the crystal part using an XRD apparatus, no peak indicating orientation may be detected. Also, in an electron diffraction pattern using an electron beam with a beam diameter larger than that of the crystal part (for example, 20 nmφ or more, or 50 nmφ or more) in nc-OS, a halo pattern may be observed. Further, in a nanoelectron diffraction pattern using an electron beam with a beam diameter equal to or smaller than that of the crystal part (for example, 10 nmφ or less, or 5 nmφ or less) in nc-OS, spots may be observed. Also, in the nanoelectron diffraction pattern of nc-OS, regions with high brightness may be observed so as to draw a circle. Also, in the nanoelectron diffraction pattern of nc-OS, a plurality of spots may be observed within the region. Also, in the nanoelectron diffraction pattern of nc-OS, a plurality of spots may be observed in the region.

[0198] Figure 10(B) is an example of the nanoelectron diffraction pattern of a sample having nc-OS. Here, the sample is cut in a direction perpendicular to the surface on which nc-OS is formed and thinned to a thickness of about 40 nm. Also, here, an electron beam with a beam diameter of 1 nmφ is incident from a direction perpendicular to the cut surface of the sample. From Figure 10(B), the nanoelectron diffraction pattern of nc-OS is as follows. Regions with high luminance are observed to draw a circle, and a plurality of spots are observed within the region It can be seen that

[0199] Since nc-OS may have periodicity in the atomic arrangement in a minute region, the density of defect levels becomes lower than that of an amorphous oxide semiconductor. However, since nc-OS has no regularity between crystal parts, the density of defect levels becomes higher than that of CAAC-OS

[0200] Therefore, the carrier density of nc-OS may be higher than that of CAAC-OS. An oxide semiconductor with a high carrier density may have a high electron mobility. Therefore a transistor using nc-OS in the channel formation region may have a high field-effect mobility However, since nc-OS has a higher density of defect levels than CAAC-OS, the trap level density may also be higher. Therefore, a transistor using nc-OS in the channel formation region may have larger fluctuations in electrical characteristics and lower reliability than a transistor using CAAC-OS in the channel formation region. However since nc-OS can be formed even when it contains a relatively large amount of impurities, it is easier to form than CAAC-OS, and may be suitably used depending on the application Note that nc-OS may be formed by a film formation method such as a sputtering method using an AC power source. Since the sputtering method using an AC power source can form a film with high uniformity on a large substrate a semiconductor device having a transistor using nc-OS in the channel formation region can be manufactured with high productivity

[0201] ​​​​​​​​​The oxide semiconductor may have an amorphous portion. Note that an oxide semiconductor having an amorphous portion is referred to as an amorphous oxide semiconductor. In an amorphous oxide semiconductor, the atomic arrangement is disordered and there is no crystalline portion. Or, the amorphous oxide semiconductor has an amorphous state like quartz and no regularity is observed in the atomic arrangement.

[0202] In some cases, a crystalline portion cannot be confirmed in the observation image by TEM for an amorphous oxide semiconductor.

[0203] When an amorphous oxide semiconductor is analyzed by the out-of-plane method using an XRD apparatus, there may be a case where no peak indicating orientation is detected. Also, in some cases, a halo pattern is observed in the electron diffraction pattern for an amorphous oxide semiconductor. Also, in an amorphous oxide semiconductor, spots cannot be observed in the nanoelectron diffraction pattern, and a halo pattern may be observed in some cases.

[0204] An amorphous oxide semiconductor may be formed by including impurities such as hydrogen at a high concentration. Therefore, an amorphous oxide semiconductor is an oxide semiconductor containing impurities at a high concentration.

[0205] When an oxide semiconductor contains impurities at a high concentration, defect levels such as oxygen vacancies may be formed in the oxide semiconductor. Therefore, an amorphous oxide semiconductor with a high impurity concentration has a high defect level density. Also, since an amorphous oxide semiconductor has low crystallinity, it has a higher defect level density than CAAC-OS or nc-OS.

[0206] Therefore, an amorphous oxide semiconductor has a higher carrier density than nc-OS. may occur. Therefore, a transistor using an amorphous oxide semiconductor in the channel formation region may have the electrical characteristics of a normally-on transistor. Therefore, it may be suitably used for a transistor that requires the electrical characteristics of a normally-on transistor. Since the amorphous oxide semiconductor has a high density of defect levels, the trap level density may also be high. Therefore, a transistor using an amorphous oxide semiconductor in the channel formation region may have larger fluctuations in electrical characteristics and lower reliability compared to a transistor using CAAC-OS or nc-OS in the channel formation region. However, since the amorphous oxide semiconductor can also be formed by a film formation method that contains a relatively large amount of impurities, it is easy to form, and depending on the application, it may be suitably used. For example, the amorphous oxide semiconductor may be formed by a film formation method such as a spin coating method, a sol-gel method, a dipping method, a spraying method, a screen printing method, a contact printing method, an inkjet printing method, a roll coating method, or a mist CVD method. Therefore, a semiconductor device having a transistor using an amorphous oxide semiconductor in the channel formation region can be manufactured with high productivity. Note that the oxide semiconductor may be a mixed film having two or more of CAAC-OS, polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and amorphous oxide semiconductor. The mixed film may have, for example, any two or more regions of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, and a CAAC-OS region. Further, the mixed film may have, for example, an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, a transistor using an amorphous oxide semiconductor in the channel formation region may have larger fluctuations in electrical characteristics and lower reliability compared to a transistor using CAAC-OS or nc-OS in the channel formation region. However, since the amorphous oxide semiconductor can also be formed by a film formation method that contains a relatively large amount of impurities, it is easy to form, and depending on the application, it may be suitably used. For example, the amorphous oxide semiconductor may be formed by a film formation method such as a spin coating method, a sol-gel method, a dipping method, a spraying method, a screen printing method, a contact printing method, an inkjet printing method, a roll coating method, or a mist CVD method. Therefore, a semiconductor device having a transistor using an amorphous oxide semiconductor in the channel formation region can be manufactured with high productivity. For example, the amorphous oxide semiconductor may be formed by a film formation method such as a spin coating method, a sol-gel method, a dipping method, a spraying method, a screen printing method, a contact printing method, an inkjet printing method, a roll coating method, or a mist CVD method. Therefore, a semiconductor device having a transistor using an amorphous oxide semiconductor in the channel formation region can be manufactured with high productivity. For example, the amorphous oxide semiconductor may be formed by a film formation method such as a spin coating method, a sol-gel method, a dipping method, a spraying method, a screen printing method, a contact printing method, an inkjet printing method, a roll coating method, or a mist CVD method. Therefore, a semiconductor device having a transistor using an amorphous oxide semiconductor in the channel formation region can be manufactured with high productivity. For example, the amorphous oxide semiconductor may be formed by a film formation method such as a spin coating method, a sol-gel method, a dipping method, a spraying method, a screen printing method, a contact printing method, an inkjet printing method, a roll coating method, or a mist CVD method. Therefore, a semiconductor device having a transistor using an amorphous oxide semiconductor in the channel formation region can be manufactured with high productivity. For example, the amorphous oxide semiconductor may be formed by a film formation method such as a spin coating method, a sol-gel method, a dipping method, a spraying method, a screen printing method, a contact printing method, an inkjet printing method, a roll coating method, or a mist CVD method. Therefore, a semiconductor device having a transistor using an amorphous oxide semiconductor in the channel formation region can be manufactured with high productivity. For example, the amorphous oxide semiconductor may be formed by a film formation method such as a spin coating method, a sol-gel method, a dipping method, a spraying method, a screen printing method, a contact printing method, an inkjet printing method, a roll coating method, or a mist CVD method. Therefore, a semiconductor device having a transistor using an amorphous oxide semiconductor in the channel formation region can be manufactured with high productivity.

[0207] Note that the oxide semiconductor may be a mixed film having two or more of CAAC-OS, polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and amorphous oxide semiconductor. The mixed film may have, for example, any two or more regions of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, and a CAAC-OS region. Further, the mixed film may have, for example, Note that the oxide semiconductor may be a mixed film having two or more of CAAC-OS, polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and amorphous oxide semiconductor. The mixed film may have, for example, any two or more regions of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, and a CAAC-OS region. Further, the mixed film may have, for example, Note that the oxide semiconductor may be a mixed film having two or more of CAAC-OS, polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and amorphous oxide semiconductor. The mixed film may have, for example, any two or more regions of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, and a CAAC-OS region. Further, the mixed film may have, for example, Note that the oxide semiconductor may be a mixed film having two or more of CAAC-OS, polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and amorphous oxide semiconductor. The mixed film may have, for example, any two or more regions of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, and a CAAC-OS region. Further, the mixed film may have, for example, Note that the oxide semiconductor may be a mixed film having two or more of CAAC-OS, polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and amorphous oxide semiconductor. The mixed film may have, for example, any two or more regions of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, and a CAAC-OS region. Further, the mixed film may have, for example, There may be a laminated structure of two or more regions of the CAAC-OS region or the like.

[0208] The oxide semiconductor may have, for example, a single crystal. Note that an oxide semiconductor having a single crystal is referred to as a single crystal oxide semiconductor.

[0209] A single crystal oxide semiconductor has, for example, a low impurity concentration and a low density of defect levels (few oxygen deficiencies), so that the carrier density can be lowered. Therefore, a transistor using a single crystal oxide semiconductor in the channel formation region may rarely have normally-on electrical characteristics. Also, since a single crystal oxide semiconductor has a low density of defect levels, the trap level density may also be low. Therefore, a transistor using a single crystal oxide semiconductor in the channel formation region may be a transistor with small fluctuations in electrical characteristics and high reliability. .

[0210] An oxide semiconductor may have a high density when there are few defects. Also, an oxide semiconductor may have a high density when its crystallinity is high. Also, an oxide semiconductor, for example, has a high density when the impurity concentration of impurities such as hydrogen is low. Also, a single crystal oxide semiconductor may have a higher density than CAAC-OS. Also, CAAC-OS may have a higher density than a microcrystalline oxide semiconductor. Also, a polycrystalline oxide semiconductor may have a higher density than a microcrystalline oxide semiconductor. Also, a microcrystalline oxide semiconductor may have a higher density than an amorphous oxide semiconductor.

[0211] In addition, in order to form a CAAC-OS film, it is preferable to apply the following conditions.

[0212] By reducing the incorporation of impurities during film formation, it is possible to suppress the breakdown of the crystal state due to impurities. This can be achieved, for example, by reducing the impurity concentrations (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber. Also, the impurity concentrations in the film formation gas may be reduced. Specifically, a film formation gas with a dew point of -80°C or lower, preferably -100°C or lower, is used. -80 °C or lower, preferably -100 °C or lower, is used.

[0213] Moreover, by increasing the heating temperature of the surface to be film-formed during film formation (for example, the substrate heating temperature), migration of sputtering particles occurs after reaching the surface to be film-formed. Specifically, film formation is performed with the temperature of the surface to be film-formed at 100°C or higher and 740°C or lower, preferably 150°C or higher and 500°C or lower. at 100 °C or higher and 740 °C or lower, preferably 150 °C or higher and 500 °C or lower.

[0214] Also, it is preferable to reduce the plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing the power. The oxygen ratio in the film formation gas is 30% by volume or more, preferably 100% by volume. at 30% by volume or more, preferably 100% by volume. at 30% by volume or more, preferably 100% by volume.

[0215] As an example of the sputtering target, an In-Ga-Zn-O compound target is shown below. As an example of the sputtering target, an In-Ga-Zn-O compound target is shown below.

[0216] InO X powder, GaO Y powder, and ZnO Z powder are mixed in a predetermined number of moles, and after pressure treatment and heat treatment is performed at a temperature of 1000°C or higher and 1500°C or lower to obtain a polycrystalline In-Ga -Zn-based metal oxide target. The pressure treatment may be performed without cooling (or slow cooling) or while heating. Here, X, Y, and Z are arbitrary positive numbers. Here, the predetermined mole ratio is, for example, InO powder, GaO powder, and ZnO X powder, GaO Y powder, and ZnO Z powder are in a ratio of 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3: There are ratios such as 1:2. Note that the type of powder and the molar ratio of its mixture can be appropriately changed depending on the target for sputtering to be produced.

[0217] Here, a comparison between an oxide semiconductor (denoted as OS) and silicon (denoted as Si) in the crystalline state is shown in Table 1. )

[0218]

Table 1

[0219] For the crystalline state of the oxide semiconductor, for example, as shown in Table 1, there are amorphous oxide semiconductors (a-OS, a-OS:H), microcrystalline oxide semiconductors (nc-OS, μc-OS), polycrystalline oxide semiconductors (polycrystalline OS), continuous crystalline oxide semiconductors (CAAC-OS), single-crystalline oxide semiconductors (single-crystalline OS), etc. Note that for the crystalline state of silicon, for example, as shown in Table 1, there are amorphous silicon (a-Si or a-Si:H), microcrystalline silicon (nc-Si, μc-Si )), polycrystalline silicon (polycrystalline Si), continuous crystalline silicon (CG (Continuous Grain) silicon), single-crystalline silicon (single-crystalline Si), etc. )

[0220] When electron beam diffraction (ultra-micro electron beam diffraction) is performed on the oxide semiconductor in each crystalline state using an electron beam focused to a beam diameter of 10 nmφ or less, the following electron beam diffraction patterns (ultra-micro electron beam diffraction patterns) are observed. In the amorphous oxide semiconductor, a halo pattern (also called a halo ring or halo) is observed. In the microcrystalline oxide semiconductor, a spot or / and ring pattern is observed. In the polycrystalline oxide semiconductor, spots are observed. It is measured. In a continuous crystal oxide semiconductor, spots are observed. In a single crystal oxide semiconductor , spots are observed.

[0221] From the ultramicroelectron beam diffraction pattern, it can be seen that the microcrystalline oxide semiconductor has a crystal part with a diameter ranging from nanometers (n m) to micrometers (μm). The polycrystalline oxide semiconductor has a grain boundary between crystal parts, and it can be seen that the boundary is discontinuous. The continuous crystal oxide semi conductor has no observed boundary between crystal parts and is continuously connected.

[0222] The density of the oxide semiconductor in each crystal state will be described. The density of the amorphous oxide semiconductor is low. The density of the microcrystalline oxide semiconductor is medium. The density of the continuous crystal oxide semiconductor is high. That is, the density of the continuous crystal oxide semiconductor is higher than that of the microcrystalline oxide semiconductor, and the density of the microcrystalline oxide semiconductor is higher than that of the amorphous oxide semiconductor.

[0223] The characteristics of the density of states (DOS) existing in the oxide semiconductor in each crystal state will be described. The amorphous oxide semiconductor has a high DOS. The microcrystalline oxide semiconductor has a slightly low DOS. The continuous crystal oxide semiconductor has a low DOS. The single crystal oxide semiconductor has an extremely low DOS. That is, the single crystal oxide semiconductor has a lower DOS than the continuous crystal oxide semiconductor, the continuous crystal oxide semiconductor has a lower DOS than the microcrystalline oxide semiconductor, and the microcrystalline oxide semiconductor has a lower DOS than the amorphous oxide semiconductor .

[0224] Also, the oxide semiconductor film may have a structure in which a plurality of oxide semiconductor films are stacked. For example, as shown in Fig. 9(A) of the transistor, the semiconductor film is composed of a first oxide semiconductor film 188a and a second ​It can be a stack of the oxide semiconductor films 188b. The first oxide semiconductor film 188a and For the second oxide semiconductor film 188b, metal oxides with different atomic ratios may be used. For example , for one of the oxide semiconductor films, one of the oxides containing two kinds of metals, the oxides containing three kinds of metals, and the oxides containing four kinds of metals is used, and for the other oxide semiconductor film, an oxide containing two kinds of metals different from those of one of the oxide semiconductor films , the oxides containing three kinds of metals, and the oxides containing four kinds of metals may be used.

[0225] Also, the constituent elements of the first oxide semiconductor film 188a and the second oxide semiconductor film 188b may be the same , and the atomic ratios of both may be made different. For example, the atomic ratio of one of the oxide semiconductor films is In:Ga:Zn = 3:1:2, and the atomic ratio of the other oxide semiconductor film may be In:Ga:Z n = 1:1:1. Also, the atomic ratio of one of the oxide semiconductor films may be In:Ga:Z n = 2:1:3, and the atomic ratio of the other oxide semiconductor film may be In:Ga:Zn = 1:3:2 . Also, the atomic ratio of one of the oxide semiconductor films may be In:Ga:Zn = 1:1:1 , and the atomic ratio of the other oxide semiconductor film may be In:Ga:Zn = 1:3:2. Also, the atomic ratio of one of the oxide semiconductor films may be In:Ga:Zn = 1:1:1, and the atomic ratio of the other acid oxide semiconductor film may be In:Ga:Zn = 1:6:4. Also, the atomic ratio of one of the acids oxide semiconductor films may be In:Ga:Zn = 1:1:1, and the atomic ratio of the other oxide semiconductor film may be In:Ga:Zn = 1:9:6. Note that the atomic ratio of each oxide semiconductor film includes fluctuations of plus or minus 20% of the above atomic ratio as an error.

[0226] ​At this time, among one oxide semiconductor film and the other oxide semiconductor film, the atomic number ratio of In and Ga in the oxide semiconductor film on the side closer to the gate electrode ( channel side) is In≧Ga, and the atomic number ratio of In and Ga in the oxide semiconductor film on the side farther from the gate electrode (back channel side) is In<Ga. By doing so, a transistor with high field-effect mobility can be fabricated. On the other hand, by setting the atomic number ratio of In and Ga in the oxide semiconductor film on the channel side to In<Ga and the atomic number ratio of In and Ga in the oxide semiconductor film on the back channel side to In≧Ga, the change over time of the transistor and the amount of change in the threshold voltage due to the reliability test can be reduced. Also, the semiconductor film of the transistor may have a three-layer structure composed of a first oxide semiconductor film to a third oxide semiconductor film. At this time, the constituent elements of the first oxide semiconductor film to the third oxide semiconductor film may be the same, and the atomic number ratios thereof may be different. The configuration of the transistor having a three-layer structure of the semiconductor film will be described with reference to FIG. 9(B). The transistor shown in FIG. 9(B) has a first oxide semiconductor film 199a, a second oxide semiconductor

[0227] film 199b, and a third oxide semiconductor film 199c laminated in this order from the gate insulating film 127 side. The materials constituting the first oxide semiconductor film 199a and the third oxide semiconductor film 199c can be expressed by InM Zn O (x≧1, y>1, z>0, M1 = Ga, Hf, etc.). However, when Ga is included in the materials constituting the first oxide semiconductor film 199a and the third oxide semiconductor film 199c, the proportion of Ga included is large. Specifically,

[0228] InM Zn are laminated in this order from the gate insulating film 127 side. The materials constituting the first oxide semiconductor film 199a and the third oxide semiconductor film 199c can be expressed by InM 1x Zn y O z (x≧1, y>1, z>0, M1 = Ga, Hf, etc.). However, when Ga is included in the materials constituting the first oxide semiconductor film 199a and the third oxide semiconductor film 199c, the proportion of Ga included is large. Specifically, InM Zn InM 1X ZnY O Z When the material represented by exceeds X = 10, powder may be generated during film formation, which is unsuitable.

[0229] Also, the material constituting the second oxide semiconductor film 199b is InM 2x Zn y O z (x ≧ 1 , y ≧ x, z > 0, M2 = Ga, Sn, etc.) is used.

[0230] The lower end of the conduction band of the first oxide semiconductor film 199a and the conduction The lower end of the conduction band of the second oxide semiconductor film 199b is the deepest from the vacuum level compared to the lower end of the conduction band of the third oxide semiconductor film 199c The materials of the first, second, and third oxide semiconductor films are appropriately selected so as to form a well - type structure.

[0231] In the oxide semiconductor film, silicon or carbon, which is one of the Group 14 elements, may contribute to the formation of donor levels. Therefore, when silicon or carbon is contained in the oxide semiconductor film, the oxide semiconductor film will be n - type. Therefore, the respective concentrations of silicon and carbon are 3×10 / cm 18 / cm 3 or less, preferably 3×10 17 / cm 3 It is preferable to form each oxide semiconductor film so as to have a region where. In particular, the first oxide semiconductor film 199a and the third oxide are arranged to sandwich or surround the second oxide semiconductor film 199b, which serves as a carrier path, so that the second oxide semiconductor film 199b is not contaminated with a large amount of Group 14 elements. That is, the first oxide semiconductor film 199a and the third oxide semiconductor film 199c of the second oxide semiconductor film 199b have a low content of Group 14 elements such as silicon and carbon. 199b.​​​​ It can also be called a barrier film that prevents mixing into 199b.

[0232] For example, the first oxide semiconductor film 199a and the third oxide semiconductor film 199c are formed of an oxide semiconductor film having an atomic ratio of In:Ga:Zn = 1:3:2, or 1:6:4, or 1:9:6, and the second oxide semiconductor film 199b can be formed of an oxide semiconductor film having an atomic ratio of In:Ga:Zn = 1:1 :1, or 3:1:2.

[0233] Alternatively, the first oxide semiconductor film 199a is formed of an oxide semiconductor film having an atomic ratio of In:Ga:Zn = 1:3:2, and the second oxide semiconductor film 199b is formed of an oxide semiconductor film having an atomic ratio of In:Ga:Z n = 1:1:1 or In:Ga:Zn = 3:1:2, and the third oxide semiconductor film 199c may be formed of an oxide semiconductor film having an atomic ratio of In:Ga:Zn = 1:6:4, or 1:9 :6.

[0234] Since the constituent elements of the first oxide semiconductor film 199a to the third oxide semiconductor film 199c are the same, the second oxide semiconductor film 199b has few defect levels (trap levels) at the interface with the first oxide semiconductor film 199a. Specifically, the defect levels (trap levels) are fewer than the defect levels at the interface between the gate insulating film 127 and the first oxide semiconductor film 199a. Therefore, due to the lamination of the oxide semiconductor films as described above, the amount of change over time of the transistor and the amount of fluctuation of the threshold voltage due to the reliability test can be reduced.

[0235] In addition, the lower end of the conduction band of the first oxide semiconductor film 199a and the third oxide semiconductor film 199c The bottom of the conduction band of the second oxide semiconductor film 199b is the deepest from the vacuum level compared to the bottom of the conduction band of By appropriately selecting the materials of the first, second, and third oxide semiconductor films so as to form a well-shaped structure in which the bottom of the conduction band becomes the deepest, it is possible to increase the field-effect mobility of the transistor, and at the same time, it is possible to reduce the amount of variation in the threshold voltage due to the change over time of the transistor and the reliability test.

[0236] In addition, oxides with different crystallinities may be applied to the first oxide semiconductor film 199a to the third oxide semiconductor film 199c. That is, single-crystalline oxide semiconductors, polycrystalline oxide semiconductors, microcrystalline (nanocrystalline) oxide semiconductors, amorphous oxide semiconductors, and CAAC-OS films may be appropriately combined. Further, when an amorphous oxide semiconductor is applied to any one of the first oxide semiconductor film 199a to the third oxide semiconductor film 199c, the internal stress and external stress of the oxide semiconductor film are relaxed, the variation in the characteristics of the transistor is reduced, and the amount of variation in the threshold voltage due to the change over time of the transistor and the reliability test can be reduced.

[0237] In addition, the second oxide semiconductor film 199b that can be at least a channel formation region is preferably a CAAC -OS film.

[0238] Note that when a conductive material that easily binds to oxygen (for example, a metal used for a source electrode or a drain electrode) is brought into contact with an oxide semiconductor film, a phenomenon occurs in which oxygen in the oxide semiconductor film diffuses to the side of the conductive material that easily binds to oxygen. This phenomenon occurs more prominently at higher temperatures. Since there are several heating steps in the manufacturing process of the transistor, due to the above phenomenon, in the oxide semiconductor ​​​An oxygen deficiency occurs in a region near the source electrode or drain electrode of the conductor layer, and the region becomes n-type. Therefore, the n-type region can function as the source or drain of the transistor.

[0239] The above n-type region is illustrated in FIGS. 9(A) and (B). The dotted line shown in the semiconductor film boundary 135 is the boundary between the intrinsic semiconductor region and the n-type semiconductor region, and the region near the source electrode or drain electrode in the oxide semiconductor becomes the n-type region. Note that the boundary 135 is schematically shown and may not be clear in reality. Also, the position of the boundary 13 5 may be different from the illustrated position.

[0240] Note that this embodiment can be appropriately combined with other embodiments described in this specification. .

[0241] (Embodiment 3) In this embodiment, the electron diffraction pattern and the localized states of the nanocrystalline oxide semiconductor film that can be used in one aspect of the present invention will be described.

[0242] The nanocrystalline oxide semiconductor film shows neither a halo pattern indicating an amorphous state nor spots having regularity indicating a crystalline state oriented in a specific plane in an electron diffraction pattern using electron diffraction (ultramicro electron diffraction) with a beam diameter of 10 nmφ or less, but rather spots without directionality are observed. It is an oxide semiconductor film.

[0243] FIG. 13(A) shows a cross-sectional TEM (Transmission El ectron Microscope (transmission electron microscope)) image of the nanocrystalline oxide semiconductor film. Also, in FIG. 13( ​​B) The electron diffraction pattern measured by using nanoelectron beam diffraction at point 1 in Fig. 13(A) is shown in Fig. 13(C), and the electron diffraction pattern measured by using nanoelectron beam diffraction at point 2 in Fig. 13(A) is shown in Fig. 13(D), and the electron diffraction pattern measured by using nanoelectron beam diffraction at point 3 in Fig. 13(A) is shown in Fig. 13(D). As an example of the nanocrystalline oxide semiconductor film, a sample formed on a quartz glass substrate with a film thickness of 50 nm is used in Fig. 13. The film formation conditions of the nanocrystalline oxide semiconductor film shown in Fig. 13 are as follows: an oxide target with In:Ga:Zn = 1:1:1 (atomic ratio) is used, and in an oxygen atmosphere (flow rate 45 sccm), pressure 0.4 Pa, DC power supply 0 .5 kW, and the substrate temperature is room temperature. Then, the formed nanocrystalline oxide semiconductor film is thinned into flakes with a width of 100 nm or less (for example, 40 nm ± 10 nm), and a cross-sectional TEM image and an electron diffraction pattern by nanoelectron beam diffraction are obtained.

[0244] Fig. 13(A) is a cross-sectional TEM image of the nanocrystalline oxide semiconductor film taken by using a transmission electron microscope (Hitachi High-Technologies Corporation's "H-9000NAR") with an acceleration voltage of 300 kV and a magnification of 2 million times. Figs. 13(B) to 13(D) are electron diffraction patterns obtained by nanoelectron beam diffraction using a transmission electron microscope (Hitachi High-Technologies Corporation's "HF-2000") with an acceleration voltage of 200 kV and a beam diameter of about 1 nmφ. Note that the measurement range in nanoelectron beam diffraction when the beam diameter is about 1 nmφ is 5 nmφ or more and 10

[0245]

[0246] nmφ or less.

[0246]

[0246]

[0246]

[0246] As shown in FIG. 13(B), in the electron diffraction pattern obtained using nano-crystalline oxide semiconductor film and electron beam micro-diffraction, a plurality of spots (bright spots) arranged in a circular shape are observed. In other words, it can be said that in the nano-crystalline oxide semiconductor film, a plurality of spots distributed in a circular (concentric circular) shape are observed. Or, it can be said that a plurality of spots distributed in a circular shape form a plurality of concentric circles. In the diffraction pattern, a plurality of spots (bright spots) arranged in a circular shape are observed. In other words, it can be said that in the nano-crystalline oxide semiconductor film, a plurality of spots distributed in a circular (concentric circular) shape are observed. Or, it can be said that a plurality of spots distributed in a circular shape form a plurality of concentric circles.

[0247] Also, in FIGS. 13(D) near the interface with the quartz glass substrate and in FIG. 13(C) at the central part in the film thickness direction of the nano-crystalline oxide semiconductor film, a plurality of spots distributed in a circular shape are observed in the same manner as in FIG. 13(B). In FIG. 13(C), the distance from the main spot to the circular spots was from 3.88 / nm to 4.93 / nm. Converting to the interplanar spacing, it was from 0.203 nm to 0.257 nm. In FIGS. 13(D) near the interface with the quartz glass substrate and in FIG. 13(C) at the central part in the film thickness direction of the nano-crystalline oxide semiconductor film, a plurality of spots distributed in a circular shape are observed in the same manner as in FIG. 13(B). In FIG. 13(C), the distance from the main spot to the circular spots was from 3.88 / nm to 4.93 / nm. Converting to the interplanar spacing, it was from 0.203 nm to 0.257 nm. In FIG. 13(C), the distance from the main spot to the circular spots was from 3.88 / nm to 4.93 / nm. Converting to the interplanar spacing, it was from 0.203 nm to 0.257 nm. 203 nm to 0.257 nm.

[0248] From the electron beam micro-diffraction pattern of FIG. 13, it can be seen that the nano-crystalline oxide semiconductor film is a film in which the plane orientation is irregular and a plurality of crystal parts with different sizes are mixed.

[0249] Next, a plan-view TEM image of the nano-crystalline oxide semiconductor film is shown in FIG. 14(A). Also, FIG. 14(B) shows an electron diffraction pattern measured using the selected area electron diffraction of the region circled in FIG. 14(A). In FIG. 14(B), an electron diffraction pattern measured using the selected area electron diffraction of the region circled in FIG. 14(A) is shown.

[0250] In FIG. 14, as an example of the nano-crystalline oxide semiconductor film, a sample in which an In-Ga-Zn-based oxide film is formed on a quartz glass substrate with a film thickness of 30 nm is used. The film formation conditions of the nano-crystalline oxide semiconductor film shown in FIG. 14 are such that the oxide target has an In:Ga:Zn = 1:1:1 (atomic ratio). In FIG. 14, as an example of the nano-crystalline oxide semiconductor film, a sample in which an In-Ga-Zn-based oxide film is formed on a quartz glass substrate with a film thickness of 30 nm is used. The film formation conditions of the nano-crystalline oxide semiconductor film shown in FIG. 14 are such that the oxide target has an In:Ga:Zn = 1:1:1 (atomic ratio). ​​​​​Using this, in an oxygen atmosphere (flow rate: 45 sccm), pressure: 0.4 Pa, direct current (DC) power supply: 0. 5 kW, and the substrate temperature was set to room temperature. Then, the sample was sliced into thin pieces, and a planar TEM image of the nanocrystalline oxide semiconductor film and an electron diffraction pattern obtained by electron beam diffraction were obtained.

[0251] Figure 14(A) is a planar TEM photograph of the nanocrystalline oxide semiconductor film taken using a transmission electron microscope (Hitachi High-Technologies Corporation's "H-9000NAR" ) with an acceleration voltage of 300 kV and a magnification of 500,000 times. Also, Figure 14(B) is an electron diffraction pattern obtained by electron beam diffraction with a restricted field of view of 300 nmφ. Considering the spread of the electron beam, the measurement range is 300 nmφ or more.

[0252] As shown in Figure 14(B), in the electron diffraction pattern obtained using restricted field of view electron beam diffraction, which has a wider measurement range than micro electron beam diffraction, no multiple spots observed by micro electron beam diffraction are seen, and a halo pattern is observed.

[0253] Next, Figure 15 conceptually shows the distribution of diffraction intensities in the electron diffraction patterns of Figures 13 and 14. Figure 15(A) is a conceptual diagram of the distribution of diffraction intensities in the micro electron beam diffraction pattern shown in Figures 13(B) to 13(D). Also, Figure 15(B) is a conceptual diagram of the distribution of diffraction intensities in the restricted field of view electron beam diffraction pattern shown in Figure 14(B). Also, Figure 15( C) is a conceptual diagram of the distribution of diffraction intensities in the electron diffraction pattern of a single crystal structure or polycrystalline structure. In Figure 15, the vertical axis represents the electron diffraction intensity (in arbitrary units) indicating the distribution of spots, etc., and the horizontal axis indicates the distance from the main spot.

[0254] ​​​​​​​

[0255] In the single crystal structure or polycrystalline structure shown in Fig. 15(C), spots are observed at a specific distance from the main spot according to the interplanar spacing (d value) of the plane in which the crystal part is oriented. On the other hand, as shown in Fig. 13, the plurality of spots observed in the electron nanodiffraction pattern of the nanocrystalline oxide semiconductor film have a relatively large width. Therefore, Fig. 15(A) shows a discrete intensity distribution. Also, in the electron nanodiffraction pattern, it can be seen that there are regions with high luminance that do not become distinct spots between the concentric regions.

[0256] On the other hand, as shown in Fig. 13, the plurality of spots observed in the electron nanodiffraction pattern of the nanocrystalline oxide semiconductor film have a relatively large width. Therefore, Fig. 15(A) shows a discrete intensity distribution. Also, in the electron nanodiffraction pattern, it can be seen that there are regions with high luminance that do not become distinct spots between the concentric regions. On the other hand, as shown in Fig. 13, the plurality of spots observed in the electron nanodiffraction pattern of the nanocrystalline oxide semiconductor film have a relatively large width. Therefore, Fig. 15(A) shows a discrete intensity distribution. Also, in the electron nanodiffraction pattern, it can be seen that there are regions with high luminance that do not become distinct spots between the concentric regions. On the other hand, as shown in Fig. 13, the plurality of spots observed in the electron nanodiffraction pattern of the nanocrystalline oxide semiconductor film have a relatively large width. Therefore, Fig. 15(A) shows a discrete intensity distribution. Also, in the electron nanodiffraction pattern, it can be seen that there are regions with high luminance that do not become distinct spots between the concentric regions. On the other hand, as shown in Fig. 13, the plurality of spots observed in the electron nanodiffraction pattern of the nanocrystalline oxide semiconductor film have a relatively large width. Therefore, Fig. 15(A) shows a discrete intensity distribution. Also, in the electron nanodiffraction pattern, it can be seen that there are regions with high luminance that do not become distinct spots between the concentric regions.

[0257] Also, as shown in Fig. 15(B), the electron diffraction intensity distribution in the selected area electron diffraction pattern of the nanocrystalline oxide semiconductor film shows a continuous intensity distribution. Since Fig. 15(B) can be approximated to the result of observing the electron diffraction intensity distribution shown in Fig. 15(A) over a wide range, it can be considered that the plurality of spots shown in Fig. 15(A) overlap and are connected to obtain a continuous intensity distribution. Also, as shown in Fig. 15(B), the electron diffraction intensity distribution in the selected area electron diffraction pattern of the nanocrystalline oxide semiconductor film shows a continuous intensity distribution. Since Fig. 15(B) can be approximated to the result of observing the electron diffraction intensity distribution shown in Fig. 15(A) over a wide range, it can be considered that the plurality of spots shown in Fig. 15(A) overlap and are connected to obtain a continuous intensity distribution. Also, as shown in Fig. 15(B), the electron diffraction intensity distribution in the selected area electron diffraction pattern of the nanocrystalline oxide semiconductor film shows a continuous intensity distribution. Since Fig. 15(B) can be approximated to the result of observing the electron diffraction intensity distribution shown in Fig. 15(A) over a wide range, it can be considered that the plurality of spots shown in Fig. 15(A) overlap and are connected to obtain a continuous intensity distribution. Also, as shown in Fig. 15(B), the electron diffraction intensity distribution in the selected area electron diffraction pattern of the nanocrystalline oxide semiconductor film shows a continuous intensity distribution. Since Fig. 15(B) can be approximated to the result of observing the electron diffraction intensity distribution shown in Fig. 15(A) over a wide range, it can be considered that the plurality of spots shown in Fig. 15(A) overlap and are connected to obtain a continuous intensity distribution. Also, as shown in Fig. 15(B), the electron diffraction intensity distribution in the selected area electron diffraction pattern of the nanocrystalline oxide semiconductor film shows a continuous intensity distribution. Since Fig. 15(B) can be approximated to the result of observing the electron diffraction intensity distribution shown in Fig. 15(A) over a wide range, it can be considered that the plurality of spots shown in Fig. 15(A) overlap and are connected to obtain a continuous intensity distribution.

[0258] As shown in Figs. 15(A) to 15(C), the nanocrystalline oxide semiconductor film is a film in which the crystal orientation is irregular and a plurality of crystal parts of different sizes are mixed, and the crystal parts are extremely fine to the extent that spots are not observed in the selected area electron diffraction pattern. As shown in Figs. 15(A) to 15(C), the nanocrystalline oxide semiconductor film is a film in which the crystal orientation is irregular and a plurality of crystal parts of different sizes are mixed, and the crystal parts are extremely fine to the extent that spots are not observed in the selected area electron diffraction pattern. As shown in Figs. 15(A) to 15(C), the nanocrystalline oxide semiconductor film is a film in which the crystal orientation is irregular and a plurality of crystal parts of different sizes are mixed, and the crystal parts are extremely fine to the extent that spots are not observed in the selected area electron diffraction pattern. As shown in Figs. 15(A) to 15(C), the nanocrystalline oxide semiconductor film is a film in which the crystal orientation is irregular and a plurality of crystal parts of different sizes are mixed, and the crystal parts are extremely fine to the extent that spots are not observed in the selected area electron diffraction pattern.

[0259] In Fig. 13 where a plurality of spots are observed, the nanocrystalline oxide semiconductor film is thinned to 50 nm or less. Also, since the beam diameter of the electron beam is converged to 1 nmφ, the measurement range is 5 nm or more and 10 nm or less. Therefore, the crystal parts contained in the nanocrystalline oxide semiconductor film In Fig. 13 where a plurality of spots are observed, the nanocrystalline oxide semiconductor film is thinned to 50 nm or less. Also, since the beam diameter of the electron beam is converged to 1 nmφ, the measurement range is 5 nm or more and 10 nm or less. Therefore, the crystal parts contained in the nanocrystalline oxide semiconductor film In Fig. 13 where a plurality of spots are observed, the nanocrystalline oxide semiconductor film is thinned to 50 nm or less. Also, since the beam diameter of the electron beam is converged to 1 nmφ, the measurement range is 5 nm or more and 10 nm or less. Therefore, the crystal parts contained in the nanocrystalline oxide semiconductor film is at least 50 nm or less, for example, 10 nm or less, or 5 nm or less. is presumed.

[0260] Here, FIG. 16 shows an electron diffraction pattern of a fused silica substrate. The measurement conditions in FIG. 16 were the same as those in FIGS. 13(B) to 13(D).

[0261] As shown in FIG. 16, in a fused silica substrate having an amorphous structure, a halo pattern in which the luminance continuously changes from the main spot without having specific spots is observed. Thus, even when electron diffraction is performed on a very small region in a film having an amorphous structure, a plurality of spots distributed in a circular shape as observed in the nanocrystalline oxide semiconductor film are not observed. Therefore, it is confirmed that the plurality of spots distributed in a circular shape

[0262] observed in FIGS. 13(B) to 13(D) are specific to the nanocrystalline oxide semiconductor film. Further, FIG. 17 shows an electron diffraction pattern measured after irradiating an electron

[0263] beam converged to a beam diameter of about 1 nmφ at point 2 shown in FIG. 13(A) for 1 minute. The electron diffraction pattern shown in FIG. 17, similar to the electron diffraction pattern shown in FIG. 13(C), shows a plurality of spots distributed in a circular shape, and no particular difference is confirmed between the two measurement results. This means that the crystal part confirmed in the electron diffraction pattern of FIG. 13(C) has existed

[0264] Next, FIG. 18 shows a partially enlarged view of the cross-sectional TEM image shown in FIG. 13(A). FIG. 18(A) is a cross-sectional TEM image obtained by observing the vicinity of point 1 (the surface of the nanocrystalline oxide semiconductor film) in FIG. 13(A) at a magnification of 8 million times. Also, FIG. 18(B) is a cross-sectional TEM image obtained by observing the vicinity of point 2 in FIG. 13(A) ( the central part in the film thickness direction of the nanocrystalline oxide semiconductor film) at a magnification of 8 million times. is.

[0265] From the cross-sectional TEM images shown in FIG. 18, the crystal structure cannot be clearly confirmed in the nanocrystalline oxide semiconductor film. confirmed.

[0266] Also, a sample in which the nanocrystalline oxide semiconductor film of this embodiment was formed on a quartz glass substrate, which was used for the observations in FIGS. 13 and 14, was analyzed using X-ray diffraction (XRD: X-Ray Diffracti on). FIG. 19 shows the results of measuring the XRD spectrum using the out-of-plane method. on). are shown.

[0267] In FIG. 19, the vertical axis represents the X-ray diffraction intensity (in arbitrary units), and the horizontal axis represents the diffraction angle 2θ (deg. ). The XRD spectrum was measured using an X-ray diffractometer D -8 ADVANCE manufactured by Bruker AXS.

[0268] As shown in FIG. 19, peaks due to quartz are observed in the vicinity of 2θ = 20 to 23°, and peaks due to the crystalline part contained in the nanocrystalline oxide semiconductor film cannot be confirmed. of.

[0269] From the results of FIGS. 18 and 19 as well, it is suggested that the crystalline part contained in the nanocrystalline oxide semiconductor film is an extremely fine crystalline part.

[0270] As described above, in the nanocrystalline oxide semiconductor film of this embodiment, X-ray diffraction with a wide measurement range In the analysis by XRD (X-ray diffraction), no peak indicating orientation was detected, and in the electron diffraction pattern obtained by the limited field of view electron diffraction with a wide measurement range, a halo pattern was observed. Therefore, it can be said that the nanocrystalline oxide semiconductor film of the present embodiment is equivalent to a film having a macroscopically disordered atomic arrangement. However, by performing ultramicro electron diffraction with an electron beam diameter small enough (for example, 10 nmφ or less) on the nanocrystalline oxide semiconductor film, spots (bright spots) can be observed in the obtained ultramicro electron diffraction pattern. Therefore, the nanocrystalline oxide semiconductor film of the present embodiment can be presumed to be a film formed by aggregation of extremely fine crystal parts with irregular plane orientations (for example, crystal parts with a particle size of 10 nm or less, or 5 nm or less, or 3 nm or less). Also, the nanocrystalline region containing extremely fine crystal parts is included in the entire region in the film thickness direction of the nanocrystalline oxide semiconductor film.

[0271] Here, the localized levels of the nanocrystalline oxide semiconductor film will be described. Here, the results of evaluating the nanocrystalline oxide semiconductor film by CPM (Constant photocurrent method) measurement will be described.

[0272] First, the structure of the measurement sample will be described.

[0273] The measurement sample has an oxide semiconductor film provided on a glass substrate, a pair of electrodes in contact with the oxide semiconductor film, and an insulating film covering the oxide semiconductor film and the pair of electrodes.

[0274] Next, the method for forming the oxide semiconductor film included in the measurement sample will be described.

[0275] A target that is an In-Ga-Zn oxide (In:Ga:Zn = 1:1:1 [atomic ratio]) was used. Argon gas at 30 sccm and oxygen gas at 15 sccm were used as the film-forming gases. Using a pressure of 0.4 Pa, a substrate temperature of room temperature, and applying a DC power of 0.5 kW, a first oxide semiconductor film was formed by a sputtering method. Note that the first oxide semiconductor film is a nanocrystalline oxide semiconductor film. Furthermore, after heating the first oxide semiconductor film in a nitrogen atmosphere at 450 °C for 1 hour and then heating it in an oxygen atmosphere at 450 °C for 1 hour, a process of desorbing hydrogen contained in the first oxide semiconductor film and a process of supplying oxygen to the first oxide semiconductor film were performed to form a second oxide semiconductor film. Note that the second oxide semiconductor film is a nanocrystalline oxide semiconductor film. Next, CPM measurements were performed on a measurement sample having the first oxide semiconductor film and a measurement sample having the second oxide semiconductor film. Specifically, with a voltage applied between a pair of electrodes provided in contact with the oxide semiconductor film, the light amount irradiated onto the measurement sample surface between the terminals was adjusted so that the photocurrent value became constant, and the absorption coefficient was derived from the irradiated light amount in the desired wavelength range. The absorption coefficient excluding the absorption coefficient due to the band tail, that is, the absorption coefficient due to defects, obtained by performing CPM measurement on each measurement sample is shown in FIG. 11. In FIG. 11, the horizontal axis represents the absorption coefficient, and the vertical axis represents the optical energy. Note that on the vertical axis of FIG. 11, the lower end of the conduction band of the oxide semiconductor film is set to 0 eV, and the upper end of the valence band is set to 3.15 eV. Also, in FIG. 11, each curve is a curve showing the relationship between the absorption coefficient and the optical energy, and corresponds to the defect level.

[0276]

[0277]

[0278] ​​​​​​​​​​​​​

[0279] FIG. 11(A) shows the measurement results of a measurement sample having a first oxide semiconductor film, and the absorption coefficient due to defect levels is 5.28×10 -1 cm -1 . FIG. 11(B) shows the measurement results of a measurement sample having a second oxide semiconductor film, and the absorption coefficient due to defect levels is 1.75×1 0 -2 cm -1 .

[0280] Therefore, by heat treatment, the defects contained in the oxide semiconductor film can be reduced.

[0281] Note that for the first oxide semiconductor film and the second oxide semiconductor film, measurements of film density were performed using X-ray reflectometry (XRR (X-ray Reflectometry)). The film density of the first oxide semiconductor film is 5.9 g / cm 3 , and the film density of the second oxide semiconductor film is 6.1 g / cm 3 .

[0282] Therefore, by heat treatment, the film density of the oxide semiconductor film can be increased.

[0283] That is, in the oxide semiconductor film, it can be seen that the higher the film density, the fewer the defects contained in the film.

[0284] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. .

[0285] (Embodiment 4) In this embodiment, an electron diffraction pattern and localized levels of a CAAC-OS film that can be used in one aspect of the present invention will be described.

[0286] ​​The CAAC-OS film used in this embodiment is a target of In-Ga-Zn oxide (In:Ga:Zn = 1:1:1 [atomic ratio]), and an In-Ga-Zn-based oxide film formed by a sputtering method using a film-forming gas containing oxygen. For details such as the manufacturing method of the CAAC-OS film, reference can be made to Embodiments 1 and 2.

[0287] FIG. 20 shows a cross-sectional TEM (Transmission Electron Microscope) image of the CAAC-OS film. FIG. 21 shows electron diffraction patterns measured using electron diffraction at Points 1 to 4 in FIG. 20.

[0288] The cross-sectional TEM image shown in FIG. 20 is an image taken using a transmission electron microscope (Hitachi High-Technologies Corporation's "H-9 000NAR") at an acceleration voltage of 300 kV and a magnification of 2 million times. The electron diffraction patterns shown in FIG. 21 are electron diffraction patterns obtained using a transmission electron microscope (Hitachi High-Technologies Corporation's "HF-2000") at an acceleration voltage of 200 kV and a beam diameter of about 1 nmφ or about 50 nmφ. Electron diffraction with a beam diameter of 10 nmφ or less is sometimes particularly referred to as ultramicro electron diffraction. Also, when the beam diameter is about 1 nmφ, the measurement range in electron diffraction is 5 nmφ or more and 10 nmφ or less.

[0289] The electron diffraction patterns at Point 1 (film surface side), Point 2 (film center), and Point 3 (film base side) shown in FIG. 20 correspond to FIGS. 21(A), (B), and (C), respectively, and are electron diffraction patterns with an electron beam diameter of about 1 nmφ. Also, the points shown in FIG. 20 The electron diffraction pattern in the entire film T4 is shown in Fig. 21(D), and it is an electron diffraction pattern with an electron beam diameter of about 5 0 nm φ.

[0290] For the electron diffraction patterns at Point 1 (film surface side) and Point 2 (center of the film), it can be confirmed that the pattern is formed by spots (bright spots), but at Point 3 (film substrate side), the pattern is slightly disrupted. This suggests that the crystalline state is different in the film thickness direction of the CAAC-OS film. Note that at Point 4 (entire film), since the formation of the pattern by spots (bright spots) can be confirmed, it can be said that the entire film is a CAAC-OS film or a film containing the CAAC-OS film.

[0291] Fig. 22 is a magnified photograph of the vicinity of Point 1 (film surface side) in Fig. 20. A clear lattice image showing the orientation of the CAAC-OS film up to the interface with the silicon oxynitride film which is the interlayer insulating film can be confirmed.

[0292] Figs. 23(A) and (B) are cross-sectional TEM photographs and X-ray diffraction spectra of a CAAC-OS film different from the CAAC-OS film used for the cross-sectional TEM observation in Fig. 20. The CAAC-OS film has various forms, and a peak A showing a crystalline component appears near 2θ = 31° as shown in Fig. 23(B). Note that this peak may not appear clearly in some cases.

[0293] In the region indicated by concentric circles in the CAAC-OS film of Fig. 23(A), electron diffraction was performed with the electron beam diameters of 1n m φ, 20 nm φ, 50 nm φ, and 70 nm φ, and the results are shown in Fig. 24( A), (B), (C), and (D). When the electron beam diameter is 1 nm φ, Fig. 21 ​​​​​It is possible to confirm the formation of a pattern by distinct spots (bright spots) as in (A) and (B). When increasing the beam diameter of the electron beam, the spots (bright spots) become slightly less distinct, but the diffraction pattern can be confirmed, and it can be said that the film as a whole is a CAAC-OS film or a film containing a CAAC-OS film.

[0294] Figures 25(A) and (B) are a cross-sectional TEM photograph and an X-ray diffraction spectrum after annealing the CAAC-OS film used for the cross-sectional TEM observation of Figure 23(A) at 4 50 °C.

[0295] In the region indicated by concentric circles in the CAAC-OS film of Figure 25(A), electron beam diffraction was performed with the beam diameters of the electron beam being 1n mφ, 20 nmφ, 50 nmφ, and 70 nmφ, and the results are shown in Figures 26( A), (B), (C), and (D). Similar to the results shown in Figure 24, when the beam diameter of the electron beam is 1 nmφ, it is possible to confirm the formation of a pattern by distinct spots (bright spots).

[0296] Figures 27(A) and (B) are a cross-sectional TEM photograph and an X-ray diffraction spectrum of a CAAC-OS film different from the CAAC-OS film used for the cross-sectional TEM photograph of Figure 20 and the cross-sectional TEM observation of Figure 23(A). The CAAC-OS film has various forms, and as shown in Figure 2 7(B), a peak A indicating a crystalline component appears near 2θ = 31°, and a peak B derived from a spinel crystal structure may also appear.

[0297] In the region indicated by concentric circles in the CAAC-OS film of Fig. 27(A), the beam diameter of the electron beam was set to 1n mφ, 20nmφ, 50nmφ, 90nmφ, and the results of electron diffraction are shown in Fig. 28( A), (B), (C), (D). When the beam diameter of the electron beam is 1nmφ, a clear pattern formation by spots (bright spots) can be confirmed. Also, as the beam diameter of the electron beam increases, the spots (bright spots) become slightly less clear, but the diffraction pattern can still be confirmed. Also, at a beam diameter of 90nmφ, clearer spots (bright spots) can be confirmed. Therefore, it can be said that the entire film is a CAAC-OS film or a film containing a CAAC- OS film.

[0298] Here, the localized levels of the CAAC-OS film will be described. Here, the CAAC-OS film was evaluated by CPM (Constant photocurrent method) measurement and the results will be described.

[0299] First, the structure of the sample measured by CPM will be described.

[0300] The measurement sample has an oxide semiconductor film provided on a glass substrate, a pair of electrodes in contact with the oxide semiconductor film, and an insulating film covering the oxide semiconductor film and the pair of electrodes.

[0301] Next, the formation method of the oxide semiconductor film included in the measurement sample will be described.

[0302] Using a target of In-Ga-Zn oxide (In:Ga:Zn = 1:1:1 [atomic ratio]), 30 sccm of argon gas and 15 sccm of oxygen gas were used as the film-forming gas, and The conditions of setting the pressure to 0.4 Pa, the substrate temperature to 400 °C, and applying a DC power of 0.5 kW were used to form an oxide semiconductor film by a sputtering method. Next, after heating in a nitrogen atmosphere at 450 °C for 1 hour, it was heated in an oxygen atmosphere at 450 °C for 1 hour to perform a process of desorbing hydrogen contained in the oxide semiconductor film and a process of supplying oxygen to the oxide semiconductor film. Note that the oxide semiconductor film is a CAAC-OS film.

[0303] Next, CPM measurement was performed on the measurement sample having the oxide semiconductor film. Specifically, with a voltage applied between a pair of electrodes provided in contact with the oxide semiconductor film, the amount of light irradiated on the sample surface between the terminals was adjusted so that the photocurrent value became constant, and the absorption coefficient was derived from the irradiated light amount in the desired wavelength range.

[0304] The absorption coefficient excluding the absorption coefficient due to the band tail from the absorption coefficient obtained by CPM measurement of each measurement sample, that is, the absorption coefficient due to defects, is shown in FIG. 12. In FIG. 12, the horizontal axis represents the absorption coefficient, and the vertical axis represents the optical energy. Note that on the vertical axis of FIG. 12, the lower end of the conduction band of the oxide semiconductor film is set to 0 eV, and the upper end of the valence band is set to 3.15 eV. Also, in FIG. 12, the curve shows the relationship between the absorption coefficient and the optical energy and corresponds to the defect level.

[0305] In the curve shown in FIG. 12, the absorption coefficient due to the defect level was 5.86×10 -4 cm -1 . That is, the CAAC-OS film has an absorption coefficient due to the defect level of less than 1×10 / cm, preferably less than 1×10 -3 / cm, and is a film with a low defect level density. -4

[0306] Regarding the oxide semiconductor film, measurement of the film density using the X-ray reflectivity method (XRR (X-ray Reflectom etry)) was performed. The film density of the oxide semiconductor film was 6.3 g / c m 3 . That is, the CAAC-OS film is a film with a high film density.

[0307] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. .

[0308] (Embodiment 5) A semiconductor device (display device) having a display function can be manufactured using the transistor and capacitor element shown as an example in the above embodiment. Further, a part or all of the drive circuit including the transistor can be integrally formed on the same substrate as the pixel portion to form a system-on-panel. In this embodiment, an example of a display device using the transistor shown as an example in the above embodiment will be described with reference to FIGS. 29 to 31. Note that FIG. 30 is a cross-sectional view showing the cross-sectional configuration of the portion indicated by the one-dot chain line of M-N in FIG. 29(B). Note that in FIG. 30, only a part of the structure of the pixel portion is shown. In FIG. 29(A), a sealing material 905 is provided so as to surround the pixel portion 902 provided on the first substrate 901, and is sealed by the second substrate 906. In FIG. 29(A), a second drive circuit 903 formed of a single crystal semiconductor or a polycrystalline semiconductor and a first drive circuit 904 are mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 905 on the first substrate 901. Further, various signals and potentials applied to the second drive circuit 903, the first drive circuit 904, or the pixel portion 902

[0309] In FIG. 29(A), a sealing material 905 is provided so as to surround the pixel portion 902 provided on the first substrate 901, and is sealed by the second substrate 906. In FIG. 29(A), a second drive circuit 903 formed of a single crystal semiconductor or a polycrystalline semiconductor and a first drive circuit 904 are mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 905 on the first substrate 901. Further, various signals and potentials applied to the second drive circuit 903, the first drive circuit 904, or the pixel portion 902 FPC (Flexible printed circuit) 918a and FPC 918 is supplied from b.

[0310] Note that the first driving circuit 904 has a function as a scanning line driving circuit. Also, the second driving circuit 903 has a function as a signal line driving circuit.

[0311] In FIGS. 29(B) and 29(C), a sealing material 905 is provided so as to surround the pixel portion 90 2 provided on the first substrate 901 and the first driving circuit 904. Also, a second substrate 906 is provided on the pixel portion 902 and the first driving circuit 904. Thus, the pixel portion 902 and the first driving circuit 904 are sealed together with the display element by the first substrate 901, the sealing material 905, and the second substrate 906. In FIGS. 29(B) and 29(C), a second driving circuit 903 formed of a separately prepared single crystal semiconductor or polycrystalline semiconductor is mounted in a region different from the region surrounded by the sealing material 905 on the first substrate 901. In FIGS. 29(B) and 29(C), various signals and potentials applied to the second driving circuit 903, the first driving circuit 904, or the pixel portion 902 are supplied from the FPC 918.

[0312] Also, in FIGS. 29(B) and 29(C), an example is shown in which the second driving circuit 903 is separately formed and mounted on the first substrate 901, but the present invention is not limited to this configuration. The first driving circuit may be separately formed and mounted, or only a part of the second driving circuit or a part of the first driving circuit may be separately formed and mounted.

[0313] Incidentally, the method of connecting the separately formed drive circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a method of implementing TCP (Tape Carrier Package), etc. can be used. FIG. 29(A) is an example of implementing the second drive circuit 903 and the first drive circuit 904 by the COG method, FIG. 29(B) is an example of implementing the second drive circuit 903 by the COG method, and FIG. 29( C) is an example of implementing the second drive circuit 903 as TCP.

[0314] Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel.

[0315] Note that the display device in this specification refers to an image display device or a display device. Also it can function as a light source (including a lighting device) instead of the display device. Also, a module to which a connector, for example, an FPC or a TCP is attached, a module in which a printed wiring board is provided at the tip of the TCP, or a module in which an IC (integrated circuit ) is directly mounted on the display element by the COG method are all included in the display device.

[0316] Further, the pixel portion and the first drive circuit provided on the first substrate have a plurality of transistors, and the transistors shown in the above embodiment can be applied.

[0317] As the display element provided in the display device, a liquid crystal element, a light emitting element, etc. can be used. As an example of the liquid crystal element, the transmission or non-transmission of light is controlled by the optical modulation action of the liquid crystal There is an element. The element can be structured by a pair of electrodes and a liquid crystal layer. Note that the optical modulation effect of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a lateral electric field, a longitudinal electric field, or an oblique direction electric field). Specifically, as an example of a liquid crystal element, nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular liquid crystal, high molecular liquid crystal, polymer dispersed liquid crystal (P DLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type high molecular liquid crystal, banana type liquid crystal, etc. can be mentioned. Also, as driving methods of the liquid crystal, TN (Twisted Nem atic) mode, STN (Super Twisted Nematic) mode, I PS (In-Plane-Switching) mode, FFS (Fringe Fie ld Switching) mode, MVA (Multi-domain Vertic al Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-ce ll) mode, OCB (Optically Compensated Birefri ngence) mode, ECB (Electrically Controlled B irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq uid Crystal) mode, PDLC (Polymer Dispersed L iquid Crystal) mode, PNLC (Polymer Network L iquid Crystal) mode, etc. can be mentioned. uid Crystal) mode, PDLC (Polymer Dispersed L iquid Crystal) mode, PNLC (Polymer Network L iquid Crystal mode, guest host mode, Blue Phase However, it is not limited to these, and the liquid crystal element and its driving method and The luminance of the light-emitting element is controlled by a current or a voltage. The category includes elements that are used in displays, specifically inorganic EL (Electro Luminescence) displays. luminescence elements, organic electroluminescence elements, etc. Also, electronic inks and other electrically-activated A display medium in which the contrast changes depending on the light can also be used. An example of a liquid crystal display device using a liquid crystal element will be described below.

[0318] FIG. 30 is a cross-sectional view of a vertical electric field type liquid crystal display device. The connecting terminal electrode 915 and the terminal electrode 916 is electrically connected to a terminal of the FPC 918 via an anisotropic conductive material 919 .

[0319] The connection terminal electrode 915 is formed from the same conductive film as the first electrode 930, and the terminal electrode 916 is The source and drain electrodes of the transistors 910 and 911 are formed of the same conductive film. is.

[0320] A pixel portion 902 and a first driver circuit 904 provided on a first substrate 901 are connected to a transistor. A transistor 910 included in a pixel portion 902 and a first driving circuit The transistor 910 and the transistor 911 included in the circuit 904 are illustrated. The insulating film 129, the insulating film 131, and the insulating film 132 shown in Embodiment 1 are formed on the transistor 911. An insulating film 924 corresponding to the insulating film 132 is provided. An insulating film 934 is provided for protection. Also, the insulating film 923 is a nitride insulating film.

[0321] In this embodiment, as the transistor 910, the transistor provided in the pixel 101 shown in the above Embodiment 1 can be applied. Also, as the transistor 911, the transistor provided in the first drive circuit 104 shown in the above Embodiment 1 can be applied. Note that the transistor 911 is illustrated as having a configuration in which a conductive film 917 is provided, but a configuration without the conductive film 917 may also be used.

[0322] Also, a capacitor element 936 is formed using the oxide semiconductor film 927, the insulating film 924, the insulating film 934, and the first electrode 930. Note that the oxide semiconductor film 927 is electrically connected to the capacitor line 929. The capacitor line 929 is formed from the same conductive film as the gate electrodes of the transistors 910 and 911. Here, although the capacitor element 936 shown in Embodiment 1 is illustrated, capacitor elements shown in other embodiments can be used as appropriate.

[0323] The transistor 910 provided in the pixel portion 902 is electrically connected to the display element and constitutes the display panel. The display element is not particularly limited as long as it can perform display, and various display elements can be used.

[0324] The liquid crystal element 913, which is a display element, includes a first electrode 930, a second electrode 931, and a liquid crystal layer 908. Note that insulating films 932 and 933, which function as alignment films, are provided so as to sandwich the liquid crystal layer 908. Also, the second electrode 931 is on the second substrate 906 side. ​​​​​​​​​​It is provided, and the first electrode 930 and the second electrode 931 overlap via a liquid crystal layer 908. It is configured like this.

[0325] In the first electrode 930 and the second electrode 931 ( also referred to as a pixel electrode, a common electrode, a counter electrode, etc.) provided for applying a voltage to the display element, the light extraction direction, the location where the electrode is provided, and the pattern structure of the electrode can be used to select translucency and reflectivity. It is possible.

[0326] The first electrode 930 and the second electrode 931 can appropriately use the same materials as the pixel electrode 121 shown in Embodiment 1. It can be used as appropriate.

[0327] Also, the spacer 935 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first electrode 930 and the second electrode 931. Note that spherical spacers may be used. It is provided for this purpose.

[0328] When using a liquid crystal element as the display element, thermotropic liquid crystals, low-molecular liquid crystals, high-molecular liquid crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions. It is possible to use these. of these liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.

[0329] Also, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent is used for the liquid crystal layer to improve the temperature range. Note that the alignment film is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent is used for the liquid crystal layer to improve the temperature range. is not used. Since it is composed of an organic resin and the organic resin contains hydrogen, water, etc., there is a risk of degrading the electrical characteristics of the transistors in the semiconductor device according to one aspect of the present invention. Therefore, by using a blue phase as the liquid crystal layer, a semiconductor device according to one aspect of the present invention can be manufactured without using an organic resin, and a highly reliable semiconductor device can be obtained. The first substrate 901 and the second substrate 906 are fixed by a sealing material 925. As the sealing material 925, an organic resin such as a thermosetting resin or a photocuring resin can be used. Also, the sealing material 925 is in contact with the insulating film 924. Note that the sealing material 925 corresponds to the sealing material 905 shown in FIG. 29. The sealing material 925 is provided on the insulating film 924. Also, the insulating film 934 is provided inside the sealing material 925. The uppermost layer of the insulating film 924 is a nitride insulating film, which can suppress the intrusion of impurities such as hydrogen and water from the outside. On the other hand, the insulating film 934 has high moisture permeability. Therefore, by providing the insulating film 934 inside the sealing material 925 and providing the sealing material 925 on the insulating film 924, the intrusion of impurities such as hydrogen and water from the outside can be suppressed, and fluctuations in the electrical characteristics of the transistors 910 and 911 can be suppressed. In the liquid crystal display device, optical members (optical substrates) such as a black matrix (light-shielding film), a polarizing member, a retardation member, and an antireflection member are appropriately provided. For example, circular polarization by a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, or the like can be used as the light source.

[0330] The first substrate 901 and the second substrate 906 are fixed by a sealing material 925. The sealing material 925 can use an organic resin such as a thermosetting resin or a photocuring resin. Also, the sealing material 925 is in contact with the insulating film 924. Note that the sealing material 925 corresponds to the sealing material 905 shown in FIG. 29. The sealing material 925 can use an organic resin such as a thermosetting resin or a photocuring resin. Also, the sealing material 925 is in contact with the insulating film 924. Note that the sealing material 925 corresponds to the sealing material 905 shown in FIG. 29. The sealing material 925 is in contact with the insulating film 924. Note that the sealing material 925 corresponds to the sealing material 905 shown in FIG. 29. The sealing material 925 corresponds to the sealing material 905 shown in FIG. 29.

[0331] The sealing material 925 is provided on the insulating film 924. Also, the insulating film 934 is provided inside the sealing material 925. The uppermost layer of the insulating film 924 is a nitride insulating film, which can suppress the intrusion of impurities such as hydrogen and water from the outside. On the other hand, the insulating film 934 has high moisture permeability. Therefore, by providing the insulating film 934 inside the sealing material 925 and providing the sealing material 925 on the insulating film 924, the intrusion of impurities such as hydrogen and water from the outside can be suppressed, and fluctuations in the electrical characteristics of the transistors 910 and 911 can be suppressed. The uppermost layer of the insulating film 924 is a nitride insulating film, which can suppress the intrusion of impurities such as hydrogen and water from the outside. On the other hand, the insulating film 934 has high moisture permeability. Therefore, by providing the insulating film 934 inside the sealing material 925 and providing the sealing material 925 on the insulating film 924, the intrusion of impurities such as hydrogen and water from the outside can be suppressed, and fluctuations in the electrical characteristics of the transistors 910 and 911 can be suppressed. The uppermost layer of the insulating film 924 is a nitride insulating film, which can suppress the intrusion of impurities such as hydrogen and water from the outside. On the other hand, the insulating film 934 has high moisture permeability. Therefore, by providing the insulating film 934 inside the sealing material 925 and providing the sealing material 925 on the insulating film 924, the intrusion of impurities such as hydrogen and water from the outside can be suppressed, and fluctuations in the electrical characteristics of the transistors 910 and 911 can be suppressed. By providing the insulating film 934 inside the sealing material 925 and providing the sealing material 925 on the insulating film 924, the intrusion of impurities such as hydrogen and water from the outside can be suppressed, and fluctuations in the electrical characteristics of the transistors 910 and 911 can be suppressed. By providing the insulating film 934 inside the sealing material 925 and providing the sealing material 925 on the insulating film 924, the intrusion of impurities such as hydrogen and water from the outside can be suppressed, and fluctuations in the electrical characteristics of the transistors 910 and 911 can be suppressed.

[0332] Also, in the liquid crystal display device, optical members (optical substrates) such as a black matrix (light-shielding film), a polarizing member, a retardation member, and an antireflection member are appropriately provided. For example, circular polarization by a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, or the like can be used as the light source. In the liquid crystal display device, optical members (optical substrates) such as a black matrix (light-shielding film), a polarizing member, a retardation member, and an antireflection member are appropriately provided. For example, circular polarization by a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, or the like can be used as the light source. For example, circular polarization by a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, or the like can be used as the light source. Also, a backlight, a side light, or the like can be used as the light source.

[0333] In addition, since transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably configured using a non-linear element.

[0334] FIG. 31 shows an example of forming a common connection portion (pad portion) on the substrate 901 for electrically connecting to the second electrode 931 provided on the substrate 906 in the liquid crystal display device shown in FIG. 30.

[0335] The common connection portion is disposed at a position overlapping with a sealing material for bonding the substrate 901 and the substrate 906, and is electrically connected to the second electrode 931 through conductive particles contained in the sealing material. Alternatively, a common connection portion may be provided at a location that does not overlap with the sealing material (excluding the pixel portion), and a paste containing conductive particles may be separately provided from the sealing material so as to overlap the common connection portion to electrically connect to the second electrode 931.

[0336] The right side of FIG. 31(A) is a cross-sectional view of the transistor 910 provided in the pixel portion, and the left side of FIG. 31(A) is a cross-sectional view of the common connection portion that can be formed using the same process as the transistor. The common connection portion shown in FIG. 31(A) corresponds to the cross-section of I-J in the top view of the common connection portion shown in FIG. 31(B).

[0337] The common potential line 975 is provided on the gate insulating film 922 and is formed using the same material and the same process as the source electrode 971 or the drain electrode 973 of the transistor 910.

[0338] In addition, the common potential line 975 is covered with the insulating film 924 and the insulating film 934, and the insulating film 924 and the insulating film 934 have a plurality of openings at positions overlapping with the common potential line 975. This opening ​​​​​​​​​​The opening is formed using the same process as the contact hole that connects one of the source electrode 971 or the drain electrode 973 of the transistor 910 and the first electrode 930.

[0339] Also, the common potential line 975 and the common electrode 977 are electrically connected at the opening provided in the insulating film 924 and the insulating film 934. The common electrode 977 is provided on the insulating film 934 and is formed using the same material and the same process as the connection terminal electrode 915 and the first electrode 930 of the pixel portion. Thus, the common connection portion can be formed in common with the manufacturing process of the switching element of the pixel portion 902.

[0340] The common electrode 977 is an electrode that contacts the conductive particles included in the sealing material, and is electrically connected to the second electrode 931 of the substrate 906.

[0341] Also, as shown in FIG. 31(C), the common potential line 985 may be formed using the same material and the same process as the gate electrode of the transistor 910.

[0342] In the common connection portion shown in FIG. 31(C), the common potential line 985 is provided under the gate insulating film 922, the insulating film 924, and the insulating film 934, and the gate insulating film 922, the insulating film 924, and the insulating film 934 have a plurality of openings at positions overlapping the common potential line 985. The openings are formed by etching the insulating film 924 and the insulating film 934 using the same process as the contact hole that connects one of the source electrode 971 or the drain electrode 973 of the transistor 910 and the first electrode 9

[0343] 30, and then selectively etching the gate insulating film 922. 30, and then further selectively etching the gate insulating film 922. 30 and the insulating film 93 4, and then further selectively etching the gate insulating film 922. ​​​​​​

[0344] Further, the common potential line 985 and the common electrode 987 are electrically connected at an opening provided in the gate insulating film 922, the insulating film 924, and the insulating film 934. The common electrode 987 is provided on the insulating film 934 and is made of the same material as the connection terminal electrode 915 and the first electrode 930 of the pixel portion and is manufactured using the same process.

[0345] As described above, by applying the transistor and the capacitor element shown in the above embodiment, it is possible to provide a semiconductor device having a capacitor element with an increased charge capacitance while increasing the aperture ratio. As a result, a semiconductor device with excellent display quality can be obtained.

[0346] In addition, since the oxide semiconductor film, which is a semiconductor film included in the transistor, has a reduced oxygen deficiency and a reduced amount of impurities such as hydrogen, the semiconductor device according to one aspect of the present invention has good electrical characteristics.

[0347] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0348] (Embodiment 6) In this embodiment, the configuration of an information processing apparatus capable of processing and displaying image information to which a semiconductor device according to one aspect of the present invention can be applied will be described with reference to FIGS. 32 and 33.

[0349] Specifically, a first mode in which a G signal for selecting a pixel is output at a frequency of 30 Hz (30 times per second) or more, preferably at a frequency of 60 Hz (60 times per second) or more and less than 960 Hz (960 times per second), and a second mode in which a G signal is output at a frequency of 11.6 μHz (once per day) or more and 0.1 Hz (0.1 time per second) or less ​​​​​​A frequency less than, preferably 0.28 mHz (once per hour) or more and less than 1 Hz (once per second). An information processing apparatus having a second mode of outputting at a frequency less than will be described.

[0350] When a still image is displayed using the information processing apparatus according to an aspect of the present invention, the refresh rate can be set to less than 1 Hz, preferably 0.2 Hz or less, providing a display that is gentle on the user's eyes, reduces eye fatigue, and does not burden the user's eyes. Also, the display image can be refreshed at an optimal frequency according to the nature of the image displayed on the display unit. Specifically, compared to the case of smoothly displaying a video, a still image with less flicker can be displayed by refreshing at a lower frequency. In addition, it also has the effect of reducing power consumption. z, preferably 0.2 Hz or less, enabling a display that is gentle on the user's eyes, reduces eye fatigue, and does not burden the user's eyes. Also, the display image can be refreshed at an optimal frequency according to the nature of the image displayed on the display unit. Specifically, compared to the case of smoothly displaying a video, a still image with less flicker can be displayed by refreshing at a lower frequency. In addition, it also has the effect of reducing power consumption. A display that is gentle on the user's eyes, reduces eye fatigue, and does not burden the user's eyes can be achieved. Also, the display image can be refreshed at an optimal frequency according to the nature of the image displayed on the display unit. Specifically, compared to the case of smoothly displaying a video, a still image with less flicker can be displayed by refreshing at a lower frequency. In addition, it also has the effect of reducing power consumption. Moreover, the display image can be refreshed at an optimal frequency according to the nature of the image displayed on the display unit. Specifically, compared to the case of smoothly displaying a video, a still image with less flicker can be displayed by refreshing at a lower frequency. In addition, it also has the effect of reducing power consumption. When a still image is displayed using the information processing apparatus according to an aspect of the present invention, the refresh rate can be set to less than 1 Hz, preferably 0.2 Hz or less, providing a display that is gentle on the user's eyes, reduces eye fatigue, and does not burden the user's eyes. Also, the display image can be refreshed at an optimal frequency according to the nature of the image displayed on the display unit. Specifically, compared to the case of smoothly displaying a video, a still image with less flicker can be displayed by refreshing at a lower frequency. In addition, it also has the effect of reducing power consumption. When a still image is displayed using the information processing apparatus according to an aspect of the present invention, the refresh rate can be set to less than 1 Hz, preferably 0.2 Hz or less, providing a display that is gentle on the user's eyes, reduces eye fatigue, and does not burden the user's eyes. Also, the display image can be refreshed at an optimal frequency according to the nature of the image displayed on the display unit. Specifically, compared to the case of smoothly displaying a video, a still image with less flicker can be displayed by refreshing at a lower frequency. In addition, it also has the effect of reducing power consumption. Moreover, it also has the effect of reducing power consumption.

[0351] FIG. 32 is a block diagram for explaining the configuration of an information processing apparatus having a display function according to an aspect of the present invention. is.

[0352] FIG. 33 is a block diagram for explaining the configuration of a display unit included in a display apparatus according to an aspect of the present invention. .

[0353] The information processing apparatus 600 having the display function described in the present embodiment includes a display apparatus 640, an arithmetic apparatus 620, and an input means 500 (see FIG. 32). The display apparatus 640 includes a display unit 630 and a control unit 610 (see FIG. 32). A primary image signal 625_V and a primary control signal 625_C can be supplied to the display apparatus 640. The display apparatus 640 can display image information on the display unit 630.

[0354] The display apparatus 640 includes a display unit 630 and a control unit 610 (see FIG. 32). A primary image signal 625_V and a primary control signal 625_C can be supplied to the display apparatus 640. The display apparatus 640 can display image information on the display unit 630. The display apparatus 640 includes a display unit 630 and a control unit 610 (see FIG. 32). A primary image signal 625_V and a primary control signal 625_C can be supplied to the display apparatus 640. The display apparatus 640 can display image information on the display unit 630. The display apparatus 640 can display image information on the display unit 630.

[0355] The primary image signal 625_V includes, in addition to the gradation information of the image (which can also be said to be luminance information), for example, chromaticity information, etc. and the like.

[0356] The primary control signal 625_C includes signals for controlling, for example, the timing of the scanning operation of the display device 640, etc. and the like.

[0357] Note that the power supply potential, etc. is supplied to the control unit 610 and the display unit 630 of the display device 640.

[0358] The control unit 610 has a function of controlling the display unit 630. For example, it generates a secondary image signal 615_V and / or a secondary control signal 615_C, etc.

[0359] For example, the control unit 610 may be configured to include a polarity determination circuit. The polarity determination circuit can invert the polarity of the signal for each frame.

[0360] The polarity determination circuit notifies the timing of inverting the polarity of the secondary image signal 615_V, and according to this timing, the control unit 610 may be configured to have a function of inverting the polarity of the secondary image signal 615_V. Note that the polarity of the secondary image signal 615_V may be inverted within the control unit 610, or may be inverted within the display unit 630 according to an instruction from the control unit 610. or may be inverted within the display unit 630 according to an instruction from the control unit 610.

[0361] Also, the polarity determination circuit may have a counter and a signal generation circuit, and may have a function of determining the timing of inverting the polarity of the secondary image signal 615_V using a synchronization signal.

[0362] Note that the counter has a function of counting the number of frame periods using the pulses of the horizontal synchronization signal. Also, the signal generation circuit determines the timing of inverting the polarity of the secondary image signal 615_V, ​​​​It has a function of notifying the control unit 610. Thereby, using the information on the number of frame periods obtained by the counter, the polarity of the secondary image signal 615_V can be inverted for each of a plurality of consecutive frame periods.

[0363] The secondary image signal 615_V can include image information.

[0364] For example, the control unit 610 may generate the secondary image signal 615_V from the primary image signal 625_V and output the secondary image signal 615_V.

[0365] Also, the control unit 610 may use the difference between the primary image signal 625_V and the reference potential Vsc as the amplitude, and generate a signal whose polarity is inverted for each frame as the secondary image signal 615_V.

[0366] The secondary control signal 615_C can include a signal for controlling the first drive circuit (also referred to as the G drive circuit 632) of the display unit 630 or a signal for controlling the second drive circuit (also referred to as the S drive circuit 633).

[0367] For example, the control unit 610 may generate the secondary control signal 615_C from the primary control signal 625_C including synchronization signals such as a vertical synchronization signal and a horizontal synchronization signal.

[0368] The secondary control signal 615_C includes, for example, a start pulse signal SP, a latch signal LP, a pulse width control signal PWC, a clock signal CK, and the like.

[0369] Specifically, the secondary control signal 615_C includes a start pulse signal SP for the S drive circuit for controlling the operation of the S drive circuit 633, a clock signal CK for the S drive circuit, a latch signal LP, and the like. ​​​​​​can be included. Also, a star for the G drive circuit that controls the operation of the G drive circuit 632 can include a top pulse signal SP for the G drive circuit, a clock signal CK for the G drive circuit, a pulse width control signal PWC, etc.

[0370] The display unit 630 includes a pixel unit 631, a first drive circuit (also referred to as the G drive circuit 632), and a second drive circuit (also referred to as the S drive circuit 633).

[0371] The pixel unit 631 does not include light with a wavelength shorter than 420 nm in the display light, and has a plurality of pixels 631p provided with a fineness of 150 ppi or more and wirings connecting the plurality of pixels. Each pixel 631p is connected to at least one of the scanning lines G and at least one of the signal lines S. Note that the type and number of the wirings depend on the configuration, number and arrangement of the pixels 631p.

[0372] For example, when the pixels 631p are arranged in the pixel unit 631 in a matrix of x columns × y rows, the signal lines S1 to Sx and the scanning lines G1 to Gy are arranged in the pixel unit 631 (see Fig. 33(A-1)). The plurality of scanning lines (G1 to Gy) can supply a G signal for each row . The plurality of signal lines (S1 to Sx) can supply an S signal to the plurality of pixels .

[0373] The G drive circuit 632 can control the supply of the G signal 632_G to select the scanning line G (see Fig. 3 2).

[0374] For example, the pixel unit 631 may be divided into a plurality of regions (specifically, the first region 631a, the second region 631b, and the third region 631c) and driven (see Fig. 33(A-2)).

[0375] ​​ Each region includes a plurality of pixels 631p, a plurality of scanning lines G for selecting the pixels 631p row by row, and a plurality of signal lines S for supplying an S signal 633_S to the selected pixels 631p. These can be provided.

[0376] In addition, a plurality of G driving circuits (specifically, a first G driving circuit 632a, a second G driving circuit 632b, and a third G driving circuit 632c) may be provided.

[0377] The G driving circuit controls the supply of a G signal 632_G to select scanning lines G provided in each region (specifically, the first G driving circuit 632a selects scanning lines G1 to Gj, the second G driving circuit 632b selects scanning lines Gj + 1 to G2j, and the third G driving circuit 632c selects scanning lines G2j + 1 to Gy). This can be done.

[0378] The G driving circuit outputs a first driving signal (also referred to as a G signal) 632_G for selecting a pixel circuit 634 to the pixel circuit 634. The G driving circuit 632 supplies a G signal 632_G for selecting each scanning line to each scanning line at a frequency of 30 Hz (30 times per second) or more, preferably 60 Hz (60 times per second) or more and less than 960 Hz (960 times per second) in a first mode, and at a frequency of 1.6 μHz (once a day) or more and less than 0.1 Hz (0.1 time per second), preferably 0.28 mHz (once an hour) or more and less than 1 Hz (1 time per second) in a second mode. The G driving circuit 632 has a second mode. 60 times) or more and less than 960 Hz (960 times per second) in a first mode, and at a frequency of 1 1.6 μHz (once a day) or more and less than 0.1 Hz (0.1 time per second), preferably is 0.28 mHz (once an hour) or more and less than 1 Hz (1 time per second) in a second mode. The G driving circuit 632 is provided with a second mode.

[0379] The G driving circuit 632 can operate by switching between the first mode and the second mode. For example, using a secondary control signal 615_C including a mode switching signal or a start pulse for the G driving circuit included in the secondary control signal 615_C, the first mode of the G driving circuit 632 C, the first mode of the G driving circuit 632 and the second mode can be switched. Specifically, the control unit 610 may control the output frequency of the start pulse for the G drive circuit.

[0380] The G signal 632_G is generated by the G drive circuit 632. The G signal 632_G is output to the pixel 631p for each row, and the pixel 631p is selected for each row.

[0381] The display unit 630 may include an S drive circuit 633. The S drive circuit generates a second drive signal (also referred to as the S signal 633_S) from the secondary image signal 615_V and controls the supply of the S signal 633 _S to the signal lines S (specifically, S1 to Sx).

[0382] The S signal 633_S includes image gradation information and the like. The S signal 633_S is supplied to the pixel 631p selected by the G signal 632_G.

[0383] The pixel unit 631 includes a plurality of pixels 631p.

[0384] The pixel 631p includes a display element 635 and a pixel circuit 634 including the display element 635 ( see FIG. 32).

[0385] The pixel circuit 634 holds the supplied S signal 633_S and displays a part of the image information on the display element 635. Note that a configuration corresponding to the type or driving method of the display element 635 can be selected and used for the pixel circuit 634. As an example of the pixel circuit 634, a configuration in which a liquid crystal element 635LC is applied to the display element 635 is shown in FIG.

[0386] 33(B-1). 33(B-1).

[0387] The pixel circuit 634 includes a gate electrode to which the G signal 632_G is input and a first A transistor 634t including the electrode of 1, and electricity to the second electrode of the transistor 634t A liquid crystal element 635 including a first electrode that is electrically connected and a second electrode to which a common potential is supplied LC.

[0388] The pixel circuit 634 has a transistor 634t that controls the supply of the S signal 633_S to the display element 635. Have 634t.

[0389] The gate of the transistor 634t is connected to any one of the scan lines G1 to Gy. One of the source and drain of the transistor 634t is connected to any one of the signal lines S1 to Sx, and the other of the source and drain of the transistor 634t is Connected to the first electrode of the display element 635.

[0390] The pixel 631p is used as a switching element that controls the input of the S signal 633_S to the pixel 631p by the transistor 634t. Also, a plurality of transistors may be used for the pixel 631p as one switching element. The plurality of transistors may be connected in parallel and used as one Switching element, or may be connected in series and used, or a connection in which series and parallel are combined may be used. Switching element, or may be connected in series and used, or a connection in which series and parallel are combined may be used.

[0391] The pixel 631p may have other circuit elements such as transistors, diodes, resistance elements, capacitance elements, and inductors, in addition to the capacitance element 634c for holding the voltage between the first electrode and the second electrode of the liquid crystal element 635LC as needed. A predetermined common potential Vcom is applied to the second electrode of the display element 635. Is given.

[0392] The capacitance of the capacitance element 634c may be adjusted as appropriate. For example, in the second mode described later , when the S signal 633_S is held for a relatively long period (specifically, 1 / 60 sec or more) , the capacitance element 634c is provided. Also, the capacitance of the pixel circuit 634 may be adjusted using a configuration other than the capacitance element 634c. Further, a substantially capacitance element may be formed by a configuration in which the first electrode and the second electrode of the liquid crystal element 635LC are provided so as to overlap each other.

[0393] As another example of the pixel circuit, a configuration in which the EL element 635EL is applied to the display element 635 is shown in FIG. 3 3(B-2).

[0394] The pixel circuit 634EL includes a gate electrode to which the G signal 632_G is input, a first electrode to which the S signal is input, a second electrode electrically connected to the first electrode of the capacitance element 634c, and has a first transistor 634t_1. Also, a gate electrode electrically connected to the second electrode of the first transistor 634t_ 1, a first electrode electrically connected to the second electrode of the capacitance element 634c, and a second electrode electrically connected to the first electrode of the EL element 635EL, has a second transistor 634t_2. Also, a power supply potential is supplied to the second electrode of the capacitance element 63 4c and the first electrode of the second transistor 634t_2, and a common potential is supplied to the second electrode of the EL element 635EL. Note that the potential difference between the power supply potential and the common potential is greater than the light emission start voltage of the EL element 635EL. In the pixel circuit 634, the transistor 634t controls whether to apply the potential of the signal line S to the first electrode of the display element 635. The potential difference between the power supply potential and the common potential is greater than the light emission start voltage of the EL element 635EL. The potential difference between the power supply potential and the common potential is greater than the light emission start voltage of the EL element 635EL.

[0395] In the pixel circuit 634, the transistor 634t controls whether to apply the potential of the signal line S to the first electrode of the display element 635.

[0396] ​Note that a transistor including an oxide semiconductor is suitable for a display device of one embodiment of the present invention. For details of a transistor using an oxide semiconductor, see Please refer to the descriptions of embodiments 1 and 2.

[0397] A transistor including an oxide semiconductor film has a low leakage current between the source and drain in an off state. The current (off-state current) is extremely low compared to conventional silicon transistors. A transistor with extremely low off-state current can be used in the pixel portion of the display unit. This makes it possible to reduce the frame frequency while suppressing the occurrence of flicker.

[0398] The display element 635 is not limited to a liquid crystal element 635LC, and may be, for example, a liquid crystal element that emits luminescence when a voltage is applied. OLED elements that generate electroluminescence and electrophoresis Various display elements can be applied, such as electronic ink that uses light.

[0399] For example, the transmittance of the polarized light of the liquid crystal element 635LC is controlled by the potential of the S signal 633_S. This makes it possible to display gradations.

[0400] For example, when a transmissive liquid crystal element is applied to the display element 635, the light supply unit 650 is The light supply unit 650 has a light source. The control unit 610 controls the light supply unit 6 50. Light is supplied to a pixel portion 631 in which a liquid crystal element is provided. It functions as a backlight.

[0401] The light source of the light supply unit 650 may be a cold cathode fluorescent lamp, a light emitting diode (LED), an OLE D elements, etc. can be used.

[0402] In particular, a configuration in which the intensity of the blue light emitted by the light source is made weaker than the intensity of the light of other colors is preferable. The light source The light having a blue color contained in the light emitted by the light source reaches the retina without being absorbed by the cornea or lens of the eye, so that long-term effects on the retina (such as age-related macular degeneration, etc.) and adverse effects on the circadian rhythm (Circadian rhythm) when exposed to blue light until midnight can be reduced. Specifically, light not containing light having a wavelength of 400 nm or less, preferably 420 nm or less, more preferably 440 nm or less (also referred to as UVA) is preferable as the light source that emits light. to the circadian rhythm when exposed to blue light until midnight can be reduced. Specifically, light not containing light having a wavelength of 400 nm or less, preferably 420 nm or less, more preferably 440 nm or less (also referred to as UVA) is preferable as the light source that emits light. hm) can be reduced. Specifically, a light source that emits light not containing light having a wavelength of 400 nm or less, preferably 420 nm or less, more preferably 440 nm or less (also referred to as UVA) is preferable. m or less, more preferably 440 nm or less (also referred to as UVA) is preferable as the light source that emits light. A light source that emits light is preferable.

[0403] In addition, in the pixel in the semiconductor device of one aspect of the present invention, it has the characteristic of absorbing light having the above wavelength and being difficult to transmit. Therefore, even when using a light source that emits light having the above wavelength, by using the semiconductor device of one aspect of the present invention, the light having the above wavelength can be reduced or blocked. In addition, in the pixel in the semiconductor device of one aspect of the present invention, it has the characteristic of absorbing light having the above wavelength and being difficult to transmit. Therefore, even when using a light source that emits light having the above wavelength, by using the semiconductor device of one aspect of the present invention, the light having the above wavelength can be reduced or blocked. In addition, in the pixel in the semiconductor device of one aspect of the present invention, it has the characteristic of absorbing light having the above wavelength and being difficult to transmit. Therefore, even when using a light source that emits light having the above wavelength, by using the semiconductor device of one aspect of the present invention, the light having the above wavelength can be reduced or blocked. The arithmetic unit 620 generates a primary control signal 625_C including the primary image signal 625_V and the mode switching signal.

[0404] The arithmetic unit 620 generates a primary control signal 625_C including the primary image signal 625_V and the mode switching signal. The arithmetic unit 620 generates a primary control signal 625_C including the primary image signal 625_V and the mode switching signal.

[0405] The mode switching signal may be generated according to an instruction from the user of the information processing device 600.

[0406] The user of the information processing device 600 can issue an instruction to switch the display using the input means 500. The image switching signal 500_C is supplied to the arithmetic unit 620, and the arithmetic unit 620 The user of the information processing device 600 can issue an instruction to switch the display using the input means 500. The image switching signal 500_C is supplied to the arithmetic unit 620, and the arithmetic unit 620 may be configured to output a primary control signal 625_C including the mode switching signal.

[0407] A primary control signal 625_C including a mode switching signal is supplied to a control unit 610 of a display device 640, and the control unit outputs a secondary control signal 615_C including the mode switching signal. For example, when the secondary control signal 615_C including the mode switching signal for switching from the second mode to the first mode is supplied to the G driving circuit 632, the G driving circuit 632 switches from the second mode to the first mode. Then, the G driving circuit 632 outputs a G signal for one frame or more and then switches to the second mode.

[0408] Specifically, when the input means 500 detects a page turning operation, the image switching signal 500_C may be configured to be output to the arithmetic unit 620. The arithmetic unit 620 generates a primary image signal 625_V including the page turning operation and outputs a primary control signal 625_C including the mode switching signal together with the primary image signal 625_V. The control unit 610 supplied with the primary image signal 625_V and the primary control signal 625_C supplies a secondary control signal 615_C including the mode switching signal and a secondary image signal 615_V including the page turning operation. The G driving circuit 632 supplied with the secondary control signal 615_C including the mode switching signal switches from the second mode to the first mode and outputs the G signal 632_G at a high frequency.

[0409] The S driving circuit 633 supplied with the secondary image signal 615_V including the page turning operation outputs an S signal 633_S generated from the secondary image signal 615_V to the pixel circuit 634.

[0410]

[0411]

[0412]

[0413] ​​​​​​​​​​​

[0414] As a result, pixel 631p can rewrite a large number of frame images including the page turning operation at a high frequency. As a result, the secondary image signal 615_V including the page turning operation can be smoothly displayed.

[0415] The arithmetic unit 620 may be configured to determine whether the primary image signal 625_V output to the display unit 630 is a moving image or a still image, and output a primary control signal 625_C including a mode switching signal according to the determination result.

[0416] Specifically, when the primary image signal 625_V is a moving image, the arithmetic unit 620 may output a switching signal for selecting the first mode, and when it is a still image, the arithmetic unit 620 may output a switching signal for selecting the second mode.

[0417] As a method for determining whether it is a moving image or a still image, if the difference between the signals of one frame included in the primary image signal 625_V and the frames before and after it is larger than a predetermined difference, it may be determined as a moving image, and if it is less than or equal to that, it may be determined as a still image.

[0418] When the control unit 610 switches the operation mode of the G drive circuit from one mode to another (for example, when switching from the second mode to the first mode), the G drive circuit may be configured to output the G signal 632_G one or more predetermined times and then switch to another mode.

[0419] Examples of the input means 500 include a touch panel, a touch pad, a mouse, a joystick, a trackball, a keyboard, a remote control, and a voice input device. A rack ball, a data glove, an imaging device, etc. can be used. The arithmetic unit 620 can associate the electrical signal input from the input means 500 with the coordinates of the display unit. By doing so, the user can input an instruction for processing the information displayed on the display unit.

[0420] Examples of the information input by the user from the input means 500 include, for example, an instruction to drag to change the display position of an image displayed on the display unit, an instruction to swipe to send the displayed image and display the next image, an instruction to scroll to send a strip-shaped image in order, an instruction to select a specific image, an instruction to pinch in or pinch out to change the size of the displayed image, and an instruction to input handwritten characters.

[0421] Note that illuminance is the amount of light incident on a surface to be illuminated per unit area per unit time, taking into account the spectral sensitivity of the eye.

[0422] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0423] (Embodiment 7) In this embodiment, an information processing method of an information processing apparatus using a semiconductor device according to an aspect of the present invention will be described with reference to FIG. 34.

[0424] Specifically, a method for generating an image that can be displayed on a display unit of an information processing apparatus using a semiconductor device according to an aspect of the present invention will be described. In particular, a method for switching an image that is easy on the user's eyes when rewriting an image displayed on the display unit to another image, and a method for switching an image that reduces the user's eye fatigue. ​​​​​​​​​A replacement method, a method for switching images that does not impose a burden on the user's eyes, will be described.

[0425] FIG. 34 is a block diagram for explaining the configuration of an information processing apparatus using a semiconductor device according to an aspect of the present invention. and a schematic diagram for explaining image data.

[0426] One aspect of the present invention gently rewrites a display image on the display unit of an information processing apparatus. That's it.

[0427] As a result, the burden on the user's eyes during display switching is reduced. As a result, a novel information processing method capable of gently displaying an image including information processed by the arithmetic unit can be provided. If an image is switched and displayed quickly, it may cause eye fatigue for the user. For example,

[0428] This includes cases such as a moving image in which significantly different scenes are switched, or cases where different still images are switched. When switching and displaying different images, it is preferable not to switch the display instantaneously, but to gently (quietly) and naturally switch and display the images. That's it.

[0429] For example, when switching the display from a first still image to a second still image, a moving image in which the first still image fades out and is displayed or / and It is preferable to insert a moving image in which the second still image fades in. Also, at the same time as the first still image fades out, a moving image in which the second still image fades in (also called a cross-fade)

[0430] For example, when switching the display from a first still image to a second still image, a moving image in which the first still image fades out and is displayed between the first still image and the second still image or / and It is preferable to insert a moving image in which the second still image fades in. Also, a moving image in which the first still image and the second still image are superimposed so that the first still image fades out and the second still image fades in (also called a cross-fade) and a moving image in which the first still image gradually changes to the second still image (also called morphing) It is also possible to insert a moving image in which the first still image fades out and at the same time the second still image fades in (also called a cross-fade). It is also possible to insert a moving image in which the two images are superimposed so that the first still image fades out and the second still image fades in (also called a cross-fade), or a moving image in which the state in which the first still image gradually changes to the second still image (also called morphing) is displayed. It may be inserted.

[0431] Note that the first still image data is displayed at a low refresh rate, and then an image for image switching is displayed at a high refresh rate, and then the second still image data may be displayed at a low refresh rate.

[0432] An example of a method for switching between different images A and B will be described below.

[0433] FIG. 34(A) is a block diagram showing the configuration of a display unit capable of performing an image switching operation. The display unit shown in FIG. 34(A) includes an arithmetic unit 701, a storage unit 702, a control unit 703, and a display unit 704.

[0434] In the first step, the arithmetic unit 701 stores the data of each of image A and image B from an external storage unit or the like in the storage unit 702.

[0435] In the second step, the arithmetic unit 701 sequentially generates new image data based on the image data of image A and image B according to a preset value of the number of divisions.

[0436] In the third step, the generated image data is output to the control unit 703. The control unit 703 causes the input image data to be displayed on the display unit 704.

[0437] FIG. 34(B) is a schematic diagram for explaining the generated image data when the image is gradually switched from image A to image B.

[0438] In FIG. 34(B), N (N is a natural number) pieces of image data are generated from image A to image B. When the image data per one is displayed for f (f is a natural number) frame periods, it is shown. Therefore, the period until switching from image A to image B is f×N frames. Here, parameters such as N and f described above are preferably freely settable by the user. The arithmetic unit 701 acquires these parameters in advance and generates image data according to the parameters. The image data generated at the i-th time (i is an integer from 1 to N) can be generated by weighting and adding the image data of image A and the image data of image B respectively. For example, at a certain pixel, if the luminance (gray level) when image A is displayed is a and the luminance (gray level) when image B is displayed is b, the luminance (gray level) c of the pixel when the image data generated at the i-th time is displayed is the value shown in Equation 1. Note that the gray level is the level of shading displayed by the display unit. An image having only two levels of white and black can be said to be an image having a gray level of two levels. For example, the display unit of a conventional personal computer has sub-pixels that display red, green, and blue. Signals for displaying 256 levels of shading are input to each sub-pixel.

[0439] Using the image data generated by such a method, when switching from image A to image B, a discontinuous image can be switched gently (quietly) and naturally. Here, parameters such as N and f described above are preferably freely settable by the user. The arithmetic unit 701 acquires these parameters in advance and generates image data according to the parameters. The image data generated at the i-th time (i is an integer from 1 to N) can be generated by weighting and adding the image data of image A and the image data of image B respectively. For example, at a certain pixel, if the luminance (gray level) when image A is displayed is a and the luminance (gray level) when image B is displayed is b, the luminance (gray level) c of the pixel when the image data generated at the i-th time is displayed is the value shown in Equation 1. Note that the gray level is the level of shading displayed by the display unit. An image having only two levels of white and black can be said to be an image having a gray level of two levels. For example, the display unit of a conventional personal computer has sub-pixels that display red, green, and blue. Signals for displaying 256 levels of shading are input to each sub-pixel.

[0440] The image data generated at the i-th time (i is an integer from 1 to N) can be generated by weighting and adding the image data of image A and the image data of image B respectively. For example, at a certain pixel, if the luminance (gray level) when image A is displayed is a and the luminance (gray level) when image B is displayed is b, the luminance (gray level) c of the pixel when the image data generated at the i-th time is displayed is the value shown in Equation 1. Note that the gray level is the level of shading displayed by the display unit. An image having only two levels of white and black can be said to be an image having a gray level of two levels. For example, the display unit of a conventional personal computer has sub-pixels that display red, green, and blue. Signals for displaying 256 levels of shading are input to each sub-pixel. The image data generated at the i-th time (i is an integer from 1 to N) can be generated by weighting and adding the image data of image A and the image data of image B respectively. For example, at a certain pixel, if the luminance (gray level) when image A is displayed is a and the luminance (gray level) when image B is displayed is b, the luminance (gray level) c of the pixel when the image data generated at the i-th time is displayed is the value shown in Equation 1. Note that the gray level is the level of shading displayed by the display unit. An image having only two levels of white and black can be said to be an image having a gray level of two levels. For example, the display unit of a conventional personal computer has sub-pixels that display red, green, and blue. Signals for displaying 256 levels of shading are input to each sub-pixel. For example, at a certain pixel, if the luminance (gray level) when image A is displayed is a and the luminance (gray level) when image B is displayed is b, the luminance (gray level) c of the pixel when the image data generated at the i-th time is displayed is the value shown in Equation 1. Note that the gray level is the level of shading displayed by the display unit. An image having only two levels of white and black can be said to be an image having a gray level of two levels. For example, the display unit of a conventional personal computer has sub-pixels that display red, green, and blue. Signals for displaying 256 levels of shading are input to each sub-pixel. For example, at a certain pixel, if the luminance (gray level) when image A is displayed is a and the luminance (gray level) when image B is displayed is b, the luminance (gray level) c of the pixel when the image data generated at the i-th time is displayed is the value shown in Equation 1. Note that the gray level is the level of shading displayed by the display unit. An image having only two levels of white and black can be said to be an image having a gray level of two levels. For example, the display unit of a conventional personal computer has sub-pixels that display red, green, and blue. Signals for displaying 256 levels of shading are input to each sub-pixel. For example, at a certain pixel, if the luminance (gray level) when image A is displayed is a and the luminance (gray level) when image B is displayed is b, the luminance (gray level) c of the pixel when the image data generated at the i-th time is displayed is the value shown in Equation 1. Note that the gray level is the level of shading displayed by the display unit. An image having only two levels of white and black can be said to be an image having a gray level of two levels. For example, the display unit of a conventional personal computer has sub-pixels that display red, green, and blue. Signals for displaying 256 levels of shading are input to each sub-pixel. For example, at a certain pixel, if the luminance (gray level) when image A is displayed is a and the luminance (gray level) when image B is displayed is b, the luminance (gray level) c of the pixel when the image data generated at the i-th time is displayed is the value shown in Equation 1. Note that the gray level is the level of shading displayed by the display unit. An image having only two levels of white and black can be said to be an image having a gray level of two levels. For example, the display unit of a conventional personal computer has sub-pixels that display red, green, and blue. Signals for displaying 256 levels of shading are input to each sub-pixel. For example, at a certain pixel, if the luminance (gray level) when image A is displayed is a and the luminance (gray level) when image B is displayed is b, the luminance (gray level) c of the pixel when the image data generated at the i-th time is displayed is the value shown in Equation 1. Note that the gray level is the level of shading displayed by the display unit. An image having only two levels of white and black can be said to be an image having a gray level of two levels. For example, the display unit of a conventional personal computer has sub-pixels that display red, green, and blue. Signals for displaying 256 levels of shading are input to each sub-pixel. For example, at a certain pixel, if the luminance (gray level) when image A is displayed is a and the luminance (gray level) when image B is displayed is b, the luminance (gray level) c of the pixel when the image data generated at the i-th time is displayed is the value shown in Equation 1. Note that the gray level is the level of shading displayed by the display unit. An image having only two levels of white and black can be said to be an image having a gray level of two levels. For example, the display unit of a conventional personal computer has sub-pixels that display red, green, and blue. Signals for displaying 256 levels of shading are input to each sub-pixel. For example, at a certain pixel, if the luminance (gray level) when image A is displayed is a and the luminance (gray level) when image B is displayed is b, the luminance (gray level) c of the pixel when the image data generated at the i-th time is displayed is the value shown in Equation 1. Note that the gray level is the level of shading displayed by the display unit. An image having only two levels of white and black can be said to be an image having a gray level of two levels. For example, the display unit of a conventional personal computer has sub-pixels that display red, green, and blue. Signals for displaying 256 levels of shading are input to each sub-pixel.

[0441]

Equation

[0442] Using the image data generated by such a method, when switching from image A to image B, a discontinuous image can be switched gently (quietly) and naturally. Using the image data generated by such a method, when switching from image A to image B, a discontinuous image can be switched gently (quietly) and naturally.

[0443] In addition, in formula 1, when a = 0 for all pixels, the image gradually switches from black to image B. This corresponds to a fade-in where the image is replaced by another image. Also, when b = 0 for all pixels, This corresponds to a fade-out, where the image gradually switches from black to black.

[0444] Above we described how to switch between two images by overlapping them temporarily. However, a method in which no overlapping occurs may also be used.

[0445] If you don't overlap two images, when switching from image A to image B, A black image may be inserted. In this case, when transitioning from image A to a black image or when transitioning from a black image to a When transitioning to image B, or both, the image switching method described above can be used. Also, the image to be inserted between image A and image B is not limited to a black image, but can be a single image such as a white image. A color image may be used, or a multi-color image different from image A and image B may be used.

[0446] By inserting another image, especially a single-color image such as a black image, between image A and image B, the image This allows the user to feel the timing of image switching more naturally, reducing stress for the user. You can switch images without feeling any discomfort.

[0447] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0448] (Embodiment 8) In this embodiment, a structure of a data processing device using a semiconductor device according to one embodiment of the present invention will be described. Description will be given with reference to Figures 35 and 36.

[0449] FIG. 35 is a diagram for explaining the effect of the information processing device.

[0450] Figure 36 is a block diagram for explaining the configuration of the information processing apparatus.

[0451] Eye fatigue is of two types: nervous system fatigue and muscular system fatigue. A schematic diagram for explaining eye fatigue is shown in Fig. 35(A).

[0452] Nervous system fatigue is caused by continuously looking at the light emitted by the display unit or the blinking screen for a long time, and its brightness stimulates the retina, nerves, or brain of the eye, causing fatigue. The phenomenon of the display unit of a fluorescent lamp or a conventional display device flickering in small increments is called flicker, and such flicker causes nervous system fatigue. The display unit of a fluorescent lamp or a conventional display device flickering in small increments is called flicker, and such flicker causes nervous system fatigue. The display unit of a fluorescent lamp or a conventional display device flickering in small increments is called flicker, and such flicker causes nervous system fatigue. to occur.

[0453] Muscular system fatigue is caused by overusing the ciliary muscle used for focusing adjustment, resulting in fatigue. to occur.

[0454] Fig. 35(A-1) shows a schematic diagram representing the display of a conventional display unit. The conventional display unit rewrites the image 60 times per second. Continuously looking at such a screen for a long time may stimulate the retina, nerves, or brain of the user's eye, causing eye fatigue. to occur. to occur.

[0455] Also, as shown in Fig. 35(A-2), when the size of one pixel is large (for example, when the resolution is less than 150 ppi), the outline of characters or the like displayed on the display unit becomes blurred. Continuously looking at the blurred characters or the like with the outline displayed on the display unit for a long time may cause the ciliary muscle to continuously move to focus and remain tense, placing a burden on the eyes. to occur. to occur. to occur.

[0456] In addition, methods for quantitatively measuring eye fatigue are being studied. For example, the evaluation of nervous system fatigue As an index, the Critical Flicker Frequency (CFF) In addition, the following are known as indicators of muscle fatigue: Known examples of such adjustment methods include the adjustment time and the near point distance.

[0457] Other methods for assessing eye fatigue include electroencephalography, thermography, and blinking. Measurement, tear volume evaluation, pupil contraction reaction rate evaluation, and questionnaire to investigate subjective symptoms Examples include

[0458] In order to solve the above problem, one aspect of the present invention is a method for controlling the illuminance of a work environment and a display device. The focus is on the gradation of the background of the image information. This includes one aspect of the present invention that was created with attention paid to the gradation information in the background of the image information.

[0459] The image information processing and display method according to one embodiment of the present invention includes: obtaining background gradation information of the image information to be processed; The display light does not include light with a wavelength shorter than 420 nm and has a resolution of 150 ppi or more. and displaying the image on a display unit having a plurality of pixels. This allows the display of information at a brightness appropriate to the illuminance of the environment. It is possible to provide a novel method for processing and displaying image information, which allows display that is easy on the eyes.

[0460] An information processing device to which the image information processing and display method according to one embodiment of the present invention can be applied An example of a block diagram is shown in FIG.

[0461] The information processing device 330 includes a calculation unit 311, a storage unit 312, and a transmission path 314. The circuit 314 connects the calculation unit 311, the storage unit 312, and the input / output interface 315 to each other. These components cannot be clearly separated, and one component can be connected to the other. For example, a touch panel may be a display unit. It is also an input means.

[0462] The input / output device 320 is connected to the transmission line 314 via the input / output interface 315. The input / output device 320 inputs information from outside the arithmetic device 310 or receives information from outside the arithmetic device 310. It is a device for outputting information to a

[0463] The input / output device 320 may be a communication device, a network connection device, a hard disk, One example is a writable external storage unit such as a removable memory. do.

[0464] The input means 321 is a human input such as a keyboard, a mouse, or a touch panel. Interface devices, digital cameras, digital video cameras, and other cameras, scanners Examples include read-only external storage devices such as CD-ROMs and DVD-ROMs. For example, the user of the information processing device 330 can input a page turning command via the input means 321. You can enter orders, etc.

[0465] As output devices, in addition to the display unit 322, speakers, printers, etc. can be connected. .

[0466] The information processing device 330 according to an embodiment of the present invention includes a display unit 322. In particular, the display unit 322 includes: The display light does not include light with a wavelength shorter than 420 nm, and preferably does not include light with a wavelength shorter than 440 nm. And it is preferable to provide a plurality of pixels having a fineness of 150 ppi or more, preferably 200 ppi or more, in the display area. This enables a user-friendly display. In this specification, the display light refers to the light emitted or reflected by the display unit of the information processing apparatus toward the user in order to display an image.

[0467] The display light of the display unit according to one aspect of the present invention reaches the retina without being absorbed by the cornea or lens of the eye, and thus does not include light that has an adverse effect on the retina over a long period of time or on the circadian rhythm. Specifically, the light for displaying an image does not include light having a wavelength of 400 nm or less, preferably 420 nm or less, more preferably 440 nm or less (also referred to as UVA).

[0468] The semiconductor device according to one aspect of the present invention can be used in the information processing apparatus 330 according to one aspect of the present invention. The pixels in the semiconductor device have the characteristic of absorbing light having the above wavelength and being difficult to transmit. Therefore, even when a light source that emits light having the above wavelength is used, by using the semiconductor device according to one aspect of the present invention, the light having the above wavelength can be reduced or blocked.

[0469] In addition, the fineness of the pixels included in the display unit according to one aspect of the present invention is 150 ppi or more, preferably 200 ppi or more, and the size of one pixel is small. This reduces the fatigue of the muscular system of the user's eyes.

[0470] A schematic diagram for explaining the effect of reducing eye fatigue of the information processing apparatus according to one aspect of the present invention is shown in FIG. 35(B).

[0471] The information processing apparatus according to one aspect of the present invention can change the frequency of outputting a signal for selecting a pixel. This is achieved. In particular, by using a transistor with an extremely small off-current in the pixel portion of the display unit, while suppressing the occurrence of flicker, the frame frequency can be lowered. For example, since the image can be rewritten once every 5 seconds, the same image can be viewed, and the flicker of the screen visible to the user is reduced. As a result, the stimulation received by the retina, nerves, or brain of the user is reduced, and the fatigue of the nervous system is alleviated (see Fig. 35(B-1)).

[0472] As the transistor with an extremely small off-current, for example, a transistor using an oxide semiconductor, particularly, a transistor using CAAC-OS is suitable.

[0473] The information processing apparatus according to one aspect of the present invention has a small size of one pixel. Specifically, high-definition display with a definition of 150 ppi, preferably 200 ppi or more, is possible. The outline of the image can be clearly, and densely and smoothly displayed. As a result, the ciliary muscle can easily focus, so that the fatigue of the muscular system of the user is reduced (see Fig. 35(B-2)). Note that the definition can be expressed using pixel density (ppi: pixel per inch). The pixel density is the number of pixels per inch. Also, a pixel is a unit that constitutes an image.

[0474] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0475] (Embodiment 9) A semiconductor device according to one aspect of the present invention can be applied to various electronic devices (including gaming machines). Examples of the electronic device include a television device, a monitor for a computer, etc., a de ​​​Digital cameras, digital video cameras, digital photo frames, mobile phones, game machines , portable game machines, personal digital assistants, audio playback devices, gaming machines (pachinko machines, slot machines etc.). An example of these electronic devices is shown in FIGS. 37 and 38.

[0476] FIG. 37(A) shows a table having a display unit. Table 9000 has a display unit 90 03 incorporated in the housing 90 01, and the display unit 9003 can display an image. . In addition, a configuration in which the housing 9001 is supported by four legs 9002 is shown.

[0477] The semiconductor device shown in any of the above embodiments can be used for the display unit 9003. Therefore, the display quality of the display unit 9003 can be improved.

[0478] The display unit 9003 has a touch input function. By touching the display button 9004 displayed on the display unit 9003 of the table 9000 with a finger or the like, screen operations and information input can be performed, and communication with other home appliances or control can be enabled, and it can also be used as a control device for controlling other home appliances by screen operations. For example, by using a semiconductor device having a touch sensor function or an image sensor function, the display unit 9003 can be provided with a touch input function.

[0479] In addition, the screen of the display unit 9003 can be set perpendicular to the floor by a hinge provided on the housing 9001, and it can also be used as a television device. In a narrow room, installing a large-screen television device will narrow the free space, but a table with a large screen can be used as a television device, which can save space. with a large screen can be used as a television device, which can save space. If a display unit is incorporated, the space of the room can be effectively utilized.

[0480] FIG. 37(B) shows a television apparatus. The television apparatus 9100 includes a housing 9 101 in which a display unit 9103 is incorporated, and the display unit 9103 can display an image. Here, a configuration is shown in which the housing 9101 is supported by a stand 9105.

[0481] The operation of the television apparatus 9100 can be performed by operation switches provided in the housing 9101 or by a separate remote controller 9110. By the operation keys 9109 provided in the remote controller 9110, operations such as channel and volume can be performed, and the image displayed on the display unit 910 3 can be operated. Further, the remote controller 9110 may be provided with a display unit 9107 for displaying information output from the remote controller.

[0482] The television apparatus 9100 shown in FIG. 37(B) includes a receiver, communication means, and the like. The television apparatus 9100 can receive general television broadcasts by a receiver, and further, by connecting to a wired or wireless communication network via communication means, one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers) information communication can also be performed.

[0483] The semiconductor device shown in any of the above embodiments can be used for the display units 9103 and 9107. Therefore, the display quality of the television apparatus can be improved.

[0484] FIG. 37(C) is a computer 9200, which includes a main body 9201, a housing 9202, a display unit 92 03, a keyboard 9204, an external connection port 9205, a pointing device 9206 and so on.

[0485] The semiconductor device shown in any of the above embodiments can be used for the display unit 9203 . Therefore, the display quality of the computer 9200 can be improved.

[0486] The display unit 9203 has a touch input function. By touching a display button or the like displayed on the display unit 9203 with a finger or the like, screen operations and information can be input. In addition, information can be input from the keyboard or voice.

[0487] FIGS. 38(A) and 38(B) are a foldable tablet terminal. FIG. 38(A ) is in an open state. The tablet terminal includes a housing 9630, a display unit 9631a, a display unit 9631b, a display mode switch 9034, a power switch 9035, a power saving mode switch 9036, a fastener 9033, an operation switch 9038.

[0488] The semiconductor device shown in any of the above embodiments can be used for the display unit 9631a and the display unit 9631b . Therefore, the display quality of the tablet terminal can be improved .

[0489] A part of the display unit 9631a can be a touch panel area 9632a, and data can be input by touching an operation key 9638 displayed thereon. In the display unit 963 1a, as an example, half of the area has a display-only function, and the other half of the area shows a configuration having a touch panel function, but is not limited to this configuration. Display unit 963 All areas of 1a may also have a touch panel function. For example, display unit 96 The entire surface of 31a can be used to display keyboard buttons to serve as a touch panel, and display unit 9631b can be used as a display screen.

[0490] Also, in display unit 9631b, similar to display unit 9631a, a part of display unit 9631b can be set as the touch panel area 9632b. Also, when a finger or a stylus touches the position where the keyboard display switch button 9639 of the touch panel is displayed, keyboard buttons can be displayed on display unit 9631b.

[0491] Also, simultaneous touch input can be performed on touch panel area 9632a and touch panel area 9632b.

[0492] Also, the display mode switch switch 9034 can select to switch the display orientation such as portrait or landscape, or switch between black and white display and color display. The power saving mode switch 9036 can optimize the display brightness according to the amount of external light detected by the optical sensor built into the tablet-type terminal during use. The tablet-type terminal may incorporate not only an optical sensor but also other detection devices such as sensors for detecting inclination such as gyroscopes and acceleration sensors.

[0493] Also, in Fig. 38(A), an example where the display areas of display unit 9631b and display unit 9631a are the same is shown but is not particularly limited, and the sizes of one and the other may be different, and the display Their quality may also be different. For example, one may be a display panel that can perform a higher-definition display than the other. This may be the case.

[0494] FIG. 38(B) is in a closed state, and the tablet terminal may have a solar cell 96 33 and a charge / discharge control circuit 9634. Note that in FIG. 38(B), the charge / discharge control circuit 9634 is shown as having a configuration including a battery 9635 and a DCDC converter 9636 as an example. This shows the configuration.

[0495] Since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Therefore, the display units 9631a and 9631b can be protected, and a tablet terminal with excellent durability and reliability from the perspective of long-term use can be provided.

[0496] In addition, the tablet terminals shown in FIGS. 38(A) and 38(B) can also have various functions such as a function to display various information (still images, moving images, text images, etc.), a function to display a calendar, date, or time on the display unit, a touch input function to touch input or edit the information displayed on the display unit, a function to control processing by various software (programs), and the like. This can be achieved.

[0497] Power can be supplied to the touch panel, display unit, or video signal processing unit, etc. by the solar cell 9633 mounted on the surface of the tablet terminal. Note that the solar cell 9633 can be provided on one side or both sides of the housing 9630, and the battery 9635 can be efficiently charged. As the battery 9635, a lithium-ion battery has advantages such as enabling miniaturization. This has advantages such as enabling miniaturization. ​

[0498] Next, the configuration and operation of the charge / discharge control circuit 9634 shown in FIG. 38(B) will be described with reference to FIG. 39. FIG. 39(A) shows a block diagram of a solar cell 9633, a battery 9635, DCDC converters 9636 and 9637, switches SW1 to SW 3, and a load (display unit 9631, etc.). The battery 9635, DCDC con verters 9636 and 9637, and switches SW1 to SW3 correspond to the parts of the charge / discharge control circuit 9634 shown in FIG. 38( B).

[0499] First, an example of the operation when power is generated by the solar cell 9633 will be described. The power generated by the solar cell is stepped up or down by the DCDC converter 9636 to a voltage for charging the battery 9635. When the power from the solar cell 9633 is used for the operation of the load (display unit 9631, etc.), switch SW1 is turned on, and the DCDC converter 9637 steps up or down the voltage to the voltage required for the load (display unit 9631, etc.). When power is not supplied to the load (display unit 9631, etc.), SW1 can be turned off and SW2 can be turned on to charge the battery 9635. When the power from the solar cell 9633 is used for the operation of the load (display unit 9631, etc.), switch SW1 is turned on, and the DCDC converter 9637 steps up or down the voltage to the voltage required for the load (display unit 9631, etc.). When power is not supplied to the load (display unit 9631, etc.), SW1 can be turned off and SW2 can be turned on to charge the battery 9635. When power is not supplied to the load (display unit 9631, etc.), SW1 can be turned off and SW2 can be turned on to charge the battery 9635. When power is not supplied to the load (display unit 9631, etc.), SW1 can be turned off and SW2 can be turned on to charge the battery 9635.

[0500] When power is always supplied to the load (display unit 9631, etc.) via the battery 9635, as shown in FIG. 39(B), the configuration can be such that switch SW1 is omitted. When power is always supplied to the load (display unit 9631, etc.) via the battery 9635, as shown in FIG. 39(B), the configuration can be such that switch SW1 is omitted.

[0501] When the appropriate voltage range supplied to the load is equal to the voltage of the battery 9635, as shown in FIG. 39(C), the configuration can be further such that the DCDC converter 9637 is omitted. When the appropriate voltage range supplied to the load is equal to the voltage of the battery 9635, as shown in FIG. 39(C), the configuration can be further such that the DCDC converter 9637 is omitted. This is also acceptable.

[0502] Although the solar cell 9633 is shown as an example of a power generation means, it is not particularly limited, and the battery 9635 may be charged by other power generation means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). For example, a contactless power transmission module that wirelessly (non-contact) transmits and receives power for charging, or a configuration that combines other charging means may be used.

[0503] Note that the configurations shown in this embodiment can be appropriately combined with the configurations shown in other embodiments.

Explanation of Reference Numerals

[0504] 100 Pixel portion 101 Pixel 102 Substrate 103 Transistor 104 Driving circuit 105 Capacitor element 106 Driving circuit 107 Scanning line 108 Liquid crystal element 109 Signal line 110 Underlying insulating film 111 Semiconductor film 113 Conductive film 115 Capacitance line 117 Opening 118 Nitride insulating film 119 Semiconductor film 121 Pixel electrode 127 Gate insulating film 129 Insulating film 130 Insulating film 131 Insulating film 132 Insulating film 135 Boundary 154 Counter electrode 188a Oxide semiconductor film 188b Oxide semiconductor film 199a Oxide semiconductor film​​​ 199b Oxide semiconductor film 199c Oxide semiconductor film 223 Transistor 227 Gate electrode 229 Wiring 231 Semiconductor film 233 Wiring 241 Conductive film 310 Arithmetic unit 311 Arithmetic section 312 Memory section 314 Transmission path 315 Input / output interface 320 Input / output device 321 Input means 322 Display section 330 Information processing device 500 Input means 500_C Signal 600 Information processing device 610 Control section 615_C Secondary control signal 615_V Secondary image signal 620 Arithmetic unit 625_C Primary control signal 625_V Primary image signal 630 Display section 631 Pixel section 631a Region 631b Region 631c Region 631p Pixel 632 G drive circuit 632_G G signal 632a G drive circuit 632b G drive circuit 632c G drive circuit 633 S drive circuit 633_S S signal 634 Pixel circuit 634c Capacitor element 634EL Pixel circuit 634t Transistor 634t_1 Transistor 634t_2 Transistor 635 represents an element 635EL EL element 635LC Liquid crystal element 640 represents a device 650 Light supply unit 701 Arithmetic unit 702 Memory unit 703 Control unit 704 Display unit 901 Substrate 902 Pixel section 903 Drive circuit 904 Drive circuit 905 Sealant 906 Substrate 908 Liquid crystal layer 910 Transistor 911 Transistor 913 Liquid crystal element 915 Connection terminal electrode 916 Terminal electrode 917 Conductive film 918 FPC 918b FPC 919 Anisotropic conductive agent 922 Gate insulating film 923 Insulating film 924 Insulating film 925 Sealant 926 Capacitor element 927 Oxide semiconductor film 929 Capacitor line 930 Electrode 931 Electrode 932 Insulating film 933 Insulating film 934 Insulating film 935 Spacer 936 Capacitor element 971 Source electrode 973 Drain electrode 975 Common potential line 977 Common electrode 985 Common potential line 987 Common electrode 9000 Table 9001 Housing 9002 Foot 9003 Display unit 9004 Display button 9005 Power cord 9033 Tool 9034 Switch 9035 Power switch 9036 Switch 9038 Operation switch 9100 Television device 9101 Housing 9103 Display unit 9105 Stand 9107 Display unit 9109 Operation key 9110 Remote controller 9200 Computer 9201 Main body 9202 Housing 9203 Display unit 9204 Keyboard 9205 External connection port 9206 Pointing device 9630 Housing 9631 Display unit 9631a Display unit 9631b Display unit 9632a Area 9632b Area 9633 Solar cell 9634 Charge and discharge control circuit 9635 Battery 9636 DCDC converter 9637 DCDC converter 9638 Operation key 9639 Button

Claims

1. A display device having a transistor and a capacitor in a pixel, comprising a first insulating film, a first oxide semiconductor film, a second oxide semiconductor film, a first conductive film, a second conductive film, a third conductive film, a second insulating film, a fourth conductive film, a third insulating film, and a fifth conductive film, wherein the first insulating film has a region in contact with the first oxide semiconductor film and a region in contact with the second oxide semiconductor film, the first oxide semiconductor film has a region in contact with the first conductive film, a region in contact with the second insulating film, and a region in contact with the second conductive film, the first oxide semiconductor film has a channel formation region of the transistor, the first conductive film has a region functioning as one of a source electrode or a drain electrode of the transistor, the second conductive film has a region functioning as the other of the source electrode or the drain electrode of the transistor, the second oxide semiconductor film has a region in contact with the third conductive film, the second oxide semiconductor film has a region functioning as an electrode of the capacitor, the second insulating film has a region in contact with the fourth conductive film and a region in contact with the third insulating film, the second insulating film has a region functioning as a gate insulating film of the transistor, the fourth conductive film has a region in contact with the third insulating film, the fourth conductive film has a region functioning as a gate electrode of the transistor, the third insulating film has a region in contact with the fifth conductive film, the fifth conductive film has a region functioning as a pixel electrode, the fifth conductive film is electrically connected to the second conductive film, and the second oxide semiconductor film has a region overlapping the fifth conductive film through the third insulating film without passing through the second insulating film. A display device.

2. A display device having a transistor and a capacitor in a pixel, comprising a first insulating film, a first oxide semiconductor film, a second oxide semiconductor film, a first conductive film, a second conductive film, a third conductive film, a second insulating film, a fourth conductive film, a third insulating film, and a fifth conductive film, wherein the first insulating film has a region in contact with the first oxide semiconductor film and a region in contact with the second oxide semiconductor film, the first oxide semiconductor film has a region in contact with the first conductive film, a region in contact with the second insulating film, and a region in contact with the second conductive film, The first oxide semiconductor film has a channel formation region of the transistor, The first conductive film has a region that functions as one of a source electrode or a drain electrode of the transistor, The second conductive film has a region that functions as the other of a source electrode or a drain electrode of the transistor, The second oxide semiconductor film has a region in contact with the third conductive film, The second oxide semiconductor film has a region that functions as an electrode of the capacitor, The second insulating film has a region in contact with the fourth conductive film and a region in contact with the third insulating film, The second insulating film has a region that functions as a gate insulating film of the transistor, The fourth conductive film has a region in contact with the third insulating film, The fourth conductive film has a region that functions as a gate electrode of the transistor, The third insulating film has a region in contact with the fifth conductive film, The fifth conductive film has a region that functions as a pixel electrode, The fifth conductive film is electrically connected to the second conductive film, The second oxide semiconductor film has a region that overlaps with the fifth conductive film via the third insulating film without passing through the second insulating film, A display device in which, in a plan view of the pixel, the fifth conductive film does not overlap with the first oxide semiconductor film.

3. In Claim 1 or Claim 2, A display device in which the first oxide semiconductor film and the second oxide semiconductor film contain In.

4. In Claim 1 or Claim 2, A display device in which the first oxide semiconductor film and the second oxide semiconductor film contain indium oxide.

Images