Integrated capacitor filter, and integrated capacitor filter with varistor function

Abstract

To provide a multiterminal multilayer ceramic device, a provision method thereof and an integrated capacitor filter that result in improved miniaturization as well as increased functionality and / or operational characteristics.SOLUTION: The invention provides an integrated multiterminal multilayer ceramic device 100 that has three or more capacitive elements. Two of such capacitive elements (capacitors 154, 156) may be in series, and a third capacitive element (capacitor 158) may be in parallel. The integrated device may be packaged as an overmolded three-leaded (148, 150, 152) component, or can be mounted as an SMD (surface mount device). The device may also be combined with a separate varistor in a stacked arrangement of leaded components.SELECTED DRAWING: Figure 1D

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is incorporated by reference in its entirety. This application claims the benefit of U.S. Provisional Patent Application No. 62 / 455,076, filed on the 6th. [Background technology]

[0002] For some time now, the design of various electronic components has been driven by a general trend towards miniaturization. The trend toward smaller electronic components with improved performance characteristics is motivated by industry trends and increased functionality. In light of this, there is a need for smaller electronic components with improved performance characteristics. For example, some applications can benefit from the equivalent of multiple components, but the amount of space such electronic components can occupy on a circuit board is severely limited.

[0003]

[0003] Multilayer ceramic devices such as multilayer ceramic capacitors or varistors are Often, multilayer ceramic devices are constructed using multiple dielectric electrode layers in a stacked arrangement. During manufacturing, the layers may be pressed and formed into a vertically stacked structure. Multilayer ceramic devices can include a single element or multiple elements. Examples of previously issued U.S. patents or U.S. published patent applications include U.S. Pat. Nos. 9,025,306, 7,307,829, and 5,870,273, and U.S. published patent applications Nos. 2012 / 0188681, 2009 / 0154055, 2009 / 0147440, and 2006 / 0262490, all of which are incorporated by reference into this disclosure for all purposes and as if fully set forth herein. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 9,025,306 [Patent Document 2] U.S. Patent No. 7,307,829 [Patent Document 3] U.S. Patent No. 5,870,273 [Patent Document 4] U.S. Patent Application Publication No. 2012 / 0188681 [Patent Document 5] U.S. Patent Application Publication No. 2009 / 0154055 [Patent Document 6] U.S. Patent Application Publication No. 2009 / 0147440 [Patent Document 7] U.S. Patent Application Publication No. 2006 / 0262490 [Summary of the Invention] [Problems to be Solved by the Invention]

[0005]

[0004] Accordingly, it would be advantageous if devices and corresponding methods could be provided that exhibit improved miniaturization as well as increased functionality and / or operating characteristics. [Means for Solving the Problems]

[0006]

[0005] According to one embodiment of the present invention, a multi-terminal multilayer ceramic device having a plurality of capacitive elements is disclosed. The multi-terminal multilayer ceramic device includes a body having a plurality of cooperating layers including electrode layers for forming an integrated capacitive structure, a first region of the electrode layer forming a split feed-through type structure of two respective capacitors, a second region of the electrode layer forming an overlap type structure of a multilayer ceramic capacitor, a first pair of terminal portions having opposite polarities outside the body, and a second pair of terminals having the same polarity outside the body. ​​comprising an end portion, wherein the end portions of the first pair are connected in series with the second region capacitor, and at least one of the end portions of the first pair and the end portions of the second pair are respectively connected in parallel with the two capacitors in the first region, so that a plurality of capacitive elements are integrated in a single package device.

[0007]

[0006] According to another embodiment of the present invention, an integrated capacitor filter having a varistor function is disclosed. The integrated capacitor filter is a discrete multi-terminal multilayer ceramic capacitor device having a plurality of capacitive elements, and includes a body having a plurality of cooperating layers including electrode layers that will form an integrated capacitance structure, first pairs of capacitor device end portions having opposite polarities outside the body, second pairs of capacitor device end portions having the same polarity outside the body, a first region of the electrode layer that forms two respective capacitors, and a second region of the electrode layer that forms a multilayer ceramic capacitor received in series connection between the first pairs of end portions, a discrete multi-terminal multilayer ceramic capacitor device, a discrete varistor having a body and having a pair of varistor end portions having opposite polarities outside the varistor body, first and second lead wires respectively attached to the first pairs of capacitor device end portions and the pair of varistor end portions, and a third lead wire attached to at least one of the second pairs of capacitor device end portions.

[0008]

[0007] According to another embodiment of the present invention, a multi-terminal multilayer ceramic having a plurality of capacitive elements A method for providing a device is disclosed. The method includes providing a body having a plurality of cooperating layers including an electrode layer used to form an integrated capacitance structure, forming a split feed-through type structure of two respective capacitors in a designated first region of the electrode layer, forming an overlap type structure of a multilayer ceramic capacitor in a designated second region of the electrode layer, adding a first pair of terminal ends outside of respective opposite faces of a pair of the body, wherein the second region capacitor is connected in series between the first pair of terminal ends, adding a second pair of terminal ends having the same polarity outside of at least a portion of respective opposite faces of another pair of the body, wherein at least one of the second pair of terminal ends and the first pair of terminal ends is connected in parallel with the two respective capacitors of the first region, and thus a plurality of capacitive elements are integrated into a single package device.

[0009]

[0008] Other features and aspects of the present invention are considered in more detail below.

[0010]

[0009] A complete and practicable description of the presently disclosed subject matter, including its best mode, is set forth in this specification with reference to the accompanying drawings.

Brief Description of the Drawings

[0011]

Figure 1A

[0010] FIG. 1 is an external perspective view of an exemplary embodiment of a multi-terminal multilayer device for use, such as for an SMD configuration, according to the presently disclosed subject matter.

Figure 1B

[0011] FIG. 1A is a perspective view of an exemplary embodiment partially in perspective to illustrate a plurality of components formed therein by a multilayer structure.

Figure 1C

[0012] FIG. 1B is a perspective view of the exemplary embodiment of FIG. 1A with a lead wire configuration added.

Figure 1D

[0013] It is a schematic diagram of an exemplary embodiment of Application Figure 1A.

Figure 2

[0014] It is a perspective view of another exemplary embodiment of the presently disclosed subject matter, which is partially in perspective to illustrate a plurality of components formed therein by a multilayer structure.

Figure 3A

[0015] It is an external perspective view of another exemplary embodiment of a multi-terminal multilayer device according to the presently disclosed subject matter.

Figure 3B

[0016] It is a perspective view of an exemplary embodiment of Application Figure 3A, which is partially in perspective to illustrate a plurality of components formed therein by a multilayer structure.

Figure 3C

[0017] It is a schematic diagram of an exemplary embodiment of Application Figure 3A.

Figure 4A

[0018] It is a perspective view of yet another exemplary embodiment of the presently disclosed subject matter, which is partially in perspective to illustrate a plurality of components formed therein by a multilayer structure.

Figure 4B

[0019] It is a top view of a selected layer within the multilayer structure of an exemplary embodiment of Figure 4A.

Figure 4C

[0020] It is a schematic diagram of an exemplary embodiment of Application Figure 4A.

Figure 5A

[0021] It is a perspective view of yet another exemplary embodiment of the presently disclosed subject matter, which is partially in perspective to illustrate a plurality of components formed therein by a multilayer structure.

Figure 5B

[0022] It is a top view of a selected layer within the multilayer structure of an exemplary embodiment of Figure 5A.

Figure 6A

[0023] An external perspective view of an exemplary embodiment of a multi-terminal multilayer device according to the presently disclosed subject matter, as illustrated, for use in a stack configuration having varistor devices, all for use with the added leads.

Figure 6B

[0024] A schematic diagram of an exemplary embodiment of Application FIG. 6A.

Figure 6C

[0025] An external perspective view of an exemplary embodiment of a multi-terminal multilayer device according to the presently disclosed subject matter.

DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0026] Reference characters repeatedly used throughout this specification and the accompanying drawings are intended to represent the same or similar features, elements, or steps thereof.

[0013]

[0027] Next, various embodiments of the present invention are referred to in detail, one or more examples of which are set forth below. The individual examples are provided by way of non-limiting illustration of the present invention. Indeed, it will be apparent to those skilled in the art that various modifications and changes can be made to the present invention without departing from the scope or spirit thereof. For example, features illustrated or described as part of one embodiment may be used on another embodiment, thereby obtaining still other embodiments. Accordingly, the present invention is intended to embrace such modifications and changes within the scope of the claims and their equivalents.

[0014]

[0028] Generally speaking, the present invention is directed to filter devices such as integrated capacitor filters, particularly integrated capacitor filters having a varistor function. Generally, a multi-terminal multilayer ceramic device is provided. In one embodiment, the device can comprise discrete varistors.

[0015]

[0029] Generally, a multilayer ceramic device such as a multilayer ceramic capacitor can include a ceramic body having external electrodes. The ceramic body is manufactured by sintering a stacked body formed of alternately stacked dielectric layers and internal electrodes. Adjacent internal electrodes of each pair face each other, with a dielectric layer interposed therebetween, and are electrically coupled to different external electrodes respectively.

[0016]

[0030] Generally, the dielectric layer can be constructed of any material widely used in the art. For example, the dielectric layer can be constructed of a ceramic material containing titanate as a main component. The titanate can include, but is not limited to, barium titanate (BaTiO3). The ceramic material can also contain rare earth metal oxides and / or compounds of acceptor-type elements such as Mn, V, Cr, Mo, Fe, Ni, Cu, Co, etc. Further, the titanate can also contain MgO, CaO, Mn3O4, Y2O3, V2O5, ZnO, ZrO2, Nb2O5, Cr2O3, Fe2O3, P2O5, SrO, Na2O, K2O, Li2O, SiO2, WO3, etc. Also, the ceramic material can include other additives, organic solvents, softeners, binders, dispersants, etc. in addition to the ceramic powder.

[0017]

[0031] Generally, the internal electrodes can be constructed of any material widely used in the art. For example, the internal electrodes can be formed by sintering a conductive paste whose main component is a noble metal material. These materials can include, but are not limited to, palladium, palladium-silver alloy, nickel, and copper. For example, in one embodiment, the electrodes can be constructed of nickel or a nickel alloy. The alloy can contain one or more of Mn, Cr, Co, Al, W, etc., and the Ni content in the alloy is preferably 95 wt% or more. Ni or Ni alloy can contain various trace components of 0.1 wt% or less such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, S, etc.

[0018]

[0032] The ceramic body can be formed using any method widely known in the art. For example, the ceramic body can be formed by forming a laminated body using alternately stacked ceramic sheets and patterned internal electrodes, removing the binder from the laminated body, sintering the laminated body from which the binder has been removed in a high-temperature non-oxidizing atmosphere in the range of 1200°C to 1300°C, and re-oxidizing the sintered laminated body in an oxidizing atmosphere.

[0019]

[0033] Generally, a varistor can include a ceramic body having external electrodes. The ceramic body is manufactured by sintering a laminated body formed of alternately stacked ceramic layers and internal electrodes. Adjacent internal electrodes of each pair face each other, a ceramic layer is interposed therebetween, and they are electrically coupled to different external electrodes respectively.

[0020]

[0034] Generally, the ceramic layer can be constructed of any material widely used in the art. For example, the ceramic layer can be constructed from metal oxides. Specifically, the metal oxide can include zinc oxide, and can also include other oxides such as oxides of bismuth, cobalt, antimony, manganese, chromium, boron and / or tin.

[0021]

[0035] Generally, the internal electrode can be constructed of any material widely used in the art. For example, the internal electrode can be formed by sintering a conductive paste whose main component is a noble metal material. These materials can include, but are not limited to, palladium, palladium-silver alloy, silver, nickel and copper. For example, in one embodiment, the electrode can be constructed of nickel or a nickel alloy. The alloy can contain one or more of Mn, Cr, Co, Al, W, etc., and the Ni content in the alloy is preferably 95 wt% or more. Ni or Ni alloy can contain various trace components of 0.1 wt% or less such as P, C, Nb, Fe, Cl, B, Li, Na, K, F, S, etc.

[0022]

[0036] Without being limited by theory, a capacitor is an electrical component that stores electrical energy in an electric field. Without being limited by theory, a varistor is an electrical component having an electrical resistance that can vary in response to an applied voltage, thereby making the varistor a voltage-dependent resistor. Capacitors and resistors can be combined to provide an RC circuit, i.e., a filter.

[0023]

[0037] In one embodiment, a multi-terminal multilayer ceramic device having three or more capacitive elements is provided. The three capacitors can include two series capacitors, and these two capacitors are in parallel with a third element. The device may be provided in parallel with a discrete varistor. The multi-terminal multilayer ceramic device may be a co-fired device, and / or the discrete varistor may be a discrete co-fired varistor.

[0024]

[0038] In one embodiment, the devices of the present disclosure can be packaged into an overmolded three-lead component. In another embodiment, the devices of the present disclosure can alternatively be implemented as surface mount devices (SMDs). With respect to the overmolded three-lead component, the overmolded three-lead component can provide an advantage in that it can be simply assembled by replacing three single discrete caps with a single integrated capacitive device. With respect to the surface mount device, the surface mount device can provide an advantage in that it results in the replacement of multiple discrete components on a printed circuit board (PCB), thereby saving space and, in some instances, reducing inductance.

[0025]

[0039] Some of the presently disclosed exemplary embodiments result in the integration of capacitive elements in a single co-fired package. In still other alternatives, the addition of varistor elements provides transient protection.

[0026]

[0040] Furthermore, other advantages may exist. For example, a substantial reduction in device size can be obtained, thereby reducing the number of solder connections and, in turn, increasing reliability. Another advantage is that the resulting integrated device can have a much smaller parasitic inductance than the corresponding number of discrete devices. Additionally, the lead wires allow for the placement of the exemplary device within the motor housing. Also, such a device can be constructed as an SMD.

[0027]

[0041] Another aspect of the present disclosure is that EMI and EMI / ESD circuit protection can be obtained that may be particularly useful for certain applications such as automotive applications. The presently disclosed subject matter may also be useful for motor start-stop applications.

[0028]

[0042] One embodiment of the present disclosure relates to a multi-terminal multilayer ceramic device, such as a multi-terminal simultaneous firing multilayer ceramic device having a plurality of capacitive elements. The device has a body, such as a generally rectangular six-sided body, having a plurality of cooperating layers including electrode layers that will form an integrated capacitive structure, a first region of such an electrode layer that forms a split feedthrough-type structure of two respective capacitors, a second region of such an electrode layer that forms an overlap-type structure of a multilayer ceramic capacitor, a first pair of terminations having opposite polarities external to such a body, and a second pair of terminations having the same polarity external to such a body. Further, preferably, such a first pair of terminations is in series connection with such a second region capacitor, and at least one of such a first pair of terminations and such a second pair of terminations is in parallel connection with such two respective capacitors of such a first region, and thus a plurality of capacitive elements are integrated into a single package device, such as a single package simultaneous firing device.

[0029]

[0043] In one embodiment, such a first region of such an electrode layer is located on opposite sides of a generally cross-shaped layer having respective front extending edges and back extending edges that each contact such a second pair of end portions, and can include at least a pair of layers such as a generally rectangular layer having side extending edges that each contact such a first pair of end portions.

[0030]

[0044] In another embodiment, such a second region of such an electrode layer can include at least a pair of alternating layers in an overlap configuration, and respective extending portions of these alternating layers each contact such a first pair of end portions.

[0031]

[0045] In one embodiment, such two respective capacitors of such a first region may be in series with each other, and both may also be in parallel with such a multilayer ceramic capacitor of such a second region.

[0032]

[0046] In another embodiment, such a first pair of end portions and a second pair of end portions are disposed on opposite side pairs of sides of such a body, and can each be wound from there around a designated bottom surface of such a body to form a surface mount device (SMD) configuration for such a device.

[0033]

[0047] According to one embodiment, a first lead wire and a second lead wire can each be attached to such a first pair of end portions, and a third lead wire can be attached to at least one of such a second pair of end portions.

[0034]

[0048] According to another embodiment, such a multi-terminal multi-layer ceramic device can further include a third region of such an electrode layer that forms a split feed-through type structure of two respective additional capacitors. According to such an alternative, at least one of such a first pair of terminal ends and such a second pair of terminal ends may be respectively connected in parallel with such two respective additional capacitors of such a third region.

[0035]

[0049] In yet another embodiment, such a second region of such an electrode layer can be present between such a first region and a third region of such an electrode layer. According to other variations, such a body can have a pair of relatively elongated sides and a pair of relatively shorter sides, such a first pair of terminal ends can each be present on such a pair of relatively elongated sides, and such a second pair of terminal ends can each be present on such a pair of relatively shorter sides.

[0036]

[0050] In some embodiments, such a pair of layers of such a first layer, such as a generally rectangular layer, can each have a different overlap area with such a generally cross-shaped layer of such a first layer, and thus different capacitance values can be obtained for such respective capacitors of such a first region. In other cases, such an exemplary multi-terminal multilayer ceramic device can further comprise a third region of such an electrode layer that forms a split feed-through type structure of two respective additional capacitors, such a third region having respective front extending edges and back extending edges that each contact such a second pair of terminations, and side extending edges that each contact such a first pair of terminations, and comprising at least a pair of layers, such as generally rectangular layers. In some embodiments, such a pair of layers of such a third layer, such as a generally rectangular layer, can each have a different overlap area with such a generally cross-shaped layer of such a third layer, and thus different capacitance values can be obtained for such respective additional capacitors of such a third region.

[0037]

[0051] In one embodiment, such an electrode layer of such a second region can include a relatively large area for forming a relatively large capacitance value overlap type multilayer ceramic capacitor.

[0038]

[0052] In one embodiment, a discrete varistor having a pair of external terminations can be stacked on such a device and such a first lead wire and such a second lead wire are each attached to such a pair of external terminations of such a varistor, and thus such a device and such a discrete varistor are connected in parallel.

[0039]

[0053] Another exemplary embodiment according to the presently disclosed subject matter relates to an integrated capacitor filter having a varistor function and comprising a discrete multi-terminal multilayer ceramic capacitor device, such as a co-fired multilayer ceramic capacitor device having a plurality of capacitive elements. The integrated capacitor filter has a generally rectangular body having a plurality of cooperating layers including electrode layers that will form an integrated capacitive structure, a first pair of capacitor device terminations having opposite polarities external to such a body, a second pair of capacitor device terminations having the same polarity external to such a body, a first region of such electrode layers forming two respective capacitors, and a second region of such electrode layers forming a multilayer ceramic capacitor received in series connection between such first pair of terminations. Such a discrete multi-terminal multilayer ceramic capacitor device is preferably further coupled to a discrete varistor, such as a discrete co-fired varistor, the discrete varistor having a body, such as a generally rectangular body having six faces, having a pair of varistor terminations having opposite polarities external to such varistor body, a first lead wire and a second lead wire respectively attached to such first pair of capacitor device terminations and such pair of varistor terminations, and a third lead wire attached to at least one of such second pair of capacitor device terminations.

[0040]

[0054] In one embodiment, at least one of such first pair of capacitor device terminations and such second pair of capacitor device terminations may be respectively in parallel connection with such two respective capacitors of such first region. In another embodiment, such first region of such electrode layers can form a split feed-through type structure of such two respective capacitors, and such second region of such electrode layers can form an overlap type structure of such multilayer ceramic capacitor.

[0041]

[0055] According to another embodiment, a method is provided that includes, for example, a method for manufacturing such a device. For example, one exemplary embodiment of the presently disclosed subject matter relates to a method for providing a multi-terminal multilayer ceramic device, such as a co-fired multilayer ceramic device having a plurality of capacitive elements. Such a method includes providing a body, generally rectangular with six sides, having a plurality of cooperating layers including electrode layers used to form an integrated capacitive structure; forming a split feedthrough type structure of two respective capacitors in a designated first region of such an electrode layer; forming an overlap type structure of a multilayer ceramic capacitor in a designated second region of such an electrode layer; adding a first pair of terminal ends external to opposite respective faces of a pair of such a body, such that such a second region capacitor is connected in series between such a first pair of terminal ends; adding a second pair of terminal ends having the same polarity external to at least a portion of opposite respective faces of another pair of such a body, such that at least one pair of terminal ends of such a second pair of terminal ends and such a first pair of terminal ends are each connected in parallel with such two respective capacitors of such a first region, and thus a plurality of capacitive elements are integrated into a single package device, such as a single package co-fired device.

[0042]

[0056] In one embodiment, such a first region of such an electrode layer may comprise at least a pair of layers, such as generally rectangular layers, located on opposite sides of a generally cross-shaped layer having respective front extending edges and back extending edges that each contact such a second pair of terminal ends, and having side extending edges that each contact such a first pair of terminal ends. Also, such a second region of such an electrode layer can comprise at least a pair of alternating layers in an overlap configuration, and respective extending portions of these alternating layers each contact a respective one of such a first pair of terminal ends.

[0043]

[0057] In one embodiment, such terminal ends of the first pair and such terminal ends of the second pair can each be wound around a designated bottom surface of such a body to form a surface mount device (SMD) configuration for such a device.

[0044]

[0058] In one embodiment, the method can further include the step of forming a separate split feed-through type structure for two respective capacitors in a designated third region of such an electrode layer, where such two respective capacitors in such a third region are each connected in parallel to at least one of such terminal ends of such second pair of terminal ends and such first pair of terminal ends.

[0045]

[0059] In one embodiment, the method can include the step of providing such a pair of layers of such a first layer, such as a generally rectangular layer, having different overlap areas with such a generally cross-shaped layer of such a first layer, and thus different capacitance values can be obtained for such respective capacitors in such a first region.

[0046]

[0060] The method can also further include the step of forming a split feed-through type structure for two respective additional capacitors in a designated third region of such an electrode layer, where such a third region comprises at least a pair of layers, such as a generally rectangular layer, having respective front extending edges and back extending edges each in contact with such second pair of terminal ends and side extending edges each in contact with such first pair of terminal ends.

[0047]

[0061] In one embodiment, the method can further include attaching a first lead wire and a second lead wire to respective terminations of such a first pair, and attaching a third lead wire to at least one of such terminations of such a second pair. In one embodiment, the method can further include stacking discrete varistors having a pair of external terminations for such a device, wherein such first and second lead wires are attached to respective external terminations of such a pair of such varistors, and thus such device and such discrete varistors are connected in parallel.

[0048]

[0062] FIG. 1A illustrates an external perspective view of a multi-terminal multilayer device, generally designated 100, according to the presently disclosed subject matter. As illustrated, exemplary embodiment 100 generally has a body, generally designated 102, such as a six-sided body having external terminations 104, 106, 108, and 110. All such external terminations are provided on a designated bottom surface, generally designated 112, of device 100 for use in a surface mount device (SMD) configuration or the like.

[0049]

[0063] Device 100 in the illustrated exemplary embodiment can comprise a multi-terminal multilayer ceramic device having three or more capacitive elements. In some such embodiments, such three capacitors can include two series capacitors, which are in parallel with a third element. As will be understood by those of ordinary skill in the art in the field related to all embodiments described herein, the cooperating layers in the subject multilayer structure comprise electrode layers, which will form an integrated capacitive structure.

[0050]

[0064] FIG. 1B is a perspective view of the exemplary embodiment of application FIG. 1A, generally designated 100 It is an illustration, and is a partial perspective view for illustrating a plurality of components formed therein by a multilayer structure. More specifically, as shown in such FIG. 1B, the upper part of the device 100, that is, the first region, collectively 114, internally provides a split feedthrough type structure to bring about two respective exemplary capacitors, while the lower part of the device 100, that is, the second region, collectively 116, internally provides a more standard overlapping multilayer capacitor structure. Therefore, such typical exemplary embodiments of FIGS. 1A and 1B result in the integration of capacitive elements in a single package such as a single co-fired package.

[0051]

[0065] More specifically, with respect to the upper region 114, a pair of layers 118 and 120, such as generally rectangular layers 118 and 120, are juxtaposed on opposite sides of a typical cross-shaped layer 122. As shown, the front extending edge and the back extending edge 124 and 126 of the layer 122 are in contact with the central (i.e., the second pair of) external terminal ends 108 and 110 respectively, while the side extending edges 128 and 130 are in contact with the side / end (i.e., the first pair of) terminal ends 104 and 106 respectively.

[0052]

[0066] With respect to the lower region 116, the paired alternating layers 132 / 134 and 136 / 138 are a standard overlapping configuration for forming a multilayer capacitor in such a region 116 of the device 100. Also as shown, the respective ends 140 and 142 of these alternating layers are in contact with the external end terminal 104, while the respective ends 144 and 146 of these alternating layers are in contact with the external end terminal 106.

[0053]

[0067] Figure 1C illustrates a perspective view of an exemplary embodiment 100 of Application Figure 1A, with a lead wire configuration added. More specifically, lead wires 148, 150, and 152 are attached to external terminals 104, 108, and 106 respectively. Lead wires 148 and 152 can each constitute a first lead wire and a second lead wire attached to a first pair of terminals 104 and 106, while lead wire 150 can constitute a third lead wire attached to at least one of a second pair of terminals 108 and 110. Those skilled in the art will also understand that terminals 108 and 110 are both connected to layer 122 in the upper region 114 of device 100 such that lead wire 150 can be connected to either of such terminals 108 or 110 with the same electrical circuit mechanism outcome. The resulting configuration of Application Figure 1C is an overmolded three-lead wire component.

[0054]

[0068] Figure 1D illustrates a schematic view of an exemplary embodiment, collectively 100, of Application Figure 1A, the connection / attachment configuration of which is as shown in Application Figure 1C. More specifically, the illustrated lead wires 148, 150, and 152 are each in contact with series and parallel capacitors. The illustrated capacitance values are intended to be merely exemplary and not limiting of their value.

[0055]

[0069] As illustrated, device 100 provides a single device solution for including series and parallel capacitors. The upper region of device 100, collectively 114, shows two typical 10 nF capacitors 154 and 156 formed by a split feedthrough configuration of typical layers 118, 122, and 130. The lower region of device 100, collectively 116, shows a typical single 1 μF capacitor 158, such as a capacitor that would be formed from a standard multilayer capacitor structure.

[0056]

[0070] Although various sizes may be practiced for any of the exemplary embodiments disclosed herein, device 100 may be considered to be of a typical standard MLC case size, such as a 1206 case size. Of course, in various embodiments, various sizes may be practiced depending on the needs or desires of a particular application and variations in capacitance values. All such variations and variations in exemplary capacitance values are intended to be within the spirit and scope of the presently disclosed subject matter. Otherwise, device 100 according to the presently disclosed subject matter represents an integrated three-terminal device having a standard multilayer capacitor (MLC: multilayer capacitor) in a designated lower region of device 100 coupled to a split feedthrough in the designated upper region of device 100. In terms of method, according to its description, and device 100 (a single-package integrated multi-capacitance element) as used herein simplifies the assembly of leaded components or SMD components by replacing three single discrete capacitors with a single integrated capacitance device. Especially when used in an SMD configuration, multiple discrete components on the PCB are avoided, which saves space on the PCB and, on the other hand, reduces inductance.

[0057]

[0071] Figure 2 illustrates another exemplary embodiment of the presently disclosed subject matter, taken as a perspective view of 200 in its entirety. Similar to Application Figure 1B, Figure 2 provides a partial perspective view to illustrate a plurality of components formed therein by a multilayer structure. More particularly, device 200 has a pair of series capacitors located generally in upper region 214, as well as a similar pair of series capacitors located generally in lower region 214', regions 214 and 214' being on either side of a central region, taken as 216 in its entirety, in which a single parallel capacitor is formed. Thus, those skilled in the art will recognize from the complete disclosure along with this disclosure that the internal configuration embodiment of device 200 of Application Figure 2 may nevertheless be used with a standard package size (or other size) and the external termination configuration shown by Application Figure 1A.

[0058]

[0072] More particularly, as shown in such Figure 2, the upper and lower (first and third) regions of device 200, taken as 214 and 214' in its entirety, each internally provide a respective split feedthrough-type structure to result in a respective pair of exemplary capacitors, while the central or middle (second) region of device 200, between regions 214 and 214', taken as 216 in its entirety, internally provides a more standard overlapping multilayer capacitor structure. Thus, this typical exemplary embodiment of Figure 2 results in another exemplary embodiment of the integration of capacitive elements in a single package, such as the presently disclosed single co-fired package.

[0059]

[0073] More specifically, with respect to the upper region 214, a pair of layers 218 and 220, such as generally rectangular coplanar layers 218 and 220, are juxtaposed on opposite sides of a typical cross-shaped layer 222. As shown, the front extending edge and the back extending edge 224 and 226 of layer 222 will respectively contact the central outer terminations 108 and 110 (of application FIG. 1A), while the side extending edges 228 and 230 will respectively contact the side / end terminations 104 and 106 (of application FIG. 1A). Similarly, with respect to the lower region 214', a pair of layers 218' and 220', such as generally rectangular layers 218' and 220', are juxtaposed on opposite sides of a typical cross-shaped layer 222'. As shown, the front extending edge and the back extending edge 224' and 226' of layer 222' will respectively contact the central outer terminations 108 and 110 (of application FIG. 1A), while the side extending edges 228' and 230' will respectively contact the side / end terminations 104 and 106 (of application FIG. 1A).

[0060]

[0074] With respect to the middle or central region 216, the paired alternating layers 232 / 234 and 236 / 238 are in a standard overlap configuration for forming multilayer capacitors in such a region 216 of the device 200. Also as shown, the respective ends 240 and 242 of these alternating layers contact the outer end termination 104 (of application FIG. 1A), while the respective ends 244 and 246 of these alternating layers contact the outer end termination 106 (of application FIG. 1A). contact, while the respective ends 244 and 246 of these alternating layers contact the outer end termination 106 (of application FIG. 1A).

[0061]

[0075] Similar to the potential alternative implementation of application embodiment 100 of FIG. 1A in the leaded configuration of application FIG. 1C, the device 200 of application FIG. 2 may be implemented as a surface mount device or may be coupled to the leads in the configuration of application FIG. 1C.

[0062]

[0076] FIG. 3A illustrates an external perspective view of another exemplary embodiment 300 of a multi-terminal multilayer device according to the presently disclosed subject matter. FIG. 3B illustrates a perspective view of such an exemplary embodiment 300 of application FIG. 3A, which is partially in perspective to illustrate a plurality of components formed therein by a multilayer structure, while FIG. 3C illustrates a schematic view of the exemplary embodiment 300 of application FIG. 3A.

[0063]

[0077] More particularly, an alternative embodiment device 300 of the presently disclosed subject matter may be considered a so-called reverse configuration that results in a relatively smaller inductance, as would be understood by one of ordinary skill in the art. Compared to the exemplary embodiments 100 of FIGS. 1A and 1B, the elongated sides of an exemplary body 302, such as the six-sided body 302, are terminated by external terminations 304 and 306, while the strip-shaped external terminations 308 and 310 are formed at respective short side ends of the body 302. Similar to FIG. 1B of the application, the device 300 has a plurality of components formed by a plurality of layers in respective lower and upper regions 314 and 316 of the device 300, respectively. However, such layers are relatively rotated by 90 degrees compared to the internal multilayer structure of the device 100 when referring to the relatively elongated sides and relatively short sides of the device 300.

[0064]

[0078] Furthermore, the partial perspective view of FIG. 3A includes an upper region of the device 300 that internally provides a split feedthrough type structure that results in two respective exemplary capacitors, collectively 314, and a lower region of the device 300 that internally provides a more standard overlapping multilayer capacitor structure, collectively 316, and illustrates a plurality of components formed therein by a multilayer structure. Thus, this typical alternative exemplary embodiment of FIGS. 3A and 3B also results in the integration of capacitive elements in a single package, such as a single co-fired package in this case.

[0065]

[0079] With respect to the upper region 314, a pair of complementary coplanar layers 318 and 320 (which may generally be T-shaped or other shapes) are juxtaposed on opposite sides of a typical cross-shaped layer 322. As shown, the side extending edges 324 and 326 of layer 322 contact the strip / side external terminations 308 and 310 respectively, while the front extending edge and the back extending edges 328 and 330 of members 318 and 320 respectively contact the elongated side terminations 304 and 306.

[0066]

[0080] With respect to the lower region 316, typical alternating layers 332 and 336 are in a standard overlap configuration for forming multilayer capacitors in such a region 316 of the device 300. Also as shown, the respective ends 340 and 342 of these alternating layers contact the external elongated side terminations 304 and 306 respectively.

[0067]

[0081] From the complete disclosure herein, those skilled in the art should understand that although the device 300 is illustrated in a SMD configuration in FIG. 3A, such a device 300 can be equally practiced in a leaded configuration as shown by the exemplary embodiment of FIG. 1C.

[0068]

[0082] Similar to FIG. 1D, FIG. 3C illustrates a schematic of the exemplary embodiment of FIG. 3A, generally 300, in its connection configuration shown by application FIG. 3A. More specifically, the connections are listed as the respective terminations 304, 308 and 306 for circuit mechanism connections shown in contact with series and parallel capacitors respectively. The capacitance values shown are intended to be merely exemplary and not limiting to that value.

[0069]

[0083] As illustrated, device 300 provides a single device solution for including series and parallel capacitors. The upper region of device 300, collectively 314, shows two typical 10 nF capacitors 354 and 356 formed by a split feedthrough configuration of typical layers 318, 322, and 330. The lower region of device 300, collectively 316, shows a typical single 1 μF capacitor 358, such as a capacitor that would be formed from a standard multilayer capacitor structure.

[0070]

[0084] FIG. 4A illustrates a perspective view of yet another exemplary embodiment of the presently disclosed subject matter, collectively 400, which is partially in perspective to illustrate a plurality of components formed therein by a multilayer structure. Specifically, such exemplary embodiment 400 utilizes different overlap areas (relative to exemplary embodiment 200) to provide different capacitances in an integrated device such as an integrated co-fired device.

[0071]

[0085] More specifically, device 400 has a pair of series capacitors located generally in upper region 414, as well as a similar pair of series capacitors located generally in lower region 414', regions 414 and 414' being on opposite sides of a central region, collectively 416, in which a single parallel capacitor is formed. Thus, one of ordinary skill in the art, from the complete disclosure along with the present disclosure, will recognize that the internal configuration embodiment of device 400 of application FIG. 4A may nonetheless be used with a standard package size (or other size) and the external termination configuration shown by application FIG. 1A.

[0072]

[0086] More specifically, as shown in such a Figure 4, the upper and lower regions of the device 400, collectively 414 and 414', internally provide respective split feed-through type structures to result in respective exemplary capacitors of two pairs, while the central or middle region of the device 400, between the regions 414 and 414', collectively 416, internally provides a more standard overlapping multilayer capacitor structure. Thus, this typical exemplary embodiment of Figure 4 results in another exemplary embodiment of the integration of capacitive elements in a single package, such as the currently disclosed single co-fired package.

[0073]

[0087] More specifically, with respect to the upper region 414, a pair of layers 418 and 420, such as generally rectangular coplanar layers 418 and 420, are juxtaposed on opposite sides of a typical cross-shaped layer 422. As shown, the front extending edge and the back extending edge 424 and 426 of the layer 422 will respectively contact the central external terminations 108 and 110 (of Application Figure 1A), while the side extending edges 428 and 430 will respectively contact the side / end terminations 104 and 106 (of Application Figure 1A). Similarly, with respect to the lower region 414', a pair of layers 418' and 420', such as generally rectangular layers 418' and 420', are juxtaposed on opposite sides of a typical cross-shaped layer 422'. As shown, the front extending edge and the back extending edge 424' and 426' of the layer 422' will respectively contact the central external terminations 108 and 110 (of Application Figure 1A), while the side extending edges 428' and 430' will respectively contact the side / end terminations 104 and 106 (of Application Figure 1A).

[0074]

[0088] With respect to the intermediate or central region 416, the paired alternating layers 432 / 434 and 436 / 438 are a standard overlap configuration for forming a multilayer capacitor in such a region 416 of the device 400. As also shown, each end 440 and 442 of these alternating layers contacts the external end termination 104 (of application FIG. 1A), while each end 444 and 446 of these alternating layers contacts the external end termination 106 (of application FIG. 1A).

[0075]

[0089] Similar to the potential alternative implementation of the application embodiment 100 of FIG. 1A in the leaded configuration of application FIG. 1C, the device 400 of application FIG. 4A may be implemented as a surface mount device or may be coupled to leads in the configuration of application FIG. 1C.

[0076]

[0090] Figure 4B illustrates a top view of a selected layer within the upper region 414 of the multilayer structure of exemplary embodiment 400 of FIG. 4A generally. More particularly, exemplary layers 418, 420, and 422 are shown. As will be appreciated by those skilled in the art, the extent of the surface area that overlaps with the opposite layer contributes to the determination of the resulting capacitance value formed thereby. In this example, each of the layers 418, 420, and 422 is configured such that the overlap area 423 present on one side of region 414 is wider than the overlap area 425 present on the other side of region 414, as shown. As will be appreciated, such different overlap areas facilitate the formation of different capacitances, as separately reflected herein. In particular, FIG. 4C illustrates a schematic diagram of exemplary embodiment 400 of applications FIGS. 4A and 4B. As shown, two series capacitors are formed with different capacitance values as a reflection of the respective degree of non-uniformity of the overlap with respect to areas 423 and 425. Although variant forms may be practiced, exemplary embodiment 400 illustrated provides exemplary capacitances for capacitors 454 and 45 of 20 nF and 10 nF, respectively, and 1 μF for capacitor 458. Although a leaded configuration may be practiced, terminations 404, 408, and 406 are shown in the schematic of FIG. 3C to reflect the surface mount device configuration of embodiment 400.

[0077]

[0091] Figure 5A illustrates a perspective view of yet another exemplary embodiment 500 of the presently disclosed subject matter, which is partially in perspective to illustrate a plurality of components formed therein by a multilayer structure. In particular, relatively large electrodes (such as a T-shaped design) are used to increase the relative degree of overlap and, accordingly, the capacitance value can be increased. Also, relatively large electrodes can be used to provide other advantageous features including, but not limited to, reduction of inductance and / or equivalent series resistance (ESR).

[0078]

[0092] More specifically, as shown in such a Figure 5A, the upper region of the device 500, collectively 514, internally provides a split feed-through type structure to result in two respective exemplary capacitors, while the lower region of the device 500, collectively 516, internally provides an overlapping multilayer capacitor structure. Thus, a typical exemplary embodiment of this Figure 5A results in the integration of capacitive elements in a single package such as a single co-fired package.

[0079]

[0093] More specifically, with respect to the upper region 514, a pair of layers 518 and 520, such as generally rectangular layers 518 and 520, are juxtaposed on opposite sides of a typical cross-shaped layer 522. As shown, the front extending edge and the back extending edges 524 and 526 of the layer 522 are in contact with the central external terminations 108 and 110 (for SMD configuration applications Figure 1A), respectively, while the side extending edges 528 and 530 are in contact with the side / end terminations 104 and 106 (Application Figure 1A), respectively.

[0080]

[0094] With respect to the lower region 516, the paired alternating layers 532 / 534 and 536 / 538 are a standard overlapping configuration for forming a multilayer capacitor in such a region 516 of the device 500. Also as shown, the respective ends 540 and 542 of these alternating layers are in contact with the external end termination 104 (Application Figure 1A), while the respective ends 544 and 546 of these alternating layers are in contact with the external end termination 106 (Application Figure 1A).

[0081]

[0095] FIG. 5B illustrates a top view of selected layers 532 and 536 within the lower region 516 of the multilayer structure of the exemplary embodiment 500 of FIG. 5A. Although various shapes can be practiced, as shown, such capacitor electrode layers 532 and 536 can comprise a T-shaped layer in some examples. As will be understood by those skilled in the art, the overlap region or area 533 contributes to the resulting capacitance formation such that the corresponding capacitance value is relatively large (when all other factors are constant) by making such overlap area relatively wide. A relatively wide area can also be used to provide other advantageous features including, but not limited to, reduction of inductance and / or equivalent series resistance (ESR).

[0082]

[0096] As separately disclosed herein, by adding the exemplary embodiments herein in parallel with discrete varistors such as discrete simultaneous firing varistors, the device facilitates providing transient protection for the resulting combination. More particularly, FIG. 6A illustrates an external perspective view of an exemplary embodiment of a multi-terminal multilayer device, generally 600, according to the presently disclosed subject matter, as illustrated for use in a stack configuration having varistor devices, generally 660, all with added lead wires 648, 650, and 652, respectively. As further contemplated herein, FIG. 6B illustrates a schematic view of the exemplary embodiment 600 of application FIG. 6A.

[0083]

[0097] Figure 6A illustrates an external perspective view of a multi-terminal multi-layer device according to the presently disclosed subject matter, collectively 600 exemplary embodiments. As illustrated, the exemplary embodiment 600 generally has a body, such as a six-sided body having external terminations 604, 606, 608, and 610, collectively 602. The device 600 in the illustrated exemplary embodiment can comprise a multi-terminal multi-layer ceramic device, such as a co-fired multi-layer ceramic device, and the multi-terminal multi-layer ceramic device comprises three or more capacitive elements. In some such embodiments, such three capacitors can include two series capacitors, and these two capacitors are in parallel with a third element.

[0084]

[0098] Also, Figure 6A also illustrates a perspective view of an exemplary embodiment 600 with a varistor device, collectively 660 added. Such a device 660 can also have a standard 1206 case size or other standard or non-standard case sizes. As shown, the varistor 660 also has external terminations, collectively 662 and 664. Further, according to Figure 6A, a lead wire configuration arrangement can be used such that the devices 600 and the varistor 660 can be arranged in parallel with each other. More specifically, the lead wires 648, 650, and 652 are respectively attached to the external (capacitor device) terminations 604, 608, and 606 of the device 600, while the lead wires 648 and 652 are respectively connected to the external side (varistor) terminations 662 and 664 of the varistor 660, as shown. The resulting configuration of the application Figure 6A is an overmolded three-lead component.

[0085]

[0099] FIG. 6B illustrates an exemplary embodiment of FIG. 6A in its connection / mounting configuration shown by application FIG. 6A, a schematic diagram of 600 in general. More specifically, the illustrated lead wires 648, 650, and 652 are in contact with series and parallel capacitors respectively. The illustrated capacitance values are intended to be merely exemplary and not limiting to that value. Similarly, varistor 660 is in contact with lead wires 648 and 652 as illustrated, and is thus in a parallel relationship with device 600. The illustrated varistor characteristics are intended to be merely exemplary and not limiting to it.

[0086]

[0100] FIG. 6C illustrates a perspective view of a multi-terminal multi-layer device. Generally, FIG. 6 C illustrates the device of FIG. 6A in another perspective. For example, the embodiment of FIG. 6C provides device 600 such as a multi-layer ceramic device at the bottom with varistor 660 at the top. Such a configuration can allow for use as a surface mount device after integrally coupling device 600 and varistor 660 by soldering or the like. Further, the embodiment illustrated in FIG. 6C is provided without the lead wires illustrated in FIG. 6A. However, it should be understood that lead wires can also be used in such a configuration.

[0087]

[0101] As illustrated, device 600 provides a single device solution for including series and parallel capacitors. Device 600 shows two typical 10 nF capacitors 654 and 656 such as capacitors that can be formed by a split feed-through configuration of multiple layers in an isolated region of device 600. Also, device 600 provides a single typical 1 μF capacitor 658 such as a capacitor that can be formed from a standard multi-layer capacitor structure in another region of device 600 as illustrated.

[0088]

[0102] For any exemplary embodiment disclosed herein, various sizes can be practiced, but the device 600 and the varistor 660 can be considered to be of a typical standard MLC case size, such as a 1206 case size. Of course, in various embodiments, various sizes can be practiced depending on the needs or desires of a particular application. All such variations and variations of exemplary capacitance values are intended to be within the spirit and scope of the presently disclosed subject matter.

[0089]

[0103] As shown by the disclosure herein, for use in SMD placement In some embodiments, the presently disclosed subject matter provides for the replacement of multiple discrete components on a printed circuit board (PCB), thereby saving space and, in some instances, reducing inductance. All such presently disclosed exemplary embodiments may, in some of their uses, be packaged in an overmolded three-lead component. According to the presently disclosed subject matter, a substantial reduction in device size is achieved, thereby reducing the number of solder joints and, by extension, increasing reliability.

[0090]

[0104] Also, the individual steps to achieve the disclosed configuration are intended to be those that are typical and are not intended to indicate any other necessary use beyond the general nature of the disclosure as separately shown. For example, one of ordinary skill in the art will recognize that practicing the selected steps can result in a particular design selected for a given application of the presently disclosed subject matter.

[0091]

[0105] Above, regarding such presently disclosed subject matter, with respect to its particular embodiments Although described in detail above, those skilled in the art will recognize that, upon understanding the above description, changes to such embodiments, variations of such embodiments, and equivalents to such embodiments can be readily brought about. Accordingly, the scope of the present disclosure is by way of example and not by way of limitation, and the subject disclosure is not intended to exclude the inclusion of such modifications, changes and / or additions to the presently disclosed subject matter as would be readily apparent to those skilled in the art.

Claims

1. A multi-terminal multilayer ceramic device having a plurality of capacitive elements, a body having a plurality of cooperating layers including electrode layers for forming an integrated capacitive structure, a first region of the electrode layer forming a split feed-through type structure of two respective capacitors, a second region of the electrode layer forming an overlap type structure of a multilayer ceramic capacitor, a first pair of terminal ends having opposite polarities outside the body, a second pair of terminal ends having the same polarity outside the body and comprising, wherein the first pair of terminal ends is in series connection with the second region capacitor, and at least one of the first pair of terminal ends and the second pair of terminal ends is in parallel connection with the two respective capacitors of the first region, and thus a plurality of capacitive elements are integrated in a single package device, a multi-terminal multilayer ceramic device.

2. The multi-terminal multilayer ceramic device according to claim 1, wherein the first region of the electrode layer is located on opposite sides of a generally cross-shaped layer having respective front extending edges and back extending edges each contacting the second pair of terminal ends, and comprises at least a pair of layers having side extending edges each contacting the first pair of terminal ends.

3. The multi-terminal multilayer ceramic device according to claim 1, wherein the second region of the electrode layer comprises at least paired alternating layers in an overlap configuration, and respective extending portions of the alternating layers each contact the first pair of terminal ends.

4. The multi-terminal multilayer ceramic device according to claim 1, wherein the two respective capacitors of the first region are in series with each other and both are in parallel with the multilayer ceramic capacitor of the second region.

5. The multi-terminal multilayer ceramic device according to claim 1, wherein the first pair of terminal ends and the second pair of terminal ends are disposed on opposite side pairs of the body and each wraps from there to a designated bottom surface of the body to form a surface mount device (SMD) configuration for the device.

6. The multi-terminal multilayer ceramic device according to claim 1, further comprising a first lead wire and a second lead wire each attached to the first pair of terminal ends, and a third lead wire attached to at least one of the second pair of terminal ends.

7. The third region of the electrode layer that forms a split feed-through type structure for each of the two additional capacitors further comprising The multi-terminal multilayer ceramic device according to claim 1, wherein at least one of the end portions of the first pair and the end portions of the second pair are each connected in parallel with the two respective additional capacitors in the third region.

8. The multi-terminal multilayer ceramic device according to claim 1, wherein the second region of the electrode layer is present between the first region and the third region of the electrode layer.

9. The body has a pair of relatively elongated side surfaces and a pair of relatively shorter side surfaces, The end portions of the first pair are each present on the relatively elongated side surfaces of the pair, The end portions of the second pair are each present on the relatively shorter side surfaces of the pair, The multi-terminal multilayer ceramic device according to claim 1.

10. The pair of layers of the first layer each have a different overlap area with the generally cross-shaped layer of the first layer, and thus provide different capacitance values for the respective capacitors in the first region. The multi-terminal multilayer ceramic device according to claim 2.

11. A third region of the electrode layer that forms a split feed-through type structure for each of the two additional capacitors, having respective front extending edges and back extending edges that each contact the end portions of the second pair, and comprising at least a pair of layers having side extending edges that each contact the end portions of the first pair further comprising The pair of layers of the third layer each have a different overlap area with the generally cross-shaped layer of the third layer, and thus provide different capacitance values for the respective additional capacitors in the third region. The multi-terminal multilayer ceramic device according to claim 10.

12. The multi-terminal multilayer ceramic device according to claim 1, wherein the electrode layer in the second region includes a relatively large area for forming a relatively large capacitance value overlap type multilayer ceramic capacitor.

13. A discrete varistor having a pair of external terminal ends is stacked against the device, and the first lead wire and the second lead wire are respectively attached to the pair of external terminal ends of the varistor, so that the device and the discrete varistor are connected in parallel. The multi-terminal multilayer ceramic device according to claim 6.

14. An integrated capacitor filter having a varistor function, A discrete multi-terminal multilayer ceramic capacitor device having a plurality of capacitive elements, A body having a plurality of cooperating layers including electrode layers that will form an integrated capacitive structure, A first pair of capacitor device terminal ends having opposite polarities outside the body, A second pair of capacitor device terminal ends having the same polarity outside the body, A first region of the electrode layer forming two respective capacitors, A discrete multi-terminal multilayer ceramic capacitor device comprising a second region of the electrode layer forming a multilayer ceramic capacitor received in series connection between the first pair of terminal ends, A discrete varistor comprising a body, the discrete varistor having a pair of varistor terminal ends having opposite polarities outside the varistor body, A first lead wire and a second lead wire respectively attached to the first pair of capacitor device terminal ends and the pair of varistor terminal ends, A third lead wire attached to at least one of the second pair of capacitor device terminal ends An integrated capacitor filter comprising.

15. The integrated capacitor filter having a varistor function according to claim 14, wherein at least one of the first pair of capacitor device terminal ends and the second pair of capacitor device terminal ends is respectively connected in parallel with the two respective capacitors of the first region.

16. The first region of the electrode layer forms a split feed-through type structure of the two respective capacitors, The integrated capacitor filter having a varistor function according to claim 14, wherein the second region of the electrode layer forms an overlap type structure of the multilayer ceramic capacitor.

17. A method for providing a multi-terminal multilayer ceramic device having a plurality of capacitive elements, Providing a body having a plurality of cooperating layers including electrode layers used to form an integrated capacitive structure, Forming a split feedthrough type structure of two respective capacitors in a designated first region of the electrode layer; Forming an overlap type structure of a multilayer ceramic capacitor in a designated second region of the electrode layer; Adding a first pair of terminal portions outside of respective opposite surfaces of a pair of the body, wherein the second region capacitor is connected in series between the first pair of terminal portions; Adding a second pair of terminal portions having the same polarity outside of at least a part of respective opposite surfaces of another pair of the body, wherein at least one pair of the terminal portions of the second pair of terminal portions and the first pair of terminal portions are respectively connected in parallel with the two respective capacitors of the first region, and thus a plurality of capacitive elements are integrated in a single package device; A method comprising the steps of.

18. The first region of the electrode layer is located on opposite sides of a generally cross-shaped layer having respective front extending edges and back extending edges that respectively contact the second pair of terminal portions, and includes at least a pair of layers having side extending edges that respectively contact the first pair of terminal portions; The second region of the electrode layer includes at least a pair of alternating layers in an overlapping configuration, and respective extending portions of the alternating layers respectively contact the first pair of terminal portions; The method according to claim 17.

19. The method according to claim 17, wherein the first pair of terminal portions and the second pair of terminal portions respectively wrap around a designated bottom surface of the body to form a surface mount device (SMD) configuration for the device.

20. The method according to claim 17, further comprising forming another split feedthrough type structure of two respective capacitors in a designated third region of the electrode layer, wherein the two respective capacitors of the third region are respectively connected in parallel with at least one of the terminal portions of the second pair of terminal portions and the first pair of terminal portions.

21. The method according to claim 18, further comprising providing the pair of layers of the first layer having respective different overlap areas with the generally cross-shaped layer of the first layer, and thus providing different capacitance values for the respective capacitors of the first region.

22. Further comprising the step of forming a split feedthrough type structure of two respective additional capacitors in a specified third region of the electrode layer, wherein the third region has respective front extending edges and back extending edges each in contact with the end portions of the second pair, and at least a pair of layers having side extending edges each in contact with the end portions of the first pair, the method according to claim 17.

23. The method according to claim 17, further comprising the step of attaching a first lead wire and a second lead wire to the end portions of the first pair respectively, and the step of attaching a third lead wire to at least one of the end portions of the second pair.

24. The method according to claim 23, further comprising the step of stacking a discrete varistor having a pair of external end portions on the device, wherein the first lead wire and the second lead wire are respectively attached to the external end portions of the pair of the varistor, and thus the device and the discrete varistor are connected in parallel.

Images