Driving circuit and semiconductor device

Abstract

To provide a novel semiconductor device.SOLUTION: A first terminal of a first transistor is connected to a first terminal of a second transistor, a first terminal of a third transistor, a first terminal of a first capacitor element, and a first terminal of a second capacitor element. A gate of the first transistor is connected to a second terminal of the first capacitor element. A second terminal of the third transistor is connected to a first terminal of a fourth transistor and a gate of the fourth transistor. A gate of the third transistor is connected to a second terminal of the fourth transistor, a first terminal of a fifth transistor, and a second terminal of the second capacitor element. A gate of the fifth transistor is connected to a second terminal of the first transistor and the gate of the first transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a drive circuit and a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an article, a method, a driving method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, an optical device, an imaging device, a lighting device, a projection device, an electro-optical device, a light-receiving device, a detection device, a power supply device, a communication device, an information processing device, an arithmetic device, a control device, a storage device, an input device, an output device, an input / output device, a signal processing device, an arithmetic processing device, an electronic computer, an electronic device, a system having them, a driving method thereof, or a manufacturing method thereof.

Background Art

[0003] Display devices are applied to various uses. Examples of uses of large display devices include home television sets and PIDs (Public Information Displays) for digital signage. Examples of uses of small display devices include portable information terminals such as smartphones and tablet terminals, wearable devices such as devices for VR (Virtual Reality) and AR (Augmented Reality), and the like. In addition, by adding functions other than display to the display device, higher functionality and higher added value of the display device are achieved. For example, display devices having a touch panel function have been developed.

[0004] In addition, circuits for driving display devices have been developed. Patent Document 1 discloses an example of a drive circuit that can be used for a display device.

Prior Art Documents

Patent Document

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] An active matrix type display device includes a drive circuit (which may be referred to as a gate driver) for selecting pixels to which data is to be written, and a drive circuit (which may be referred to as a source driver) for supplying data to the selected pixels.

[0007] With the increasing functionality and added value of display devices, there is also a demand for the high functionality and added value of drive circuits. For example, not only is it required to drive the pixels arranged in a matrix one row at a time in order, but also a function to drive all rows simultaneously is required.

[0008] One aspect of the present invention is to provide a drive circuit with increased operating speed or a semiconductor device having such a drive circuit as one of the problems. Or, one aspect of the present invention is to provide a drive circuit with reduced power consumption or a semiconductor device having such a drive circuit as one of the problems. Or, one aspect of the present invention is to provide a drive circuit with reduced occupied area or a semiconductor device having such a drive circuit as one of the problems. Or, one aspect of the present invention is to provide a highly reliable drive circuit or a semiconductor device having such a drive circuit as one of the problems. Or, one aspect of the present invention is to provide a drive circuit capable of enhancing the performance of a display device or a semiconductor device having such a drive circuit as one of the problems. Or, one aspect of the present invention is to provide a drive circuit capable of enhancing the performance of an imaging device or a semiconductor device having such a drive circuit as one of the problems. Or, one aspect of the present invention is to provide a novel drive circuit or a semiconductor device having such a drive circuit as one of the problems.

[0009] Note that the above problems do not prevent the existence of other problems. A person skilled in the art can naturally derive other problems from the descriptions in this specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in this specification, drawings, claims, etc. Note that one aspect of the present invention does not need to solve all of these problems (the above problems and other problems).

Means for Solving the Problems

[0010] (1) One aspect of the present invention has a first circuit and a second circuit. The first circuit has a first transistor, a second transistor, and a first capacitive element. The second circuit has a third transistor, a fourth transistor, a fifth transistor, and a second capacitive element. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor, the first terminal of the third transistor, the first terminal of the first capacitive element, the first terminal of the second capacitive element, and a first signal line. The second terminal of the first transistor is electrically connected to a second signal line. The gate of the first transistor is electrically connected to the second terminal of the first capacitive element and a first wiring. The second terminal of the second transistor is electrically connected to a second wiring. The gate of the second transistor is electrically connected to a third wiring. The second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor, the gate of the fourth transistor, and a third signal line. The gate of the third transistor is electrically connected to the second terminal of the fourth transistor, the first terminal of the fifth transistor, and the second terminal of the second capacitive element. The second terminal of the fifth transistor is electrically connected to a fourth wiring. The gate of the fifth transistor is electrically connected to the second signal line or the gate of the first transistor, and it is a drive circuit.

[0011] (2) Also, in the above (1), the gate of the fifth transistor may be electrically connected to the second signal line.

[0012] (3) Further, in the above (1), the gate of the fifth transistor may be electrically connected to the gate of the first transistor.

[0013] (4) Further, in the above (2), the first circuit may have a function of supplying a first potential from the second signal line to the first signal line, and the second circuit may have a function of supplying a second potential from the third signal line to the first signal line in a period different from the period of supplying the first potential.

[0014] (5) Further, in the above (3), the first circuit may have a function of supplying a first potential from the second signal line to the first signal line, and the second circuit may have a function of supplying a second potential from the third signal line to the first signal line in a period different from the period of supplying the first potential.

[0015] (6) Further, in any one of the above (1) to (5), the channel width of the third transistor may be larger than the channel width of the fourth transistor.

[0016] (7) Further, in any one of the above (1) to (5), the channel width of the first transistor may be larger than the channel width of the fifth transistor.

[0017] (8) Further, in any one of the above (1) to (5), the width of the third signal line may be larger than the width of the second signal line.

[0018] (9) Also, one aspect of the present invention includes the drive circuit described in the above (4) or (5) and a pixel. The pixel includes a sixth transistor and a functional element. The gate of the sixth transistor is electrically connected to the first signal line, the first terminal of the sixth transistor is electrically connected to the functional element, the second terminal of the sixth transistor is electrically connected to the fourth signal line, and each of the first potential and the second potential is a potential capable of turning on the sixth transistor. It is a semiconductor device.

[0019] (10) Also, in the above (9), the functional element may be a liquid crystal element.

[0020] (11) One aspect of the present invention has m (m is an integer of 2 or more) first circuits and m second circuits. Each of the m first circuits has a first transistor, a second transistor, and a first capacitor element. Each of the m second circuits has a third transistor, a fourth transistor, a fifth transistor, and a second capacitor element. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor, the first terminal of the third transistor, the first terminal of the first capacitor element, the first terminal of the second capacitor element, and the first signal line. The second terminal of the first transistor is electrically connected to the second signal line. The gate of the first transistor is electrically connected to the second terminal of the first capacitor element and the first wiring. The second terminal of the second transistor is electrically connected to the second wiring. The gate of the second transistor is electrically connected to the third wiring. The second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor, the gate of the fourth transistor, and the third signal line. The gate of the third transistor is electrically connected to the second terminal of the fourth transistor, the first terminal of the fifth transistor, and the second terminal of the second capacitor element. The second terminal of the fifth transistor is electrically connected to the fourth wiring. The gate of the fifth transistor is electrically connected to the second signal line or the gate of the first transistor. The m first circuits have a function of sequentially supplying a first potential from the second signal line electrically connected to each of the m first circuits to m first signal lines electrically connected to each of the m first circuits. The m second circuits have a function of simultaneously supplying a second potential from the third signal line electrically connected to the m first circuits to the m first signal lines electrically connected to each of the m first circuits in a period different from the period of sequentially supplying the first potential. It is a drive circuit.

[0021] (12) Also, in the above (11), the gate of the fifth transistor may be electrically connected to the second signal line.

[0022] (13) Also, in the above (11), the gate of the fifth transistor may be electrically connected to the gate of the first transistor.

[0023] (14) Also, in any one of the above (11) to the above (13), the channel width of the third transistor may be larger than the channel width of the fourth transistor.

[0024] (15) Also, in any one of the above (11) to the above (13), the channel width of the first transistor may be larger than the channel width of the fifth transistor.

[0025] (16) Also, in any one of the above (11) to the above (13), the width of the third signal line may be larger than the width of the second signal line.

[0026] (17) Also, one aspect of the present invention has the drive circuit described in any one of the above (11) to the above (13) and m pixels, and each of the m pixels has a sixth transistor and a functional element. The gate of the sixth transistor is electrically connected to the first signal line, the first terminal of the sixth transistor is electrically connected to the functional element, the second terminal of the sixth transistor is electrically connected to the fourth signal line, and each of the first potential and the second potential is a potential capable of turning on the sixth transistor, which is a semiconductor device.

[0027] (18) Also, in the above (17), the functional element may be a liquid crystal element.

Effects of the Invention

[0028] According to one aspect of the present invention, a drive circuit with increased operating speed or a semiconductor device having the drive circuit can be provided. Or, according to one aspect of the present invention, a drive circuit with reduced power consumption or a semiconductor device having the drive circuit can be provided. Or, according to one aspect of the present invention, a drive circuit with reduced occupied area or a semiconductor device having the drive circuit can be provided. Or, according to one aspect of the present invention, a highly reliable drive circuit or a semiconductor device having the drive circuit can be provided. Or, according to one aspect of the present invention, a drive circuit capable of enhancing the performance of a display device or a semiconductor device having the drive circuit can be provided. Or, according to one aspect of the present invention, a drive circuit capable of enhancing the performance of an imaging device or a semiconductor device having the drive circuit can be provided. Or, according to one aspect of the present invention, a novel drive circuit or a semiconductor device having the drive circuit can be provided.

[0029] Note that the above effects do not prevent the existence of other effects. A person skilled in the art can naturally derive other effects from the descriptions in this specification, drawings, claims, etc., and it is possible to extract other effects from the descriptions in this specification, drawings, claims, etc. Note that one aspect of the present invention does not necessarily have all of these effects (the above effects and other effects).

Brief Description of the Drawings

[0030]

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DETAILED DESCRIPTION OF THE INVENTION

[0031] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics. For example, it refers to a circuit including semiconductor elements (such as transistors or diodes), or a device having such a circuit. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an electronic circuit including semiconductor elements, a chip equipped with an electronic circuit, an electronic component in which a chip is housed in a package, or an electronic device in which an electronic component is mounted is an example of a semiconductor device. Also, for example, a display device, a light-emitting device, a power storage device, an optical device, an imaging device, a lighting device, a projection device, an electro-optical device, a light-receiving device, a detection device, a power supply device, a communication device, an information processing device, an arithmetic device, a control device, a storage device, an input device, an output device, an input / output device, a signal processing device, an arithmetic processing device, an electronic computer, or an electronic device, etc., is itself a semiconductor device and may have a semiconductor device.

[0032] Embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different forms. Therefore, it is easily understood by those skilled in the art that the embodiments and their details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0033] Also, in this specification and the like, it is possible to combine the configurations shown in each embodiment with the configurations shown in other embodiments as appropriate to form an aspect of the present invention. Also, when a plurality of configurations are shown in one embodiment, it is possible to combine those configurations as appropriate to form an aspect of the present invention.

[0034] In the drawings for explaining the embodiments, in the configuration of the invention, the same reference numerals may be commonly used between different drawings for the same part or parts having similar functions, and the repeated description thereof may be omitted. Also, in the drawings, when referring to similar functions, for example, the hatching patterns may be the same, and there may be no particular reference numerals. Also, for ease of understanding, in the drawings, for example, in perspective views or top views (also referred to as "plan views"), the description of some components may be omitted. Also, in the drawings, for example, the description of some hidden lines may be omitted. Also, in the drawings, for example, the description of hatching patterns and the like may be omitted.

[0035] Also, in the drawings, the size, layer thickness, or area, etc. may be exaggerated for clarity. Therefore, the drawings are not limited, for example, to their size or aspect ratio. Note that the drawings are schematically shown to assist in understanding the present invention and are not limited to, for example, the shapes or values shown in the drawings. For example, in an actual manufacturing process, due to processes such as etching, layers or resist masks may unintentionally become thinner, but for ease of understanding, these may not be reflected in the drawings. Also, for example, in an actual circuit operation, variations in voltage or current may occur due to noise or timing deviations, etc., but for ease of understanding, these may not be reflected in the drawings.

[0036] Also, in this specification, the drawings, etc., components may be classified according to function and shown as independent elements from each other. However, it may be difficult to separate components by function, and there may be cases where a single element is related to multiple functions, or a single function is related to multiple elements. Therefore, the elements shown in this specification and the drawings, etc. are not limited to their description and may be appropriately rephrased in some cases.

[0037] In addition, in this specification, drawings, etc., when the same reference numerals are used for a plurality of elements, especially when it is necessary to distinguish them, the reference numerals may be described with identification symbols such as "A", "b", "_1", "[n]", or "[m,n]". Also, when describing matters common to a plurality of elements with identification symbols, or when it is not necessary to distinguish them, they may be described without the identification symbols.

[0038] In this specification, etc., the "conductive state" or "on state" of a transistor means, for example, a state in which the source and drain of the transistor can be considered to be electrically short-circuited, or a state in which a current can flow between the source and drain (also referred to as a state in which a current can flow). For example, in an n-channel transistor, a state in which the voltage between the gate and the source is higher than the threshold voltage, or in a p-channel transistor, a state in which the voltage between the gate and the source is lower than the threshold voltage, etc. may be referred to as the "conductive state" or "on state". Also, the "non-conductive state", "cut-off state", or "off state" of a transistor means a state in which the source and drain of the transistor can be considered to be electrically cut off. For example, in an n-channel transistor, a state in which the voltage between the gate and the source is lower than the threshold voltage, or in a p-channel transistor, a state in which the voltage between the gate and the source is higher than the threshold voltage, etc. may be referred to as the "non-conductive state", "cut-off state", or "off state".

[0039] In this specification and the like, the voltage between the gate and the source (between the gate and the source, with the potential of the source as the reference unless otherwise specified) is referred to as the "gate voltage", the voltage between the drain and the source (between the drain and the source, with the potential of the source as the reference unless otherwise specified) is referred to as the "drain voltage", and the voltage between the back gate and the source (between the back gate and the source, with the potential of the source as the reference unless otherwise specified) may be referred to as the "back gate voltage". Also, the current flowing between the drain and the source (with the direction from the drain to the source as positive unless otherwise specified) may be referred to as the "drain current". In an n-channel transistor, descriptions such as a high gate voltage, a high drain voltage, and a high back gate voltage, and in a p-channel transistor, descriptions such as a low gate voltage, a low drain voltage, and a low back gate voltage can be appropriately interchanged with each other. Also, in an n-channel transistor, descriptions such as a low gate voltage, a low drain voltage, and a low back gate voltage, and in a p-channel transistor, descriptions such as a high gate voltage, a high drain voltage, and a high back gate voltage can be appropriately interchanged with each other.

[0040] In this specification and the like, the "off-current" of a transistor refers to the drain current when the transistor is in the off state, unless otherwise specified. In this specification and the like, the off-current and the current flowing between the gate and the source and the drain (also referred to as the gate leakage current) may be collectively referred to as the leakage current.

[0041] In addition, in this specification and the like, one of the source or drain of a transistor (also referred to as two input / output terminals) may be referred to as the first terminal, and the other of the source or drain of the transistor may be referred to as the second terminal. That is, a transistor has at least a gate (also referred to as a gate terminal), a first terminal, and a second terminal. Also, one terminal of a capacitive element (also referred to as one of a pair of terminals) may be referred to as the first terminal, and the other terminal of the capacitive element (also referred to as the other of a pair of terminals) may be referred to as the second terminal. Also, one terminal of a display element may be referred to as the first terminal, and the other terminal of the display element may be referred to as the second terminal. Also, one terminal of a liquid crystal element may be referred to as the first terminal, and the other terminal of the liquid crystal element may be referred to as the second terminal. Also, one terminal of a light-emitting element may be referred to as the first terminal, and the other terminal of the light-emitting element may be referred to as the second terminal. Also, one terminal of a light-receiving element may be referred to as the first terminal, and the other terminal of the light-receiving element may be referred to as the second terminal. Also, one of the anode or cathode of a diode (also referred to as one of a pair of terminals) may be referred to as the first terminal, and the other of the anode or cathode of the diode (also referred to as the other of a pair of terminals) may be referred to as the second terminal.

[0042] (Embodiment 1) A drive circuit according to an aspect of the present invention will be described with reference to the drawings. At least a part of the drive circuit according to an aspect of the present invention can be used in semiconductor devices such as a display device and an imaging device.

[0043] <Configuration Example of Drive Circuit> FIG. 1 is a circuit diagram for explaining a drive circuit according to an aspect of the present invention.

[0044] As shown in FIG. 1, the drive circuit 100 has a first circuit 110 and a second circuit 120. The first circuit 110 has transistors Mg1 and Mg2. Also, it may have a capacitive element Cg1. The second circuit 120 has transistors Mb1, Mb2, and Mb3. Also, it may have a capacitive element Cb1.

[0045] In the drive circuit 100, each transistor (transistors Mg1, Mg2, Mb1, Mb2, and Mb3) is an n-channel transistor or a p-channel transistor. Here, it will be described assuming that each transistor is an n-channel transistor. An n-channel transistor has a larger on-current than a p-channel transistor. Therefore, by using an n-channel transistor, the operating speed of the drive circuit 100 can be improved. Also, an n-channel transistor has a smaller channel width required to obtain the same on-current compared to a p-channel transistor. Therefore, by using an n-channel transistor, the occupied area of the drive circuit 100 can be reduced.

[0046] Note that when using p-channel transistors for each transistor, in the following description, descriptions regarding the positive-negative relationship of voltages and the magnitude relationship of potentials may be appropriately rewritten. For example, "the potential is large" may be appropriately rewritten as "the potential is small", and "the potential is small" may be appropriately rewritten as "the potential is large". Also, for example, "raising the potential" may be appropriately rewritten as "lowering the potential", and "lowering the potential" may be appropriately rewritten as "raising the potential".

[0047] As shown in FIG. 1, one of the source or drain of transistor Mg1 is connected to one of the source or drain of transistor Mg2, one of the source or drain of transistor Mb1, one terminal of capacitor element Cg1, one terminal of capacitor element Cb1, and wiring OL. The other of the source or drain of transistor Mg1 is connected to the gate of transistor Mb3 and wiring CKL. The gate of transistor Mg1 is connected to the other terminal of capacitor element Cg1 and wiring NLg1. The other of the source or drain of transistor Mg2 is connected to wiring VLS1. The gate of transistor Mg2 is connected to wiring NLg2. The other of the source or drain of transistor Mb1 is connected to one of the source or drain of transistor Mb2, the gate of transistor Mb2, and wiring BKL. The gate of transistor Mb1 is connected to the other of the source or drain of transistor Mb2, one of the source or drain of transistor Mb3, and the other terminal of capacitor element Cb1. The other of the source or drain of transistor Mb3 is connected to wiring VLS2.

[0048] Note that one aspect of the present invention includes a configuration in which at least one of the gates, sources, and drains of one or more transistors is not connected to anything or is connected to arbitrary wiring. Also, one aspect of the present invention includes a configuration in which nothing is input to one or more wirings, or an arbitrary signal or potential is input.

[0049] In the drive circuit 100, the first circuit 110 has a function of supplying an arbitrary potential from the wiring CKL to the wiring OL. For example, when the transistor Mg1 is in the on state, the potential H applied to the wiring CKL (here, the potential that can turn on the transistor by supplying it to the gate of the transistor) can be transmitted to the wiring OL via the transistor Mg1. At this time, by floating the wiring NLg1 and making the capacitive element Cg1 function as a bootstrap capacitor, the voltage between the gate and the source of the transistor Mg1 (hereinafter sometimes simply referred to as the gate voltage) is maintained. Therefore, for example, when the potential of the wiring OL rises, the potential of the wiring NLg1 also rises. As a result, the potential H can be transmitted without a potential drop due to the threshold voltage of the transistor Mg1. In addition, the time (rise time) for the potential of the wiring OL to reach the potential H can be shortened. Note that the capacitive element Cg1 may be a parasitic capacitance between the wiring NLg1 and the wiring OL.

[0050] Further, the first circuit 110 has a function of supplying an arbitrary potential from the wiring VLS1 to the wiring OL. For example, when the transistor Mg2 is in the on state, the potential L applied to the wiring VLS1 (here, the potential that can turn off the transistor by supplying it to the gate of the transistor) can be transmitted to the wiring OL via the transistor Mg2.

[0051] In addition, the second circuit 120 has a function of supplying an arbitrary potential from the wiring BKL to the wiring OL. For example, the potential H applied to the wiring BKL can be transmitted to the wiring OL via the transistor Mb1. At this time, by floating the wiring NLb1 and making the capacitive element Cb1 function as a bootstrap capacitor, the gate voltage of the transistor Mb1 is maintained. Therefore, for example, when the potential of the wiring OL rises, the potential of the wiring NLb1 also rises. As a result, the potential H can be transmitted without a potential drop due to the threshold voltage of the transistor Mb1. In addition, the time (rise time) for the potential of the wiring OL to reach the potential H can be shortened. Note that the capacitive element Cb1 may be a parasitic capacitance between the wiring NLb1 and the wiring OL.

[0052] Note that one of the source or drain of the transistor Mg1 and one of the source or drain of the transistor Mg2 can be said to correspond to the output of the first circuit 110. Also, one of the source or drain of the transistor Mb1 can be said to correspond to the output of the second circuit 120.

[0053] In this specification and the like, for the sake of easy understanding, the potential applied to each wiring is set as the potential L or the potential H, but different potentials may be applied to each wiring.

[0054] Here, in the operation of the drive circuit 100, it is preferable that the supply of the high potential from the wiring CKL to the wiring OL by the first circuit 110, the supply of the low potential from the wiring VLS1 to the wiring OL by the first circuit 110, and the supply of the high potential from the wiring BKL to the wiring OL by the second circuit 120 are each performed in different periods. That is, it can be said that the first circuit 110 has a function of supplying a high potential from the wiring CKL to the wiring OL and a function of supplying a low potential from the wiring VLS1 to the wiring OL in a period different from the period of supplying a high potential from the wiring BKL to the wiring OL. Further, it can be said that the second circuit 120 has a function of supplying a high potential from the wiring BKL to the wiring OL in a period different from both the period of supplying a high potential from the wiring CKL to the wiring OL and the period of supplying a low potential from the wiring VLS1 to the wiring OL.

[0055] At this time, in the drive circuit 100 according to one aspect of the present invention, when the supply of the high potential from the wiring CKL to the wiring OL by the first circuit 110 is performed, it is preferable that the transistor Mb3 is turned on, so that a low potential is supplied from the wiring VLS2 to the wiring NLb1. Thereby, the capacitive element Cb1 functions as a bootstrap capacitor, and it is possible to prevent the transistor Mb1 from being turned on and the wiring OL and the wiring BKL from being in a conductive state.

[0056] Here, in the drive circuit 100, it is preferable that the on-currents of the transistors Mg1, Mg2, and Mb1 are each larger than the on-currents of the transistors Mb2 and Mb3. For this purpose, for example, the channel widths of the transistors Mg1, Mg2, and Mb1 may be larger than the channel widths of the transistors Mb2 and Mb3, respectively. Also, the channel lengths of the transistors Mg1, Mg2, and Mb1 may be smaller than the channel lengths of the transistors Mb2 and Mb3, respectively.

[0057] For example, by increasing the on-currents of transistor Mg1, transistor Mg2, and transistor Mb1 respectively, it is possible to shorten the time required when changing the potential of wiring OL (i.e., the rise time and the fall time). Therefore, the operating speed can be improved.

[0058] Also, for example, the channel widths of transistor Mb2 and transistor Mb3 may be reduced respectively. Thereby, the occupied area of the transistor can be reduced, and miniaturization can be achieved.

[0059] Note that in one aspect of the present invention, as the transistors constituting the drive circuit 100, for example, transistors including single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor in the channel formation region can be used. Further, as the semiconductor, it is not limited to a simple semiconductor (e.g., silicon or germanium) whose main component is composed of a single element, and for example, compound semiconductors (e.g., silicon germanium or gallium arsenide) or oxide semiconductors can be used.

[0060] For example, as the transistors constituting the drive circuit 100, transistors including silicon in the channel formation region (Si transistors) may be used, transistors including oxide semiconductor in the channel formation region (OS transistors) may be used, or both Si transistors and OS transistors may be used.

[0061] Also, as the transistors constituting the drive circuit 100, various types of transistors can be used. For example, MOS field-effect transistors, junction field-effect transistors, or bipolar transistors can be used.

[0062] In addition, as the transistors constituting the drive circuit 100, transistors with various structures can be used. For example, top-gate types (e.g., planar type, staggered type, etc.), bottom-gate types (e.g., inverse planar type, inverse staggered type, etc.), dual-gate types (a structure in which gates are arranged on both sides (e.g., top and bottom) sandwiching the channel formation region), FIN types (fin type), TRI-GATE types (trigate type), and GAA types (gate-all-around type), etc., transistors with various structures can be used. Also, for example, vertical transistors (transistors having a component in which the channel length direction is the vertical direction (also referred to as the height direction or the direction perpendicular to the formation surface)) can be used.

[0063] Note that a configuration example of the transistor applicable to the drive circuit 100 will be described in Embodiment 2 to be described later.

[0064] 〔Specific Example〕 FIG. 2(A) and FIG. 2(B) are circuit diagrams for explaining a specific configuration example of the first circuit 110 included in the drive circuit 100.

[0065] In FIG. 2(A), as a configuration example of the first circuit 110, a configuration in which the transistors Mg1, Mg2, and the capacitor element Cg1 shown in FIG. 1 are connected to each other is taken as a buffer unit 111, and in addition, a register unit 112 is illustrated. That is, as an example, it can be said that the first circuit 110 has a buffer unit 111 and a register unit 112.

[0066] The register unit 112 has a function of applying an arbitrary potential to each of the wirings NLg1 and NLg2 according to the potentials applied to the wirings IL1, IL2, and IL3, and a function of floating each of the wirings NLg1 and NLg2. For example, by applying a potential H to the wiring IL1, it has a function of setting the wiring NLg1 to the potential H and the wiring NLg2 to the potential L. Thereby, the transistor Mg1 can be turned on and the transistor Mg2 can be turned off. Also, for example, by applying a potential H to the wiring IL2, it has a function of setting the wiring NLg1 to the potential L and the wiring NLg2 to the potential H. Thereby, the transistor Mg1 can be turned off and the transistor Mg2 can be turned on. Also, for example, by applying a potential H to the wiring IL3, it has a function of setting each of the wirings NLg1 and NLg2 to the potential L. Thereby, each of the transistors Mg1 and Mg2 can be turned off. Also, for example, by applying a potential L to each of the wirings IL1, IL2, and IL3, it has a function of floating each of the wirings NLg1 and NLg2.

[0067] FIG. 2(B) illustrates, as a configuration example of the register unit 112, a transistor Mga1, a transistor Mga2, a transistor Mga3, a transistor Mga4, a transistor Mga5, and a transistor Mga6. That is, as an example, it can be said that the register unit 112 includes a transistor Mga1, a transistor Mga2, a transistor Mga3, a transistor Mga4, a transistor Mga5, and a transistor Mga6.

[0068] One of the source or drain of transistor Mga1 is connected to one of the source or drain of transistor Mga3, one of the source or drain of transistor Mga5, and wiring NLg1. One of the source or drain of transistor Mga2 is connected to the gate of transistor Mga3, one of the source or drain of transistor Mga4, one of the source or drain of transistor Mga6, and wiring NLg2. The other of the source or drain of transistor Mga1 is connected to the other of the source or drain of transistor Mga2 and wiring VLD3. The other of the source or drain of transistor Mga3 is connected to the other of the source or drain of transistor Mga4, the other of the source or drain of transistor Mga5, the other of the source or drain of transistor Mga6, and wiring VLS3. The gate of transistor Mga1 is connected to the gate of transistor Mga4 and wiring IL1. The gate of transistor Mga2 is connected to wiring IL2. The gate of transistor Mga5 is connected to the gate of transistor Mga6 and wiring IL3.

[0069] In the register unit 112, for example, when a potential H is applied to the wiring IL1, the transistors Mga1 and Mga4 are turned on, and a potential H may be supplied from the wiring VLD3 to the wiring NLg1 and a potential L may be supplied from the wiring VLS3 to the wiring NLg2. As a result, the transistor Mg1 is turned on and the transistor Mg2 is turned off. Further, for example, when a potential H is applied to the wiring IL2, the transistor Mga2 is turned on, and a potential H may be supplied from the wiring VLD3 to the wiring NLg2. Furthermore, the transistor Mga3 is turned on, and a potential L may be supplied from the wiring VLS3 to the wiring NLg1. As a result, the transistor Mg1 is turned off and the transistor Mg2 is turned on. Also, for example, when a potential H is applied to the wiring IL3, the transistors Mga5 and Mga6 are each turned on, and a potential L may be supplied from the wiring VLS3 to each of the wiring NLg1 and the wiring NLg2. As a result, each of the transistors Mg1 and Mg2 is turned off. Also, for example, when a potential L is applied to each of the wiring IL1, the wiring IL2, and the wiring IL3, each of the transistors Mga1 to Mga6 is turned off, and each of the wiring NLg1 and the wiring NLg2 may become floating. At this time, each of the transistors Mg1 and Mg2 maintains its on-state or off-state.

[0070] 〔Operation Example〕 FIG. 3 is a timing chart for explaining an operation example of the drive circuit 100. FIGS. 4 to 13 are circuit diagrams for explaining an operation example of the drive circuit 100. Here, as an example, the operation of the drive circuit 100 shown in FIG. 2(A) will be described.

[0071] In the drive circuit 100, each of the wiring CKL and the wiring BKL has a function as a signal line. The potential of the signal applied to each of the wiring CKL and the wiring BKL is either the potential L (which may be simply denoted as "L") or the potential H (which may be simply denoted as "H") that is greater than the potential L. At this time, the difference between the potential H and the potential L is set to be greater than the threshold voltage of the transistor. Note that the potential L may be, for example, the ground potential.

[0072] Also, each of the wiring VLS1 and the wiring VLS2 has a function as a power supply line. Here, it is assumed that the potential L is applied to each of the wiring VLS1 and the wiring VLS2.

[0073] Note that different potentials may be applied to each of the wiring VLS1 and the wiring VLS2. Also, a signal may be applied to at least one of the wiring VLS1 and the wiring VLS2. That is, at least one of the wiring VLS1 and the wiring VLS2 can also have a function as a signal line.

[0074] Note that in the description of the operation, when the potential changes, for example, due to a load (parasitic capacitance and parasitic resistance) such as wiring, a rise time and a fall time may occur. Also, for example, even if it is shown that two different operations are at the same timing, it does not necessarily mean that they are exactly at the same timing. For example, even if there is a slight time difference due to signal delay in the wiring, etc., it may be regarded as being at the same timing.

[0075] Also, in the timing chart, for the sake of easy understanding of the explanation, even if each period is shown to have the same length on the drawing, the time lengths of each period may be different.

[0076] The timing chart shown in FIG. 3 shows the potentials applied to each of the wirings CKL, BKL, IL1, IL2, and IL3 during each period of operation. It also shows the changes in the potentials of each of the wirings NLg1, NLg2, and NLb1. Further, for the outputs of the first circuit 110 (indicated as "OUT(110)" in the drawing) and the second circuit 120 (indicated as "OUT(120)" in the drawing), it shows the potential H, potential L, or high impedance (indicated as "Hi-Z" in the drawing). It also shows the change in the potential of the wiring OL.

[0077] Also, in each of FIGS. 4 to 13, it shows the potential of each of the wirings CKL, BKL, IL1, IL2, IL3, VLS1, VLS2, NLg1, NLg2, NLb1, and OL at each point in time of the operation. At that time, adjacent to each wiring, a symbol indicating a potential such as "H" or "L" (also referred to as a potential symbol) may be marked with a character with a surrounding line. In particular, when a potential change occurs, the surrounding line may be marked thickly, and when it becomes floating, the surrounding line may be marked with a dotted line. Also, an "×" symbol may be attached on top of a transistor in the off state. Further, a broken line arrow indicating the direction in which current flows (which can also be said to be the direction in which positive charges move) may be attached along each wiring.

[0078] Also, for the sake of easy understanding of the explanation, when the potential changes due to the capacitive coupling of the capacitive element, there may be cases where the explanation is given without considering the influence of the parasitic capacitance.

[0079] In period T10 (periods T11 to T16), either the potential L or the potential H is applied to the wiring OL by the first circuit 110. In period T20 (periods T21 to T23), either the potential L or the potential H is applied to the wiring OL by the second circuit 120.

[0080] During period T11, a potential H is applied to wiring CKL, and a potential L is applied to wiring BKL. Therefore, transistor Mb2 is in the off state, and transistor Mb3 is in the on state. Thus, the potential of wiring NLb1 is potential L, and transistor Mb1 is in the off state. Also, a potential L is applied to each of wiring IL1, wiring IL2, and wiring IL3. Therefore, each of wiring NLg1 and wiring NLg2 is floating. At this time, assume that the potential of wiring NLg1 is potential L and the potential of wiring NLg2 is potential H. Therefore, transistor Mg1 is in the off state, and transistor Mg2 is in the on state. Thus, the potential of wiring OL is potential L. The potentials of each wiring at this time are shown in FIG. 4. In the following description, unless otherwise specified, it is assumed that the immediately preceding state is maintained.

[0081] During period T12, a potential L is applied to wiring CKL. Then, transistor Mb3 turns off, and wiring NLb1 becomes floating. At this time, the potential of wiring NLb1 is potential L, and transistor Mb1 remains in the off state. Also, a potential H is applied to wiring IL1. Thereby, the potential of wiring NLg1 becomes potential H, and the potential of wiring NLg2 becomes potential L. Therefore, transistor Mg1 turns on, and transistor Mg2 turns off. At this time, since a potential L is applied to wiring CKL, the potential of wiring OL remains potential L. The potentials of each wiring at this time are shown in FIG. 5.

[0082] During period T13, a potential H is applied to wiring CKL. Then, a current flows from wiring CKL to wiring OL via transistor Mg1, and the potential of wiring OL rises. Also, a potential L is applied to wiring IL1. As a result, wirings NLg1 and NLg2 become floating. Therefore, when the potential of wiring OL rises, due to the capacitive coupling of capacitor element Cg1, a state where "potential H - potential L" is applied as the gate voltage of transistor Mg1 (here, the voltage between the gate of transistor Mg1 and one of the source or drain) is maintained, and the potential of wiring NLg1 also rises by the same amount as the rise in the potential of wiring OL. Finally, the potential of wiring NLg1 becomes "2 × potential H - potential L (2H - L)", and the potential of wiring OL becomes potential H.

[0083] At this time, transistor Mb3 turns on, and the potential of wiring NLb1 becomes potential L. Therefore, it is possible to prevent the potential of wiring NLb1 from rising due to the capacitive coupling of capacitor element Cb1 and transistor Mb1 from turning on. Thus, by maintaining the off state of transistor Mb1, it is possible to prevent the conduction between wiring OL to which potential H is applied from wiring CKL via transistor Mg1 and wiring BKL to which potential L is applied. The potentials of each wiring at this time are shown in FIG. 6.

[0084] Note that the timing at which the potential of wiring CKL becomes potential H is earlier than the timing at which the potential of wiring OL becomes potential H due to the influence of the load of wiring OL. By connecting such wiring CKL to the gate of transistor Mb3, after turning on transistor Mb3, the potential of wiring OL can be made potential H. Therefore, it is possible to prevent wiring OL from becoming potential H before transistor Mb3 turns on.

[0085] At this time, it is preferable that the gate capacitance of transistor Mb3 is small so that transistor Mb3 turns on before the potential of wiring OL becomes potential H. For example, it is preferable that the gate capacitance of transistor Mb3 is smaller than the gate capacitance of transistor Mg1. For example, it is preferable that the channel area (i.e., channel length × channel width) of transistor Mb3 is smaller than the channel area of transistor Mg1. For example, it is preferable that the channel length of transistor Mb3 is smaller than the channel length of transistor Mg1. For example, it is preferable that the channel width of transistor Mb3 is smaller than the channel width of transistor Mg1. Thereby, the operation can be stabilized.

[0086] During period T14, potential L is applied to wiring CKL. Then, transistor Mb3 turns off and wiring NLb1 becomes floating. At this time, the potential of wiring NLb1 is potential L and transistor Mb1 remains off. Also, potential H is applied to wiring IL2. Thereby, the potential of wiring NLg1 becomes potential L and the potential of wiring NLg2 becomes potential H. Therefore, transistor Mg1 turns off and transistor Mg2 turns on. Then, current flows from wiring OL to wiring VLS1 through transistor Mg2, and the potential of wiring OL decreases. Thus, the potential of wiring OL becomes potential L. The potentials of the respective wirings at this time are shown in FIG. 7.

[0087] During period T15, potential H is applied to wiring CKL. Then, transistor Mb3 turns on and the potential of wiring NLb1 becomes potential L. Thus, transistor Mb1 remains off. Also, potential L is applied to wiring IL2. Thereby, wiring NLg1 and wiring NLg2 become floating. Then, transistor Mg1 remains off and transistor Mg2 remains on. Thus, the potential of wiring OL remains at potential L. The potentials of the respective wirings at this time are shown in FIG. 8.

[0088] During period T16, potential L is applied to wiring CKL. Then, transistor Mb3 turns off and wiring NLb1 becomes floating. At this time, the potential of wiring NLb1 is potential L, and transistor Mb1 remains in the off state. Also, transistor Mg1 remains in the off state and transistor Mg2 remains in the on state. Therefore, the potential of wiring OL remains at potential L. The potentials of each wiring at this time are shown in FIG. 9.

[0089] During period T21, potential H is applied to wiring IL3. As a result, the potentials of each of wiring NLg1 and wiring NLg2 become potential L. Then, each of transistor Mg1 and transistor Mg2 turns off and wiring OL becomes floating. At this time, the potential of wiring OL remains at potential L. The potentials of each wiring at this time are shown in FIG. 10.

[0090] During period T22, potential H is applied to wiring BKL. Then, first, current flows from wiring BKL to wiring NLb1 through transistor Mb2, and the potential of wiring NLb1 becomes potential H. Thereby, transistor Mb1 turns on. Note that the potential of wiring NLb1 is "potential H - threshold voltage of transistor Mb2", but here, for simplicity of explanation, the threshold voltage of transistor Mb2 is set to 0V. The potentials of each wiring at this time are shown in FIG. 11.

[0091] Thereafter, current flows from wiring BKL to wiring OL through transistor Mb1, and the potential of wiring OL rises. Here, in transistor Mb2, no current flows from the other of the source or drain (i.e., the terminal connected to wiring NLb1) to one of the source or drain (i.e., the terminal connected to wiring BKL). Therefore, when the potential of wiring NLb1 becomes higher than the potential of wiring BKL, wiring NLb1 becomes floating. Thus, when the potential of wiring OL rises, due to the capacitive coupling of capacitor element Cb1, the state where "potential H - potential L" is applied as the gate voltage of transistor Mb1 (here, the voltage between the gate of transistor Mb1 and one of the source or drain) is maintained, and the potential of wiring NLb1 also rises by the same amount as the rise in the potential of wiring OL. Finally, the potential of wiring NLb1 becomes "2 × potential H - potential L", and the potential of wiring OL becomes potential H. The potentials of each wiring at this time are shown in FIG. 12.

[0092] At this time, it is preferable that the gate capacitance of transistor Mb2 is small so that the potential of wiring NLb1 becomes potential H before the potential of wiring OL becomes potential H. For example, it is preferable that the gate capacitance of transistor Mb2 is smaller than the gate capacitance of transistor Mb1. For example, it is preferable that the channel area (i.e., channel length × channel width) of transistor Mb2 is smaller than the channel area of transistor Mb1. For example, it is preferable that the channel length of transistor Mb2 is smaller than the channel length of transistor Mb1. For example, it is preferable that the channel width of transistor Mb2 is smaller than the channel width of transistor Mb1. Thereby, the operation can be stabilized.

[0093] During period T23, potential L is applied to wiring BKL. Then, current flows from wiring OL to wiring BKL through transistor Mb1, and the potential of wiring OL decreases. Also, due to the capacitive coupling of capacitor element Cb1, the potential of wiring NLb1 also decreases. Thus, the potential of wiring NLb1 becomes potential H, and the potential of wiring OL becomes potential L. The potentials of each wiring at this time are shown in FIG. 13.

[0094] Here, for example, instead of the second circuit 120, the gate of the transistor Mb1 can be connected to the other of the source or drain of the transistor Mb1 and the wiring BKL without having the transistor Mb2, the transistor Mb3, and the capacitor element Cb1. However, in this case, when a potential H is applied to the wiring BKL as in the operation of the period T22, due to the voltage drop caused by the threshold voltage of the transistor Mb1, the potential of the wiring OL becomes "potential H - threshold voltage of the transistor Mb1". That is, for example, in order to make the potential of the wiring OL the potential H, it is necessary to make the potential applied to the wiring BKL "potential H + threshold voltage of the transistor Mb1". Therefore, it causes an increase in power consumption.

[0095] One aspect of the present invention has a configuration such as the second circuit 120, so that in the operation of the period T22, a potential H can be applied from the wiring BKL to the wiring OL without a voltage drop due to the threshold voltage of the transistor Mb1. Therefore, an increase in power consumption can be suppressed. Further, since the gate voltage of the transistor Mb1 is maintained, the time until the potential of the wiring OL reaches the potential H (also referred to as the rise time) can be shortened. Therefore, the operating speed can be improved.

[0096] <Another configuration example of the drive circuit> The drive circuit according to one aspect of the present invention is not limited to the above-described configuration example.

[0097] 〔Modification example 1〕 FIG. 14 is a circuit diagram for explaining a modification example of the drive circuit 100. The drive circuit 100 shown in FIG. 14 is different from the drive circuit 100 shown in FIG. 1 in that the other of the source or drain of the transistor Mg2 is connected to the other of the source or drain of the transistor Mb3 and the wiring VLS1.

[0098] By adopting such a configuration, it is not necessary to have the wiring VLS2. That is, the number of wirings can be reduced. Therefore, the occupied area of the drive circuit 100 can be reduced. Thus, for example, when the drive circuit is used in a display device or the like, the frame width can be reduced.

[0099] 〔Modification Example 2〕 FIG. 15 is a circuit diagram for explaining a modification example of the drive circuit 100. The drive circuit 100 shown in FIG. 15 is different from the drive circuit 100 shown in FIG. 1 in that in the second circuit 120, it has a capacitive element Cb2 instead of the transistor Mb3. One terminal of the capacitive element Cb2 is connected to the gate of the transistor Mb1, the other of the source or drain of the transistor Mb2, the other terminal of the capacitive element Cb1, and the wiring NLb1, and the other terminal of the capacitive element Cb2 is connected to the wiring VLS2.

[0100] In the drive circuit 100 shown in FIG. 15, the increase in the potential of the wiring NLb1 during the above-described period T13 is “the increase in the potential of the wiring OL × the capacitance of the capacitive element Cb1 / (the capacitance of the capacitive element Cb1 + the capacitance of the capacitive element Cb2)”. That is, by increasing the capacitance of the capacitive element Cb2, the increase in the potential of the wiring NLb1 during the period T13 can be reduced. At this time, for example, it is preferable to increase the capacitance of the capacitive element Cb2 so that the gate voltage of the transistor Mb1 does not exceed the threshold voltage due to the increase in the potential of the wiring NLb1. For example, by making the capacitance of the capacitive element Cb2 larger than “the capacitance of the capacitive element Cb1 × (the increase in the potential of the wiring OL / the threshold voltage of the transistor Mb1 - 1)”, it is possible to prevent the transistor Mb1 from being turned on during the period T13.

[0101] By adopting such a configuration, it is not necessary to have the transistor Mb3. Therefore, an increase in power consumption associated with repeatedly turning on and off the transistor Mb3 can be suppressed. Thus, for example, when the drive circuit is used in a display device or the like, power consumption can be reduced.

[0102] 〔Modification Example 3〕 FIG. 16 is a circuit diagram for explaining a modification example of the drive circuit 100. The drive circuit 100 shown in FIG. 16 is different from the drive circuit 100 shown in FIG. 1 in that the first circuit 110 further includes a transistor Mg3 and a transistor Mg4. One of the source or drain of the transistor Mg3 is connected to the wiring NLg1. One of the source or drain of the transistor Mg4 is connected to the wiring NLg2. The other of the source or drain of the transistor Mg3 is connected to the other of the source or drain of the transistor Mg4 and the wiring VLS1. The gate of the transistor Mg3 is connected to the gate of the transistor Mg4 and the wiring BKL.

[0103] Note that the first circuit 110 shown in FIG. 16 corresponds to a configuration in which the wiring IL3 is connected to the wiring BKL in the first circuit 110 shown in FIG. 2(B), for example. At this time, the transistor Mg3 corresponds to the transistor Mga5, and the transistor Mg4 corresponds to the transistor Mga6.

[0104] In the drive circuit 100 shown in FIG. 16, when a potential H is supplied from the wiring BKL to the wiring NLb1 via the transistor Mb2 and then a potential H is supplied from the wiring BKL to the wiring OL via the transistor Mb1, as in the above-described period T22, each of the transistors Mg3 and Mg4 is turned on. Thereby, each of the wiring NLg1 and the wiring NLg2 becomes a potential L, and each of the transistors Mg1 and Mg2 can be turned off.

[0105] At this time, due to the influence of the load of the wiring OL, after the potential of the wiring BKL becomes the potential H, the potential of the wiring OL becomes the potential H. Therefore, after turning on the transistors Mg3 and Mg4 by the potential of the wiring BKL, the potential of the wiring OL can be set to the potential H. In this way, by connecting the wiring BKL to the gates of the transistors Mg3 and Mg4, it is possible to prevent the potential of the wiring OL from becoming the potential H before the transistors Mg3 and Mg4 are turned on. Therefore, the operation can be stabilized.

[0106] In addition, in FIG. 16, the transistor Mg3 may be omitted. Alternatively, in FIG. 16, the transistor Mg4 may be omitted.

[0107] 〔Modification Example 4〕 FIG. 17 is a circuit diagram for explaining a modification example of the drive circuit 100. The drive circuit 100 shown in FIG. 17 further includes an inversion circuit 130. In the drive circuit 100 shown in FIG. 17, each of the first circuit 110 and the second circuit 120 is shown as a circuit block, and the outputs of the first circuit 110 and the second circuit 120 are connected to the wiring NLr1. Note that the wiring NLr1 corresponds to the input of the inversion circuit 130, and the wiring OL corresponds to the output of the inversion circuit 130.

[0108] The inverter circuit 130 includes a transistor Mgr1, a transistor Mgr2, a transistor Mgr3, a transistor Mgr4, and a capacitor element Cgr1. One of the source or drain of the transistor Mgr1 is connected to the gate of the transistor Mgr2, one of the source or drain of the transistor Mgr3, and one terminal of the capacitor element Cgr1. One of the source or drain of the transistor Mgr2 is connected to one of the source or drain of the transistor Mgr4, the other terminal of the capacitor element Cgr1, and the wiring OL. The other of the source or drain of the transistor Mgr1 is connected to the other of the source or drain of the transistor Mgr2 and the wiring VLDr. The other of the source or drain of the transistor Mgr3 is connected to the other of the source or drain of the transistor Mgr4 and the wiring VLSr. The gate of the transistor Mgr1 is connected to the wiring ILr1. The gate of the transistor Mgr3 is connected to the gate of the transistor Mgr4 and the wiring NLr1.

[0109] The inverter circuit 130 has a function of outputting a potential L to the wiring OL when a potential H is input to the wiring NLr1. Also, it has a function of outputting a potential H to the wiring OL when a potential L is input to the wiring NLr1.

[0110] At this time, for example, a potential H is applied to the wiring VLDr and a potential L is applied to the wiring VLSr. Also, a constant potential of potential H may be applied to the wiring ILr1, or a signal that becomes potential H at an arbitrary timing may be applied.

[0111] When a signal that becomes potential H at an arbitrary timing is applied to the wiring ILr1, a potential L may be applied to the wiring ILr1 when a potential H is applied to the wiring NLr1, and a potential H may be applied to the wiring ILr1 when a potential L is applied to the wiring NLr1.

[0112] [Modification Example 5] FIG. 18 is a circuit diagram for explaining a modified example of the first circuit 110. The first circuit 110 shown in FIG. 18 has a transistor Mga7 and is different from the first circuit 110 shown in FIG. 2(B) in that the connection related to the wiring NLg1 is different. One of the source or drain of the transistor Mga7 is connected to the gate of the transistor Mg1, one terminal of the capacitor element Cg1, and the wiring NLg1. The other of the source or drain of the transistor Mga7 is connected to one of the source or drain of the transistor Mga1, one of the source or drain of the transistor Mga3, and one of the source or drain of the transistor Mga5. The gate of the transistor Mga7 is connected to the wiring VLD3.

[0113] In the drive circuit 100 shown in FIG. 18, when the potential of the wiring NLg1 rises during the above-described period T13, the transistor Mga7 is turned off, so that the potential rise of the wiring NLg3 can be suppressed. As a result, for example, it is possible to suppress an increase in the drain voltage of each of the transistors Mga3 and Mga5 and deterioration of each transistor characteristic.

[0114] 〔Modified Example 6〕 FIG. 51 is a circuit diagram for explaining a modified example of the drive circuit 100. The drive circuit 100 shown in FIG. 51 is different from the drive circuit 100 shown in FIG. 1 in that the gate of the transistor Mb3 is connected to the gate of the transistor Mg1.

[0115] With such a configuration, since the gate of the transistor Mb3 is not connected to the wiring CKL, the load on the wiring CKL can be reduced. Therefore, the current flowing through the wiring CKL when driving the transistor Mb3 can be reduced, and the power consumption can be reduced. In addition, the wiring CKL can be made thinner to reduce the occupied area.

[0116] Also, the gate of transistor Mg1 is connected to wiring NLg1, and the potential of the wiring NLg1 becomes potential H during period T12. Therefore, transistor Mb3 is turned on during period T12. Thereafter, transistor Mb3 remains on even during period T13. In this way, after turning on transistor Mb3 during period T12, the potential of wiring OL can be set to potential H during period T13. Therefore, it is possible to sufficiently prevent wiring OL from becoming potential H before transistor Mb3 is turned on. Thus, the operation can be stabilized.

[0117] In the modification shown in FIG. 51, since it is possible to sufficiently prevent wiring OL from becoming potential H before transistor Mb3 is turned on, the gate capacitance of transistor Mb3 does not necessarily have to be smaller than the gate capacitance of transistor Mg1. However, further stabilization of the operation may be achieved by making the gate capacitance of transistor Mg3 smaller than the gate capacitance of transistor Mg1.

[0118] <Configuration example of semiconductor device> Next, a semiconductor device according to an aspect of the present invention will be described with reference to the drawings. At least a part of the drive circuit according to an aspect of the present invention can be used in the semiconductor device.

[0119] FIG. 19(A) is a block diagram for explaining a configuration example of a semiconductor device according to an aspect of the present invention.

[0120] As shown in FIG. 19(A), the semiconductor device 160 includes a pixel portion 162, a gate driver portion 163, and a source driver portion 164. The pixel portion 162 includes, for example, a plurality of pixels 161 arranged in a matrix of m rows and n columns (m is an integer of 2 or more, and n is an integer of 2 or more).

[0121] Pixel 161 can include a functional element. Here, for example, when the functional element is a display element such as a liquid crystal element and a light-emitting element, the semiconductor device 160 has a function as a display device (which may also be referred to as an output device). Further, for example, when the functional element is a light-receiving element, the semiconductor device 160 has a function as an imaging device (which may also be referred to as an input device). Note that pixel 161 may include both a display element and a light-receiving element. In this case, the semiconductor device 160 has functions as both a display device and an imaging device (which may also be referred to as an input / output device).

[0122] In FIG. 19(A), the pixel 161 arranged in the first row and first column is denoted as pixel 161[1,1], the pixel 161 arranged in the first row and nth column is denoted as pixel 161[1,n], the pixel 161 arranged in the mth row and first column is denoted as pixel 161[m,1], and the pixel 161 arranged in the mth row and nth column is denoted as pixel 161[m,n]. Note that the pixel 161 arranged in the u-th row and v-th column (u is an integer of 1 or more and m or less, and v is an integer of 1 or more and n or less) may be denoted as pixel 161[u,v]. Note that when explaining matters common to each of the plurality of pixels 161, it may be described without attaching an identification code such as “[u,v]”.

[0123] Further, the semiconductor device 160 has m gate lines 165 that are each arranged in parallel and whose potentials are controlled by circuits included in the gate driver section 163. The potential of one gate line 165 is applied to n pixels 161 arranged in the row direction. Note that, according to the configuration of pixel 161, a configuration in which a plurality of wirings are included per one gate line 165 may be employed.

[0124] Further, the semiconductor device 160 has n source lines 166 that are each arranged in parallel and whose potentials are controlled by circuits included in the source driver section 164. The potential of one source line 166 is applied to m pixels 161 arranged in the column direction. Note that, according to the configuration of pixel 161, a configuration in which a plurality of wirings are included per one source line 166 may be employed.

[0125] The circuit included in the gate driver unit 163 functions as, for example, a scanning line driving circuit (which may also be referred to as a gate line driving circuit, a gate driver, a scan driver, or a load driver).

[0126] The circuit included in the source driver unit 164 functions as, for example, a signal line driving circuit (which may also be referred to as a source line driving circuit, a source driver, a data driver, or a column driver).

[0127] In one aspect of the present invention, at least a part of the above-described driving circuit 100 can be used in the gate driver unit 163. FIG. 19(A) shows, as the gate driver unit 163, a sequential driving unit 163a including a first circuit 110 of the driving circuit 100 and a simultaneous driving unit 163b including a second circuit 120 of the driving circuit 100.

[0128] FIG. 19(B) is a circuit diagram for explaining an example of using the above-described driving circuit 100 in the gate driver unit 163.

[0129] FIG. 19(B) shows, as a representative example, a pixel 161[u, v] at the u-th row and v-th column and a driving circuit 100[u] at the u-th row.

[0130] Also, each of the first circuit 110[u] and the second circuit 120[u] included in the driving circuit 100[u] is shown as a circuit block. The output of the first circuit 110[u] and the output of the second circuit 120[u] are connected to a wiring OL[u].

[0131] Also, as an example of the pixel 161[u, v], a pixel 161[u, v] having a transistor Mpix and a functional element Elm is shown. One of the source or drain of the transistor Mpix is connected to the functional element Elm. The other of the source or drain of the transistor Mpix is connected to a wiring SL[v] corresponding to a source line 166. The gate of the transistor Mpix is connected to a wiring GL[u] corresponding to a gate line 165. Note that the wiring GL[u] is connected to the wiring OL[u].

[0132] As the functional element Elm, a liquid crystal element, a light-emitting element, a light-receiving element, or the like can be used.

[0133] 〔Configuration example of a pixel using a liquid crystal element〕 FIG. 20 is a circuit diagram for explaining an example in which a liquid crystal element LC is used as the functional element Elm.

[0134] In FIG. 20, a pixel 161A[u, v] is illustrated as the pixel 161[u, v]. The pixel 161A[u, v] includes a transistor M11 (corresponding to the transistor Mpix), a liquid crystal element LC, and a capacitive element C11.

[0135] One of the source or drain of the transistor M11 is connected to one terminal of the liquid crystal element LC, one terminal of the capacitive element C11, and a wiring NL11. The other of the source or drain of the transistor M11 is connected to a wiring SL[v]. The gate of the transistor M11 is connected to a wiring GL[u]. The other terminal of the liquid crystal element LC is connected to a wiring COM. The other terminal of the capacitive element C11 is connected to a wiring CS.

[0136] The liquid crystal element LC changes the light transmittance according to the voltage between a pair of terminals.

[0137] The transistor M11 functions as a switch for controlling whether to write a data potential to the pixel 161A[u, v]. The capacitive element C11 functions to hold the voltage between a pair of terminals.

[0138] The operations of the pixel 161A[u, v], namely, the write operation and the black scan (also referred to as blackening) operation, will be described.

[0139] In the writing operation, first, a potential H is applied to the wiring GL[u]. As a result, a data potential is applied from the wiring SL[v] to the wiring NL11. That is, a voltage corresponding to the data potential is applied across a pair of terminals of the liquid crystal element LC. Thereafter, a potential L is applied to the wiring GL[u], and the voltage is held in the capacitor element C11.

[0140] In the black scan operation, first, a potential H is applied to the wiring GL[u]. As a result, a predetermined potential is applied from the wiring SL[v] to the wiring NL11. That is, a voltage corresponding to the predetermined potential is applied across a pair of terminals of the liquid crystal element LC. Thereafter, a potential L is applied to the wiring GL[u], and the voltage is held in the capacitor element C11.

[0141] The predetermined potential is, for example, the same potential as the potential of the wiring COM. That is, 0 V is applied across a pair of terminals of the liquid crystal element LC. Thereby, the residual DC of the liquid crystal element LC can be suppressed.

[0142] Here, the residual DC refers to a voltage caused by charges remaining between electrodes (or between alignment films) when a voltage is applied to the liquid crystal layer. Due to this voltage, during the period when a voltage is applied to the liquid crystal element, an extra voltage is applied between the electrodes in addition to the originally applied voltage. Also, even during the period when no voltage is applied to the liquid crystal element, a voltage remains between the electrodes due to the charges remaining in the liquid crystal layer. When residual DC occurs, the voltage applied to the liquid crystal layer changes even after the writing of the data potential is completed, so the transmittance of the liquid crystal element also changes. Also, residual DC makes it easier for image sticking on the screen to occur.

[0143] Therefore, it is preferable to perform the black scan operation to discharge the charges remaining in the liquid crystal layer and suppress the residual DC. The black scan operation may be performed, for example, immediately before shutting down a semiconductor device (here, a liquid crystal display device).

[0144] In one aspect of the present invention, various transistors can be used as the transistor constituting pixel 161A[u, v]. For example, an OS transistor may be used.

[0145] The OS transistor has the characteristic that its off-current is extremely small. Therefore, for example, in pixel 161A[u, v], by using the OS transistor for transistor M11, the voltage applied between a pair of terminals of liquid crystal element LC can be held for a long time by a writing operation. Thus, for example, by reducing the frequency of the writing operation, power consumption can be reduced.

[0146] At this time, by reducing the frequency of the writing operation, the period during which a constant voltage is continuously applied to the liquid crystal element becomes longer, so residual DC is likely to occur. Therefore, it is preferable to perform a black scan operation to suppress the residual DC.

[0147] 〔Specific Example of Gate Driver Section〕 FIG. 21(A) is a circuit diagram for explaining an example in which a plurality of drive circuits 100 are connected to each other in gate driver section 163. FIG. 21(B) is a circuit block corresponding to the first circuit 110 shown in FIG. 21(A). FIG. 21(C) is a circuit block corresponding to the second circuit 120 shown in FIG. 21(A). FIG. 22 is a circuit diagram for explaining an example of the first circuit 110 used in the drive circuit 100 shown in FIG. 21(A).

[0148] The gate driver unit 163 has at least m drive circuits 100 (drive circuits 100[1] to 100[m]) to drive the pixels 161 arranged in an m×n matrix row by row. FIG. 21(A) illustratively shows the drive circuit 100[u−1] in the (u−1)-th row, the drive circuit 100[u] in the u-th row, and the drive circuit 100[u + 1] in the (u + 1)-th row. Also, the first circuit 110[u−1] and the second circuit 120[u−1] included in the drive circuit 100[u−1], the first circuit 110[u] and the second circuit 120[u] included in the drive circuit 100[u], and the first circuit 110[u + 1] and the second circuit 120[u + 1] included in the drive circuit 100[u + 1] are illustrated in circuit blocks. When explaining matters common to each of the m drive circuits 100, the m first circuits 110, and the m second circuits 120, etc., they may be described without attaching identification symbols such as “[u]”.

[0149] The output of the first circuit 110[u−1] and the output of the second circuit 120[u−1] are connected to the wiring OL[u−1]. The output of the first circuit 110[u] and the output of the second circuit 120[u] are connected to the wiring OL[u]. The output of the first circuit 110[u + 1] and the output of the second circuit 120[u + 1] are connected to the wiring OL[u + 1].

[0150] The wiring CKL[u−1] connected to each of the first circuit 110[u−1] and the second circuit 120[u−1] is connected to the wiring CKL2. The wiring CKL[u] connected to each of the first circuit 110[u] and the second circuit 120[u] is connected to the wiring CKL1. The wiring CKL[u + 1] connected to each of the first circuit 110[u + 1] and the second circuit 120[u + 1] is connected to the wiring CKL2.

[0151] The wiring BKL[u−1] connected to the second circuit 120[u−1] is connected to the wiring BKL0. The wiring BKL[u] connected to the second circuit 120[u] is connected to the wiring BKL0. The wiring BKL[u + 1] connected to the second circuit 120[u + 1] is connected to the wiring BKL0.

[0152] The wiring IL1[u] connected to the first circuit 110[u] is connected to the wiring SROL[u - 1] connected to the first circuit 110[u - 1]. The wiring IL2[u] connected to the first circuit 110[u] is connected to the wiring SROL[u + 1] connected to the first circuit 110[u + 1]. The wiring IL3[u] connected to the first circuit 110[u] is connected to the wiring BKL0. The wiring SROL[u] connected to the first circuit 110[u] is connected to each of the wiring IL2[u - 1] connected to the first circuit 110[u - 1] and the wiring IL1[u + 1] connected to the first circuit 110[u + 1].

[0153] The first circuit 110 shown in FIG. 22 (i.e., the first circuit 110 used in the driving circuit 100 shown in FIG. 21(A)) has, in addition to the first circuit 110 shown in FIG. 2(B), a transistor Msr1 and a transistor Msr2. One of the source or drain of the transistor Msr1 is connected to one of the source or drain of the transistor Msr2 and the wiring SROL. The other of the source or drain of the transistor Msr1 is connected to the wiring CKL. The other of the source or drain of the transistor Msr2 is connected to the wiring VLS3. The gate of the transistor Msr1 is connected to the wiring NLg1. The gate of the transistor Msr2 is connected to the wiring NLg2.

[0154] Note that in FIG. 22, either one of the other of the source or drain of the transistor Mg1 or the other of the source or drain of the transistor Msr1 may be connected to another wiring to which a signal different from the wiring CKL or a fixed potential is supplied. For example, by configuring the other of the source or drain of the transistor Mg1 to be connected to another wiring to which a signal different from the wiring CKL is supplied, the period during which the signal output from the first circuit 110 to the wiring OL becomes the potential H can be made different from the period during which the signal applied to the wiring CKL becomes the potential H.

[0155] In the configuration of the gate driver unit 163 shown in FIG. 21(A) and the like, either one of the signals applied to each of the wirings CKL1 and CKL2 is sequentially applied to each of the m wirings OL (wirings OL[1] to OL[m]) by the m first circuits 110 included in the sequential drive unit 163a. Further, the signal applied to the wiring BKL0 is simultaneously supplied to each of the m wirings OL by the m second circuits 120 included in the simultaneous drive unit 163b.

[0156] At this time, in the first circuit 110[u], a wiring SROL[u] is provided separately from the wiring OL[u], and the wiring SROL[u] is connected to the wiring IL1[u + 1] and the wiring IL2[u - 1]. Thereby, it is possible to prevent the signals simultaneously supplied to each of the m wirings OL by the m second circuits 120 from being input to each of the m wirings IL1 and the m wirings IL2, and prevent the m first circuits 110 from malfunctioning.

[0157] 〔Operation example of gate driver unit〕 FIG. 23 is a timing chart for explaining an operation example of the gate driver unit 163.

[0158] The timing chart shown in FIG. 23 shows the potentials applied to each of the wirings CKL1, CKL2, and BKL0 during each period of operation. Also, for the outputs of the first circuits 110[u-1], 110[u], 110[u+1], the second circuits 120[u-1], 120[u], and 120[u+1] (each indicated as “OUT(110[u-1])”, “OUT(110[u])”, “OUT(110[u+1])”, “OUT(120[u-1])”, “OUT(120[u])”, and “OUT(120[u+1])” in the drawing), the potential H, potential L, or high impedance (indicated as “Hi-Z” in the drawing) is shown. Further, the potential changes of the wirings SROL[u-1], SROL[u], and SROL[u+1] are shown. Note that the potential applied to the wiring IL1[u] corresponds to the potential of the wiring SROL[u-1], the potential applied to the wiring IL2[u] corresponds to the potential of the wiring SROL[u+1], and the potential applied to the wiring IL3[u] corresponds to the potential of the wiring BKL0. Also, although not shown, during the period T100, the outputs of the first circuits 110[u-1], 110[u], and 110[u+1] are applied to the wirings OL[u-1], OL[u], and OL[u+1] respectively, and during the period T200, the outputs of the second circuits 120[u-1], 120[u], and 120[u+1] are applied to the wirings OL[u-1], OL[u], and OL[u+1] respectively.

[0159] The operation of each driving circuit 100 during the period T100 corresponds to the operation of the driving circuit 100 during the period T10 shown in FIG. 3 etc. described above. The operation of each driving circuit 100 during the period T200 corresponds to the operation of the driving circuit 100 during the period T20 shown in FIG. 3 etc. described above. Therefore, since the above description can be referred to as appropriate, a detailed description may be omitted here.

[0160] As shown in FIG. 23, in period T100, signals with potential H are sequentially output from the m first circuits 110 included in the sequential drive unit 163a. That is, signals with potential H are sequentially applied to each of the m wirings OL. In period T200, signals with potential H are simultaneously output from the m second circuits 120 included in the simultaneous drive unit 163b. That is, signals with potential H are simultaneously supplied to each of the m wirings OL.

[0161] In one aspect of the present invention, in the operation of a semiconductor device using a liquid crystal element, period T100 can be a period for performing a writing operation, and period T200 can be a period for performing a black scan operation. That is, for the pixels 161A corresponding to m rows, the writing operation can be sequentially performed one row at a time by the signals output from the sequential drive unit 163a. Also, the black scan operation can be performed simultaneously for all rows by the signals output from the simultaneous drive unit 163b.

[0162] At this time, by using the drive circuit 100 in the gate driver unit 163, when performing the black scan operation, the potential H can be applied to the wiring OL without a voltage drop due to the threshold voltage of the transistor Mb1 included in the second circuit 120 included in the simultaneous drive unit 163b. Therefore, for example, since it is not necessary to apply "potential H + threshold voltage of transistor Mb1" to the wiring BKL, an increase in power consumption can be suppressed. Also, since the gate voltage of the transistor Mb1 is maintained, the time until the potential of the wiring OL reaches the potential H can be shortened. Therefore, by shortening the period for performing the black scan operation (that is, period T200), the operation speed can be improved.

[0163] <Another configuration example of the semiconductor device> The semiconductor device according to one aspect of the present invention is not limited to the above-described configuration.

[0164] 〔Configuration example of a pixel using a light-emitting element〕 FIG. 24 is a circuit diagram for explaining an example in which a light-emitting element LD is used as a functional element Elm in a pixel 161 included in the semiconductor device 160.

[0165] In FIG. 24, a pixel 161B[u, v] is illustrated as the pixel 161[u, v]. Also, as the driving circuit 100[u], a configuration having an inverter circuit 130[u] (corresponding to the driving circuit 100 shown in FIG. 17) is illustrated by circuit blocks.

[0166] The pixel 161B[u, v] includes a transistor M21, a transistor M22, a transistor M23 (corresponding to the transistor Mpix), and a light-emitting element LD. One of the source or drain of the transistor M23 is connected to one terminal of the light-emitting element LD. The other of the source or drain of the transistor M23 is connected to one of the source or drain of the transistor M22. The gate of the transistor M23 is connected to a wiring GLb[u] (corresponding to the wiring GL[u]). The other terminal of the light-emitting element LD is connected to the wiring CATH. The other of the source or drain of the transistor M22 is connected to the wiring ANO. The gate of the transistor M22 is connected to a wiring to which a potential corresponding to the potential of one of the source or drain of the transistor M21 is applied. The other of the source or drain of the transistor M21 is connected to the wiring SL[v]. The gate of the transistor M21 is connected to the wiring GLa[u].

[0167] The light-emitting element LD emits light with a light-emitting intensity corresponding to the amount of current flowing through the light-emitting element LD. As the light-emitting element LD, for example, an organic EL element can be used.

[0168] The transistor M22 can change the drain current according to the potential applied to the gate. Therefore, in the pixel 161B[u, v], the transistor M22 has a function of controlling the amount of current flowing through the light-emitting element LD. That is, the transistor M22 has a function of controlling the light-emitting intensity of the light-emitting element LD. In this specification and the like, a transistor having a function such as the transistor M22 may be referred to as a driving transistor.

[0169] Transistor M21 functions as a switch for controlling whether to write the data potential to pixel 161B[u, v]. Transistor M23 functions as a switch for controlling whether to pass a current through the light-emitting element LD.

[0170] Pixel 161B[u, v] can be configured to have a function of correcting the threshold voltage variation of the driving transistor (also referred to as having an internal correction circuit).

[0171] FIG. 25 is a circuit diagram for explaining a specific configuration example of pixel 161B[u, v] having an internal correction circuit.

[0172] Pixel 161BA shown in FIG. 25 includes transistor M21, transistor M22, transistor M23, light-emitting element LD, in addition to transistor M24, transistor M25, transistor M26, capacitor element C21, and capacitor element C22.

[0173] One of the source or drain of transistor M23 is connected to one terminal of light-emitting element LD. The other of the source or drain of transistor M23 is connected to one of the source or drain of transistor M22, one of the source or drain of transistor M24, one of the source or drain of transistor M26, one terminal of capacitor element C21, and wiring NL21. The gate of transistor M23 is connected to wiring GLb. The other terminal of light-emitting element LD is connected to wiring CATH. The other of the source or drain of transistor M22 is connected to wiring ANO. The gate of transistor M22 is connected to one of the source or drain of transistor M25, one terminal of capacitor element C22, and wiring NL22. The other terminal of capacitor element C22 is connected to one of the source or drain of transistor M21, the other of the source or drain of transistor M26, the other terminal of capacitor element C21, and wiring NL23. The other of the source or drain of transistor M21 is connected to wiring SL. The gate of transistor M21 is connected to the gate of transistor M24 and wiring GLa. The other of the source or drain of transistor M24 is connected to wiring VL0. The other of the source or drain of transistor M25 is connected to wiring VL1. The gate of transistor M25 is connected to the gate of transistor M26 and wiring GLc.

[0174] Each of transistor M24, transistor M25, and transistor M26 has a function as a switch. Each of capacitor element C21 and capacitor element C22 has a function of holding the voltage between a pair of terminals.

[0175] The operation of pixel 161BA will be described in terms of a correction operation and a writing operation.

[0176] In the correction operation, first, a potential L is applied to wiring GLa, and potentials H are applied to wiring GLb and wiring GLc. Next, a potential L is applied to wiring GLb. Then, a potential L is applied to wiring GLc. Through such a series of operations, a voltage corresponding to the threshold voltage of transistor M22 is held in capacitor element C22.

[0177] In the writing operation, first, a potential H is applied to wiring GLa, and potentials L are applied to wiring GLb and wiring GLc. Thereby, a data potential is applied from wiring SL to wiring NL23, and a predetermined potential is applied from wiring VL0 to wiring NL21. At this time, the potential of wiring NL22 becomes "data potential + voltage corresponding to the threshold voltage of transistor M22 held in capacitor element C22". That is, a voltage corresponding to the data potential is applied as the gate voltage of transistor M22. Then, a potential L is applied to wiring GLa, and the gate voltage is held in capacitor elements C21 and C22.

[0178] Next, a potential H is applied to wiring GLb. Thereby, a current amount corresponding to the gate voltage applied to transistor M22 flows through light-emitting element LD. Then, light-emitting element LD emits light with a light-emitting intensity corresponding to the current amount. At this time, a voltage independent of the threshold voltage of transistor M22 is applied as the gate voltage of transistor M22. Therefore, a current amount independent of the threshold voltage of transistor M22 flows through light-emitting element LD.

[0179] FIG. 26 is a circuit diagram for explaining a specific configuration example different from pixel 161BA described above as pixel 161B[u, v] having an internal correction circuit.

[0180] Pixel 161BB shown in FIG. 26 includes transistor M21, transistor M22, transistor M23, light-emitting element LD, in addition to transistor M24, transistor M27, transistor M28, capacitor element C21, and capacitor element C23. Also, transistor M22 has a back gate.

[0181] One of the source or drain of transistor M23 is connected to one terminal of light-emitting element LD. The other of the source or drain of transistor M23 is connected to one of the source or drain of transistor M22, one of the source or drain of transistor M24, one of the source or drain of transistor M27, one terminal of capacitor element C21, one terminal of capacitor element C23, and wiring NL21. The gate of transistor M23 is connected to wiring GLb. The other terminal of light-emitting element LD is connected to wiring CATH. The other of the source or drain of transistor M22 is connected to wiring ANO. The gate of transistor M22 is connected to one of the source or drain of transistor M21, the other of the source or drain of transistor M27, the other terminal of capacitor element C21, and wiring NL22. The back gate of transistor M22 is connected to one of the source or drain of transistor M28, the other terminal of capacitor element C23, and wiring NL24. The other of the source or drain of transistor M21 is connected to wiring SL. The gate of transistor M21 is connected to the gate of transistor M24 and wiring GLa. The other of the source or drain of transistor M24 is connected to wiring VL0. The gate of transistor M27 is connected to the gate of transistor M28 and wiring GLc. The other of the source or drain of transistor M28 is connected to wiring VL2.

[0182] Transistor M22 can change the threshold voltage according to the potential applied to the back gate.

[0183] Each of transistor M24, transistor M27, and transistor M28 has a function as a switch. Each of capacitor element C21 and capacitor element C23 has a function of holding the voltage between a pair of terminals.

[0184] The operation of pixel 161BB will be described with a correction operation and a writing operation.

[0185] In the correction operation, first, a potential L is applied to wiring GLa, and potentials H are applied to wiring GLb and wiring GLc. Next, a potential L is applied to wiring GLb. After that, a potential L is applied to wiring GLc. By such a series of operations, a back-gate voltage for correcting the threshold voltage of transistor M22 to 0 V is held in capacitor element C23.

[0186] In the writing operation, first, a potential H is applied to wiring GLa, and potentials L are applied to wiring GLb and wiring GLc. Thereby, a data potential is applied from wiring SL to wiring NL22, and a predetermined potential is applied from wiring VL0 to wiring NL21. That is, a voltage corresponding to the data potential is applied as the gate voltage of transistor M22. After that, a potential L is applied to wiring GLa, and the gate voltage is held in capacitor element C21.

[0187] Next, a potential H is applied to wiring GLb. Thereby, a current amount corresponding to the gate voltage applied to transistor M22 flows through light-emitting element LD. Then, light-emitting element LD emits light with a light-emitting intensity corresponding to the current amount. At this time, as the back-gate voltage of transistor M22, a voltage for correcting the threshold voltage of transistor M22 to 0 V is applied. Therefore, a current amount independent of the threshold voltage of transistor M22 flows through light-emitting element LD.

[0188] FIG. 27 is a circuit diagram for explaining a modified example of the above-described pixel 161BB.

[0189] The pixel 161BC shown in FIG. 27 further includes a transistor M29 and a capacitor element C24 in addition to the pixel 161BB.

[0190] One of the source or drain of transistor M23 is connected to one terminal of light-emitting element LD and one terminal of capacitor element C24. The gate of transistor M23 is connected to one of the source or drain of transistor M29, the other terminal of capacitor element C24, and wiring NL25. The other of the source or drain of transistor M29 is connected to wiring GLb. The gate of transistor M29 is connected to wiring VL3.

[0191] Transistor M29 has a function as a switch. Capacitor element C24 has a function of holding the voltage between a pair of terminals.

[0192] In the operation of pixel 161BC, when a current amount corresponding to the gate voltage applied to transistor M22 flows through light-emitting element LD and the potential of one terminal of light-emitting element LD (i.e., one of the source or drain of transistor M23) rises, the potential of wiring NL25 (i.e., the gate of transistor M23) also rises following by capacitive coupling through capacitor element C24. Therefore, transistor M23 can be surely turned on. Thus, a current can be stably supplied to light-emitting element LD. Note that capacitor element C23 may be referred to as a bootstrap capacitor.

[0193] In one aspect of the present invention, various transistors can be used as the transistors constituting pixel 161B[u,v]. For example, an OS transistor may be used.

[0194] The OS transistor has the characteristic that its off-current is extremely small. Therefore, for example, in pixel 161BA, by using the OS transistor as the transistor having the function of a switch, the voltage between a pair of terminals of the capacitive element C22 obtained by the correction operation (that is, the voltage corresponding to the threshold voltage of transistor M22) can be held for a long period of time. Also, for example, in pixel 161BB or pixel 161BC, by using the OS transistor as the transistor having the function of a switch, the voltage between a pair of terminals of the capacitive element C23 obtained by the correction operation (that is, the back-gate voltage for correcting the threshold voltage of transistor M22 to 0V) can be held for a long period of time. Therefore, for example, the frequency of the correction operation can be reduced. Thereby, power consumption can be reduced.

[0195] In one aspect of the present invention, in the operation of the semiconductor device using the pixel having the internal correction circuit, period T100 can be set as the period for performing the writing operation, and period T200 can be set as the period for performing the correction operation. That is, for the pixels 161B for m rows, the writing operation can be sequentially performed one row at a time by the signal output from the sequential driving unit 163a. Also, the correction operation can be performed simultaneously for all rows by the signal output from the simultaneous driving unit 163b. Therefore, it is possible to suppress a reduction in the operation speed due to the correction operation.

[0196] At this time, by using the driving circuit 100 for the gate driver unit 163, when performing the correction operation, the potential H can be applied to the wiring NLr1 without a voltage drop due to the threshold voltage of the transistor Mb1 included in the second circuit 120 included in the simultaneous driving unit 163b. Therefore, for example, since it is not necessary to apply "potential H + the threshold voltage of transistor Mb1" to the wiring BKL, an increase in power consumption can be suppressed. Also, since the gate voltage of transistor Mb1 is maintained, the time until the potential of the wiring NLr1 reaches the potential H and the potential of the wiring OL reaches the potential L can be shortened. Therefore, by shortening the period for performing the correction operation (that is, period T200), the operation speed can be improved.

[0197] 〔Configuration Example of Pixel Using Light-Receiving Element〕 FIG. 28 is a circuit diagram for explaining an example in which a light-receiving element PD is used as a functional element Elm in a pixel 161 included in a semiconductor device 160.

[0198] In FIG. 28, a pixel 161C[u, v] is illustrated as a pixel 161[u, v].

[0199] The pixel 161C[u, v] includes a transistor Mtx, a transistor Mrs (corresponding to the transistor Mpix), a transistor Mam, a transistor Mse, and a light-receiving element PD. One of the source or drain of the transistor Mrs is connected to one of the source or drain of the transistor Mtx, the gate of the transistor Mam, and a wiring NL31. The other of the source or drain of the transistor Mrs is connected to a wiring VLRS. The gate of the transistor Mrs is connected to a wiring RS[u] (corresponding to the wiring GL[u]). The other of the source or drain of the transistor Mtx is connected to one terminal of the light-receiving element PD. The other terminal of the light-receiving element PD is connected to a wiring VLPD. The gate of the transistor Mtx is connected to a wiring TX. One of the source or drain of the transistor Mam is connected to one of the source or drain of the transistor Mse. The other of the source or drain of the transistor Mam is connected to a wiring VLAM. The other of the source or drain of the transistor Mse is connected to a wiring WX[v]. The gate of the transistor Mse is connected to a wiring SE[u].

[0200] Although not shown, the pixel 161C[u, v] may include a capacitive element, and one terminal of the capacitive element may be connected to the wiring NL31. At this time, the other terminal of the capacitive element may be connected to the wiring VLPD, the wiring VLRS, the wiring VLAM, or a wiring to which an arbitrary potential is applied.

[0201] When a reverse bias is applied between a pair of terminals of the light-receiving element PD, charges are generated according to the amount of light received by the light-receiving element PD. For example, when a constant potential is applied to the other terminal of the light-receiving element PD and one terminal is made floating, charges are accumulated at the one terminal and the potential rises.

[0202] The transistor Mtx has a function as a switch for controlling the exposure of the light-receiving element. The transistor Mrs has a function as a switch for controlling the initialization of the potential of the wiring NL31. The transistor Mam has a function as an amplifier that conducts a drain current according to the potential of the gate (i.e., the potential of the wiring NL31). The transistor Mse has a function as a switch for controlling whether to read out a current according to the potential of the wiring NL31 from the pixel 161C[u, v].

[0203] The operations of the pixel 161C will be described in terms of an imaging operation and a readout operation.

[0204] In the imaging operation, first, a potential H is applied to the wiring TX and the wiring RS[u], and a potential L is applied to the wiring SE[u]. Thereby, the potential of the wiring NL31 and the reverse bias applied between the pair of terminals of the light-receiving element PD are initialized. Next, a potential L is applied to the wiring TX and the wiring RS[u]. After an arbitrary exposure time has elapsed, a potential H is applied to the wiring TX, and then a potential L is applied. By such a series of operations, the charges generated according to the amount of light received by the light-receiving element PD are transferred to the wiring NL31, and the potential corresponding to the charges is held in the wiring NL31.

[0205] In the read operation, first, a potential H is applied to the wiring SE[u], and potentials L are applied to the wiring TX and the wiring RS[u]. As a result, a current corresponding to the potential held in the wiring NL31 flows through the wiring WX[v], and the current is converted into a first voltage outside the pixel portion 162 (for example, the source driver portion 164). Then, a potential H is applied to the wiring RS[u], and the potential of the wiring NL31 is initialized. As a result, a current corresponding to the initialized potential flows through the wiring WX[v], and the current is converted into a second voltage outside the pixel portion 162. At this time, by correlated double sampling that reads the difference between the first voltage and the second voltage, it is possible to read as a voltage independent of the threshold voltage of the transistor Mam.

[0206] In one aspect of the present invention, various transistors can be used as the transistors constituting the pixel 161C[u,v]. For example, an OS transistor may be used.

[0207] The OS transistor has a characteristic that its off-current is extremely small. Therefore, for example, in the pixel 161C, by using the OS transistor as a transistor having a function as a switch, the charge accumulated in the wiring NL31 (that is, the potential of the wiring NL31) by the imaging operation can be held for a long period of time. As a result, a global shutter method in which the imaging operation is performed simultaneously for all pixels can be realized.

[0208] In one aspect of the present invention, in the operation of the semiconductor device using the light receiving element, the period T100 can be set as the period for performing the read operation, and the period T200 can be set as the period for performing the imaging operation. That is, for the pixels 161C for m rows, the read operation can be sequentially performed one row at a time by the signal output from the sequential driving unit 163a. Also, the imaging operation can be performed simultaneously for all rows by the signal output from the simultaneous driving unit 163b.

[0209] At this time, by using the drive circuit 100 in the gate driver unit 163, when performing the imaging operation, the potential H can be applied to the wiring OL without causing a voltage drop due to the threshold voltage of the transistor Mb1 included in the second circuit 120 included in the simultaneous drive unit 163b. Therefore, for example, since it is not necessary to apply "potential H + threshold voltage of the transistor Mb1" to the wiring BKL, an increase in power consumption can be suppressed.

[0210] 〔Modification Example of Semiconductor Device〕 FIG. 29(A) is a block diagram for explaining a modification example of the semiconductor device 160. The semiconductor device 160 shown in FIG. 29(A) is different from the semiconductor device 160 shown in FIG. 19(A) in that in the gate driver unit 163, the sequential drive unit 163a and the simultaneous drive unit 163b are arranged to face each other via the pixel unit 162. That is, in the drawing, the sequential drive unit 163a is arranged on the left outer side of the pixel unit 162, and the simultaneous drive unit 163b is arranged on the right outer side of the pixel unit 162. By adopting such a configuration, compared with the case where both the sequential drive unit 163a and the simultaneous drive unit 163b are arranged on the left outer side of the pixel unit 162 in the drawing as shown in FIG. 19(A), the narrow bezel of the display device using the semiconductor device 160 can be achieved.

[0211] FIG. 29(B) is a block diagram for explaining a modification example of the semiconductor device 160. The semiconductor device 160 shown in FIG. 29(B) is different from the semiconductor device 160 shown in FIG. 19(A) in that it has two gate driver units 163 arranged to face each other via the pixel unit 162. In the configuration shown in FIG. 29(B), the potentials of the m gate lines 165 are controlled by the two gate driver units 163. By adopting such a configuration, for example, the substantial wiring load (parasitic capacitance and parasitic resistance) can be made 1 / 4 of the wiring load in the semiconductor device 160 shown in FIG. 19(A). Therefore, the high speed, high definition, high resolution, narrow bezel, and large screen of the display device using the semiconductor device 160 can be achieved.

[0212] FIG. 52(A) and FIG. 52(B) are block diagrams for explaining a modified example of the semiconductor device 160. The semiconductor device 160 shown in FIGS. 52(A) and 52(B) is different from the semiconductor device 160 shown in FIGS. 19(A) and 19(B) in that, in the gate driver section 163, two simultaneous drive sections 163b are arranged to face each other via the pixel section 162. That is, in the drawing, the sequential drive section 163a is arranged on the left outer side of the pixel section 162, and the simultaneous drive sections 163b are arranged on both the left outer side and the right outer side of the pixel section 162. Since the simultaneous drive section 163b changes the potentials of the m gate lines 165 using the potential of the wiring BKL, the load on the wiring when driving the simultaneous drive section 163b is large. In the modified example shown in FIGS. 52(A) and 52(B), by arranging the two simultaneous drive sections 163b to face each other via the pixel section 162, the substantial wiring load when driving the simultaneous drive section 163b can be reduced. That is, it can be said that the driving ability when driving the simultaneous drive section 163b is improved by arranging the two simultaneous drive sections 163b. On the other hand, since the sequential drive section 163a has a smaller wiring load when being driven compared to the simultaneous drive section 163b, it is not necessarily required to arrange a plurality of them. For example, by arranging it only on the left outer side or the right outer side of the pixel section (the left outer side in FIG. 52(A)), an increase in the frame width can be suppressed compared to the case where it is arranged to face the left outer side and the right outer side. That is, by adopting the configuration of the modified example shown in FIGS. 52(A) and 52(B), it is possible to achieve both an improvement in the driving ability of the gate driver section 163 and space saving.

[0213] Note that, as the transistors constituting the semiconductor device 160, various transistors can be used in one aspect of the present invention. For example, Si transistors may be used, or OS transistors may be used, or both Si transistors and OS transistors may be used.

[0214] Since the OS transistor can be freely arranged, for example, on a silicon substrate on which Si transistors are provided, integration can be easily performed. In addition, since the same manufacturing equipment as that for Si transistors can be used to manufacture the OS transistor, it can be manufactured at low cost.

[0215] Therefore, in the semiconductor device 160, for example, Si transistors including a part of the silicon substrate may be used for the transistors constituting the source driver unit 164, and OS transistors provided on the silicon substrate may be used for the transistors constituting the gate driver unit 163 and the pixel unit 162, respectively. Note that OS transistors may be used for at least a part of the transistors constituting the source driver unit 164, or Si transistors may be used for at least a part of the transistors constituting the gate driver unit 163 and the pixel unit 162, respectively.

[0216] In addition, various circuits (which may include arithmetic circuits and memory circuits, etc.) for controlling the operation of the semiconductor device 160 may be provided using Si transistors including a part of the silicon substrate. Therefore, one aspect of the present invention can be configured such that, for example, OS transistors are arranged on a silicon substrate on which Si transistors are provided, and display elements or light receiving elements are arranged on the layer on which the OS transistors are provided.

[0217] Note that one aspect of the present invention is not limited to the configuration examples, operation examples, etc. described in the present embodiment. The described contents of the present embodiment can be appropriately combined and implemented. In addition, the described contents of the present embodiment can be appropriately combined with the described contents of other embodiments, etc. and implemented.

[0218] (Embodiment 2) In this embodiment, a transistor according to one aspect of the present invention will be described. At least a part of the transistors shown in this embodiment can be applied to the drive circuits and semiconductor devices shown in the above-described Embodiment 1.

[0219] <Configuration Example 1 of Transistor> FIG. 30(A) is a top view of transistor 200A. FIG. 30(B) is a cross-sectional view taken along line A1 - A2 shown by the dashed-dotted line in FIG. 30(A). FIG. 30(C) is a cross-sectional view taken along line A3 - A4 shown by the dashed-dotted line in FIG. 30(A). In the top view of FIG. 30(A), some elements are omitted for clarity of the figure. In other top views as well, some elements may be omitted.

[0220] Transistor 200A has an insulating layer 202 on a substrate 201, and has a semiconductor layer 203 on the insulating layer 202. Also, it has an insulating layer 204 on the insulating layer 202 and the semiconductor layer 203. Further, it has a conductive layer 205 on the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have a region overlapping with each other via the insulating layer 204.

[0221] The semiconductor layer 203 has a region 203a that functions as one of the source region or the drain region of transistor 200A, a channel formation region 203b, and a region 203c that functions as the other of the source region or the drain region. In the semiconductor layer 203, the region overlapping with the conductive layer 205 functions as the channel formation region 203b. Thus, the conductive layer 205 functions as the gate electrode of transistor 200A. Also, the insulating layer 204 functions as the gate insulating film of transistor 200A.

[0222] Also, in the semiconductor layer 203, the length in the X direction of the channel formation region 203b (corresponding to the distance between the region 203a and the region 203c in the channel formation region 203b) is the channel length Lch of transistor 200A (see FIGS. 30(A) and 30(B)). Also, in the semiconductor layer 203, the length in the Y direction of the channel formation region 203b (corresponding to the length of the portion where the region 203a and the region 203c face each other in the channel formation region 203b) is the channel width Wch of transistor 200A (see FIGS. 30(A) and 30(C)).

[0223] Further, it has an insulating layer 206 on the insulating layer 204 and the conductive layer 205. Also, in a region overlapping with the region 203a of the semiconductor layer 203, an opening 207a is provided in the insulating layer 204 and the insulating layer 206. Also, in a region overlapping with the region 203c of the semiconductor layer 203, an opening 207b is provided in the insulating layer 204 and the insulating layer 206.

[0224] Further, a conductive layer 208a is provided on the insulating layer 206 and inside the opening 207a, and a conductive layer 208b is provided on the insulating layer 206 and inside the opening 207b. The conductive layer 208a is in contact with the region 203a of the semiconductor layer 203 at the bottom of the opening 207a. Also, the conductive layer 208b is in contact with the region 203c of the semiconductor layer 203 at the bottom of the opening 207b. Thus, the conductive layer 208a functions as one of the source electrode or the drain electrode of the transistor 200A, and the conductive layer 208b functions as the other of the source electrode or the drain electrode of the transistor 200A.

[0225] Also, an insulating layer 209 is provided on the insulating layer 206 and the conductive layer 208 (the conductive layer 208a and the conductive layer 208b).

[0226] <Configuration Example 2 of Transistor> FIG. 31(A) is a top view of the transistor 200B. The transistor 200B is a modified example of the transistor 200A. To reduce repetition in the description, mainly the differences between the transistor 200B and the transistor 200A will be described.

[0227] FIG. 31(B) is a cross-sectional view taken along the line A1 - A2 indicated by the dashed-dotted line in FIG. 31(A). FIG. 31(C) is a cross-sectional view taken along the line A3 - A4 indicated by the dashed-dotted line in FIG. 31(A).

[0228] Transistor 200B is different from transistor 200A in that it has a conductive layer 219 between the substrate 201 and the insulating layer 202. The conductive layer 219 overlaps with the channel formation region 203b via the insulating layer 202. Therefore, the insulating layer 202 functions as the back gate insulating film of transistor 200B, and the conductive layer 219 functions as the back gate electrode of transistor 200B. Note that the insulating layer 202 may have different film thicknesses in the region overlapping with the conductive layer 219 and the region not overlapping with the conductive layer 219, or the film thickness may be uniform. Also, the conductive layer 219 may extend beyond the end of the channel formation region 203b. Although not shown, an insulating layer may be provided between the substrate 201 and the conductive layer 219.

[0229] Here, in a transistor having a back gate, the gate and the back gate of the transistor are arranged so as to sandwich the channel formation region of the semiconductor layer. The back gate can function in the same manner as the gate. When the gate is used to control the on-state and off-state of the transistor, the potential of the back gate can be set to the same potential as the gate. Also, it can be set to an arbitrary potential.

[0230] For example, when turning on the transistor, by supplying the potential for turning on the transistor to both the gate and the back gate, the on-current can be increased compared to the case where it is supplied to only one of them. For example, by connecting the gate and the back gate, it is possible to always set the gate and the back gate to the same potential. Also, by independently controlling the potential of the back gate from the potential of the gate, the threshold voltage of the transistor can be adjusted.

[0231] Alternatively, a fixed potential such as a ground potential may be supplied to the back gate. Since the gate and the back gate are formed of a conductive layer or the like, by sandwiching the channel formation region of the semiconductor layer between the gate and the back gate, an electric field generated outside the transistor is less likely to act on the channel formation region (also referred to as the "electric field shielding effect"). Therefore, by providing a back gate to the transistor, the operation of the transistor becomes stable. In addition, by providing a back gate to the transistor, the variation in characteristics between a plurality of transistors is reduced. By providing a back gate to the transistor, the reliability of the transistor can be enhanced. Thus, the reliability of the semiconductor device including the transistor can be enhanced. Note that the electric field shielding effect can be obtained even when one or both of the gate and the back gate are in an electrically floating state (also referred to as the "floating state"), but the effect can be enhanced by supplying a potential to the gate and the back gate.

[0232] <Configuration Example 3 of Transistor> FIG. 32(A) is a top view of the transistor 200C. FIG. 32(B) is a cross-sectional view taken along the line A1 - A2 indicated by the dashed-dotted line in FIG. 32(A).

[0233] The transistor 200C has an insulating layer 202 on a substrate 201, and has a conductive layer 255 on the insulating layer 202. Further, it has an insulating layer 257 on the conductive layer 255, has an insulating layer 258 on the insulating layer 257, and has an insulating layer 259 on the insulating layer 258. In this specification and the like, the insulating layer 257, the insulating layer 258, and the insulating layer 259 may be collectively referred to as the insulating layer 256 or the spacer layer. Also, it has a conductive layer 261 on the insulating layer 259.

[0234] Further, in a region overlapping a part of the conductive layer 255, an opening 262 is provided in the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257. Also, a semiconductor layer 263 is provided in contact with the inner wall of the opening 262.

[0235] The semiconductor layer 263 has a region overlapping with the bottom of the opening 262 and a region overlapping with the inner wall of the opening 262. That is, the semiconductor layer 263 has a region in contact with the insulating layer 256 in the opening 262. Further, the semiconductor layer 263 has a region in contact with the conductive layer 255 and a region in contact with the conductive layer 261 in the opening 262.

[0236] An insulating layer 264 is provided over the insulating layer 259, the conductive layer 261, and the semiconductor layer 263. A conductive layer 265 is provided over the insulating layer 264. The conductive layer 265 has a region overlapping with the semiconductor layer 263. The conductive layer 265 has a region overlapping with the semiconductor layer 263 via the insulating layer 264.

[0237] Each of the insulating layer 264 and the conductive layer 265 has a region overlapping with the opening 262. In the opening 262, the semiconductor layer 263 has a region overlapping with the conductive layer 265 via the insulating layer 264 and a region overlapping with the inner wall (side surface of the insulating layer 256) of the opening 262.

[0238] An insulating layer 266 is provided over the insulating layer 264. It is preferable that the upper surface of the insulating layer 266 is flat. Alternatively, the heights (positions in the Z direction) of the upper surfaces of the insulating layer 266 and the conductive layer 265 may coincide. For example, by performing a chemical mechanical polishing (CMP) process or the like, the flatness of the upper surface of the insulating layer 266 can be enhanced. Also, by performing the CMP process, the heights of the upper surfaces of the insulating layer 266 and the conductive layer 265 can be made to coincide. By performing the CMP process, the unevenness of the sample surface is reduced, and the coating properties of the insulating layer and the conductive layer formed thereafter can be enhanced.

[0239] When an oxide semiconductor is used for the semiconductor layer 263, it is preferable that the conductive layer 255 in contact with the semiconductor layer 263 and the conductive layer 261 in contact with the semiconductor layer 263 use a conductive material for n-type doping of the oxide semiconductor. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Also, another conductive material may be provided on top of the conductive material containing nitrogen.

[0240] When an oxide semiconductor is used for the semiconductor layer 263, it is preferable that the insulating layer 258 has hydrogen reduced and uses a material containing oxygen. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide or silicon oxynitride may be used. Since hydrogen is an impurity element in the oxide semiconductor, when the semiconductor layer 263, which is an oxide semiconductor, is in contact with the insulating layer 258 with reduced hydrogen, it becomes difficult to n-type dope the semiconductor layer 263. Also, when the semiconductor layer 263, which is an oxide semiconductor, is in contact with the insulating layer 258 containing oxygen, the oxygen deficiency in the semiconductor layer 263 is reduced, the characteristics of the transistor are stabilized, and the reliability is improved.

[0241] When an oxide semiconductor is used for the semiconductor layer 263, the insulating layer 258 may contain excess oxygen. In this specification and the like, excess oxygen refers to oxygen that desorbs upon heating. A material that desorbs oxygen upon heating is a material in which, in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0242] Also, when a material containing excess oxygen is used for the insulating layer 258, it is preferable to use a material with low oxygen permeability for the insulating layers 257 and 259. As the material with low oxygen permeability, for example, an oxide containing one or both of aluminum and hafnium, silicon nitride, or the like can be used. By using a material with low oxygen permeability for the insulating layers 257 and 259, the excess oxygen contained in the insulating layer 258 is less likely to desorb into the lower layer or the upper layer. Thus, sufficient oxygen can be supplied to the oxide semiconductor. For example, a configuration may be adopted in which an insulating layer (insulating layer 258) containing silicon and oxygen is provided between two insulating layers (insulating layers 257 and 259) containing silicon and nitrogen.

[0243] Also, when an oxide semiconductor is used for the semiconductor layer 263, a material containing hydrogen may be used for the insulating layers 257 and 259. Thereby, hydrogen is supplied to the region of the semiconductor layer 263 in contact with the insulating layer 257 and the region of the semiconductor layer 263 in contact with the insulating layer 259, and each region of the semiconductor layer 263 is n-type doped. Thus, the region of the semiconductor layer 263 in contact with the conductive layer 261 and the region of the semiconductor layer 263 in contact with the insulating layer 259 function as one of the source region or the drain region. Also, the region of the semiconductor layer 263 in contact with the conductive layer 255 and the region of the semiconductor layer 263 in contact with the insulating layer 257 function as the other of the source region or the drain region.

[0244] The conductive layer 261 functions as one of the source electrode or the drain electrode of the transistor 200C. The conductive layer 255 functions as the other of the source electrode or the drain electrode of the transistor 200C. The transistor 200C is a transistor in which the source electrode and the drain electrode are arranged in the Z direction. That is, the source electrode and the drain electrode of the transistor 200C are arranged at different heights. In other words, the source electrode and the drain electrode of the transistor 200C are arranged at different positions in the Z direction. Such a transistor is also referred to as a "vertical channel type transistor", "vertical channel transistor", "vertical transistor", or "VFET (Vertical Field Effect Transistor)".

[0245] In the case of the above configuration, in the transistor 200C which is a VFET, the length of the side surface of the insulating layer 258 as viewed from the X direction or the Y direction becomes the channel length Lch of the transistor 200C (here, the channel length L1) (see Fig. 32(B)). Therefore, the channel length Lch of the transistor 200C is determined according to the thickness t1 of the insulating layer 258.

[0246] Also, materials containing no hydrogen or extremely little hydrogen may be used for the insulating layer 257 and the insulating layer 259. For example, silicon nitride with extremely little hydrogen or silicon oxynitride with extremely little hydrogen may be used. In this case, the regions where the semiconductor layer 263 is in contact with the insulating layer 257 and the regions where the semiconductor layer 263 is in contact with the insulating layer 259 are not n-type. Therefore, the region where the semiconductor layer 263 is in contact with the conductive layer 261 functions as one of the source region or the drain region. Also, the region where the semiconductor layer 263 is in contact with the conductive layer 255 functions as the other of the source region or the drain region. Also, the region where the semiconductor layer 263 is in contact with the insulating layer 258 functions as the channel formation region.

[0247] In this case, the sum of the lengths of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259 as viewed from the X direction or the Y direction becomes the channel length Lch of the transistor 200C (here, the channel length L2). Therefore, the channel length Lch of the transistor 200C is determined according to the combined thickness t2 obtained by adding up the thicknesses of the insulating layer 257, the insulating layer 258, and the insulating layer 259. In this way, the transistor 200C has a region where the channel formation region is along the side surface of the insulating layer 256.

[0248] In addition, since the semiconductor layer 263 is provided in the opening 262, the length of the periphery of the opening 262 when viewed from the Z direction becomes the channel width Wch of the transistor 200C (see Fig. 32(A)). The peripheral length can be obtained, for example, at a position half of the thickness t1 of the insulating layer 258 or at a position half of the thickness t2. Note that, if necessary, the peripheral length at an arbitrary position of the opening 262 may be used as the channel width Wch. For example, the peripheral length at the lowermost part of the opening 262 may be used as the channel width Wch, or the peripheral length at the uppermost part of the opening 262 may be used as the channel width Wch. Also, in Fig. 32(A), the contour (planar shape) of the opening 262 when viewed from the Z direction is shown as a circle, but it is not limited thereto. For example, the contour of the opening 262 when viewed from the Z direction may be an ellipse or a rectangle.

[0249] In addition, the channel length Lch of the transistor 200C is preferably at least smaller than the channel width Wch of the transistor 200C. For example, the channel length Lch can be 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, with respect to the channel width Wch.

[0250] In addition, in order to enhance the coverage of the semiconductor layer 263, the insulating layer 264, and the conductive layer 265 formed inside the opening 262, the taper angle θ of the inner wall of the opening 262, that is, the taper angle θ of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259, may be set to 45° or more and 90° or less, preferably 50° or more and 75° or less. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle formed by the bottom surface and the side surface of the layer (see Fig. 32(B)).

[0251] For a vertical transistor, the channel formation region, the source region, and the drain region are provided separately on the XY plane, and thus the occupied area can be reduced compared to a transistor (also referred to as a "horizontal transistor") in which these regions are provided separately on the XY plane. Therefore, by using a vertical transistor in a semiconductor device, the occupied area of the semiconductor device can be reduced. In addition, by using a vertical transistor in a semiconductor device, high integration of the semiconductor device can be achieved.

[0252] In addition, in a horizontal transistor, the channel length is limited by the exposure limit of photolithography, and further miniaturization has been difficult. On the other hand, in a vertical transistor, the channel length can be set by the film thickness of the insulating layer 256 or the insulating layer 258. Therefore, the channel length of the transistor can be made into a very fine structure (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more) below the exposure limit of photolithography. As a result, the on-current of the transistor 200C increases, and the frequency characteristics can be improved. By using a vertical transistor, a semiconductor device with a high operating speed can be provided.

[0253] <Example configuration of transistor 4> FIG. 33(A) is a top view of the transistor 200D. FIG. 33(B) is a cross-sectional view taken along the line A1 - A2 indicated by the dashed-dotted line in FIG. 33(A). FIG. 33(C) is a cross-sectional view taken along the line A3 - A4 indicated by the dashed-dotted line in FIG. 33(A). Note that FIG. 33(B) is a cross-sectional view in the channel length direction of the transistor 200D, and FIG. 33(C) is a cross-sectional view in the channel width direction of the transistor 200D.

[0254] As shown in FIGS. 33(A) to 33(C), the transistor 200D includes a semiconductor layer 520a disposed on a substrate 201, a semiconductor layer 520b disposed on the semiconductor layer 520a, conductive layers 542a and 542b disposed on the semiconductor layer 520b with a space therebetween, an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening formed between the conductive layer 542a and the conductive layer 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed between the semiconductor layer 520b, the conductive layers 542a and 542b, and the insulating layer 580, and the conductive layer 560, and a semiconductor layer 520c disposed between the semiconductor layer 520b, the conductive layers 542a and 542b, and the insulating layer 580, and the insulating layer 550. Here, as shown in FIGS. 33(B) and 33(C), the height of the upper surface of the conductive layer 560 is the same as the height of the upper surfaces of the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580. In the following, the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may be collectively referred to as the semiconductor layer 520. Also, the conductive layers 542a and 542b may be collectively referred to as the conductive layer 542.

[0255] As shown in FIGS. 33(A) to 33(C), an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layers 542a and 542b, and the insulating layer 580. The insulating layer 554 is in contact with the upper surface and side surfaces of the conductive layer 542a, the upper surface and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the upper surface of the insulating layer 524.

[0256] The conductive layer 542a functions as one of the source electrode or the drain electrode of the transistor 200D. The conductive layer 542b functions as the other of the source electrode or the drain electrode of the transistor 200D. In the semiconductor layer 520, the region overlapping the conductive layer 560 functions as the channel formation region of the transistor 200D. Therefore, the conductive layer 560 functions as the gate electrode of the transistor 200D. Also, the insulating layer 550 functions as the gate insulating film of the transistor 200D.

[0257] Here, the channel formation region of the transistor 200D is formed in the semiconductor layer 520 between a region that functions as one of the source region or the drain region and a region that functions as the other of the source region or the drain region. Therefore, the distance between the conductive layer 542a and the conductive layer 542b can be defined as the channel length Lch of the transistor 200D (see FIGS. 33(A) and 33(B)). Also, the length of the portion where the conductive layer 542a and the conductive layer 542b face each other can be defined as the channel width Wch of the transistor 200D (see FIGS. 33(A) and 33(C)).

[0258] Note that, in the transistor 200D, a configuration in which three layers of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c are stacked in the vicinity of the channel formation region is shown, but it is not limited thereto. For example, a two-layer structure of the semiconductor layer 520b and the semiconductor layer 520c or a stacked structure of four or more layers may be provided. Also, each of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may have a stacked structure of two or more layers.

[0259] For example, when an oxide semiconductor, which is a kind of metal oxide, is used as the semiconductor layer 520, and when the semiconductor layer 520c has a stacked structure including a first metal oxide and a second metal oxide on the first metal oxide, the first metal oxide may have the same composition as the semiconductor layer 520b, and the second metal oxide may have the same composition as the semiconductor layer 520a.

[0260] The conductive layer 560 is formed so as to be embedded in an opening formed in the insulating layer 580 and in a region sandwiched between the conductive layer 542a and the conductive layer 542b. Here, the conductive layer 560, the conductive layer 542a, and the conductive layer 542b are arranged self-aligned with respect to the opening formed in the insulating layer 580. That is, in the transistor 200D, the gate electrode can be arranged self-aligned between the source electrode and the drain electrode. Therefore, since the conductive layer 560 can be formed without providing an alignment margin, the occupied area of the transistor 200D can be reduced. Thereby, the occupied area of the semiconductor device can be reduced. Also, the integration degree of the semiconductor device can be increased.

[0261] As shown in FIGS. 33(A) to 33(C), the conductive layer 560 has a conductive layer 560a provided on the insulating layer 550 and a conductive layer 560b provided on the conductive layer 560a inside the opening formed in the insulating layer 580. The insulating layer 550 and the conductive layer 560 are provided so as to be embedded inside the opening formed in the insulating layer 580. Note that in the transistor 200D, the conductive layer 560 is shown as a two-layer stacked structure, but it is not limited thereto. For example, the conductive layer 560 may have a single-layer structure or a stacked structure of three or more layers.

[0262] The transistor 200D has an insulating layer 202 disposed on the substrate 201, an insulating layer 514 disposed on the insulating layer 202, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. Further, a semiconductor layer 520a is disposed on the insulating layer 524.

[0263] Also, an insulating layer 574 and an insulating layer 581 that function as an interlayer film are disposed on the transistor 200D. The insulating layer 574 is disposed in contact with the upper surfaces of the conductive layer 560, the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580.

[0264] When an oxide semiconductor is used as the semiconductor layer 520, the insulating layers 522, 554, and 574 may be insulating layers having a function of suppressing the diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, etc.). For example, as the insulating layers 522, 554, and 574, insulating layers having lower hydrogen permeability than the insulating layers 524, 550, and 580 may be used. Further, the insulating layers 522 and 554 may be insulating layers having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). For example, as the insulating layers 522 and 554, insulating layers having lower oxygen permeability than the insulating layers 524, 550, and 580 may be used. As the insulating layers 522, 554, and 574, for example, silicon nitride, silicon oxynitride, etc. can be used.

[0265] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are separated from the upper layer of the insulating layer 574 and the lower layer of the insulating layer 522 by the insulating layers 522 and 574, respectively. Therefore, it is possible to suppress impurities such as hydrogen and excessive oxygen contained in the upper layer of the insulating layer 574 and the lower layer of the insulating layer 522 from mixing into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0266] FIG. 33(B) shows an example in which a conductive layer 545 (conductive layers 545a and 545b) that is connected to the transistor 200D and functions as a plug is provided. An example in which an insulating layer 541 (insulating layers 541a and 541b) is provided in contact with the side surface of the conductive layer 545 that functions as a plug is also shown. That is, the insulating layers 541a and 541b are provided in contact with the inner walls of the two openings formed in the insulating layers 554, 580, 574, and 581, respectively. Further, in FIG. 33(B), a first conductive layer of the conductive layer 545 is provided in contact with the side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside.

[0267] Here, the height of the upper surface of the conductive layer 545 and the height of the upper surface of the insulating layer 581 can be made approximately the same. Note that in the transistor 200D, a configuration in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked is shown, but it is not limited to this. For example, the conductive layer 545 may be provided with a single-layer or a stacked structure of three or more layers.

[0268] Further, in the semiconductor layer 520b, the film thickness of the region that does not overlap with the conductive layer 542 may be thinner than the film thickness of the region that overlaps with the conductive layer 542. This is formed by removing a part of the upper surface of the semiconductor layer 520b when forming the conductive layer 542a and the conductive layer 542b. When a conductive film that becomes the conductive layer 542 is formed on the upper surface of the semiconductor layer 520b, a region with low resistance may be formed in the vicinity of the interface with the conductive film. In this case, in the semiconductor layer 520b, by removing the low-resistance region located between the conductive layer 542a and the conductive layer 542b, it is possible to prevent a channel from being formed in the region.

[0269] Subsequently, the detailed configuration of the transistor 200D will be described.

[0270] The conductive layer 505 is arranged so as to have a region that overlaps with the conductive layer 560 via the semiconductor layer 520. Further, by providing the conductive layer 505 so as to be embedded in the insulating layer 516, the unevenness of the upper surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and the covering property of the layer formed in a later process can be improved.

[0271] The conductive layer 505 includes a conductive layer 505a, a conductive layer 505b, and a conductive layer 505c. The conductive layer 505a is provided in contact with the bottom and the inner wall of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to be embedded in a recess formed in the conductive layer 505a. Here, the height of the upper surface of the conductive layer 505b is lower than the height of the upper surface of the conductive layer 505a and the height of the upper surface of the insulating layer 516. The conductive layer 505c is provided in contact with the upper surface of the conductive layer 505b and the side surface of the conductive layer 505a. Here, the height of the upper surface of the conductive layer 505c is the same as the height of the upper surface of the conductive layer 505a and the height of the upper surface of the insulating layer 516. That is, the conductive layer 505b is configured to be surrounded by the conductive layer 505a and the conductive layer 505c.

[0272] When an oxide semiconductor is used as the semiconductor layer 520, the conductive layer 505a and the conductive layer 505c may be made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) may be used.

[0273] By using a conductive material having a function of reducing the diffusion of hydrogen for the conductive layer 505a and the conductive layer 505c, it is possible to suppress impurities such as hydrogen contained in the conductive layer 505b from diffusing into the semiconductor layer 520 through the insulating layer 524 or the like. Further, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductive layer 505a and the conductive layer 505c, it is possible to suppress the conductive layer 505b from being oxidized and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. can be used. Therefore, as the conductive layer 505a, the above conductive material can be a single layer or a laminate. For example, titanium nitride can be used for the conductive layer 505a.

[0274] In addition, the conductive layer 505b may be made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten can be used for the conductive layer 505b.

[0275] When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a back gate electrode. Also, the insulating layers 522 and 524 function as a back gate insulating film.

[0276] Note that the conductive layer 505 may be used as a gate electrode. In this case, the conductive layer 560 functions as a back gate electrode. Also, the insulating layers 522 and 524 function as a gate insulating film, and the insulating layer 550 functions as a back gate insulating film.

[0277] The conductive layer 505 may be provided larger than the channel formation region in the semiconductor layer 520. In particular, as shown in FIG. 33(C), the conductive layer 505 may extend to a region outside the end portion intersecting the channel width direction of the semiconductor layer 520. That is, on the outside of the side surface in the channel width direction of the semiconductor layer 520, the conductive layer 505 and the conductive layer 560 may overlap via an insulating layer.

[0278] By having the above configuration, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 having a function as a gate electrode and the electric field of the conductive layer 505 having a function as a back gate electrode.

[0279] The conductive layer 505 may be extended beyond the end portion of the semiconductor layer 520 and used as a wiring. However, it is not limited to this, and a configuration may be adopted in which a conductive layer functioning as a wiring is provided under the conductive layer 505.

[0280] As the insulating layer 514, an insulating material that functions as a barrier insulating film for suppressing the mixing of impurities such as water or hydrogen into the transistor 200D from the substrate side may be used. Therefore, as the insulating layer 514, an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms (that is, it is difficult for impurities to permeate) may be used. Alternatively, an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (that is, it is difficult for oxygen to permeate) may be used.

[0281] For example, as the insulating layer 514, aluminum oxide or silicon nitride can be used. Thereby, it is possible to suppress the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 200D side rather than through the insulating layer 514. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulating layer 524 or the like to the substrate side rather than through the insulating layer 514.

[0282] As the insulating layer 516, insulating layer 580, and insulating layer 581 that function as interlayer films, an insulating material having a lower dielectric constant than that of the insulating layer 514 may be used. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulating layer 516, insulating layer 580, and insulating layer 581, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or silicon oxide having pores can be used.

[0283] Here, the insulating layer 524 in contact with the semiconductor layer 520 may contain excess oxygen. For example, the insulating layer 524 can use silicon oxide or silicon oxynitride. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, the oxygen deficiency in the semiconductor layer 520 is reduced, and the reliability of the transistor 200D is improved.

[0284] As shown in FIG. 33(C), the thickness of the insulating layer 524 in the region where it does not overlap with the insulating layer 554 and does not overlap with the semiconductor layer 520b may be thinner than the thickness of the other regions. In the insulating layer 524, it is preferable that the thickness of the region where it does not overlap with the insulating layer 554 and does not overlap with the semiconductor layer 520b is a thickness that allows sufficient diffusion of the above oxygen.

[0285] As the insulating layer 522, similar to the insulating layer 514 and the like, a material that functions as a barrier insulating film for suppressing the mixing of impurities such as water or hydrogen into the transistor 200D from the substrate side may be used. For example, as the insulating layer 522, a material with lower hydrogen permeability than the insulating layer 524 may be used. By surrounding the insulating layer 524, the semiconductor layer 520, the insulating layer 550, etc. with the insulating layer 522, the insulating layer 554, and the insulating layer 574, it is possible to suppress the intrusion of impurities such as water or hydrogen from the outside into the transistor 200D.

[0286] Furthermore, as the insulating layer 522, a material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (that is, oxygen is less permeable) may be used. For example, as the insulating layer 522, a material with lower oxygen permeability than the insulating layer 524 may be used. Since the insulating layer 522 has a function of suppressing the diffusion of oxygen, the oxygen diffusing from the semiconductor layer 520 to the substrate side can be reduced. Also, it is possible to suppress the reaction of the conductive layer 505 with the oxygen contained in the insulating layer 524 or the semiconductor layer 520.

[0287] As the insulating layer 522, an insulating layer containing one or both of oxides of aluminum and hafnium, which are insulating materials, may be used. As the insulating layer containing one or both of oxides of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. can be used. When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer for suppressing the release of oxygen from the semiconductor layer 520 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 200D into the semiconductor layer 520.

[0288] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulating layers. Alternatively, these insulating layers may be nitrided. Further, a structure in which the insulating layer and silicon oxide, silicon oxynitride, or silicon nitride are laminated may be used. For example, as the insulating layer 522, a structure in which silicon nitride, silicon oxide, and aluminum oxide are laminated in three layers in this order can be used.

[0289] As the insulating layer 522, an insulating layer containing a high dielectric constant (high-k) material (such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST)) may be used as a single layer or in a laminated structure. As the miniaturization and high integration of transistors progress, problems such as gate leakage current may occur due to the thinning of the gate insulating film. By using a material with a high dielectric constant for the insulating layer that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0290] Note that each of the insulating layer 522 and the insulating layer 574 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure composed of the same material, and may have a laminated structure composed of different materials.

[0291] The semiconductor layer 520 has a semiconductor layer 520a, a semiconductor layer 520b on the semiconductor layer 520a, and a semiconductor layer 520c on the semiconductor layer 520b. By having the semiconductor layer 520a under the semiconductor layer 520b, the diffusion of impurities from the structure formed below the semiconductor layer 520a into the semiconductor layer 520b can be suppressed. Also, by having the semiconductor layer 520c on the semiconductor layer 520b, the diffusion of impurities from the structure formed above the semiconductor layer 520c into the semiconductor layer 520b can be suppressed.

[0292] When an oxide semiconductor is used as the semiconductor layer 520, the semiconductor layer 520 may have a stacked structure of a plurality of oxide layers with different atomic ratios of each metal atom. For example, when the semiconductor layer 520 contains at least indium (In) and element M, the ratio of the number of atoms of element M contained in the semiconductor layer 520a to the total number of atoms of all elements constituting the semiconductor layer 520a may be higher than the ratio of the number of atoms of element M contained in the semiconductor layer 520b to the total number of atoms of all elements constituting the semiconductor layer 520b. Also, the atomic ratio of element M contained in the semiconductor layer 520a to In may be made larger than the atomic ratio of element M contained in the semiconductor layer 520b to In. Here, the semiconductor layer 520c may use a metal oxide that can be used for the semiconductor layer 520a or the semiconductor layer 520b.

[0293] The energy level of the lower end of the conduction band of the semiconductor layer 520a and the semiconductor layer 520c may be higher than the energy level of the lower end of the conduction band of the semiconductor layer 520b. Also, in other words, the electron affinity of the semiconductor layer 520a and the semiconductor layer 520c may be smaller than the electron affinity of the semiconductor layer 520b. In this case, as the semiconductor layer 520c, a metal oxide that can be used for the semiconductor layer 520a may be used. Specifically, the ratio of the number of atoms of element M contained in the semiconductor layer 520c to the total number of atoms of all elements constituting the semiconductor layer 520c may be higher than the ratio of the number of atoms of element M contained in the semiconductor layer 520b to the total number of atoms of all elements constituting the semiconductor layer 520b. Also, the atomic ratio of element M contained in the semiconductor layer 520c to In may be made larger than the atomic ratio of element M contained in the semiconductor layer 520b to In.

[0294] Here, the energy level of the conduction band minimum changes gradually at the junction of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c. In other words, it can be said that the energy level of the conduction band minimum at the junction of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c changes continuously or is a continuous junction. To achieve this, the defect level density of the mixed layer formed at the interface between the semiconductor layer 520a and the semiconductor layer 520b and the interface between the semiconductor layer 520b and the semiconductor layer 520c may be reduced.

[0295] Specifically, the semiconductor layer 520a and the semiconductor layer 520b, and the semiconductor layer 520b and the semiconductor layer 520c have a common element other than oxygen, so that a mixed layer with a low defect level density can be formed. For example, when the semiconductor layer 520b is indium gallium zinc oxide (In-Ga-Zn oxide), the semiconductor layer 520a and the semiconductor layer 520c may be made of In-Ga-Zn oxide, gallium zinc oxide (Ga-Zn oxide), gallium oxide, or the like. The semiconductor layer 520c may have a laminated structure. For example, a laminated structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a laminated structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, a laminated structure of In-Ga-Zn oxide and an oxide not containing In can be used as the semiconductor layer 520c.

[0296] Specifically, as the semiconductor layer 520a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or in the vicinity thereof, or an atomic ratio of 1:1:0.5 or in the vicinity thereof may be used. Further, as the semiconductor layer 520b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or in the vicinity thereof, or an atomic ratio of 3:1:2 or in the vicinity thereof, or an atomic ratio of 1:1:1 or in the vicinity thereof may be used. Further, as the semiconductor layer 520c, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or in the vicinity thereof, an atomic ratio of In:Ga:Zn = 4:2:3 or in the vicinity thereof, an atomic ratio of Ga:Zn = 2:1 or in the vicinity thereof, or an atomic ratio of Ga:Zn = 2:5 or in the vicinity thereof may be used. Further, as a specific example in the case where the semiconductor layer 520c has a stacked structure, a stacked structure of In:Ga:Zn = 4:2:3 or in the vicinity thereof and Ga:Zn = 2:1 or in the vicinity thereof, a stacked structure of In:Ga:Zn = 4:2:3 or in the vicinity thereof and Ga:Zn = 2:5 or in the vicinity thereof, a stacked structure of In:Ga:Zn = 4:2:3 or in the vicinity thereof and gallium oxide, etc. can be mentioned.

[0297] At this time, the main path of the carriers becomes the semiconductor layer 520b. By configuring the semiconductor layer 520a and the semiconductor layer 520c as described above, the density of defect levels at the interface between the semiconductor layer 520a and the semiconductor layer 520b and at the interface between the semiconductor layer 520b and the semiconductor layer 520c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200D can obtain a large on-current and high frequency characteristics. When the semiconductor layer 520c has a stacked structure, in addition to the effect of reducing the density of defect levels at the interface between the semiconductor layer 520b and the semiconductor layer 520c, it is possible to suppress the diffusion of the constituent elements of the semiconductor layer 520c toward the insulating layer 550 side. More specifically, since the semiconductor layer 520c has a stacked structure and an oxide containing no In is positioned above the stacked structure, it is possible to suppress In that may diffuse toward the insulating layer 550 side. Since the insulating layer 550 functions as a gate insulating film, if In diffuses, the characteristics of the transistor deteriorate. Therefore, by configuring the semiconductor layer 520c to have a stacked structure, it is possible to provide a highly reliable semiconductor device.

[0298] On the semiconductor layer 520b, a conductive layer 542 (conductive layer 542a and conductive layer 542b) that functions as a source electrode and a drain electrode is provided. When an oxide semiconductor is used as the semiconductor layer 520b, a conductive material that is difficult to be oxidized or a conductive material that maintains conductivity even when absorbing oxygen may be used as the conductive layer 542.

[0299] The region in contact with the conductive layer 542 of the semiconductor layer 520 functions as a source region or a drain region of the transistor 200D. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with an opening formed in the insulating layer 580. Thereby, the conductive layer 560 can be self-alignedly disposed between the conductive layer 542a and the conductive layer 542b.

[0300] The insulating layer 550 functions as a gate insulating film. The insulating layer 550 is disposed in contact with the upper surface of the semiconductor layer 520c. As the insulating layer 550, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide having pores can be used. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 550.

[0301] As the insulating layer 550, similar to the insulating layer 524, an insulating material with a reduced impurity concentration such as water or hydrogen may be used. Also, the film thickness of the insulating layer 550 may be 1 nm or more and 20 nm or less.

[0302] A metal oxide may be provided between the insulating layer 550 and the conductive layer 560. By the metal oxide, oxygen diffusion from the insulating layer 550 to the conductive layer 560 is suppressed. Thereby, oxidation of the conductive layer 560 by oxygen contained in the insulating layer 550 can be suppressed.

[0303] The conductive layer 560 is shown as a two-layer structure in FIGS. 33(A) to 33(C), but it may be a single-layer structure or a laminated structure of three or more layers.

[0304] As the conductive layer 560a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms may be used. Alternatively, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) may be used.

[0305] Since the conductive layer 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductive layer 560b from being oxidized by oxygen contained in the insulating layer 550 and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide can be used.

[0306] The conductive layer 560b may be made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductive layer 560 also functions as wiring, a conductive layer with high conductivity may be used. Further, the conductive layer 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0307] As shown in FIGS. 33(B) and 33(C), in a region that does not overlap with the conductive layer 542 of the semiconductor layer 520b, in other words, in the channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is arranged to be covered with the conductive layer 560. Thereby, the electric field of the conductive layer 560 that functions as the gate electrode of the transistor 200D is likely to act on the side surface of the semiconductor layer 520. Therefore, the on-current of the transistor 200D can be increased and the frequency characteristics can be improved.

[0308] The insulating layer 554 may be made of an insulating material that suppresses the mixing of impurities such as water or hydrogen into the transistor 200D, similar to the insulating layer 514 and the like. For example, as the insulating layer 554, an insulating material with lower hydrogen permeability than the insulating layer 524 may be used. Further, as shown in FIGS. 33(B) and 33(C), the insulating layer 554 is provided in contact with the side surface of the semiconductor layer 520c, the upper surface and side surface of the conductive layer 542a, the upper surface and side surface of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the upper surface of the insulating layer 524. By adopting such a configuration, it is possible to suppress the hydrogen contained in the insulating layer 580 from entering the semiconductor layer 520.

[0309] Furthermore, as the insulating layer 554, an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (that is, oxygen is difficult to permeate) may be used. For example, as the insulating layer 554, an insulating material with lower oxygen permeability than the insulating layer 580 or the insulating layer 524 may be used.

[0310] When an oxide semiconductor is used as the semiconductor layer 520, the insulating layer 554 may be formed by a sputtering method. By forming the insulating layer 554 by using the sputtering method in an atmosphere containing oxygen, oxygen can be added in the vicinity of the region where the insulating layer 554 of the insulating layer 524 is in contact. Thereby, oxygen can be supplied from the region into the semiconductor layer 520 through the insulating layer 524. Here, since the insulating layer 554 has a function of suppressing the upward diffusion of oxygen, it is possible to prevent oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. Further, since the insulating layer 522 has a function of suppressing the downward diffusion of oxygen, it is possible to prevent oxygen from diffusing from the semiconductor layer 520 to the substrate side. In this way, oxygen is supplied to the channel formation region of the semiconductor layer 520. Thereby, the oxygen deficiency of the semiconductor layer 520 can be reduced, and the normal ionization of the transistor can be suppressed.

[0311] As the insulating layer 554, for example, an insulating layer containing one or both of oxides of aluminum and hafnium may be formed. Note that, as the insulating layer containing one or both of oxides of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like can be used.

[0312] The insulating layer 580 is provided on the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, as the insulating layer 580, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are suitable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are suitable because they can easily form a region containing oxygen that desorbs by heating.

[0313] As the insulating layer 574, an insulating material that functions as a barrier insulating film for suppressing the mixing of impurities such as water or hydrogen into the insulating layer 580 from above, similar to the insulating layer 514 or the like, may be used. As the insulating layer 574, for example, an insulating material that can be used for the insulating layer 514, the insulating layer 554, or the like may be used.

[0314] In FIGS. 33(A) to 33(C), an example in which an insulating layer 581 that functions as an interlayer film is provided on the insulating layer 574 is shown. As the insulating layer 581, an insulating material with a reduced impurity concentration such as water or hydrogen, similar to the insulating layer 524 or the like, may be used.

[0315] The conductive layers 545a and 545b are disposed in each of the two openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554. The conductive layers 545a and 545b are provided to face each other with the conductive layer 560 interposed therebetween. Note that the height of the upper surfaces of the conductive layers 545a and 545b may be the same as the height of the upper surface of the insulating layer 581.

[0316] An insulating layer 541a is provided in contact with one inner wall of the two openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545a is formed in contact with the side surface thereof. The conductive layer 542a is located at at least a part of the bottom of the opening, and the conductive layer 545a is in contact with the conductive layer 542a. Similarly, an insulating layer 541b is provided in contact with the other inner wall of the two openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545b is formed in contact with the side surface thereof. The conductive layer 542b is located at at least a part of the bottom of the opening, and the conductive layer 545b is in contact with the conductive layer 542b.

[0317] As the conductive layers 545a and 545b, a conductive material mainly composed of tungsten, copper, or aluminum may be used. In addition, each of the conductive layers 545a and 545b may have a laminated structure of two or more layers.

[0318] When the conductive layer 545 has a laminated structure, a conductive layer having a function of suppressing the diffusion of impurities such as water or hydrogen may be used for the conductive layer in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like can be used. By using the conductive material, it is possible to suppress oxygen contained in the insulating layer 580 from being absorbed by the conductive layer 545a and the conductive layer 545b. In addition, it is possible to suppress impurities such as water or hydrogen from mixing into the semiconductor layer 520 through the conductive layer 545a and the conductive layer 545b from the upper layer of the insulating layer 581.

[0319] As the insulating layers 541a and 541b, for example, an insulating layer that can be used for the insulating layer 554 or the like may be used. Since the insulating layers 541a and 541b are provided in contact with the insulating layer 554, it is possible to suppress impurities such as water or hydrogen from mixing into the semiconductor layer 520 through the conductive layer 545a and the conductive layer 545b from the insulating layer 580 or the like. In addition, it is possible to suppress oxygen contained in the insulating layer 580 from being absorbed by the conductive layer 545a and the conductive layer 545b.

[0320] <Configuration Example 5 of Transistor> A modified example of the transistor 200D shown in FIG. 33 is shown in FIG. 34. FIG. 34(A) is a top view of a transistor 200E which is a modified example of the transistor 200D. FIG. 34(B) is a cross-sectional view taken along the line A1 - A2 indicated by the dashed line in FIG. 34(A). FIG. 34(C) is a cross-sectional view taken along the line A3 - A4 indicated by the dashed line in FIG. 34(A). Since the transistor 200E is a modified example of the transistor 200D, mainly the differences from the transistor 200D of the transistor 200E will be described.

[0321] The transistor 200E has a configuration obtained by removing the semiconductor layer 520c and the conductive layer 505c from the configuration of the transistor 200D. By reducing the components of the transistor, the production cost can be reduced. In addition, when the components of the transistor are reduced, the manufacturing process is shortened and the manufacturing yield is improved.

[0322] In addition, the transistor 200E has a region where the insulating layer 554 and the insulating layer 522 are in contact outside the semiconductor layer 520, and has a configuration in which the side surface of the insulating layer 524 is covered with the insulating layer 554. When an oxide semiconductor is used as the semiconductor layer 520, covering the side surface of the insulating layer 524 with the insulating layer 554 not only prevents oxygen from diffusing from the semiconductor layer 520 to the outside through the insulating layer 524, but also prevents excessive oxygen supply from the insulating layer 524 side to the semiconductor layer 520.

[0323] An insulating layer may be provided between the insulating layer 580, the insulating layer 554, the conductive layer 542, the semiconductor layer 520b, and the insulating layer 550. As the insulating layer, aluminum oxide, hafnium oxide, or the like can be used. By providing the insulating layer, desorption of oxygen from the semiconductor layer 520 to the insulating layer 550 side, excessive oxygen supply from the insulating layer 550 side to the semiconductor layer 520, oxidation of the conductive layer 542, and the like can be suppressed.

[0324] <Constituent Materials of Transistor> Subsequently, the constituent materials that can be used for the transistor 200 (transistor 200A, transistor 200B, transistor 200C, transistor 200D, and transistor 200E) will be described.

[0325] 〔Substrate〕 When a transistor is provided on a substrate, there are no major restrictions on the material used for the substrate. The material used for the substrate can be determined in consideration of the presence or absence of translucency and heat resistance that can withstand heat treatment, etc., according to the purpose. As the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. As the insulator substrate, for example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), etc. can be used. Also, as the substrate, a semiconductor substrate, a flexible substrate (flexible substrate), a resin substrate, etc. may be used.

[0326] Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or the like, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, such as a SOI (Silicon On Insulator) substrate. The semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.

[0327] Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there is a substrate having a metal nitride or a substrate having a metal oxide. Further, there is a substrate in which a conductive layer or a semiconductor layer is provided on an insulator substrate, a substrate in which a conductive layer or an insulating layer is provided on a semiconductor substrate, or a substrate in which a semiconductor layer or an insulating layer is provided on a conductor substrate.

[0328] Examples of materials such as flexible substrates or resin substrates include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, cellulose nanofiber, and the like can be used.

[0329] By using the above materials as the substrate, a lightweight semiconductor device can be provided. Also, by using the above materials as the substrate, a semiconductor device resistant to impact can be provided. Further, by using the above materials as the substrate, a semiconductor device that is difficult to break can be provided. Also, those in which elements are provided on these substrates may be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0330] 〔Insulating layer〕 For the insulating layer (insulating layer 202, insulating layer 204, insulating layer 206, insulating layer 209, insulating layer 257, insulating layer 258, insulating layer 259, insulating layer 264, insulating layer 266, insulating layer 516, insulating layer 522, insulating layer 524, insulating layer 541, insulating layer 554, insulating layer 580, insulating layer 574, insulating layer 581, etc.), an inorganic insulating film can be used. Examples of the inorganic insulating film include an insulating oxide film, an insulating nitride film, an oxynitride insulating film, and a nitroxide insulating film. Examples of the insulating oxide film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of the insulating nitride film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, a yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitroxide insulating film include a silicon nitroxide film and an aluminum nitroxide film. In addition, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0331] In this specification, etc., oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and nitroxide refers to a material having a higher nitrogen content than oxygen in its composition. For example, when silicon oxynitride is described, it refers to a material having a higher oxygen content than nitrogen in its composition, and when silicon nitroxide is described, it refers to a material having a higher nitrogen content than oxygen in its composition. The content of each element can be measured using, for example, the Rutherford Backscattering Spectrometry (RBS).

[0332] For example, as the miniaturization and high integration of transistors progress, problems such as gate leakage current may occur due to the thinning of the gate insulating film. By using a material with a high relative permittivity (high-k) for the insulating layer that functions as a gate insulating film such as insulating layer 204 and insulating layer 202, it becomes possible to lower the voltage during transistor operation while maintaining the physical film thickness. Also, it becomes possible to thin the equivalent oxide thickness (EOT) of the gate insulating film. Further, by using a material with a high relative permittivity for the insulating layer that functions as the dielectric of the capacitor element, the capacitance per unit area can be increased. On the other hand, by using a material with a low relative permittivity for the insulating layer that functions as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, materials can be selected according to the function of the insulating layer. Note that a material with a low relative permittivity is also a material with high dielectric strength.

[0333] Examples of materials with a high relative permittivity include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, aluminum and hafnium-containing oxynitrides, silicon and hafnium-containing oxides, silicon and hafnium-containing oxynitrides, and silicon and hafnium-containing nitrides.

[0334] Examples of materials with a low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Also, other inorganic insulating materials with a low relative permittivity include, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen. Also, for example, silicon oxide having pores can be mentioned. Note that these silicon oxides may contain nitrogen.

[0335] 〔Conductive layer〕 For the conductive layers (such as conductive layer 205, conductive layer 208, conductive layer 219, conductive layer 255, conductive layer 261, conductive layer 265, conductive layer 505, conductive layer 545, conductive layer 560, etc.) used in transistor 200, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing the above metal element as a component, or an alloy combining the above metal elements. As the alloy containing the above metal element as a component, a nitride or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Also, a semiconductor with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0336] Further, it is preferable to use a conductive material that is difficult to be oxidized, a conductive material having a function of suppressing the diffusion of oxygen, or a material that maintains conductivity even when absorbing oxygen. Examples of such materials include nitrogen-containing conductive materials such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum. Further, oxygen-containing conductive materials such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel can be mentioned. In addition, materials containing metal elements such as titanium, tantalum, or ruthenium can be mentioned. Note that, as the oxygen-containing conductive material, materials containing tungsten oxide and indium oxide, materials containing titanium oxide and indium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide can be mentioned. In this specification and the like, a conductive layer formed using an oxygen-containing conductive material may be referred to as an oxide conductive layer.

[0337] Further, as a material having a high conductivity, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum.

[0338] Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure combining the material containing the above-described metal element and the oxygen-containing conductive material may be used. Further, a laminated structure combining the material containing the above-described metal element and the nitrogen-containing conductive material may be used. Further, a laminated structure combining the material containing the above-described metal element, the oxygen-containing conductive material, and the nitrogen-containing conductive material may be used.

[0339] For example, in the case of using an oxide semiconductor, which is a type of metal oxide, for the semiconductor layer 203 in the transistor 200A or the transistor 200B, a stacked structure combining the material containing the above-described metal element and the conductive material containing oxygen may be used for the conductive layer that functions as a gate electrode such as the conductive layer 205 and the conductive layer 219. In this case, the conductive material containing oxygen may be provided on the semiconductor layer 203 side. By providing the conductive material containing oxygen on the semiconductor layer 203 side, the oxygen desorbed from the conductive material is easily supplied to the channel formation region of the semiconductor layer 203.

[0340] Also, in the case of using an oxide semiconductor, which is a type of metal oxide, for the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520, the conductive layers 208a, 208b, 255, 261, 542a, and 542b in contact with the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520 may each use a conductive material that is difficult to be oxidized, a conductive material whose electrical resistance is kept low even when oxidized, a conductive metal oxide (also referred to as an oxide conductor), or a conductive material having a function of suppressing the diffusion of oxygen. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. Thereby, it is possible to suppress a decrease in the conductivity of the conductive layers 208a, 208b, 255, 261, 542a, and 542b.

[0341] By using a conductive material containing oxygen as the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b, the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b can maintain conductivity even when absorbing oxygen. For example, even when using an insulating layer containing excess oxygen as the insulating layer in contact with the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b, the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b are suitable because they can maintain conductivity. As each of the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b, for example, ITO, ITSO, IZO (registered trademark), etc. can be used.

[0342] 〔Semiconductor layer〕 As the semiconductor layer (such as the semiconductor layer 203, the semiconductor layer 263, the semiconductor layer 520, etc.), a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor, etc. can be used alone or in combination.

[0343] As the semiconductor layer, a semiconductor composed of a single element or a compound semiconductor may be used. Examples of the semiconductor composed of a single element include silicon and germanium. Examples of the compound semiconductor include gallium arsenide, silicon carbide, and silicon germanium. In addition, examples of the compound semiconductor include organic semiconductors and nitride semiconductors. Note that an oxide semiconductor is also a kind of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.

[0344] When using silicon as the semiconductor layer, examples of the silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of the polycrystalline silicon include low temperature poly silicon (LTPS).

[0345] For example, in transistor 200A or transistor 200B, silicon is used for the semiconductor layer 203, and phosphorus or arsenic is included as an n-type dopant in regions 203a and 203c of the semiconductor layer 203, so that the transistor can function as an n-type transistor. Also, by including boron as a p-type dopant in regions 203a and 203c of the semiconductor layer 203, the transistor can function as a p-type transistor. Note that when both an n-type dopant and a p-type dopant are included in regions 203a and 203c of the semiconductor layer 203, the conductivity type with the higher dopant concentration is more likely to appear.

[0346] Also, as the semiconductor layer, a two-dimensional material that functions as a semiconductor may be used. A two-dimensional material is also called a layered material and is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than covalent bonds or ionic bonds, such as van der Waals bonds. Layered materials have high conductivity within the unit layer, that is, high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity for the semiconductor layer, a transistor with a large on-current can be provided.

[0347] Examples of the above-mentioned layered materials include graphene, silicene, chalcogenides, etc. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Also, examples of chalcogenides include transition metal chalcogenides, Group 13 chalcogenides, etc. Specific examples of transition metal chalcogenides applicable as the semiconductor layer include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc.

[0348] In addition, an oxide semiconductor, which is a kind of metal oxide, may be used as the semiconductor layer. At this time, the band gap of the metal oxide is preferably 2.0 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap as the semiconductor layer, the off-current of the transistor can be significantly reduced. Since the OS transistor has a small off-current, the power consumption of the semiconductor device can be reduced.

[0349] In a transistor using an oxide semiconductor for the semiconductor layer, the channel formation region of the transistor preferably has less oxygen deficiency or a lower impurity concentration (for example, the concentration of hydrogen, nitrogen, and metal elements, etc.) than the source region and the drain region. Also, due to hydrogen near the oxygen deficiency, V O H (a defect in which hydrogen enters the oxygen deficiency) may be formed and electrons serving as carriers may be generated. Therefore, it is also preferable that there is less V O H. Thus, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, it can be said that the channel formation region of the transistor is of i-type (intrinsic) or substantially i-type.

[0350] In addition, the source region and the drain region of the transistor preferably have more oxygen deficiency, more V O H, or a higher impurity concentration than the channel formation region. Thus, the source region and the drain region of the transistor are regions with a higher carrier concentration and lower resistance, which are n-type regions compared to the channel formation region.

[0351] The oxide semiconductor will be described in detail in Embodiment 3 described later.

[0352] Note that the described contents of this embodiment can be implemented by appropriately combining them with each other. Also, the described contents of this embodiment can be implemented by appropriately combining them with the described contents of other embodiments and the like.

[0353] (Embodiment 3) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one aspect of the present invention will be described.

[0354] <Oxide semiconductor layer> The oxide semiconductor layer preferably has a crystalline metal oxide. Examples of the structure of the crystalline metal oxide include a CAAC (c-axis aligned crystal) structure, a poly-crystal structure, and an nc (nano-crystal) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect levels in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor using the oxide semiconductor layer can be improved, and the reliability of a semiconductor device on which the transistor is mounted can be improved.

[0355] In particular, the oxide semiconductor layer preferably has a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and, in the a-b plane, the plurality of microcrystals are connected without being oriented. Further, when observing a cross section of an oxide semiconductor layer having a CAAC structure using a high-resolution transmission electron microscope (TEM: Transmission Electron Microscope) image, it can be confirmed that metal atoms are arranged in layers in the crystal portion. Therefore, it can be said that the oxide semiconductor layer having a CAAC structure has a structure having a layered crystal portion.

[0356] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, analysis may be performed by combining a plurality of these methods.

[0357] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), or a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystal region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0358] Examples of the metal oxide include indium oxide, gallium oxide, and zinc oxide. Further, the metal oxide preferably contains at least indium (In). Further, the metal oxide preferably contains at least indium (In) or zinc (Zn). Further, the metal oxide preferably has two or three selected from indium, element M, and zinc. Note that element M is a metal element or a semimetal element having a high bond energy with oxygen, for example, a metal element or a semimetal element having a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. Element M included in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and still more preferably gallium. When element M is gallium, the metal oxide preferably has any one or more selected from indium, gallium, and zinc. Note that in this specification and the like, a metal element and a semimetal element may be collectively referred to as a "metal element", and the "metal element" described in this specification and the like may include a semimetal element.

[0359] Examples of the metal oxide include, for example, indium oxide. Further, examples of the metal oxide include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (also referred to as In-Ga-Sn oxide, IGTO), gallium zinc oxide (also referred to as Ga-Zn oxide, GZO), aluminum zinc oxide (also referred to as Al-Zn oxide, AZO), indium aluminum zinc oxide (also referred to as In-Al-Zn oxide, IAZO), indium tin zinc oxide (also referred to as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (also referred to as In-Ga-Zn oxide, IGZO), indium gallium tin zinc oxide (also referred to as In-Ga-Sn-Zn oxide, IGZTO), indium gallium aluminum zinc oxide (also referred to as In-Ga-Al-Zn oxide, IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide containing silicon oxide (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be mentioned.

[0360] By increasing the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide (also referred to as the indium (In) content rate), the transistor can obtain a large on-current and high frequency characteristics.

[0361] Note that the metal oxide may have one or more kinds of metal elements with a large periodic number in the periodic table instead of indium. Or, the metal oxide may have one or more kinds of metal elements with a large periodic number in the periodic table in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the tendency for carrier conduction in the metal oxide. Therefore, including a metal element with a large periodic number in the periodic table may increase the field-effect mobility of the transistor. Examples of the metal element with a large periodic number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specifically, examples of the metal element include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0362] In addition, the metal oxide may have one or more kinds of non-metal elements. By having a non-metal element in the metal oxide, the field-effect mobility of the transistor may be increased. Examples of the non-metal element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0363] In addition, by increasing the ratio of the number of zinc atoms to the sum of the number of atoms of all the metal elements contained in the metal oxide, a highly crystalline metal oxide is obtained, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and the reliability can be improved.

[0364] In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all the metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies is suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor are suppressed, and the reliability can be improved.

[0365] In this embodiment, indium-gallium-zinc oxide may be cited as an example of the metal oxide for description.

[0366] 〔Fabrication method〕 The oxide semiconductor layer can be fabricated by forming a metal oxide using one film formation method, or can also be fabricated by forming a metal oxide using at least two film formation methods. For example, the oxide semiconductor layer can be fabricated by forming a metal oxide using the first film formation method or the second film formation method, or can also be fabricated by forming a metal oxide using the first film formation method and the second film formation method. Note that an oxide semiconductor layer formed using at least two film formation methods may be referred to as a Hybrid OS.

[0367] The oxide semiconductor layer can be fabricated by forming a metal oxide as the first layer using the first film formation method, and then forming a metal oxide as the second layer on the first layer using the second film formation method. At this time, it is preferable to use, as the first film formation method, a film formation method that causes less damage to the surface to be formed than the second film formation method. By using a film formation method that causes less damage to the surface to be formed as the first film formation method, formation of a mixed layer at the interface between the oxide semiconductor layer and the layer that is the surface to be formed of the oxide semiconductor layer can be suppressed. In addition, since impurities such as silicon can be prevented from being mixed into the second layer, the crystallinity of the oxide semiconductor layer can be increased.

[0368] As the first film formation method, for example, the atomic layer deposition (ALD) method, the chemical vapor deposition (CVD) method, the molecular beam epitaxy (MBE) method, the wet method, etc. can be mentioned. As the CVD method, for example, the plasma CVD (PECVD) method, the thermal CVD method, the photo CVD method, the metal organic CVD (MOCVD) method, etc. can be mentioned. As the wet method, for example, the spray coating method, etc. can be mentioned. The ALD method and the CVD method are suitable as the first film formation method because they can suppress damage to the surface to be formed as compared with the sputtering method described later.

[0369] As the ALD method, the thermal ALD method that performs the reaction of the precursor and the reactant only with thermal energy and the plasma enhanced ALD (PEALD) method that uses a plasma-excited reactant can be mentioned.

[0370] Since the ALD method can deposit atoms one layer at a time, it has the following effects: it enables the formation of extremely thin films, enables film formation on structures with a high aspect ratio or surfaces with large steps, enables film formation with few defects such as pinholes, enables film formation with excellent coverage, and enables film formation at low temperatures. In addition, the PEALD method may be preferable because it can perform film formation at a lower temperature by utilizing plasma. Note that some of the precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, the film formed by the ALD method may contain more elements such as carbon or chlorine compared to the film formed by other film formation methods. The quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). When one or both of the adoption of high substrate temperature conditions during film formation and the implementation of impurity removal treatment are applied to the ALD method, the amount of carbon and chlorine contained in the film may be less than when the ALD method is used without applying these.

[0371] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of the object to be processed. Therefore, it is less affected by the shape of the object to be processed and is a film formation method having good step coverage. In particular, since the ALD method has excellent step coverage and excellent thickness uniformity, it is suitable for covering the surface of an opening with a high aspect ratio.

[0372] The plasma CVD method can obtain high-quality films at relatively low temperatures. In addition, since the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to the object to be processed. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0373] As a second film formation method, for example, a sputtering method, a pulsed laser deposition (PLD) method, or the like can be mentioned. The metal oxide formed using the second film formation method is likely to have a CAAC structure.

[0374] Here, as the first layer, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure may be formed. Even in such a case, by forming a second layer (for example, CAAC) with high crystallinity on the first layer with low crystallinity, or forming it and then applying heat treatment, the crystallinity of the first layer may increase with the second layer as a nucleus. Thereby, the crystallinity can be enhanced throughout the oxide semiconductor layer including the vicinity of the interface with the surface to be formed.

[0375] In addition, a third layer can be further formed on the second layer. Since the second layer has high crystallinity, the third layer can grow crystallographically with the crystals of the second layer as nuclei or seeds. Therefore, even when a film formation method that is not likely to have crystallinity is used as the film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method with higher coating properties than the second layer, the oxide semiconductor layer can have both high crystallinity and high coating properties throughout the layer.

[0376] The oxide semiconductor layer can be produced, for example, by forming a metal oxide using the first film formation method as the first layer, then forming a metal oxide using the second film formation method as the second layer, and forming a metal oxide using the first film formation method as the third layer. Specifically, the ALD method can be used as the first film formation method, and the sputtering method can be used as the second film formation method. The ALD method is a film formation method with excellent coating properties compared to the sputtering method. By using the ALD method as the film formation method for the first layer and the third layer, the coating properties of the oxide semiconductor layer can be enhanced. Therefore, the oxide semiconductor layer can be well coated on steps, openings, etc. with a high aspect ratio.

[0377] An example of a method for manufacturing the semiconductor layer 230 will be described with reference to FIGS. 35(A) to 35(D) and FIGS. 36(A) to 36(D).

[0378] When a metal oxide film is formed by a sputtering method, alloying may occur between the components contained in the metal oxide film and the components contained in the layer to be formed due to damage caused by sputtering particles or energy applied to the substrate side by sputtering particles or the like to the surface to be formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when the heat treatment described later is performed. In addition, using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between the components contained in the metal oxide film and the components contained in the layer to be formed.

[0379] Therefore, first, a semiconductor layer 230a is formed on the layer 229 using the ALD method (FIG. 35(A)). Subsequently, a semiconductor layer 230b is formed on the semiconductor layer 230a using the sputtering method (FIG. 35(B)).

[0380] In the method for manufacturing the oxide semiconductor layer according to the present embodiment, since the semiconductor layer 230a is formed between the semiconductor layer 230b and the layer 229 using a film formation method with less damage to the surface to be formed, alloying between the components contained in the semiconductor layer 230 and the components contained in the layer 229 can be suppressed, and the crystallinity of the semiconductor layer 230 can be made higher.

[0381] By adopting the above configuration, the thickness of the alloyed region can be reduced, or can be reduced to such an extent that it is difficult to observe the alloyed region. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and still more preferably 0 nm or more and less than 0.3 nm. Note that FIGS. 35(A) and 35(B) show examples in which no alloyed region is formed between the layer 229 and the semiconductor layer 230a.

[0382] Note that the thickness of the alloyed region can sometimes be calculated by performing line analysis of the composition by secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX) on the region and its periphery.

[0383] For example, with the direction perpendicular to the formation surface of the semiconductor layer 230a as the depth direction, EDX line analysis is performed on the above region and its periphery. Next, in the profile of the quantitative values of each element with respect to the depth direction obtained by the analysis, the depth at which the quantitative value of a metal (In if the semiconductor layer 230a contains In) that is the main component of the semiconductor layer 230a and not the main component of the layer that becomes the formation surface (here, the layer 229) becomes half value is defined as the depth (position) of the interface between the above region and the semiconductor layer 230a. Also, the depth at which the quantitative value of an element (for example, Si) that is the main component of the layer that becomes the formation surface and not the main component of the semiconductor layer 230a becomes half value is defined as the depth (position) of the interface between the above region and the layer that becomes the formation surface. Thus, the thickness of the alloyed region can be calculated.

[0384] In the case of observing the thickness of the alloyed region in the oxide semiconductor layer by EDX analysis, for example, the thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and still more preferably 0 nm or more and less than 0.3 nm.

[0385] For example, when performing SIMS analysis of the semiconductor layer 230 formed on the silicon oxide layer as the layer 229, the depth at which the silicon concentration becomes 50% of the maximum value of the concentration of the layer 229 is defined as the interface, and the distance between the depth at which the silicon concentration decreases to 1.0×10 21 atoms / cm 3 , preferably 5.0×10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 and the interface is defined as the thickness t_s2. The thickness t_s2 is preferably 3 nm or less, more preferably 2 nm or less.

[0386] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0387] Note that by reducing the thickness of the alloyed region, it becomes possible to form a CAAC structure near the surface to be formed. Here, the vicinity of the surface to be formed refers to, for example, a region that is more than 0 nm and 3 nm or less, preferably more than 0 nm and 2 nm or less, and more preferably 1 nm or more and 2 nm or less perpendicular to the surface to be formed of the semiconductor layer 230.

[0388] Note that the CAAC structure in the vicinity of the surface to be formed may be confirmed in an observation using TEM. For example, in a cross-sectional observation using a high-resolution TEM of the semiconductor layer 230, bright spots arranged in layers in a direction parallel to the surface to be formed are confirmed in the vicinity of the surface to be formed.

[0389] Note that when forming the semiconductor layer 230a using the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure may be formed. That is, in the manufacturing stage shown in FIG. 35(A), the semiconductor layer 230a may have a region with lower crystallinity than the semiconductor layer 230b.

[0390] The semiconductor layer 230b is preferably made to have a composition suitable for forming a CAAC structure.

[0391] When forming the semiconductor layer 230b using a sputtering method, a mixed layer 231 is formed on or near the surface of the semiconductor layer 230a. Also, due to the energy applied to the substrate side by sputtering particles or the like during the formation of the semiconductor layer 230b, minute crystal regions may be formed in the mixed layer 231. In subsequent heat treatment steps, the mixed layer 231 or the minute crystal regions formed in the mixed layer 231 may serve as nuclei, and at least a part of the semiconductor layer 230a may crystallize.

[0392] In the film formation of the semiconductor layer 230b using a sputtering method, it is preferable to heat the substrate. In the formation of a metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, a metal oxide with high crystallinity may be formed.

[0393] Next, a semiconductor layer 230c is formed on the semiconductor layer 230b using an ALD method (FIG. 35(C)). The formation of the semiconductor layer 230c using the ALD method can refer to the formation method of the semiconductor layer 230a.

[0394] When forming the semiconductor layer 230c on the semiconductor layer 230b having a CAAC structure using an ALD method, the semiconductor layer 230c may epitaxially grow with the semiconductor layer 230b as a nucleus. Therefore, when forming the semiconductor layer 230c, the semiconductor layer 230c may have a region having a CAAC structure. Also, it is preferable that the region having a CAAC structure is formed over the entire semiconductor layer 230c.

[0395] Next, a heat treatment step may be performed. By this heat treatment step, the crystallinity of the region having a CAAC structure in the semiconductor layer 230c may be enhanced. Also, when the region is formed only below the semiconductor layer 230c after film formation by the ALD method, the region may spread upward by this heat treatment step (FIG. 35(D)). That is, by performing the heat treatment, a region having a CAAC structure may be formed over the entire layer in the semiconductor layer 230c.

[0396] Also, it is preferable that at least a part of the semiconductor layer 230a is CAAC-ized by the heat treatment step (FIG. 35(D)). In the CAAC-ization, the mixed layer 231 formed in the semiconductor layer 230a serves as nuclei or seeds in the formation of the semiconductor layer 230b, and the possibility of occurrence is increased. It is preferable that the region CAAC-ized in the semiconductor layer 230a is wide, and it is preferable that CAAC-ization reaches the vicinity of the layer 229.

[0397] Also, in order for the semiconductor layer 230a to be CAAC-ized from the upper part to the lower part, it is possible to CAAC-ize up to the vicinity of the layer 229 without being limited to the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, a highly crystalline semiconductor layer 230a can be formed. Therefore, the method for manufacturing an oxide semiconductor layer shown in this embodiment is particularly suitable when the layer to be formed has an amorphous structure.

[0398] Note that FIGS. 35(A) to 35(D) are cross-sectional views for explaining a method of forming a metal oxide. Also, FIGS. 35(A) to 35(D) can be regarded as conceptual diagrams showing a film formation model of a metal oxide. As shown in FIGS. 35(A) to 35(D), the semiconductor layer 230a and the semiconductor layer 230c each have high crystallinity with the highly crystalline semiconductor layer 230b as nuclei or seeds. Specifically, the crystallinity of the semiconductor layer 230a may increase during the formation of the semiconductor layer 230b or by heat treatment after the formation of the semiconductor layer 230c. Also, the crystallinity of the semiconductor layer 230c may increase during the formation of the semiconductor layer 230c or by heat treatment after the formation of the semiconductor layer 230c. Note that the above heat treatment has a function of assisting in increasing crystallinity.

[0399] Thus, in the method for forming a metal oxide film according to this embodiment, the crystallinity of the upper and lower oxide semiconductors (here, semiconductor layer 230a and semiconductor layer 230c) can be increased using the highly crystalline semiconductor layer 230b (e.g., CAAC) as a nucleus or seed. Thereby, the crystallinity of the entire oxide semiconductor can be increased. In other words, using the semiconductor layer 230b as a nucleus or seed, the upper and lower oxide semiconductors can be solid-phase grown to form a highly crystalline oxide semiconductor. An oxide semiconductor formed using such a film-forming method, here a CAAC film, can be referred to as Axial Growth CAAC (AG CAAC). Note that in FIGS. 36(A) to 36(D), a configuration having the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c is illustrated, but the present invention is not limited thereto. For example, even in a configuration having the semiconductor layer 230a and the semiconductor layer 230b, it can be referred to as AG CAAC.

[0400] In the semiconductor layer 230, it is preferable that a region having a CAAC structure widely exists over the entire layer. FIG. 36(A) shows a state in which the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c are each crystallized. At this time, the boundary between the semiconductor layer 230a and the semiconductor layer 230b may not be observed. Also, the boundary between the semiconductor layer 230b and the semiconductor layer 230c may not be observed. In some cases, the semiconductor layer 230 can be expressed as one layer in which the interface is not clearly observed. In some cases, the semiconductor layer 230 can be expressed as a single layer.

[0401] In addition, a part of the semiconductor layer 230a or the semiconductor layer 230c may not be crystallized. The example shown in FIG. 36(B) shows a state in which the vicinity of the interface with the layer 229 in the semiconductor layer 230a is not crystallized. FIG. 36(C) shows a state in which the vicinity of the surface in the semiconductor layer 230c is not crystallized. FIG. 36(D) shows a state in which the vicinity of the interface of the semiconductor layer 230a with the layer 229 and the vicinity of the surface of the semiconductor layer 230c are not crystallized, respectively.

[0402] By enhancing the crystallinity of the oxide semiconductor layer, the initial characteristics (especially the on-current) of a transistor using the oxide semiconductor layer can be improved, enabling a transistor suitable for high-speed driving. Also, the reliability of the transistor can be enhanced and the on-current can be increased.

[0403] The oxide semiconductor layer shown in this embodiment has high crystallinity throughout the layer. Therefore, in the semiconductor layer 230, it may be difficult to confirm the boundaries between the stacked films of the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c. In particular, after performing heat treatment, it may be difficult to confirm the boundaries between the stacked films. Confirmation of the presence or absence of boundaries between the stacked films can be performed using, for example, TEM.

[0404] Here, by using a metal oxide with a high In content in a transistor, the field-effect mobility of the transistor can be increased. On the other hand, an oxide semiconductor with a high In content tends to polycrystallize. Using a metal oxide with a polycrystalline structure in a transistor can have an adverse effect on the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the semiconductor layer 230a and the semiconductor layer 230c, a crystal in which the crystal orientation of the semiconductor layer 230b is reflected is formed, and polycrystallization can be suppressed.

[0405] At this time, it is preferable that the lattice mismatch between the crystal of the semiconductor layer 230b and the crystal of the semiconductor layer 230a or the semiconductor layer 230c is small. Thereby, the semiconductor layer 230a or the semiconductor layer 230c can form a crystal in which the crystal orientation of the semiconductor layer 230b is reflected. At this time, for example, in a cross-sectional observation using a high-resolution TEM of the semiconductor layer 230, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the semiconductor layer 230a or the semiconductor layer 230c.

[0406] If the lattice mismatch between the crystal of the semiconductor layer 230b and the crystal of the semiconductor layer 230a or the semiconductor layer 230c is small, the crystal structure of the semiconductor layer 230a or the semiconductor layer 230c is not particularly limited. The crystal structure of the semiconductor layer 230a or the semiconductor layer 230c may be any of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0407] 〔Composition〕 The semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. For example, a sputtering method can be used to form the semiconductor layer 230b. The semiconductor layer 230b preferably contains zinc, for example. By containing zinc, a highly crystalline metal oxide is obtained. Further, the semiconductor layer 230b preferably contains an element M in addition to zinc. By the semiconductor layer 230b containing the element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of a transistor to which the oxide semiconductor layer is applied can be improved. Specifically, as the semiconductor layer 230b, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, In:M:Zn = 1:1:1.2 [atomic ratio] or in the vicinity thereof, In:M:Zn = 1:1:0.5 [atomic ratio] or in the vicinity thereof, In:M:Zn = 1:1:2 [atomic ratio] or in the vicinity thereof, In:M:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, In:M:Zn = 1:3:2 [atomic ratio] or in the vicinity thereof, or In:M:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof may be used. Here, the composition in the vicinity means a range including plus or minus 30% of the desired atomic ratio. Further, as the element M, it is preferable to use one or more of gallium, aluminum, and tin.

[0408] Further, the semiconductor layer 230b may have a configuration that does not contain the element M. For example, it may be an In-Zn oxide. Specifically, the composition may be In:Zn = 1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn = 2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn = 4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, the semiconductor layer 230b may have a configuration that does not contain the element M and Zn. For example, indium oxide may be used. Further, it may have a configuration that contains a trace amount of the element M. For example, the composition may be In:Ga:Zn = 4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Ga:Zn = 2:0.1:1 [atomic ratio] or a composition in the vicinity thereof. Also, for example, the composition may be In:Sn:Zn = 4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn = 2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0409] The semiconductor layer 230a and the semiconductor layer 230c can be metal oxides with a high proportion of In. For example, the ALD method can be used to form the semiconductor layer 230a and the semiconductor layer 230c. In particular, it is preferable to use a metal oxide in which the proportion of In is higher than that of the element M. By using a metal oxide with a high proportion of In, when the oxide semiconductor layer is applied to a transistor, the on-current can be increased and the frequency characteristics can be improved.

[0410] Further, the semiconductor layers 230a and 230c may be configured not to contain the element M. For example, they may be In-Zn oxide. Specifically, the composition may be In:Zn = 1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn = 2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn = 4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, the semiconductor layers 230a and 230c may be configured not to contain the element M and Zn. For example, indium oxide may be used. Further, the semiconductor layers 230a and 230c may be configured to contain a trace amount of the element M. Specifically, the composition may be In:Ga:Zn = 4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Ga:Zn = 2:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Sn:Zn = 4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn = 2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0411] Note that by increasing the atomic ratio of zinc contained in the oxide semiconductor, the crystallinity of the oxide semiconductor can be improved. In particular, it is preferable that the semiconductor layer 230a contains zinc. For example, when the semiconductor layer 230a is formed by ALD and the semiconductor layer 230b is formed by sputtering, zinc contained in the semiconductor layer 230a may diffuse into the semiconductor layer 230b. Note that such diffusion may occur during sputtering or subsequent heat treatment. By diffusing zinc from the semiconductor layer 230a to the semiconductor layer 230b, the crystallinity can be improved in the semiconductor layer 230b. Alternatively, by diffusing zinc from the semiconductor layer 230a to the semiconductor layer 230b, the lateral growth of the crystal portion having c-axis orientation in the semiconductor layer 230b can promote the CAAC formation.

[0412] Further, the semiconductor layers 230a and 230c can be metal oxides having a higher ratio of In compared to the semiconductor layer 230b.

[0413] For example, as the semiconductor layers 230a and 230c, metal oxides with a higher Ga ratio compared to the semiconductor layer 230b can also be used. For example, for the semiconductor layers 230a and 230c, metal oxides with a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, metal oxides with a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or in the vicinity thereof, or metal oxides with a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof are preferably used. By increasing the ratio of Ga, for example, the band gaps of the semiconductor layers 230a and 230c may be made larger than that of the semiconductor layer 230b respectively. Thereby, the semiconductor layer 230b is sandwiched between the semiconductor layers 230a and 230c with large band gaps, and the semiconductor layer 230b mainly functions as a current path. By sandwiching the semiconductor layer 230b between the semiconductor layers 230a and 230c, the trap levels at the interface of the semiconductor layer 230b and in the vicinity thereof can be reduced. Thereby, an embedded channel type transistor in which the channel is separated from the insulator interface can be realized, and the field effect mobility can be increased.

[0414] Also, as the semiconductor layers 230a and 230c, even when a composition that is difficult to form a CAAC structure in a single layer formation is used, crystal growth occurs with the semiconductor layer 230b as a nucleus, so that the entire oxide semiconductor layer including the semiconductor layers 230a and 230c can have a CAAC structure. Alternatively, a structure having a CAAC structure can be adopted in a region including at least a part of each of the semiconductor layers 230a and 230c and in a region spanning the semiconductor layer 230b.

[0415] In particular, even in a composition with a high In ratio in the semiconductor layers 230a and 230c, suitable crystallinity can be achieved as the semiconductor layer of the transistor. In the oxide semiconductor layer shown in this embodiment, it is possible to achieve both an improvement in the on characteristics of the transistor by increasing the ratio of In and an improvement in reliability by forming a highly crystalline CAAC structure.

[0416] Note that the compositions of the semiconductor layer 230a and the semiconductor layer 230c may be different.

[0417] Also, the semiconductor layer 230a and the semiconductor layer 230c may use a metal oxide having the same composition as the semiconductor layer 230b.

[0418] In this way, by using the oxide semiconductor layer having the CAAC structure formed by the above-described two film formation methods in the channel formation region of the transistor, a transistor having excellent characteristics (for example, a transistor having a large on-current, a transistor having a high field-effect mobility, a transistor having a small S value, a transistor having high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0419] Note that, for the analysis of the composition of the metal oxide used for the semiconductor layer 230, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, analysis may be performed by combining a plurality of these methods. Note that, for an element having a low content, the content obtained by analysis may be different from the actual content due to the influence of the analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0420] 〔Crystallinity〕 The degree of crystallinity of the oxide semiconductor layer can be evaluated, for example, using crystal orientation.

[0421] The crystal orientation can be obtained from the FFT pattern obtained by performing fast Fourier transform (FFT) processing on the TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by the FFT processing reflects the reciprocal lattice space information similar to the electron beam diffraction pattern.

[0422] By performing FFT processing on each region within the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, within a certain area range, by obtaining the crystal orientation for each region, a map showing the crystal orientation can be formed. Specifically, in the FFT pattern of a region having a layered crystal part, two spots with high intensity are observed. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0423] In the map showing the crystal orientation, the c-axis orientation ratio can be calculated by calculating the ratio of the region oriented along the c-axis.

[0424] In the oxide semiconductor layer, the c-axis orientation ratio can be calculated, for example, by performing TEM observation on the cross-section or plane of the oxide semiconductor layer. Also, the region where FFT is performed (also referred to as the FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0425] In the oxide semiconductor layer, when calculating the ratio of the region where the difference from the c-axis is within 20° as the c-axis orientation ratio, the c-axis orientation ratio is 60% or more, preferably 70% or more, more preferably 80% or more, still more preferably 90% or more, and even more preferably 95% or more.

[0426] Also, let the c-axis orientation ratios of the regions where the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c are formed be Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more. It is preferable that Rc3 / Rc1 is greater than 1. Also, it is preferable that Rc2 / Rc1 is greater than 1.

[0427] Note that, after fabrication, the boundaries between the semiconductor layers 230a, 230b, and 230c may not be clearly observed in the semiconductor layer 230.

[0428] The semiconductor layer 230 can be divided into three regions: a first region, a second region, and a third region, in this order from above the layer 229. Each region is a layered region.

[0429] The first region, the second region, and the third region each have a CAAC structure. Also, it is preferable that the c-axis orientation ratio of the third region is higher than the c-axis orientation ratio of the first region. Also, it is preferable that the c-axis orientation ratio of the second region is higher than the c-axis orientation ratio of the first region. Also, the c-axis orientation ratios of the second region and the third region are each 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0430] The first region is located from 0 nm to 3 nm above the upper surface of the layer 229, and the third region is located from 0 nm to 3 nm above the upper surface of the semiconductor layer 230.

[0431] Alternatively, the thicknesses of the layers in each region are, for example, the same.

[0432] Note that the described contents of this embodiment can be implemented in appropriate combination with each other. Also, the described contents of this embodiment can be implemented in appropriate combination with the described contents of other embodiments and the like.

[0433] (Embodiment 4) In this embodiment, an example of the layout when applying the transistor shown in Embodiment 2 described above to the drive circuit shown in Embodiment 1 described above will be described.

[0434] <Layout Example> FIG. 37 is a top view showing an example of the layout when the transistor 200A shown in FIG. 30 is applied as the transistor constituting the drive circuit 100 shown in FIG. 1 described above. FIG. 38(A) is a cross-sectional view taken along the line A1 - A2 indicated by the dashed-dotted line in FIG. 37. FIG. 38(B) is a cross-sectional view taken along the line A3 - A4 indicated by the dashed-dotted line in FIG. 37.

[0435] In FIG. 37 and the like, a semiconductor layer 203_1, a semiconductor layer 203_2, a semiconductor layer 203_3, a semiconductor layer 203_4, a semiconductor layer 203_5, a semiconductor layer 203_6, and a semiconductor layer 203_7 corresponding to the semiconductor layer 203 on the insulating layer 202 are illustrated. Also, a conductive layer 205_1, a conductive layer 205_2, a conductive layer 205_3, a conductive layer 205_4, a conductive layer 205_5, and a conductive layer 205_6 corresponding to the conductive layer 205 on the insulating layer 204 are illustrated. Further, a conductive layer 208_1, a conductive layer 208_2, a conductive layer 208_3, a conductive layer 208_4, a conductive layer 208_5, a conductive layer 208_6, a conductive layer 208_7, and a conductive layer 208_8 corresponding to the conductive layer 208 on the insulating layer 206 are illustrated.

[0436] Each of the semiconductor layer 203_1, the semiconductor layer 203_2, the semiconductor layer 203_3, and the semiconductor layer 203_4 has a region that functions as a channel formation region of the transistor Mg1 and a region that functions as a channel formation region of the transistor Mg2. The semiconductor layer 203_5 has a region that functions as a channel formation region of the transistor Mb2 and a region that functions as a channel formation region of the transistor Mb3. Each of the semiconductor layer 203_6 and the semiconductor layer 203_7 has a region that functions as a channel formation region of the transistor Mb1.

[0437] The conductive layer 205_1 has a region that functions as the gate of the transistor Mg1, a region that functions as the other terminal of the capacitor element Cg1, and a region that functions as the wiring NLg1. The conductive layer 205_2 has a region that functions as the gate of the transistor Mg2 and a region that functions as the wiring NLg2. The conductive layer 205_3 has a region that functions as one terminal of the capacitor element Cb1 and a region that functions as the wiring OL. The conductive layer 205_4 has a region that functions as the gate of the transistor Mb3 and a region that functions as the wiring CKL. The conductive layer 205_5 has a region that functions as the gate of the transistor Mb2 and a region that functions as the wiring BKL. The conductive layer 205_6 has a region that functions as the gate of the transistor Mb1 and a region that functions as the wiring NLb1.

[0438] The conductive layer 208_1 has a region that functions as one of the source or drain of the transistor Mg1, a region that functions as one of the source or drain of the transistor Mg2, a region that functions as one of the terminals of the capacitor element Cg1, and a region that functions as the wiring OL. The conductive layer 208_2 has a region that functions as the other of the source or drain of the transistor Mg1 and a region that functions as the wiring CKL. The conductive layer 208_3 has a region that functions as the other of the source or drain of the transistor Mg2 and a region that functions as the wiring VLS1. The conductive layer 208_4 has a region that functions as the wiring CKL. The conductive layer 208_5 has a region that functions as the other of the source or drain of the transistor Mb3 and a region that functions as the wiring VLS2. The conductive layer 208_6 has a region that functions as the other of the source or drain of the transistor Mb2, a region that functions as one of the source or drain of the transistor Mb3, a region that functions as the other terminal of the capacitor element Cb1, and a region that functions as the wiring NLb1. The conductive layer 208_7 has a region that functions as the other of the source or drain of the transistor Mb1, a region that functions as one of the source or drain of the transistor Mb2, and a region that functions as the wiring BKL. The conductive layer 208_8 has a region that functions as one of the source or drain of the transistor Mb1 and a region that functions as the wiring OL.

[0439] The conductive layer 208_1 is connected to the conductive layer 205_3 at the opening provided in the insulating layer 206. The conductive layer 208_2 is connected to the conductive layer 205_4 at the opening provided in the insulating layer 206. The conductive layer 208_4 is connected to the conductive layer 205_4 at the opening provided in the insulating layer 206. The conductive layer 208_6 is connected to the conductive layer 205_6 at the opening provided in the insulating layer 206. The conductive layer 208_7 is connected to the conductive layer 205_5 at the opening provided in the insulating layer 206. The conductive layer 208_8 is connected to the conductive layer 205_4 at the opening provided in the insulating layer 206. FIGS. 37 and 38(B) illustrate a via in which the conductive layer 208_8 and the conductive layer 205_3 are connected to each other at the opening provided in the insulating layer 206.

[0440] In the transistor 200A applied to each transistor constituting the drive circuit 100, a plurality of transistors 200A may share a semiconductor layer 203 provided in a continuous manner. FIG. 37 illustrates a state in which four transistors 200A share the semiconductor layer 203_1, four transistors 200A share the semiconductor layer 203_2, four transistors 200A share the semiconductor layer 203_3, four transistors 200A share the semiconductor layer 203_4, two transistors 200A share the semiconductor layer 203_5, four transistors 200A share the semiconductor layer 203_6, and four transistors 200A share the semiconductor layer 203_7.

[0441] Here, in FIG. 37, as an example, transistor Mg1 and transistor Mg2 share each of semiconductor layer 203_1, semiconductor layer 203_2, semiconductor layer 203_3, and semiconductor layer 203_4. Transistor Mb2 and transistor Mb3 share semiconductor layer 203_5 as an example. FIG. 38(A) illustrates a state in which transistor Mb2 and transistor Mb3 share semiconductor layer 203_5 provided continuously. In this way, by sharing semiconductor layer 203 in which a plurality of transistors 200A are provided continuously, the occupied area of the transistors can be reduced. Thereby, the occupied area of gate driver unit 163 can be reduced, and the frame width can be reduced. Therefore, miniaturization of the semiconductor device can be achieved.

[0442] Also, in transistor 200A applied to each transistor constituting drive circuit 100, it may have a configuration in which a plurality of transistors 200A are connected in parallel. In FIG. 37, as an example, transistor Mg1 has a configuration in which eight transistors 200A are connected in parallel. Transistor Mg2 has a configuration in which eight transistors 200A are connected in parallel as an example. Transistor Mb1 has a configuration in which eight transistors 200A are connected in parallel as an example. FIG. 38(B) shows two transistors 200A as part of transistor Mb1. In this way, by adopting a configuration in which a plurality of transistors 200A are connected in parallel, the substantial channel width can be increased, and the on-current of the transistor can be increased. Thereby, the time required to change the potential of wiring OL (i.e., rise time and fall time) can be shortened. Therefore, the operating speed of the semiconductor device can be improved.

[0443] Here, in FIG. 37, the channel length (i.e., the width of the conductive layer 205) and the channel width (i.e., the width of the semiconductor layer 203) of each transistor 200A in each of the transistors Mg1, Mg2, and Mb1 are made equal to the channel length and the channel width of the transistor 200A in each of the transistors Mb2 and Mb3. In this way, when increasing the on-current of the transistor, by adopting a configuration in which a plurality of transistors with equal channel length and channel width are connected in parallel, it is possible to reduce the variation in the characteristics of the transistors.

[0444] Although not shown, in order to increase the on-current of the transistor, the channel length of each transistor may be decreased, or the channel width of each transistor may be increased. Thereby, when obtaining the same on-current, the number of transistors connected in parallel can be reduced, and the occupied area can be reduced.

[0445] The capacitive element Cg1 can be configured such that a part of the insulating layer 206 serves as a dielectric in a region where the conductive layer 205_1 and the conductive layer 208_1 overlap each other. The capacitive element Cb1 can be configured such that a part of the insulating layer 206 serves as a dielectric in a region where the conductive layer 205_3 and the conductive layer 208_6 overlap each other. FIG. 38(A) shows, as an example, the capacitive element Cb1 in which a part of the insulating layer 206 serves as a dielectric and a part of each of the conductive layer 205_3 and the conductive layer 208_6 serves as a pair of terminals.

[0446] Note that, although not shown, as the capacitive element, for example, a configuration may be used in which a part of each of the insulating layer 204 and the insulating layer 206 is used as a dielectric, and a part of each of the semiconductor layer 203 and the conductive layer 208 is used as a pair of terminals. Further, for example, a conductive layer (not shown) may be provided between the substrate 201 and the insulating layer 202, a part of each of the insulating layer 202 and the insulating layer 204 is used as a dielectric, and a part of each of the conductive layer (not shown) and the conductive layer 205 is used as a pair of terminals. Further, for example, a conductive layer (not shown) may be provided between the substrate 201 and the insulating layer 202, a part of the insulating layer 202 is used as a dielectric, and a part of each of the conductive layer (not shown) and the semiconductor layer 203 is used as a pair of terminals.

[0447] Here, in FIG. 37, in a region other than the region where the capacitive element Cg1 and the capacitive element Cb1 are located, a region where the conductive layer 205 and the conductive layer 208 overlap each other functions as a parasitic capacitance having a part of the insulating layer 206 as a dielectric. Therefore, the area of the capacitive element Cg1 (that is, the area of the region where the conductive layer 205_1 and the conductive layer 208_1 overlap each other) is preferably larger than the area of the region where the conductive layer 208_1 and the conductive layer 205_2 overlap each other, preferably larger than the area of the region where the conductive layer 205_3 and the conductive layer 208_3 overlap each other, preferably larger than the area of the region where the conductive layer 205_3 and the conductive layer 208_4 overlap each other, preferably larger than the area of the region where the conductive layer 205_3 and the conductive layer 208_5 overlap each other, and preferably larger than the area of the region where the conductive layer 205_3 and the conductive layer 208_7 overlap each other. Further, the area of the capacitive element Cb1 (that is, the area of the region where the conductive layer 205_3 and the conductive layer 208_6 overlap each other) is preferably larger than the area of the region where the conductive layer 208_1 and the conductive layer 205_2 overlap each other, preferably larger than the area of the region where the conductive layer 205_3 and the conductive layer 208_3 overlap each other, preferably larger than the area of the region where the conductive layer 205_3 and the conductive layer 208_4 overlap each other, preferably larger than the area of the region where the conductive layer 205_3 and the conductive layer 208_5 overlap each other, and preferably larger than the area of the region where the conductive layer 205_3 and the conductive layer 208_7 overlap each other.

[0448] Also, in FIG. 37, the capacitive element Cb1 is arranged near the transistor Mb2, not near the transistor Mb1. Since the occupied area of the transistor Mb2 is smaller than the occupied area of the transistor Mb1, when the capacitive element Cb1 is arranged near the transistor Mb2, the layout area can be reduced as compared with the case where the capacitive element Cb1 is arranged near the transistor Mb1. In FIG. 37 laid out based on such a technical concept, both the region functioning as the other terminal of the capacitive element Cb1 and the region functioning as the other of the source or drain of the transistor Mb2 are provided in the conductive layer 208_6. This conductive layer 208_6 is connected to the conductive layer 205_6, and the conductive layer 205_6 has a region functioning as the gate of the transistor Mb1. Also, the region functioning as one terminal of the capacitive element Cb1 is provided in the conductive layer 205_3. This conductive layer 205_3 is connected to the conductive layer 208_8, and the conductive layer 208_8 has a region functioning as one of the source or drain of the transistor Mb1.

[0449] Furthermore, by connecting the capacitive element Cb1 and the transistor Mb2 and the transistor Mb1 using the conductive layer 205_3 and the conductive layer 205_6, a conductive layer 208_7 can be provided between the capacitive element Cb1 and the transistor Mb2 and the transistor Mb1. The conductive layer 208_7 can intersect the conductive layer 205_6 and the conductive layer 205_3. By the conductive layer 208_7 having the region functioning as the other of the source or drain of the transistor Mb1, the region functioning as one of the source or drain of the transistor Mb2, and the region functioning as the wiring BKL, the transistor Mb1, the transistor Mb2, the capacitive element Cb1, and the wiring BKL can be arranged efficiently.

[0450] Further, a conductive layer 208_2 having a region that functions as the other of the source or drain of the transistor Mg1 is connected to a conductive layer 205_4 having a region that functions as the gate of the transistor Mb3, and the conductive layer 205_4 is connected to a conductive layer 208_4 provided between the transistor Mg1 and the transistor Mb1. Since this conductive layer 208_4 has a region that functions as the wiring CKL, the transistor Mg1, the transistor Mb3, and the wiring CKL can be efficiently arranged.

[0451] Here, the potential of the wiring BKL is supplied to m gate lines 165 (corresponding to the wiring OL) all at once. At this time, the current flowing through the wiring BKL instantaneously increases, and the voltage of the wiring BKL drops significantly. In order to suppress the influence of this voltage drop of the wiring BKL, it is preferable to increase the width of the wiring BKL. However, since an instantaneously large current also flows through the wiring CKL, the wiring VLS1, and the wiring VLS2, it is also preferable to increase the widths of the wiring CKL, the wiring VLS1, and the wiring VLS2. In this way, if the widths of any of the wiring BKL, the wiring CKL, the wiring VLS1, and the wiring VLS2 are all increased, the layout area will increase. Therefore, by preferentially increasing the width of the wiring through which an instantaneously large current flows, it is possible to suppress the increase in the layout area while suppressing the influence of the voltage drop. Further, by preferentially increasing the width of the wiring through which an instantaneously large current flows, the current density in the wiring can be lowered. As a result, disconnection or short-circuit of the wiring due to electromigration is less likely to occur, so the reliability can be improved.

[0452] Specifically, regarding the wiring BKL, the wiring CKL, the wiring VLS1, and the wiring VLS2, the current flowing instantaneously through the wiring BKL is larger than that through any of the wiring CKL, the wiring VLS1, and the wiring VLS2. Therefore, as shown in FIG. 53, it is preferable that the width of the wiring BKL is larger than the respective widths of the wiring CKL, the wiring VLS1, and the wiring VLS2. Thereby, while suppressing an increase in the layout area, the influence of the voltage drop of the wiring BKL can be suppressed.

[0453] Incidentally, when the wiring width of the wiring BKL is increased, the overlap between the conductive layer 208_7 having a region functioning as the wiring BKL and the conductive layer 205_3 having a region functioning as the wiring OL increases. Therefore, there may be a concern about an increase in the parasitic capacitance due to the overlap of the two conductive layers. Thus, although not shown, in such a case, in order to suppress an increase in the parasitic capacitance, for example, in a region where the conductive layer 205_3 and the conductive layer 208_7 overlap each other, the wiring width of the conductive layer 205_3 may be selectively reduced, or an opening may be formed in the conductive layer 205_3, etc. The same applies to the overlap between other conductive layers where parasitic capacitance can be formed.

[0454] Incidentally, for example, when the driving circuit 100 is used in a display device having a liquid crystal element, the black scan operation of supplying a potential from the wiring BKL to the wiring OL via the transistor Mb1 is performed immediately before shutting down the display device. Therefore, even if the operation speed of the black scan operation is slower than the operation speed of the writing operation of supplying a potential from the wiring CKL to the wiring OL via the transistor Mg1, the influence on the operation of the display device is small. Thus, for example, the on-current of the transistor Mb1 may be smaller than the on-current of the transistor Mg1. For example, as shown in FIG. 54, the channel width of the transistor Mb1 may be smaller than the channel width of the transistor Mg1. Thereby, the layout area can be reduced.

[0455] Note that one aspect of the present invention is not limited to the configuration examples, operation examples, etc. described in the present embodiment. The description contents of the present embodiment can be implemented by appropriately combining them with each other. Further, the description contents of the present embodiment can be implemented by appropriately combining them with the description contents of other embodiments, etc.

[0456] (Embodiment 5) In the present embodiment, a display device according to one aspect of the present invention will be described.

[0457] Note that at least a part of the drive circuit, semiconductor device, etc. shown in the above-described Embodiment 1 can be applied to the display device and modules having the display device described in this embodiment.

[0458] Here, examples of the module having the display device include a module to which a connector such as a flexible printed circuit board (FPC) or a tape carrier package (TCP) is attached to the display device, or a module in which an integrated circuit (IC) is mounted by a chip on glass (COG) method, a chip on film (COF) method, or the like.

[0459] <Configuration Example of Display Device> FIG. 39(A) is a perspective view showing a configuration example of a display device 400 according to an aspect of the present invention.

[0460] The display device 400 has a configuration in which a substrate 411 and a substrate 451 are bonded together. In FIG. 39(A), the substrate 411 is shown by a broken line.

[0461] The display device 400 includes a display unit 452, a circuit unit 454a, a circuit unit 454b, a connection unit 457, a wiring unit 458, and the like. FIG. 39(A) shows an example in which an IC chip 456 and an FPC 459 are mounted on the display device 400. Therefore, the configuration shown in FIG. 39(A) can also be referred to as a display module having the display device 400, the IC chip, and the FPC.

[0462] Note that at least a part of the semiconductor device 160 shown in the above-described Embodiment 1 can be applied to the display device 400. For example, at least a part of the drive circuit 100 shown in the above-described Embodiment 1 can be applied to the circuit unit 454a and the circuit unit 454b. Further, for example, at least a part of the pixel 161 shown in the above-described Embodiment 1 can be applied to the display unit 452.

[0463] The circuit section 454a has, for example, a scanning line driving circuit (also referred to as a gate driver or a scan driver). Further, the circuit section 454b has, for example, a signal line driving circuit (also referred to as a source driver or a data driver).

[0464] The wiring section 458 has a function of supplying signals and power to the display section 452, the circuit section 454a, and the circuit section 454b. The signals and power are input to the wiring section 458 from the outside of the display device 400 via the FPC 459, or are input to the wiring section 458 from the IC chip 456.

[0465] FIG. 39(A) shows an example in which the IC chip 456 is provided on the substrate 451 by a COG method, a COF method, or the like. As the IC chip 456, for example, an IC chip having one or both of a scanning line driving circuit and a signal line driving circuit can be applied. Note that the display device 400 and the display module may be configured not to include an IC chip. Further, the IC chip may be mounted on the FPC by a COF method or the like.

[0466] Note that one or both of the IC chip 456 and the circuit section 454a may constitute a scanning line driving circuit. In that case, the IC chip 456 may be referred to as a gate driver IC. Further, one or both of the IC chip 456 and the circuit section 454b may constitute a signal line driving circuit. In that case, the IC chip 456 may be referred to as a source driver IC.

[0467] The display section 452 is an area for displaying an image in the display device 400 and has a plurality of pixels 455 arranged periodically. FIG. 39(A) shows an enlarged view of one pixel 455.

[0468] The pixel 455 shown in FIG. 39(A) has a pixel 453R that exhibits red (R) light, a pixel 453G that exhibits green (G) light, and a pixel 453B that exhibits blue (B) light. By configuring one pixel 455 with the pixels 453R, 453G, and 453B, full-color display can be realized. The pixels 453R, 453G, and 453B each function as a sub-pixel. In the display device 400 shown in FIG. 39(A), an example is shown in which the pixels 453R, 453B, and 453G that function as sub-pixels are arranged in a stripe array. Note that the number of sub-pixels constituting one pixel 455 is not limited to three, and may be four or more. For example, it may have four sub-pixels that exhibit the respective lights of red (R), green (G), blue (B), and white (W). Or, it may have four sub-pixels that exhibit the respective lights of red (R), green (G), blue (B), and yellow (Y).

[0469] In this specification and the like, when explaining each matter, an identification code "R" may be attached to an element related to red light, an identification code "G" may be attached to an element related to green light, and an identification code "B" may be attached to an element related to blue light. Also, when explaining common matters, those identification codes may not be attached. For example, when it is necessary to distinguish a plurality of pixels 453, they may be shown as pixel 453R, pixel 453G, or pixel 453B. Also, for example, when it is not necessary to distinguish the pixels 453R, 453G, and 453B, they may simply be shown as pixel 453.

[0470] The pixels 453R, 453G, and 453B each have a display element and a circuit (pixel circuit) that controls the driving of the display element.

[0471] The connection portion 457 is provided outside the display portion 452. The connection portion 457 can be provided along one side or a plurality of sides of the display portion 452. The connection portion 457 may be singular or plural. FIG. 39(A) shows an example in which the connection portion 457 is provided so as to surround the four sides of the display portion. In the connection portion 457, a common electrode of the display element and the wiring portion 458 are connected, and a potential can be supplied to the common electrode.

[0472] As the substrates 451 and 411, glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, etc. can be used respectively. For the substrate (here, substrate 411) on the side for extracting light from the display element, it is preferable to use a material that transmits the light. Also, as at least one of the substrates 451 and 411, a polarizing plate may be used. Further, as the substrates 451 and 411, a flexible material can be used. Thereby, the flexibility of the display device can be enhanced, and a flexible display (for example, a bendable display, a foldable display, a rollable display, a slidable display, and a stretchable display, etc.) can be realized.

[0473] Note that the display device according to an aspect of the present invention may have a function as a touch panel. For example, various detection elements (which can also be called sensor elements) capable of detecting the proximity or contact of a detected object such as a finger can be applied to the display device.

[0474] Examples of the sensor method include a capacitance method, a resistive film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method.

[0475] As the capacitance method, for example, there are a surface capacitance method and a projected capacitance method. Also, as the projected capacitance method, for example, there are a self-capacitance method and a mutual-capacitance method. Using the mutual-capacitance method is preferable because simultaneous multi-point detection becomes possible.

[0476] Examples of the touch panel include an out-cell type, an on-cell type, and an in-cell type. Note that the in-cell type touch panel refers to a configuration in which electrodes constituting detection elements are provided on one or both of the substrate and the counter substrate that support the display element (also called a display device).

[0477] 〔Pixel array〕 FIGS. 39(B) to 39(F) are top views for explaining a pixel array. In the display device according to one aspect of the present invention, the arrangement of pixels is not particularly limited, and various arrangements can be applied. Examples of the pixel arrangement include a stripe arrangement (see FIG. 39(B)), an S-stripe arrangement (see FIG. 39(C)), a delta arrangement (see FIG. 39(D)), a zigzag arrangement (see FIG. 39(E)), and a pentile arrangement (see FIG. 39(F)). Further, for example, a mosaic arrangement, a diamond arrangement, and a Bayer arrangement can be mentioned.

[0478] Also, in FIGS. 39(B) to 39(F), examples of the top surface shape of each sub-pixel (pixel 453R, pixel 453G, and pixel 453B) include polygons such as a triangle, a quadrilateral (including a rectangle and a square), a pentagon, a shape in which the corners of these polygons are rounded, an ellipse, and a circle. Here, the top surface shape of each sub-pixel corresponds to the top surface shape of the display region of the display element included in each sub-pixel. The top surface shape and size of each sub-pixel can be determined independently. Note that the arrangements of pixel 453R, pixel 453G, and pixel 453B may be appropriately interchanged. Also, each of the display element and the pixel circuit may have the same arrangement or different arrangements.

[0479] 〔Display Element〕 As the display element, various elements can be used. For example, a liquid crystal element and a light-emitting element can be mentioned. In addition, a MEMS (Micro Electro Mechanical Systems) element of a shutter type or an optical interference type, or a display element to which a microcapsule method, an electrophoresis method, an electro-wetting method, or an electronic ink (registered trademark) method is applied can also be used. Further, a QLED (Quantum-dot LED) using a light source and a color conversion technology using a quantum dot material may be used.

[0480] Examples of the display device using a liquid crystal element include a transmissive liquid crystal display device, a reflective liquid crystal display device, and a transflective liquid crystal display device.

[0481] Examples of modes that can be used in a display device using a liquid crystal element include, for example, a vertical alignment (VA) mode, a fringe field switching (FFS) mode, an in-plane switching (IPS) mode, a twisted nematic (TN) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, an electrically controlled birefringence (ECB) mode, and a guest-host mode. Examples of the VA mode include, for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, and an advanced super view (ASV) mode.

[0482] Examples of liquid crystal materials that can be used in a liquid crystal element include, for example, thermotropic liquid crystals, low molecular liquid crystals, high molecular liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or a blue phase, etc. Also, as the liquid crystal material, either a positive-type liquid crystal or a negative-type liquid crystal may be used.

[0483] Examples of light-emitting elements include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), organic EL (Electro Luminescence) elements (also referred to as OLEDs (Organic LEDs)), and semiconductor lasers. As the LED, for example, mini-LEDs, or micro-LEDs can be used.

[0484] Examples of the light-emitting substance of the light-emitting element include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (such as quantum dot materials).

[0485] The light-emitting element can be configured to emit light such as red, green, blue, cyan, magenta, yellow, or white. Further, the light-emitting element may be configured to emit ultraviolet light or infrared light. Also, the color purity can be enhanced by providing a microcavity structure to the light-emitting element.

[0486] Of the pair of electrodes of the light-emitting element, one electrode functions as an anode (also referred to as an anode electrode), and the other electrode functions as a cathode (also referred to as a cathode electrode).

[0487] <Example of cross-sectional structure of display device> FIG. 40 is a cross-sectional view for explaining an example of the cross-sectional structure of a display device according to an aspect of the present invention.

[0488] In the display device 490 shown in FIG. 40, the configurations shown in regions 490a, 490b, 490c, and 490d can be used in the display device 400, respectively. For example, the configuration shown in region 490a can be used in the region where the pixel 453 is provided. The configuration shown in region 490b can be used in the region where the circuit units 454a and 454b and the like are provided. The configuration shown in region 490c can be used in the region where the FPC 459 is provided. The configuration shown in region 490d can be used in the region where the connection unit 457 is provided.

[0489] Note that region 490a corresponds to the region where the pixel 161 shown in the above-described Embodiment 1 is provided. That is, the transistor provided in region 490a corresponds to the transistor (such as transistor Mpix) included in the pixel 161 shown in the above-described Embodiment 1. Further, region 490b corresponds to the region where the drive circuit 100 shown in the above-described Embodiment 1 is provided. That is, the transistors provided in region 490b correspond to the transistors (such as transistors Mg1, Mg2, Mb1, Mb2, and Mb3) included in the drive circuit 100 shown in the above-described Embodiment 1.

[0490] The display device 490 includes a substrate 351 (corresponding to the substrate 451 described above) and a substrate 352 (corresponding to the substrate 411 described above). Further, in region 490a, liquid crystal 375 is provided between the substrate 351 and the substrate 352, and in regions 490b and 490d, an adhesive layer 362 is provided between the substrate 351 and the substrate 352. The substrate 352 faces the substrate 351 with the liquid crystal 375 and the adhesive layer 362 interposed therebetween. Note that in region 490c, the substrate 352, the liquid crystal 375, and the adhesive layer 362 are not provided.

[0491] An insulating layer 382 is provided on the side of the substrate 352 of the substrate 351. Transistors, liquid crystal elements, and the like are provided on the insulating layer 382.

[0492] Here, as an example, a configuration in which the transistor 200A shown in the above-described Embodiment 2 is provided in each of the regions 490a and 490b is shown. Also, in the region 490c, a conductive layer 384 is provided, and in the region 490d, a conductive layer 398 is provided. Each of the conductive layer 384 and the conductive layer 398 can be formed in the same process as the conductive layer 208 (such as the conductive layer 208a and the conductive layer 208b) in the transistor 200A.

[0493] Note that the configuration of the region 490a can be applied to the pixel 161A[u, v] using the liquid crystal element LC as the functional element Elm in the semiconductor device 160 shown in the above-described Embodiment 1.

[0494] Also, the transistors provided in each of the regions 490a and 490b are not limited to the structure such as the transistor 200A. Various structures of transistors such as the transistor 200B, the transistor 200C, the transistor 200D, and the transistor 200E shown in the above-described Embodiment 2 can be provided in each of the regions 490a and 490b. At this time, two or more different structures of transistors may be provided.

[0495] An insulating layer 209 and an insulating layer 218 are provided so as to cover the transistor 200A. Note that the display device 490 may not have the insulating layer 218.

[0496] <Configuration example of liquid crystal element> In the region 490a, a liquid crystal element 370 or the like is provided on the insulating layer 218.

[0497] The liquid crystal element 370 has a pixel electrode 311 and a common electrode 379, and a liquid crystal 375 is provided between the pixel electrode 311 and the common electrode 379. The pixel electrode 311 is provided so as to cover the insulating layer 209 and the insulating layer 218 and an opening provided so as to reach the conductive layer 208b. Here, a case where a vertical alignment (VA) mode liquid crystal element is used as the liquid crystal element 370 will be described.

[0498] An insulating layer 373 is provided between the pixel electrode 311 and the liquid crystal 375, and an insulating layer 377 is provided between the liquid crystal 375 and the common electrode 379. The insulating layer 373 and the insulating layer 377 have the function of an alignment film. Further, an insulating layer 369 is provided between the liquid crystal elements 370. The insulating layer 369 has the function of controlling the interval (cell gap) between the pixel electrode 311 and the common electrode 379.

[0499] A light-shielding layer 317 and a coloring layer 332 are provided on the surface of the substrate 352 on the side of the substrate 351. The coloring layer 332 has the function of selectively transmitting light in a specific wavelength range, such as red, green, or blue, and absorbing light in other wavelength ranges. Further, a protective layer 367 is provided so as to cover the light-shielding layer 317 and the coloring layer 332.

[0500] The coloring layer 332 has a region overlapping with the liquid crystal element 370, and the transmittance of light of a specific color is higher than the transmittance of light of other colors. For example, in the coloring layer 332, when the transmittance of red light is higher than the transmittance of light of other colors, the light emitted from the liquid crystal element 370 having a region overlapping with the coloring layer 332 (which may be referred to as the coloring layer 332R) is taken out of the display device 490 as red light. Further, for example, when the transmittance of green light is higher than the transmittance of light of other colors, the light emitted from the liquid crystal element 370 having a region overlapping with the coloring layer 332 (which may be referred to as the coloring layer 332G) is taken out of the display device 490 as green light. Furthermore, for example, when the transmittance of blue light is higher than the transmittance of light of other colors, the light emitted from the liquid crystal element 370 having a region overlapping with the coloring layer 332 (which may be referred to as the coloring layer 332B) is taken out of the display device 490 as blue light. Thus, the display device 490 can perform full-color display.

[0501] In the region where the coloring layer 332 is not provided, a light-shielding layer 317 can be provided. Thereby, it is possible to suppress light emitted from the liquid crystal element 370 from entering the coloring layer 332 that does not overlap with the liquid crystal element 370. For example, it is possible to suppress light emitted from the liquid crystal element 370 that overlaps with the coloring layer 332R from entering the coloring layer 332G and being taken out as green light to the outside of the display device 490. Thereby, color mixing can be suppressed.

[0502] Further, by providing the light-shielding layer 317, it is possible to suppress components of the display device 490 from being visually recognized. For example, by providing the light-shielding layer 317 so as to have a region overlapping with the transistor 200A, it is possible to suppress the transistor 200A from being visually recognized. Here, it is preferable to provide the light-shielding layer 317 in the region 490b and the region 490d so as to suppress the circuit unit 454a, the circuit unit 454b, the connection unit 457, etc. from being visually recognized.

[0503] The protective layer 367 is provided at least in the region 490a, and is preferably provided so as to cover the entire region 490a. The protective layer 367 is preferably provided so as to cover not only the region 490a but also the region 490b and the region 490d. Further, the protective layer 367 is preferably provided up to the end of the display device 490.

[0504] The insulating layer 218 and the protective layer 367 are bonded by an adhesive layer 362. Further, liquid crystal 375 is sealed in the region surrounded by the substrate 351, the substrate 352, and the adhesive layer 362. A polarizing plate 360a is located on the outer surface (opposite side to the substrate 352 side) of the substrate 351, and a polarizing plate 360b is located on the outer surface (opposite side to the substrate 351 side) of the substrate 352. When the display device 490 is a reflective liquid crystal display device, one of the polarizing plate 360a and the polarizing plate 360b may not be provided. When the display device 490 is a transmissive liquid crystal display device, although not shown, a backlight can be provided outside the polarizing plate 360a or outside the polarizing plate 360b.

[0505] When the display device 490 is a transmissive liquid crystal display device, the pixel electrode 311 and the common electrode 379 transmit visible light. For example, when a backlight is disposed on the substrate 351 side, the light from the backlight polarized by the polarizing plate 360a passes through the substrate 351, the pixel electrode 311, the liquid crystal 375, the common electrode 379, and the substrate 352 and reaches the polarizing plate 360b. At this time, the alignment of the liquid crystal 375 can be controlled by the voltage applied between the pixel electrode 311 and the common electrode 379, and the optical modulation of the light can be controlled. That is, the intensity of the light emitted through the polarizing plate 360b can be controlled. Further, since the light other than the specific wavelength region is absorbed by the coloring layer 332, the emitted light becomes light having, for example, a specific color (such as red, green, or blue).

[0506] In FIG. 40, the state in which the light emitted from a backlight (not shown) disposed on the substrate 351 side is emitted to the outside of the display device 490 through the polarizing plate 360a, the substrate 351, the pixel electrode 311, the liquid crystal 375, the common electrode 379, the substrate 352, and the polarizing plate 360b is represented by a broken-line arrow and the description "Light".

[0507] Here, a linear polarizing plate may be used as the polarizing plate 360b, but a circular polarizing plate can also be used. As the circular polarizing plate, for example, a laminate of a linear polarizing plate and a quarter-wave retardation plate can be used. By using a circular polarizing plate for the polarizing plate 360b, external light reflection can be suppressed.

[0508] When a circular polarizing plate is used as the polarizing plate 360b, a circular polarizing plate may also be used for the polarizing plate 360a, or a normal linear polarizing plate can be used. By adjusting the cell gap, alignment, driving voltage, etc. of the liquid crystal element used for the liquid crystal element 370 according to the type of polarizing plate applied to the polarizing plate 360a and the polarizing plate 360b, a desired contrast can be realized.

[0509] The common electrode 379 is connected in the region 490d via a conductive layer 399 provided on the substrate 351 side and a connector 397. The conductive layer 399 is connected to the conductive layer 398 at the openings provided in the insulating layer 209 and the insulating layer 218. The conductive layer 399 has, for example, a region in contact with the conductive layer 398 inside the opening. Although not shown in FIG. 40, the conductive layer 398 is connected to an FPC or an IC chip disposed on the substrate 351 side.

[0510] As described above, a potential or a signal can be supplied from the FPC or the IC chip disposed on the substrate 351 side to the common electrode 379. FIG. 40 shows an example in which the conductive layer 398 is provided in the same layer as the conductive layers 208a and 208b, that is, formed in the same process using the same material as the conductive layers 208a and 208b. Further, FIG. 40 shows an example in which the conductive layer 399 is provided in the same layer as the pixel electrode 311, that is, formed in the same process using the same material as the pixel electrode 311.

[0511] As the connector 397, for example, conductive particles can be used. As the conductive particles, those obtained by coating the surface of particles such as organic resin or silica with a metal material can be used. It is preferable to use nickel or gold as the metal material because the contact resistance can be reduced. Further, it is preferable to use particles coated with two or more kinds of metal materials in layers, such as coating nickel with gold. It is also preferable to use a material that elastically deforms or plastically deforms as the connector 397. At this time, the conductive particles may have a shape crushed in the vertical direction as shown in FIG. 40. By doing so, the contact area between the connector 397 and the conductive layer in contact therewith increases, the contact resistance can be reduced, and the occurrence of defects such as poor connection can be suppressed. The connector 397 is preferably disposed so as to be covered with the adhesive layer 362. For example, it is preferable to disperse the connector 397 in the adhesive layer 362 before curing.

[0512] In region 490c, the conductive layer 384 is connected to the FPC 459 via the conductive layer 386 and the connection layer 388. The conductive layer 384 can be provided in the same layer as the conductive layers 208a and 208b. Therefore, the conductive layer 384 can have the same material as the conductive layers 208a and 208b and can be formed in the same process. For example, the conductive layer 208a, the conductive layer 208b, and the conductive layer 384 can be formed by processing the same conductive film. Also, the conductive layer 386 can be provided in the same layer as the pixel electrode 311. Therefore, the conductive layer 386 can have the same material as the pixel electrode 311 and can be formed in the same process. For example, the pixel electrode 311 and the conductive layer 386 can be formed by processing the same conductive film. In region 490c, the conductive layer 386 is exposed. Thus, the conductive layer 386 and the FPC 459 can be connected via the connection layer 388.

[0513] As the connection layer 388, an anisotropic conductive film (ACF: Anisotropic Conductive Film), an anisotropic conductive paste (ACP: Anisotropic Conductive Paste), or the like can be used.

[0514] 〔Another Configuration Example 1〕 FIG. 41(A) is a cross-sectional view showing a configuration example of a display device 490U which is a modified example of the display device 490. The display device 490U has, in region 490a, in addition to the above-described display device 490, a conductive layer 391 embedded in the insulating layer 218, and has a capacitive element 390 having the conductive layer 391 and the pixel electrode 311 as a pair of electrodes. The conductive layer 391 may use a conductive film that transmits visible light. For example, it can have the same material as the pixel electrode 311.

[0515] The capacitive element 390 can be applied to the capacitive element included in the pixel 161 shown in the above-described Embodiment 1. For example, it can be applied to the capacitive element C11 included in the pixel 161A shown in the above-described Embodiment 1.

[0516] 〔Another Configuration Example 2〕 FIG. 41(B) is a cross-sectional view showing a configuration example of a display device 490V which is a modified example of the display device 490. Here, a case where a liquid crystal element of a FFS (Fringe Field Switching) mode is used as the liquid crystal element 370 in the region 490a of the display device 490V will be described.

[0517] The liquid crystal element 370 included in the display device 490V includes a common electrode 371, an insulating layer 372 on the common electrode 371, a pixel electrode 311 on the insulating layer 372, and liquid crystal 375 on the pixel electrode 311. The pixel electrode 311 is provided so as to cover an opening provided in the insulating layers 209, 218, and 372 so as to reach the conductive layer 208b.

[0518] An insulating layer 373 is provided between the pixel electrode 311 and the insulating layer 372, and the liquid crystal 375. An insulating layer 377 is provided on the liquid crystal 375.

[0519] The common electrode 371 can be provided, for example, over the entire surface of the region 490a. At this time, the common electrode 371 is provided with an opening so as to overlap with the openings provided in the insulating layers 209, 218, and 372.

[0520] The pixel electrode 311 can be provided so as to have a shape in which a slit is provided in a top view or a comb-like shape in a region overlapping with the coloring layer 332. Thus, the common electrode 371 has a region that overlaps with the coloring layer 332 and does not overlap with the pixel electrode 311.

[0521] The common electrode 371 may use a conductive film that transmits visible light. For example, it can have the same material as the pixel electrode 311.

[0522] Note that it can also be said that the display device 490V has a capacitive element using the common electrode 371 and the pixel electrode 311 as a pair of electrodes. The capacitive element can be applied to, for example, the capacitive element included in the pixel 161 shown in the above-described Embodiment 1. For example, it can be applied to the capacitive element C11 included in the pixel 161A shown in the above-described Embodiment 1.

[0523] <Configuration example of a light-emitting element> In one aspect of the present invention, when the display device has a light-emitting element, light-emitting elements with various configurations can be used.

[0524] The configuration described below can be applied to the pixel 161B[u, v] using the light-emitting element LD as the functional element Elm in the semiconductor device 160 shown in the above-described Embodiment 1.

[0525] FIGS. 42(A), 42(B), 43(A), and 43(B) are cross-sectional views for explaining light-emitting elements with various configurations, respectively.

[0526] 〔Configuration example 1〕 The display device 490A shown in FIG. 42(A) has a light-emitting element 330R, a light-emitting element 330G, a light-emitting element 330B, etc. between a substrate 351 and a substrate 352. The light-emitting element 330R is a display element included in a pixel that emits red light, the light-emitting element 330G is a display element included in a pixel that emits green light, and the light-emitting element 330B is a display element included in a pixel that emits blue light. When explaining matters common to the light-emitting element 330R, the light-emitting element 330G, and the light-emitting element 330B, they may be simply referred to as the light-emitting element 330.

[0527] In FIG. 42(A), a part of the configuration between the substrate 351 and the light-emitting element 330 and the configuration between the substrate 352 and the light-emitting element 330 are shown with some omissions. The display device 490A has, for example, a transistor constituting a pixel circuit and an insulating layer 218 provided so as to cover the transistor between the substrate 351 and the light-emitting element 330.

[0528] The display device 490A has an SBS (Side By Side) structure applied thereto. The SBS structure is fabricated using a metal mask (or a fine metal mask). Therefore, the degree of freedom in selecting materials and configurations for each light-emitting element is increased. Thus, since the materials and configurations can be optimized for each light-emitting element, it becomes easy to improve the light-emitting intensity and reliability.

[0529] The display device 490A is a top emission type. In the top emission type, since transistors and the like can be arranged overlapping the light-emitting region of the light-emitting element, the aperture ratio of the pixel can be increased compared to the bottom emission type.

[0530] On the insulating layer 218, a light-emitting element 330R, a light-emitting element 330G, and a light-emitting element 330B are provided.

[0531] The light-emitting element 330R includes a pixel electrode 311R on the insulating layer 218, an EL layer 313R on the pixel electrode 311R, and a common electrode 315 on the EL layer 313R. The light-emitting element 330R shown in FIG. 42(A) emits red (R) light. The EL layer 313R has a light-emitting layer that emits red light.

[0532] The light-emitting element 330G includes a pixel electrode 311G on the insulating layer 218, an EL layer 313G on the pixel electrode 311G, and a common electrode 315 on the EL layer 313G. The light-emitting element 330G shown in FIG. 42(A) emits green (G) light. The EL layer 313G has a light-emitting layer that emits green light.

[0533] The light-emitting element 330B includes a pixel electrode 311B on the insulating layer 218, an EL layer 313B on the pixel electrode 311B, and a common electrode 315 on the EL layer 313B. The light-emitting element 330B shown in FIG. 42(A) emits blue (B) light. The EL layer 313B has a light-emitting layer that emits blue light.

[0534] Note that in FIG. 42(A), although EL layer 313R, EL layer 313G, and EL layer 313B are all shown with the same thickness, this is not restrictive. The respective thicknesses of EL layer 313R, EL layer 313G, and EL layer 313B may be different. For example, it is preferable to set the thicknesses of EL layer 313R, EL layer 313G, and EL layer 313B such that the optical path lengths for the light emitted therefrom are increased. Thereby, a microcavity structure can be realized, and the color purity of the light emitted from each light-emitting element can be enhanced.

[0535] Pixel electrode 311R is connected to a transistor (not shown) included in a pixel circuit corresponding to light-emitting element 330R at an opening provided in insulating layer 218 or the like. Similarly, pixel electrode 311G is connected to a transistor (not shown) included in a pixel circuit corresponding to light-emitting element 330G. Similarly, pixel electrode 311B is connected to a transistor (not shown) included in a pixel circuit corresponding to light-emitting element 330B.

[0536] The respective end portions of pixel electrode 311R, pixel electrode 311G, and pixel electrode 311B are covered by insulating layer 237. Insulating layer 237 functions as a partition. Insulating layer 237 can be provided in a single-layer structure or a laminated structure using one or both of an inorganic insulating material and an organic insulating material. For example, materials that can be used for insulating layer 218 can be applied to insulating layer 237. Insulating layer 237 can insulate the pixel electrode and the common electrode. Also, insulating layer 237 can insulate adjacent light-emitting elements from each other.

[0537] Common electrode 315 is a continuous film provided in common to light-emitting element 330R, light-emitting element 330G, and light-emitting element 330B. Although not shown, common electrode 315, which is commonly provided by a plurality of light-emitting elements, is connected to a conductive layer formed of the same material and in the same process as pixel electrode 311R, pixel electrode 311G, and pixel electrode 311B in a region where no light-emitting element is provided.

[0538] Of the pixel electrode and the common electrode, it is preferable to use a conductive film that transmits visible light for the electrode on the light extraction side (here, the common electrode 315). Further, for the electrode on the side where light is not extracted (here, the pixel electrodes 311R, 311G, and 311B), it is preferable to use a conductive film that reflects visible light.

[0539] Note that a conductive film that transmits visible light may also be used for the electrode on the side where lig...

Claims

1. having a first circuit and a second circuit; the first circuit having a first transistor, a second transistor, and a first capacitor; the second circuit having a third transistor, a fourth transistor, a fifth transistor, and a second capacitor; a first terminal of the first transistor being electrically connected to a first terminal of the second transistor, a first terminal of the third transistor, a first terminal of the first capacitor, a first terminal of the second capacitor, and a first signal line; a second terminal of the first transistor being electrically connected to a second signal line; a gate of the first transistor being electrically connected to a second terminal of the first capacitor and a first wiring; a second terminal of the second transistor being electrically connected to a second wiring; a gate of the second transistor being electrically connected to a third wiring; a second terminal of the third transistor being electrically connected to a first terminal of the fourth transistor, a gate of the fourth transistor, and a third signal line; a gate of the third transistor being electrically connected to a second terminal of the fourth transistor, a first terminal of the fifth transistor, and a second terminal of the second capacitor; a second terminal of the fifth transistor being electrically connected to a fourth wiring; a gate of the fifth transistor being electrically connected to the second signal line or a gate of the first transistor; a drive circuit.

2. The drive circuit according to claim 1, wherein the gate of the fifth transistor is electrically connected to the second signal line. a drive circuit.

3. The drive circuit according to claim 1, wherein the gate of the fifth transistor is electrically connected to the gate of the first transistor. a drive circuit.

4. The drive circuit according to claim 2, wherein the first circuit has a function of supplying a first potential from the second signal line to the first signal line, and the second circuit has a function of supplying a second potential from the third signal line to the first signal line during a period different from a period in which the first potential is supplied. a drive circuit.

5. The drive circuit according to claim 3, wherein the first circuit has a function of supplying a first potential from the second signal line to the first signal line, and the second circuit has a function of supplying a second potential from the third signal line to the first signal line during a period different from a period in which the first potential is supplied. a drive circuit.

6. The drive circuit according to any one of claims 1 to 5, The channel width of the third transistor is larger than the channel width of the fourth transistor. Drive circuit.

7. In any one of Claims 1 to 5, The channel width of the first transistor is larger than the channel width of the fifth transistor. Drive circuit.

8. In any one of Claims 1 to 5, The width of the third signal line is larger than the width of the second signal line. Drive circuit.

9. A drive circuit according to Claim 4 or Claim 5, and a pixel, The pixel includes a sixth transistor and a functional element, The gate of the sixth transistor is electrically connected to the first signal line, The first terminal of the sixth transistor is electrically connected to the functional element, The second terminal of the sixth transistor is electrically connected to the fourth signal line, Each of the first potential and the second potential is a potential capable of turning on the sixth transistor. Semiconductor device.

10. In Claim 9, The functional element is a liquid crystal element. Semiconductor device.

11. It has m (m is an integer of 2 or more) first circuits and m second circuits, Each of the m first circuits includes a first transistor, a second transistor, and a first capacitor element, Each of the m second circuits includes a third transistor, a fourth transistor, a fifth transistor, and a second capacitor element, The first terminal of the first transistor is electrically connected to the first terminal of the second transistor, the first terminal of the third transistor, the first terminal of the first capacitor element, the first terminal of the second capacitor element, and the first signal line, The second terminal of the first transistor is electrically connected to the second signal line, The gate of the first transistor is electrically connected to the second terminal of the first capacitor element and the first wiring, The second terminal of the second transistor is electrically connected to the second wiring, The gate of the second transistor is electrically connected to the third wiring, The second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor, the gate of the fourth transistor, and the third signal line, The gate of the third transistor is electrically connected to the second terminal of the fourth transistor, the first terminal of the fifth transistor, and the second terminal of the second capacitor element, The second terminal of the fifth transistor is electrically connected to the fourth wiring, The gate of the fifth transistor is electrically connected to the second signal line or the gate of the first transistor. The m first circuits have a function of sequentially supplying a first potential from the second signal line electrically connected to each of the m first circuits to m first signal lines electrically connected to each of the m first circuits. The m second circuits have a function of simultaneously supplying a second potential from the third signal line electrically connected to the m first circuits to m first signal lines electrically connected to each of the m first circuits in a period different from the period of sequentially supplying the first potential. Drive circuit.

12. In claim 11, The gate of the fifth transistor is electrically connected to the second signal line. Drive circuit.

13. In claim 11, The gate of the fifth transistor is electrically connected to the gate of the first transistor. Drive circuit.

14. In any one of claims 11 to 13, The channel width of the third transistor is larger than the channel width of the fourth transistor. Drive circuit.

15. In any one of claims 11 to 13, The channel width of the first transistor is larger than the channel width of the fifth transistor. Drive circuit.

16. In any one of claims 11 to 13, The width of the third signal line is larger than the width of the second signal line. Drive circuit.

17. A drive circuit according to any one of claims 11 to 13, and m pixels, wherein each of the m pixels has a sixth transistor and a functional element, the gate of the sixth transistor is electrically connected to the first signal line, the first terminal of the sixth transistor is electrically connected to the functional element, the second terminal of the sixth transistor is electrically connected to a fourth signal line, and each of the first potential and the second potential is a potential capable of turning on the sixth transistor. Semiconductor device.

18. In claim 17, The functional element is a liquid crystal element. Semiconductor device. ​ ​ ​ ​ ​

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