Chip with cascode circuits

Abstract

SOLUTION: To provide a chip 1400 comprising a plurality of cascode circuits 1401, in which each cascode circuit has at least one cascode 1402 having at least one respective cascode transistor 1403, and a voltage generation circuit 1404 which is set up to generate control voltages for controlling the cascode transistors of the cascode circuits, a respective transistor circuit 1405 for each cascode, which is connected between the voltage generation circuit and the cascode, having a respective source follower 1406 and being set up to generate a cascode transistor control voltage for the at least one cascode transistor of the cascode by means of the respective source follower from a respective control voltage of the control voltages generated by the voltage generation circuit.EFFECT: Reliability of a transistor is improved, and fast switching is made possible.SELECTED DRAWING: Figure 14

Description

Technical Field

[0001] The embodiments generally relate to a chip having a cascode circuit.

Background Art

[0002] According to future technologies, transistors will become smaller and smaller, and the reliability of transistors will become increasingly important, especially in products for the automotive industry where there must be no errors throughout the entire lifespan. Since the limit of the allowable voltage range for smaller components should also become smaller and smaller, a situation may occur where a circuit portion without the corresponding rated voltage has to handle high voltages. An example of this is an input / output interface that desirably has tolerance to overvoltage.

[0003] That is, for example, a 5V device (in other words, a device equipped with a 5V power supply voltage section and a 5V input / output interface) is provided, but this device may have to be driven using transistors having an operating voltage lower than 5V, for example 3.3V.

[0004] One approach to enable this is the use of a cascode where a high voltage is divided among a plurality of transistors and thus these transistors can be designed for a lower voltage. However, an appropriate cascode voltage must be supplied to the cascode transistors of the cascode, and thus an approach that can perform this efficiently (with a small required area) and robustly (for example, so that the switching process in one cascode does not affect another cascode) is desired.

Summary of the Invention

Means for Solving the Problems

[0005] According to one embodiment, a chip having a plurality of cascode circuits each having at least one cascode including each cascode transistor, and a voltage forming circuit configured to form a control voltage for controlling the cascode transistors of the cascode circuits, wherein for each cascode, each transistor circuit connected between the voltage forming circuit and the cascode has each source follower, and using each source follower, from each control voltage of the control voltage formed by the voltage forming circuit, a cascode transistor control voltage for at least one cascode transistor of the cascode is formed, is provided.

[0006] It should be understood that the figures do not reflect actual dimensional ratios and are used to illustrate the basic schemes of various embodiments. Hereinafter, various embodiments will be described with reference to the figures.

Brief Description of the Drawings

[0007]

Figure 1

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Figure 11

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Figure 13

Figure 14

[0008] The following detailed description relates to the accompanying drawings showing each detail and each example. These examples are described in detail so that those skilled in the art can practice the present invention. Other embodiments are also possible, and each example can be modified in terms of structure, logic, and electricity without departing from the subject matter of the present invention. These various examples are not mutually essential, and various embodiments can be combined with each other, thereby obtaining new embodiments. In the framework of this specification, the terms "connected", "connected", and "coupled" are used to represent both direct and indirect connections, direct or indirect connections, and direct or indirect couplings.

[0009] FIG. 1 shows an electronic device 100 according to one embodiment.

[0010] The electronic device 100 is, for example, an electronic control unit (ECU) for a vehicle in particular, but may also be a control device or a data processing device for other devices such as machines, generators, and the like.

[0011] The electronic device 100 includes two electronic components 101, 102, for example, a (data processing) chip 101 and a sensor 102 (this sensor 102 may be implemented as a chip or may include a chip). However, the electronic device 100 is only used as an example below, and the electronic components 101, 102 may be other components, and these electronic components 101, 102 do not have to be part of the same electronic device and may be arranged separately from each other.

[0012] The chip 101 includes an input / output circuit 103 by, for example, E / A (or I / O) cells from a corresponding library. The input / output circuit 103 is connected, for example, on the one hand to a processor 104 in the chip 101 and on the other hand to a pad 105 of the chip 101. The connection line 106 connects the pad 105 to the sensor 102.

[0013] The main feature of the E / A cell is the connection between an on-chip signal with a low voltage (core voltage VDD, for example 3.3V) and an off-chip signal with a higher voltage (pad voltage VDDP, for example 5V), and vice versa. In this case, both the input direction (from off-chip to on-chip, for example when receiving a signal from a sensor) and the output direction (from on-chip to off-chip, for example when controlling a sensor or another circuit) can be supported.

[0014] If the technology used to manufacture the chip 101 includes only components that cannot withstand the pad voltage for a relatively long time, a stacking concept can be used, as shown in the example of the output driver in FIG. 2.

[0015] FIG. 2 shows an output driver 200 for a pad 205 according to an embodiment.

[0016] Two (or more) first components (in the example described herein, field effect transistors (FETs), such as nMOS and / or pMOS) 201, 202 are used connected in series to form an HS (high voltage side, high side) driver 207, and two (or more) second components (FETs) 203, 204 are used connected in series to form an LS (low voltage side, low side) driver 208. The HS driver 207 and the LS driver 208 are each implemented as a cascode (having two stages in this example, but more stages are possible). The HS driver 207 and the LS driver 208 together form a cascode circuit 220.

[0017] The connection point between the HS driver 207 and the LS driver 208 is connected to a pad 205. The HS driver 207 is connected between a high pad supply potential (VDDP) and the pad 205, and the LS driver 208 is connected between the pad 205 and a low pad supply potential (GND).

[0018] In the concept here, the pad voltage between VDDP and the pad 205 or the pad voltage between the pad 205 and GND is divided to the components 201, 202 of the HS driver 207 or the components 203, 204 of the LS driver 208 so that only the voltages that the individual components 201 - 204 can handle are recognized. Here, for example, the pad voltage may be up to 5V, and the components 201 - 204 may be only 201, 202 which are 3.3V components (another example of the voltage ratio is VDDP = 3.3V and the components are designed for 1.8V).

[0019] Hereinafter, the components directly connected to the PAD, namely components 202 and 203, are referred to as cascode transistors, and the other two components 201 and 204 connected to VDDP or GND are referred to as switching transistors. The switching transistors 201 and 204 are driven and controlled by a signal Sh or Sl (also referred to as the switching transistor control voltage). Voltages CascodeH and CascodeL internally formed by the intermediate voltage forming circuit 206 are supplied to the gates of the cascode transistors 202 and 203, and these voltages are driven and controlled so that the voltage VDDP is accurately divided and none of the four components 201 to 204 are damaged.

[0020] As soon as the pad voltage VDDP is applied to pad 205, the internally formed voltages CascodeH and CascodeL become available. Therefore, the intermediate voltage forming circuit 206 is configured as a voltage divider circuit that forms a voltage based on, for example, VDDP but typically cannot drive a large current. This is because otherwise, a large amount of DC (direct current) power consumption would be required for each individual E / A cell. The intermediate voltage forming circuit 206 can also be realized in other forms, but in this case, typically, a certain start-up time is required, which means stress on components 201 - 204. This is because in this case, the voltages CascodeH and CascodeL are not immediately powered from the pad voltage VDDP, and their lifespan is shortened. Here, it should be noted that due to the stacking of components 201 - 204, strong edges occur at the sources and drains of the cascode transistors 202, 203 during the switching phase (signal changes of Sh and Sl). Therefore, each cascode transistor 202, 203 has a parasitic coupling to its gate (generally the control input side, for example, the control pin) where CascodeH or CascodeL is supplied. As a result, each internally formed control voltage CascodeH or CascodeL changes during the switching process, which can cause a voltage in the stacked module. However, this voltage is outside the allowable range of the module and can have a negative impact on the switching characteristics. To avoid this, for example, a large capacitor can be connected to the control pins of the cascode transistors 202, 203, but this requires space and charging must be performed during the start-up phase, further extending the start-up time.

[0021] According to the above considerations, various embodiments provide a concept of a driver for a cascode (which has two stages hereinafter, but can also have more stages), which enables high-speed switching while improving accuracy and the reliability of the stacked transistors used (i.e., components 201 to 204 in FIG. 2). Thus, transistors with a low voltage class can be used for a relatively high pad voltage without shortening the lifespan of the transistors.

[0022] According to various embodiments, a circuit is inserted between a block that forms a cascode voltage with a low driver potential (intermediate voltage forming circuit 206 in FIG. 2) and the gate of the cascode transistor (i.e., a control pin for example) that must be stabilized due to parasitic coupling. The circuit is shown in FIG. 3 which illustrates its basic concept.

[0023] FIG. 3 shows an output driver 300 according to one embodiment.

[0024] As described with reference to FIG. 2, the output driver 300 includes an HS driver 307 formed by a first switching transistor 301 and a first cascode transistor 302, and an LS driver 308 formed by a second cascode transistor 303 and a second switching transistor 304. The connection nodes of these drivers 307, 308 are connected to a pad 305, and also includes an intermediate voltage forming circuit 306. The HS driver 307 and the LS driver 308 form a cascode circuit 320.

[0025] However, unlike the output driver 200 in FIG. 2, the voltages Vh and Vl formed by the intermediate voltage forming circuit 306 are not directly used as the control voltages CascodeH and CascodeL of the cascode transistors 302 and 303. Instead, the output driver 300 includes a buffering section for the control signals Vh and Vl, and the voltages CascodeH and CascodeL are controlled via this buffering section.

[0026] Specifically, the first source follower 309 receives a voltage Vh shifted by only the voltage Vsh (at its gate, generally on the control input side) to form CascodeH (which is powered from VDDP), and the second source follower 310 receives a voltage Vl shifted by only the voltage Vsl (at its gate) to form CascodeL (which is powered from GND).

[0027] It should be understood that a source follower is a field effect transistor of a drain circuit (English: common drain, source follower). The input voltage is the shift voltage Vh or Vl and the output voltage CascodeH or CascodeL. VDDP is a power supply section.

[0028] By driving and controlling the transistor that raises the control voltage Vh with respect to the voltage drop Vsh and forms a voltage loss having an equivalent voltage drop Vsh as the source follower 309, the cascode control voltage CascodeH has a voltage level equivalent to Vh. However, as soon as the voltage of CascodeH becomes lower than Vh, current is directly drawn from the power supply section (VDDP), so the driver capability becomes extremely high. The same applies to the cascode control voltage CascodeL by the use of the second source follower 310.

[0029] As shown in FIG. 4, such a buffer can be added against the bidirectional switching noise that can occur at the gates (for example, control pins) of the respective cascode transistors 302 and 303.

[0030] FIG. 4 shows an output driver 400 according to one embodiment.

[0031] Similar to the output driver 300 in FIG. 3, the output driver 400 includes an HS driver 407 formed by a first switching transistor 401 and a first cascode transistor 402, and an LS driver 408 formed by a second cascode transistor 403 and a second switching transistor 404. Connection nodes of these drivers 407 and 408 are connected to a pad 405. The output driver 400 further includes an intermediate voltage generation circuit 406 (implemented as a voltage divider circuit, for example), a first source follower 409, and a second source follower 410. The HS driver 407 and the LS driver 408 form a cascode circuit 420.

[0032] Furthermore, the output driver 400 receives a voltage Vh shifted by a voltage Vsh at its gate, and further includes a third source follower 411 powered from GND. Since the output side of the third source follower 411 is connected to the output side of the first source follower 409, these two source followers 409 and 411 together form CascodeH.

[0033] Similarly, the output driver 400 receives a voltage Vl shifted by a voltage Vsl at its gate, and further includes a fourth source follower 412 powered from VDDP. Since the output side of the fourth source follower 412 is connected to the output side of the second source follower 410, these two source followers 410 and 412 together form CascodeL.

[0034] Thus, in order to maintain the allowable voltage regions of all transistors by the HS driver 407 and the LS driver 408, it is possible to compensate for both the decrease and increase of the voltage CascodeH or CascodeL. As a result, the formed internal voltages Vh and Vl are separated from the switching noise, and thus the internal voltages Vh and Vl are more stabilized, and the DC current consumption of the intermediate voltage forming circuit 406 is reduced. This is because the intermediate voltage forming circuit 406 only needs to drive a small noise-free load. Additionally, the noise generated by the coupling with the gates of the respective cascode transistors 402 and 403 can be compensated by a current that is almost unrestricted during the switching phase without causing an increase in the overall DC current consumption (and the parasitic capacitance can be charged accordingly).

[0035] FIG. 5 shows an output driver 500 according to an embodiment in which the example of FIG. 3 is extended by a closed-loop control unit.

[0036] Similar to the output driver 300 of FIG. 3, the output driver 500 includes an HS driver 507 formed by a first switching transistor 501 and a first cascode transistor 502, and an LS driver 508 formed by a second cascode transistor 503 and a second switching transistor 504, wherein the connection nodes of these drivers 507 and 508 are connected to a pad 505, an intermediate voltage forming circuit 506 (implemented as a voltage divider circuit, for example), a first source follower 509, and a second source follower 510. The HS driver 507 and the LS driver 508 form a cascode circuit 520.

[0037] Unlike the output driver 300 of FIG. 3, the voltages Vh and Vl between the intermediate voltage forming circuit 506 and the respective source followers 509 and 510 are buffered by the respective buffer circuits 511 and 512.

[0038] In the driver circuit 300 of FIG. 3, due to the voltage shifts (Vsh and Vsl), current can flow into or out of the intermediate voltage forming circuit 306. The mismatch of the two currents that cause the voltage shifts of Vsh and Vsl may cause an error during voltage formation, and this error also causes a voltage shift at the gates of the cascode transistors 302, 303. By using the (true) buffer circuits 511 and 512, the flow of current (possibly caused by Vsh and Vsl) into or out of the intermediate voltage forming circuit 506 is avoided, thereby preventing the flow of this current at the gates of the cascode transistors 502, 503. Additionally, the buffer circuits 511, 512 can be used as control loops for each equivalent intermediate node or as the finally used control voltages CascodeH and CascodeL (by feeding back CascodeH and CascodeL to each operational amplifier of each buffer circuit 511, 512 as shown in FIG. 5), thereby further enhancing the accuracy. Thus, the mismatch of the voltage shifts upward and downward is replaced by the offset of the buffer circuit, making it much better reducible.

[0039] The buffers described with reference to FIG. 5 can also be applied to the other source followers 411, 412 in the structure of FIG. 4.

[0040] FIG. 6 shows an output driver 600 according to an embodiment that extends the example of FIG. 3 by the guide modules 611, 612.

[0041] Similar to the output driver 300 in FIG. 3, the output driver 600 includes an HS driver 607 formed by a first switching transistor 601 and a first cascode transistor 602, and an LS driver 608 formed by a second cascode transistor 603 and a second switching transistor 604. The connection nodes of these drivers 607 and 608 are connected to a pad 605. The output driver 600 further includes an intermediate voltage forming circuit 606 (which is realized as a voltage divider circuit, for example), a first source follower 609, and a second source follower 610. The HS driver 607 and the LS driver 608 form a cascode circuit 620.

[0042] For the cascode transistor control voltages CascodeH and CascodeL, guide modules 611 and 612 are respectively provided. By these guide modules 611 and 612, each cascode transistor control voltage can be adjusted in advance. For example, when a switching transistor control signal Sh or Sl of the switching transistors 601 and 604 switches one of the largest circuits of the chip 101, which is typically the final stage of the output driver, a fault is input to the cascode transistor control voltages CascodeH and CascodeL. Each guide module 611 or 612 can cause a shift of each cascode voltage CascodeH or CascodeL depending on the switching transistor control signals Sh and / or Sl by any circuit.

[0043] FIG. 7 shows an example in which the guide modules 611 and 612 are realized by capacitors 713 and 714 between the gates of the switching transistors 701 and 704 and the gates of the cascode transistors 702 and 703.

[0044] Although the source follower is not shown in FIG. 7, a source follower may be provided as described with reference to FIG. 3, FIG. 4, or FIG. 5.

[0045] By using capacitors 713 and 714, a simple solution is provided to input noise to the cascode transistor control voltages CascodeH and CascodeL based on parasitic couplings 715 and 716. Each capacitor 713, 714 can shift the cascode control voltage by the predicted value of the input voltage from the assumed voltage, so that during switching, the parasitic couplings 715, 716 pull the cascode control voltage back to the region of the assumed voltage again.

[0046] FIG. 8 shows an example in which the guide modules 611, 612 are realized in parallel with the source followers 809, 810 by the respective boost circuits 813, 814. When the source followers 809, 810 are switched on, the cascode transistor control voltages CascodeH and CascodeL are amplified, whereby the assumed voltage is achieved more quickly and / or the obstacles described with reference to FIG. 7 are removed. This is the source follower itself according to one embodiment, and is further powered and driven in the same manner as the source followers 809, 810 (i.e., its gate (generally the control input side) is connected to the gate of, for example, the source followers 809, 810).

[0047] For example, a logic circuit 815 (represented here by switches 816, 817) is provided, and when Sh and Sl are switched, the logic circuit 815 activates the power supply to the boost circuits 813, 814.

[0048] As shown in FIGS. 7 and 8, the switching transistor control signals Sh and Sl are generated from, for example, the control signals Shin and Slin supplied to the buffer.

[0049] The guide module in FIG. 7 and the guide module in FIG. 8 may be combined (can be coupled).

[0050] FIG. 9 shows an example of an output driver 900 (based on the output driver 300 of FIG. 3), where the output side of the first source follower 909 is connected to VDDP via the first current source 911, and the output side of the second source follower 910 is connected to GND via the second current source 912.

[0051] This has the advantage that the maximum supply voltage is applied to the cascode transistors in a voltage region where the intermediate voltage forming circuit 906 is not yet fully operational and / or where the source follower is still unable to switch on due to this, or in a voltage region where the desired target voltage difference regions (VDDP - CascodeH) for CascodeH and (CascodeL - VSSP) for CascodeL are assumed and the voltage VDDP is exceeded, and the transistors are protected, but the gate voltage by the second source follower can be further limited. As a result, complete performance can be achieved at a relatively low VDDP voltage.

[0052] FIG. 10 shows an example of an output driver 1000 (based on the output driver 900 of FIG. 9), where the output stage is not realized by stacked transistors, but additional transistors 1007, 1008 (e.g., DMOS or high - voltage transistors having a VDS voltage that meets the 5V requirement but whose gates are still enabled only for, e.g., 3.3V) are provided. Subsequently, source followers etc. within the output driver path can be used only for the internal circuit, e.g., only for the driver of the output stage and the signal level shifter. That is, from this example here, not only the preceding circuit connected to the PAD but also the circuits used only internally can be driven.

[0053] FIG. 11 shows an example of an output driver 1100 (based on the output driver 900 of FIG. 9), where in addition to the cascode formed by transistors 1101 to 1104, there is a further stage having a cascode formed by a third switching transistor 1111 and a third cascode transistor 1112 or two cascodes formed by a fourth switching transistor 1114 and a fourth cascode transistor 1113.

[0054] The example of FIG. 11 is equivalent to the example of FIG. 10. In FIG. 11, the additional (e.g., DMOS) transistors of the output stage are again replaced by the stacked circuits of FIGS. 2 to 9, and the only difference is that additionally a driver from that stage is also shown in front of it.

[0055] In the above-described examples, one output driver has been described for each, i.e., the output signal is output via a pad, where the output signal is determined by the result of the Sh and Sl states set for data transmission by, for example, the processor 104 (optionally via the interface circuit of the chip 101). However, the concepts described above in relation to the output driver can also be used for data reception via the pad. In this case, the switching transistor is controlled not by the signals Sh and Sl, but by the signal applied to the pad. Examples of this are shown in FIGS. 12 and 13.

[0056] FIG. 12 shows an input circuit 1200 according to an embodiment.

[0057] The input circuit 1200 is configured in the same manner as the output driver 1100 in FIG. 11, except that the gates of the first switching transistor 1201 and the second switching transistor 1204 are connected to the pad 1205 via the third cascode transistor 1212 or the fourth cascode transistor 1213. As a result, at the pad 1205, the first switching transistor 1201 and the second switching transistor 1204 are controlled by the level applied to the pad 1205 from the second electronic component 102 (e.g., a sensor). The third switching transistor 1111 and the fourth switching transistor 1114 are omitted.

[0058] The connection node between the first cascode transistor 1202 and the second cascode transistor 1203 forms a reception node and is connected to, for example, the input side of the processor 104 or the interface circuit of the chip 101.

[0059] FIG. 13 shows an input circuit 1300 according to another embodiment.

[0060] Similar to the output driver 1100 in FIG. 11 being extended by two additional cascodes with respect to the output driver 900 in FIG. 9, the input circuit 1300 corresponds to the input circuit 1200 in FIG. 12 being extended by another stage including two additional cascodes 1314, 1315 (here added on the left side. This is because, unlike the output driver 1100 in FIG. 11, the pad is used as an input side).

[0061] Furthermore, in the above example, two complementary input nodes are used (the connection nodes between the switching transistors and the cascode transistors of the added cascodes).

[0062] The circuit of FIG. 13 is equivalent to the circuit of FIG. 12, and here, additional internal buffer cells not connected to the pads are included. Further, different from FIG. 12, the connection nodes 1202 and 1203 are not used as input signals (this signal is often also, for example, 5V in the same way), but a voltage amplitude limited by the voltages of CascodeH and CascodeL is used. That is, also in this case, the next pMOS transistor (equivalent to 1201) and the next nMOS transistor (equivalent to 1204) can be drive-controlled (as shown also in FIG. 13), which means that the amplitude of the signal is reduced and the transistors to be drive-controlled are not damaged.

[0063] As described above, by connecting the unit that forms the cascode voltage (also referred to as the intermediate voltage forming circuit in the above example) via a source follower, the noise in the cascode (for example, as in the HS driver and LS driver of the above embodiment, noise can be avoided, and here they may each have a plurality of cascodes as in the examples of FIGS. 11 and 13) has a negative impact on the unit that forms the cascode voltage. This is particularly important when the intermediate voltage forming circuit supplies (the same cascode transistor control voltage or in some cases at least partially different cascode transistor control voltages) to a plurality of cascode circuits. Because noise propagation from one cascode circuit to another cascode circuit is avoided.

[0064] In summary, according to various embodiments, a chip shown in FIG. 14 is provided.

[0065] FIG. 14 shows a chip 1400 according to an embodiment.

[0066] The chip 1400 has a plurality of cascode circuits 1401, and in this case, each cascode circuit 1401 has at least one cascode 1402 including at least one cascode transistor 1403.

[0067] The chip 1400 further has a voltage forming circuit 1404, which is configured to form a control voltage for controlling the cascode transistor 1403 of the cascode circuit 1401.

[0068] For each cascode 1402, the chip 1400 further has each transistor circuit 1405 connected between the voltage forming circuit 1404 and the cascode 1402, and each source follower 1406. Using each source follower 1406, a cascode transistor control voltage for at least one cascode transistor 1403 of the cascode 1402 is formed from each control voltage of the control voltage formed by the voltage forming circuit 1404.

[0069] In other words, according to various embodiments, the voltage forming circuit supplies power to a plurality of cascodes, but each cascode is separated by a source follower as long as the voltage fluctuation in one cascode does not affect other cascodes.

[0070] By the method according to FIG. 14, a stabilized switching behavior of a plurality of cascodes that improves the reliability and lifespan of the components involved becomes possible. The signal frequency can be increased, and since the drop of the gate voltage of the cascode transistor can be limited, jitter can be reduced by the coupling between cascodes. The method here requires only a small required area (even when additionally provided as in the example of FIG. 7) compared to, for example, the use of capacitance to stabilize the cascode transistor control voltage.

[0071] Various examples are shown below.

[0072] Example 1 is the chip described with reference to FIG. 14.

[0073] Example 2 is the chip according to Example 1. Each transistor circuit increases each control voltage of the control voltages formed by the voltage forming circuit in correspondence with the voltage drop in the source follower, and each source follower is controlled by the increased control voltage.

[0074] Example 3 is the chip according to Example 1 or 2. For each cascode, each transistor circuit has two source followers respectively, and is configured to form a cascode transistor control voltage for at least one cascode transistor of each cascode from each control voltage of the control voltages formed by the voltage forming circuit by using the source followers. A high supply potential is supplied to one of the source followers, and a low supply potential is supplied to another one of the source followers.

[0075] Example 4 is the chip according to any one of Examples 1 to 3. Each transistor circuit has each buffer circuit configured to buffer each control voltage of the control voltages formed by the voltage forming circuit, and each source follower is controlled by the buffered control voltage.

[0076] Example 5 is the chip according to any one of Examples 1 to 4. The chip includes each guide module for each cascode. The guide module supplies a cascode transistor control voltage to at least one cascode transistor, and is further configured to compensate for the variation of the cascode transistor control voltage based on the switching of the cascode.

[0077] Example 6 is the chip according to Example 5. Each guide module has a capacitor between the line for supplying the cascode transistor control voltage to the cascode transistor and the line for supplying the switching transistor control voltage to the switching transistor of the cascode.

[0078] Example 7 is a chip according to Example 5 or 6, each guide module having a respective source follower that is switched on during the switching of the cascode, and the cascode transistor control voltage being amplified by the respective source follower.

[0079] Example 8 is one chip according to Example 7, each respective source follower having the same power supply section as the each source follower, and / or for each respective source follower, the same voltage as the each source follower is supplied to its control input side.

[0080] Example 9 is a chip according to any one of Examples 1 to 8, a supply potential corresponding to the supply potential of the cascode being supplied to one supply terminal of the source follower, and a current source being supplied to the other supply terminal.

[0081] Example 10 is a chip according to any one of Examples 1 to 9, each of at least most of the cascodes having an output side connected to each output terminal of the chip.

[0082] Example 11 is a chip according to any one of Examples 1 to 9, each of at least most of the cascodes being configured to form an output voltage for controlling each output transistor of the chip.

[0083] Example 12 is a chip according to any one of Examples 1 to 9, each of at least most of the cascodes being controlled by the voltage applied to each input terminal of the chip.

[0084] Example 13 is a chip according to any one of Examples 1 to 12, the cascodes being at least partially connected in series, whereby each of a plurality of cascode circuits has one high-voltage side driver and / or one low-voltage side driver.

[0085] Example 14 is the chip according to Example 13, and the cascodes are at least partially connected in parallel, whereby a high-voltage side driver and / or a low-voltage side driver are formed by a plurality of cascodes connected in parallel.

[0086] Example 15 is the chip according to Example 14, and the cascode transistors of the cascodes connected in parallel are controlled by the same cascode transistor control voltage.

[0087] Example 16 is an electronic device, and the electronic device includes a chip according to any one of Examples 1 to 15, and a cascode is formed from a transistor having a rated voltage lower than the input voltage of the input circuit formed by the input circuit of the chip in the device and / or from a transistor having a rated voltage lower than the output voltage of the output circuit formed by the output circuit of the chip in the device.

[0088] Although the present invention has been illustrated and described in connection with specific embodiments, those skilled in the art should understand that many changes can be made to the configuration and details without departing from the essence and scope of the present invention defined by the following claims. Therefore, the scope of the present invention is determined by the appended claims, and it is intended to include all modifications that fall within the literal meaning or the equivalent scope of the claims.

Explanation of Reference Numerals

[0089] 100 Electronic device 101 Electronic component, such as a chip 102 Electronic component, such as a sensor 103 Input / output circuit 104 Processor 105 Pad 106 Connection line 200 Output driver 201 Switching transistor 202, 203 Cascode transistors 204 Switching Transistor 205 Pad 206 Intermediate Voltage Formation Circuit 207 HS Driver 208 LS Driver 220 Cascode Circuit 300 Output Driver 301 Switching Transistor 302, 303 Cascode Transistors 304 Switching Transistor 305 Pad 306 Intermediate Voltage Formation Circuit 307 HS Driver 308 LS Driver 309, 310 Source Follower 320 Cascode Circuit 400 Output Driver 401 Switching Transistor 402, 403 Cascode Transistors 404 Switching Transistor 405 Pad 406 Intermediate Voltage Formation Circuit 407 HS Driver 408 LS Driver 409~412 Source Follower 420 Cascode Circuit 500 Output Driver 501 Switching Transistor 502, 503 Cascode Transistors 504 Switching Transistor 505 Pad 506 Intermediate Voltage Formation Circuit 507 HS Driver 508 LS Driver 509, 510 Source Follower 511, 512 Buffer Circuit 520 Cascode Circuit 600 Output Driver 601 Switching Transistor 602, 603 cascode transistors 604 switching transistor 605 pad 606 intermediate voltage formation circuit 607 HS driver 608 LS driver 609, 610 source follower 611, 612 guide module 620 cascode circuit 700 output driver 701 switching transistor 702, 703 cascode transistors 704 switching transistor 705 pad 713, 714 capacitor 715, 716 parasitic coupling 800 output driver 809, 810 source follower 813, 814 boost circuit 815 logic circuit 816, 817 switch 900 output driver 909, 910 source follower 911, 912 current source 1000 output driver 1001, 1004 switching transistors 1007 HS driver 1008 LS driver 1011, 1012 another transistor 1100 output driver 1101 switching transistor 1102, 1103 cascode transistors 1104 switching transistor 1107 HS driver 1108 LS driver 1111 switching transistor 1112, 1113 cascode transistors 114 switching transistor 1200 Input Circuit 1201 Switching Transistor 1202, 1203 Cascode Transistors 1204 Switching Transistor 1205 Pad 1212, 1213 Cascode Transistors 1300 Input Circuit 1314, 1315 Another Cascode

Claims

1. A plurality of cascode circuits each having at least one cascode including at least one cascode transistor; A voltage forming circuit configured to form a control voltage for controlling the cascode transistors of the cascode circuits; A chip having: For each cascode, each transistor circuit connected between the voltage forming circuit and the cascode has each source follower, and using each source follower, from each control voltage of the control voltage formed by the voltage forming circuit, it is configured to form a cascode transistor control voltage for at least one cascode transistor of the cascode. Chip.

2. Each transistor circuit increases each control voltage of the control voltage formed by the voltage forming circuit corresponding to the voltage drop in the source follower, and each source follower is controlled by the increased control voltage. The chip according to claim 1.

3. For each cascode, each transistor circuit has two source followers each, and using the source followers, from each control voltage of the control voltage formed by the voltage forming circuit, it is configured to form a cascode transistor control voltage for at least one cascode transistor of each cascode. A high supply potential is supplied to one of the source followers, and a low supply potential is supplied to another one of the source followers. The chip according to claim 1 or 2.

4. Each transistor circuit has each buffer circuit configured to buffer each control voltage of the control voltage formed by the voltage forming circuit, and each source follower is controlled by the buffered control voltage. The chip according to any one of claims 1 to 3.

5. The chip includes one guide module for each cascode, and the guide module is configured to supply a cascode transistor control voltage to at least one of the cascode transistors and further compensate for fluctuations in the cascode transistor control voltage based on the switching of the cascode. The chip according to any one of claims 1 to 4.

6. Each guide module has a capacitor between a line that supplies a cascode transistor control voltage to the cascode transistor and a line that supplies a switching transistor control voltage to the switching transistor of the cascode. The chip according to claim 5.

7. Each guide module has a separate source follower that is switched on when the cascode switches, and the separate source follower amplifies the control voltage of the cascode transistor. The chip according to claim 5 or 6.

8. Each separate source follower has the same power supply unit as each source follower, and / or the same voltage as each source follower is supplied to the control input side of each separate source follower. The chip according to claim 7.

9. A supply potential corresponding to the supply potential of the cascode is supplied to one supply terminal of the source follower, and a current source is supplied to the other supply terminal. The chip according to any one of claims 1 to 8.

10. At least most of each of the cascodes has an output side connected to each output terminal of the chip. The chip according to any one of claims 1 to 9.

11. At least most of each of the cascodes is configured to form an output voltage for controlling each output transistor of the chip. The chip according to any one of claims 1 to 9.

12. At least most of each of the cascodes is controlled by a voltage applied to each input terminal of the chip. The chip according to any one of claims 1 to 9.

13. The cascodes are at least partially connected in series, whereby each of the plurality of cascode circuits has one high-voltage side driver and / or one low-voltage side driver. The chip according to any one of claims 1 to 12.

14. The cascodes are at least partially connected in parallel, whereby the high-voltage side driver and / or the low-voltage side driver is formed by a plurality of cascodes connected in parallel. The chip according to claim 13.

15. The cascode transistors of the plurality of cascodes connected in parallel are controlled by the same cascode transistor control voltage. The chip according to claim 14.

16. An electronic device comprising a chip according to any one of claims 1 to 15, wherein the cascode is formed from a transistor having a rated voltage lower than the input voltage of the input circuit formed by the input circuit of the chip in the electronic device and / or from a transistor having a rated voltage lower than the output voltage of the output circuit formed by the output circuit of the chip in the electronic device, the electronic device.

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