Semiconductor device

Abstract

To provide a semiconductor device with a small circuit scale.SOLUTION: A semiconductor device includes first and second circuits. The first circuit includes first to n-th (n is an integer of 2 or more) transistors, and the second circuit includes (n+1)-th to 2n-th transistors. The first to n-th transistors are connected in parallel, and the (n+1)-th to 2n-th transistors are connected in series. The first to n-th signals are supplied to the first and second circuits. The first circuit has a function of outputting a first potential when all of the potentials of the first to n-th signals are lower than or equal to a first reference potential and outputting a second potential when at least one of the potentials of the first to n-th signals is higher than the first reference potential. The second circuit has a function of outputting a third potential when all of the potentials of the first to n-th signals are higher than a second reference potential, and a function of outputting the first potential when at least one of the potentials of the first to n-th signals is lower than or equal to the second reference potential.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a driving method thereof.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof.

[0003] Note that in this specification and the like, the semiconductor device generally refers to any device that can function by utilizing semiconductor characteristics. A display device (such as a liquid crystal display device, a light-emitting display device, etc.), a projection device, an illumination device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, a signal processing device, a transmission / reception device, a wireless sensor, and a sensor device may be said to have a semiconductor device.

Background Art

[0004] Semiconductor devices having a function of detecting a potential level have been developed. For example, Patent Document 1 discloses a semiconductor device that detects the potential level of a signal line using a potential level detection circuit having a comparator.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] When attempting to endow a comparator with the function of detecting a potential level, especially when the number of signals for detecting the potential level is large, a large number of comparators are required. As a result, the circuit scale of the semiconductor circuit becomes large. Thereby, the semiconductor device becomes large-sized, and the power consumption of the semiconductor device also increases.

[0007] In addition, a comparator is generally constituted by CMOS (Complementary Metal Oxide Semiconductor) in order to enhance characteristics such as gain and input voltage range. That is, it is constituted by both an n-channel type transistor and a p-channel type transistor. Here, for example, a transistor having a metal oxide in a region where a channel is formed (hereinafter also referred to as a channel formation region) (hereinafter also referred to as an OS transistor) is an n-channel type transistor. Therefore, for example, if a comparator is constituted only by OS transistors, the characteristics of the comparator will be significantly degraded.

[0008] Therefore, one of the problems of one aspect of the present invention is to provide a semiconductor device with a small circuit scale. Or, one of the problems is to provide a semiconductor device constituted by transistors of the same polarity. Or, one of the problems is to provide a small-sized semiconductor device. Or, one of the problems is to provide a semiconductor device with low power consumption. Or, one of the problems is to provide a semiconductor device that can be manufactured by a simple method. Or, one of the problems is to provide a low-cost semiconductor device. Or, one of the problems is to provide a semiconductor device that can output a signal with high accuracy. Or, one of the problems is to provide a semiconductor device that can be driven at high temperatures. Or, one of the problems is to provide a highly reliable semiconductor device. Or, one of the problems is to provide a novel semiconductor device.

[0009] Another object is to provide a method for driving a semiconductor device with a small circuit scale. Another object is to provide a method for driving a semiconductor device composed of transistors of the same polarity. Another object is to provide a method for driving a small-sized semiconductor device. Another object is to provide a method for driving a semiconductor device with low power consumption. Another object is to provide a method for driving a semiconductor device that can be manufactured by a simple method. Another object is to provide a method for driving a low-cost semiconductor device. Another object is to provide a method for driving a semiconductor device that can output signals with high accuracy. Another object is to provide a method for driving a semiconductor device that can be driven at high temperatures. Another object is to provide a method for driving a highly reliable semiconductor device. Another object is to provide a method for driving a novel semiconductor device.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention has a first circuit and a second circuit. The first circuit has transistors numbered from the first to the nth (n is an integer of 2 or more). The second circuit has transistors numbered from the (n + 1)th to the 2nth. One of the sources or drains of the transistors numbered from the first to the nth is electrically connected to each other. The other of the sources or drains of the transistors numbered from the first to the nth is electrically connected to each other. The sources and drains of the transistors numbered from the (n + 1)th to the 2nth are connected in series with each other. The first to the nth signals are supplied to the first circuit and the second circuit. When all of the potentials of the first to the nth signals are equal to or lower than the first reference potential, the first circuit has a function of outputting a first potential. When at least one of the potentials of the first to the nth signals is higher than the first reference potential, the first circuit has a function of outputting a second potential. When all of the potentials of the first to the nth signals are higher than the second reference potential, the second circuit has a function of outputting a third potential. When at least one of the potentials of the first to the nth signals is equal to or lower than the second reference potential, the second circuit has a function of outputting the first potential. This is a semiconductor device.

[0012] Alternatively, in the above aspect, the second potential may be a potential corresponding to the first reference potential, and the third potential may be a potential corresponding to the second reference potential. This is a semiconductor device.

[0013] Alternatively, in the above aspect, the transistors numbered from the first to the 2nth may be n-channel transistors.

[0014] Alternatively, in the above aspect, the second reference potential may be lower than the first reference potential.

[0015] Alternatively, in the above aspect, the second potential and the third potential may be lower than the first potential.

[0016] Alternatively, in the above aspect, the transistors numbered from the first to the 2nth may have a metal oxide in the channel formation region.

[0017] Alternatively, in the above aspect, it may have a (2n + 1)-th transistor and a (2n + 2)-th transistor. One of the source or drain of the (2n + 1)-th transistor is electrically connected to the first circuit, one of the source or drain of the (2n + 2)-th transistor is electrically connected to the second circuit, the other of the source or drain of the (2n + 1)-th transistor is supplied with a second potential, and the other of the source or drain of the (2n + 2)-th transistor is supplied with a third potential.

[0018] Alternatively, in the above aspect, it may have a (2n + 3)-th transistor and a (2n + 4)-th transistor. One of the source or drain of the (2n + 3)-th transistor is electrically connected to the first circuit, one of the source or drain of the (2n + 4)-th transistor is electrically connected to the second circuit, and the first potential may be supplied to the other of the source or drain of the (2n + 3)-th transistor and the other of the source or drain of the (2n + 4)-th transistor.

[0019] Alternatively, one aspect of the present invention has a first circuit and a second circuit. The first circuit has transistors numbered from the first to the nth (n is an integer of 2 or more), and the second circuit has transistors numbered from the (n + 1)th to the 2nth. The transistors numbered from the first to the 2nth have back gates. One of the sources or drains of the transistors numbered from the first to the nth is electrically connected to each other, and the other of the sources or drains of the transistors numbered from the first to the nth is electrically connected to each other. The sources and drains of the transistors numbered from the (n + 1)th to the 2nth are connected in series with each other. The first to the nth signals are supplied to the first circuit and the second circuit. The first potential is supplied to the back gates of the transistors numbered from the first to the nth, and the second potential is supplied to the back gates of the transistors numbered from the (n + 1)th to the 2nth. When all of the potentials of the first to the nth signals are equal to or lower than the first reference potential, the first circuit has a function of outputting a third potential. When at least one of the potentials of the first to the nth signals is higher than the first reference potential, the first circuit has a function of outputting a fourth potential. When all of the potentials of the first to the nth signals are higher than the second reference potential, the second circuit has a function of outputting a fourth potential. When at least one of the potentials of the first to the nth signals is equal to or lower than the second reference potential, the second circuit has a function of outputting a third potential. This is a semiconductor device.

[0020] Alternatively, in the above aspect, the transistors numbered from the first to the 2nth may be n-channel transistors, and the second potential may be higher than the first potential.

[0021] Alternatively, in the above aspect, the fourth potential may be lower than the third potential.

[0022] Alternatively, in the above aspect, the transistors numbered from the first to the 2nth may have a metal oxide in the channel formation region.

[0023] Alternatively, in the above aspect, it has a (2n + 1)-th transistor and a (2n + 2)-th transistor. One of the source or drain of the (2n + 1)-th transistor is electrically connected to the first circuit, and one of the source or drain of the (2n + 2)-th transistor is electrically connected to the second circuit. A fourth potential may be supplied to the other of the source or drain of the (2n + 1)-th transistor and the other of the source or drain of the (2n + 2)-th transistor.

[0024] Alternatively, in the above aspect, it has a (2n + 3)-th transistor and a (2n + 4)-th transistor. One of the source or drain of the (2n + 3)-th transistor is electrically connected to the first circuit, and one of the source or drain of the (2n + 4)-th transistor is electrically connected to the second circuit. A third potential may be supplied to the other of the source or drain of the (2n + 3)-th transistor and the other of the source or drain of the (2n + 4)-th transistor.

[0025] Alternatively, one aspect of the present invention is a first circuit having first to nth (n is an integer of 2 or more) transistors, a second circuit having (n + 1)th to 2nth transistors, a (2n + 1)th transistor, a (2n + 2)th transistor, a (2n + 3)th transistor, and a (2n + 4)th transistor, wherein one of the sources or drains of the first to nth transistors is electrically connected to each other, the other of the sources or drains of the first to nth transistors is electrically connected to each other, the sources and drains of the (n + 1)th to 2nth transistors are connected in series to each other, one of the sources or drains of the (2n + 1)th transistor is electrically connected to the first circuit, one of the sources or drains of the (2n + 2)th transistor is electrically connected to the second circuit, one of the sources or drains of the (2n + 3)th transistor is electrically connected to the first circuit, and one of the sources or drains of the (2n + 4)th transistor is electrically connected to the second circuit. A driving method of a semiconductor device, wherein first to nth signals are supplied to the first circuit and the second circuit, an ith signal is supplied to the gates of the ith (i is 1 to n) transistor and the (n + i)th transistor, a first potential is supplied to the other of the source or drain of the (2n + 1)th transistor and the other of the source or drain of the (2n + 2)th transistor, a second potential is supplied to the other of the source or drain of the (2n + 3)th transistor, a third potential is supplied to the other of the source or drain of the (2n + 4)th transistor, in a first period, the (2n + 1)th transistor and the (2n + 2)th transistor are turned on, the (2n + 3)th transistor and the (2n + 4)th transistor are turned off, and in a second period, the (2n + 1)th transistor and the (2n + 2)th transistor are turned off, and the (2n + 3)th transistor and the (2n + 4)th transistor are turned on.

[0026] Alternatively, in the above aspect, the first to 2nth transistors may be n-channel type transistors.

[0027] Alternatively, in the above aspect, the third potential may be lower than the second potential.

[0028] Alternatively, in the above aspect, the second potential and the third potential may be lower than the first potential.

[0029] Alternatively, one aspect of the present invention is a semiconductor device driving method having a first circuit including transistors numbered from 1 to n (n is an integer of 2 or more), a second circuit including transistors numbered from n + 1 to 2n, a transistor numbered 2n + 1, a transistor numbered 2n + 2, a transistor numbered 2n + 3, and a transistor numbered 2n + 4. The transistors numbered from 1 to 2n have back gates. One of the sources or drains of the transistors numbered from 1 to n is electrically connected to each other, and the other of the sources or drains of the transistors numbered from 1 to n is electrically connected to each other. The sources and drains of the transistors numbered from n + 1 to 2n are connected in series to each other. One of the sources or drains of the transistor numbered 2n + 1 is electrically connected to the first circuit, one of the sources or drains of the transistor numbered 2n + 2 is electrically connected to the second circuit, one of the sources or drains of the transistor numbered 2n + 3 is electrically connected to the first circuit, and one of the sources or drains of the transistor numbered 2n + 4 is electrically connected to the second circuit. The driving method includes supplying signals numbered from 1 to n to the first circuit and the second circuit, supplying the i-th signal to the gates of the i-th transistor (i is from 1 to n) and the (n + i)-th transistor, supplying a first potential to the back gates of the transistors numbered from 1 to n, supplying a second potential to the back gates of the transistors numbered from n + 1 to 2n, supplying a third potential to the other of the sources or drains of the transistor numbered 2n + 1 and the other of the sources or drains of the transistor numbered 2n + 2, supplying a fourth potential to the other of the sources or drains of the transistor numbered 2n + 3 and the other of the sources or drains of the transistor numbered 2n + 4, turning on the transistor numbered 2n + 1 and the transistor numbered 2n + 2 and turning off the transistor numbered 2n + 3 and the transistor numbered 2n + 4 in a first period, and turning off the transistor numbered 2n + 1 and the transistor numbered 2n + 2 and turning on the transistor numbered 2n + 3 and the transistor numbered 2n + 4 in a second period.

[0030] Alternatively, in the above aspect, the first to 2n-th transistors are n-channel transistors, and the second potential may be higher than the first potential.

[0031] Alternatively, in the above aspect, the fourth potential may be lower than the third potential.

Advantages of the Invention

[0032] According to one aspect of the present invention, a semiconductor device with a small circuit scale can be provided. Alternatively, a semiconductor device composed of transistors of the same polarity can be provided. Alternatively, a small-sized semiconductor device can be provided. Alternatively, a low-power-consumption semiconductor device can be provided. Alternatively, a semiconductor device that can be manufactured by a simple method can be provided. Alternatively, an inexpensive semiconductor device can be provided. Alternatively, a semiconductor device that can output signals with high accuracy can be provided. Alternatively, a semiconductor device that can be driven at high temperatures can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a novel semiconductor device can be provided.

[0033] Alternatively, a driving method for a semiconductor device with a small circuit scale can be provided. Alternatively, a driving method for a semiconductor device composed of transistors of the same polarity can be provided. Alternatively, a driving method for a small-sized semiconductor device can be provided. Alternatively, a driving method for a low-power-consumption semiconductor device can be provided. Alternatively, a driving method for a semiconductor device that can be manufactured by a simple method can be provided. Alternatively, a driving method for an inexpensive semiconductor device can be provided. Alternatively, a driving method for a semiconductor device that can output signals with high accuracy can be provided. Alternatively, a driving method for a semiconductor device that can be driven at high temperatures can be provided. Alternatively, a driving method for a highly reliable semiconductor device can be provided. Alternatively, a driving method for a novel semiconductor device can be provided.

[0034] Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0035]

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MODE FOR CARRYING OUT THE INVENTION

[0036] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions in different drawings, and the repeated description thereof will be omitted.

[0037] In addition, the positions, sizes, ranges, etc. of the respective components shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, a resist mask or the like may be unintentionally reduced in size due to a process such as etching, but this may not be reflected in the drawing for the sake of easy understanding.

[0038] In addition, in a top view (also referred to as a "plan view") and a perspective view, etc., for the sake of easy understanding of the drawing, the description of some components may be omitted.

[0039] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" or "wirings" are integrally formed.

[0040] In addition, in this specification and the like, the resistance value of a "resistor" may be determined by the length of the wiring. Or, the resistance value may be determined by connecting to a conductive layer having a resistivity different from that of the conductive layer used for the wiring. Or, the resistance value may be determined by doping a semiconductor with impurities.

[0041] In addition, in this specification and the like, the "terminal" in an electric circuit refers to a part where input or output of current or voltage, and reception or transmission of signals are performed. Therefore, a part of the wiring or electrode may function as a terminal.

[0042] Note that in this specification and the like, the terms "upper" or "lower" do not limit the positional relationship of the components to be directly above or directly below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be directly formed in contact with insulating layer A above it, and those including other components between insulating layer A and electrode B are not excluded.

[0043] In addition, when transistors with different polarities are employed, or when the direction of current changes during circuit driving, etc., the functions of the source and drain are interchanged depending on driving conditions and the like. Therefore, it is difficult to limit which one is the source or the drain. For this reason, in this specification and the like, the terms "source" and "drain" are assumed to be interchangeable.

[0044] In this specification and the like, "electrically connected" includes both the case of direct connection and the case of being connected via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the exchange of electrical signals between the connection targets. Therefore, even when expressed as "electrically connect", in an actual circuit, there may be a case where there is no physical connection part and only wiring extends. Also, even when expressed as "directly connected", it includes the case where different conductive layers are connected via a contact. Note that the wiring may be such that different conductive layers contain one or more identical elements or different elements.

[0045] In this specification and the like, regarding count values and measured values, when using terms such as "identical", "the same", "equal", or "uniform", unless otherwise specified, they shall include an error of plus or minus 20%.

[0046] In this specification and the like, when performing an etching process after forming a resist mask, unless otherwise specified, the resist mask shall be removed after the etching process is completed.

[0047] In addition, voltage often indicates the potential difference between a certain potential and a reference potential (e.g., ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and the like, unless otherwise explicitly stated, voltage and potential can be used interchangeably.

[0048] Even when described as a "semiconductor," for example, when its conductivity is sufficiently low, it has the characteristics of an "insulator." Therefore, it is also possible to use it by replacing "semiconductor" with "insulator." In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "insulator" described in this specification and the like may be mutually interchangeable.

[0049] Also, even when described as a "semiconductor," for example, when its conductivity is sufficiently high, it has the characteristics of a "conductor." Therefore, it is also possible to use it by replacing "semiconductor" with "conductor." In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "conductor" described in this specification and the like may be mutually interchangeable.

[0050] Note that the ordinal numbers such as "first," "second," etc. in this specification and the like are attached to avoid confusion of components, and do not indicate any order or rank such as the process order or the stacking order. Also, even for a term without an ordinal number in this specification, an ordinal number may be attached in the claims to avoid confusion of components. Also, even for a term with an ordinal number in this specification, a different ordinal number may be attached in the claims. Also, even for a term with an ordinal number in this specification, the ordinal number may be omitted in the claims and the like.

[0051] Note that in this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as the "conducting state"). Also, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as the "non-conducting state").

[0052] In addition, in this specification and the like, the "on-current" may refer to the current flowing between the source and the drain when the transistor is in the on state. Also, the "off-current" may refer to the current flowing between the source and the drain when the transistor is in the off state.

[0053] In addition, in this specification and the like, the "gate" refers to part or all of the gate electrode and the gate wiring. The "gate wiring" refers to the wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0054] In addition, in this specification and the like, the "source" refers to part or all of the source region, the source electrode, and the source wiring. The "source region" refers to the region in the semiconductor where the resistivity is below a certain value. The "source electrode" refers to the conductive layer connected to the source region. The "source wiring" refers to the wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0055] In addition, in this specification and the like, the "drain" refers to part or all of the drain region, the drain electrode, and the drain wiring. The "drain region" refers to the region in the semiconductor where the resistivity is below a certain value. The "drain electrode" refers to the conductive layer connected to the drain region. The "drain wiring" refers to the wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0056] In this specification and the like, "metal oxide" is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the semiconductor of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when referring to an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0057] In addition, in this specification and the like, a metal oxide containing nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[0058] (Embodiment 1) In this embodiment, a configuration example of a semiconductor device according to an aspect of the present invention and an example of its driving method will be described with reference to the drawings. However, the present invention is not limited to the configuration example shown in this embodiment. Also, each configuration can be used in appropriate combination.

[0059] <Configuration example of semiconductor device_1> FIG. 1 is a diagram showing a configuration example of a semiconductor device 10 which is a semiconductor device according to an aspect of the present invention. The semiconductor device 10 includes a circuit 20, a circuit 30, a transistor 22, a transistor 23, a transistor 32, a transistor 33, a capacitor 24, and a capacitor 34. Note that the capacitor 24 and the capacitor 34 may not be provided. The circuit 20 includes transistors 21[1] to 21[n] (n is an integer of 2 or more), and the circuit 30 includes transistors 31[1] to 31[n].

[0060] One of the source or drain of the transistor 23 is electrically connected to one of the source or drain of the transistors 21[1] to 21[n]. That is, one of the source or drain of the transistors 21[1] to 21[n] is electrically connected to each other. Also, the other of the source or drain of the transistors 21[1] to 21[n] is electrically connected to one of the source or drain of the transistor 22 and one electrode of the capacitor 24. That is, the other of the source or drain of the transistors 21[1] to 21[n] is electrically connected to each other. From the above, it can be said that the transistors 21[1] to 21[n] are connected in parallel.

[0061] One of the source or drain of transistor 33 is electrically connected to one of the source or drain of transistor 31[1]. The other of the source or drain of transistor 31[1] is electrically connected to one of the source or drain of transistor 31[2]. In this way, the other of the source or drain of transistor 31[k] (k is an integer from 1 to n - 1) is electrically connected to one of the source or drain of transistor 31[k + 1]. From the above, it can be said that transistors 31[1] to 31[n] are connected in series. Here, the other of the source or drain of transistor 31[n] is electrically connected to one of the source or drain of transistor 32 and one electrode of capacitor 34.

[0062] A node to which the other of the source or drain of transistors 21[1] to 21[n], one of the source or drain of transistor 22, and one electrode of capacitor 24 are electrically connected is defined as node N1. Also, a node to which the other of the source or drain of transistor 31[n], one of the source or drain of transistor 32, and one electrode of capacitor 34 are electrically connected is defined as node N2.

[0063] The gates of transistors 21[1] to 21[n] and the gates of transistors 31[1] to 31[n] are electrically connected to transmission line 11. Signals IN[1] to IN[n] are input to transmission line 11. The signals IN[1] to IN[n] input to transmission line 11 are supplied to transistors 21[1] to 21[n] and transistors 31[1] to 31[n]. Specifically, signal IN[i] is supplied to the gate of transistor 21[i] (i is an integer from 1 to n) and the gate of transistor 31[i].

[0064] Signal OUT1 can be output from node N1. Signal OUT2 can be output from node N2.

[0065] A signal PRE can be supplied to the gates of transistor 22 and transistor 32. The signal PRE has a function of controlling the on / off states of transistor 22 and transistor 32. Transistor 22 and transistor 32 have a function as switches whose on / off states are switched by the signal PRE.

[0066] Also, a signal EVA can be supplied to the gates of transistor 23 and transistor 33. The signal EVA has a function of controlling the on / off states of transistor 23 and transistor 33. Transistor 23 and transistor 33 have a function as switches whose on / off states are switched by the signal EVA.

[0067] Capacitor 24 has a function of holding the potential of node N1. Also, capacitor 34 has a function of holding the potential of node N2.

[0068] Also, by providing capacitor 24, when transistor 22 is switched from the on state to the off state, it is possible to suppress the potential of signal OUT1 from fluctuating due to parasitic capacitance or the like between the gate of transistor 22 and one of the source or drain of transistor 22. Specifically, when transistor 22 is switched from the on state to the off state, it is possible to suppress the potential of signal OUT1 from fluctuating in conjunction with the potential fluctuation of the gate of transistor 22 caused by the parasitic capacitance or the like. Also, by providing capacitor 34, when transistor 32 is switched from the on state to the off state, it is possible to suppress the potential of signal OUT2 from fluctuating due to parasitic capacitance or the like between the gate of transistor 32 and one of the source or drain of transistor 32. Specifically, when transistor 32 is switched from the on state to the off state, it is possible to suppress the potential of signal OUT2 from fluctuating in conjunction with the potential fluctuation of the gate of transistor 32 caused by the parasitic capacitance or the like.

[0069] The other of the source or drain of transistor 22 and the other of the source or drain of transistor 32 are supplied with a potential VC. The other of the source or drain of transistor 23 and the other electrode of capacitor 24 are supplied with a potential VDET1. The other of the source or drain of transistor 33 and the other electrode of capacitor 34 are supplied with a potential VDET2.

[0070] Although details will be described later, transistors 21[1] to 21[n], transistor 22, transistor 23, transistors 31[1] to 31[n], transistor 32, and transistor 33 can all have the same polarity. For example, transistors 21[1] to 21[n], transistor 22, transistor 23, transistors 31[1] to 31[n], transistor 32, and transistor 33 can be n-channel transistors.

[0071] For transistors 21[1] to 21[n], transistor 22, transistors 31[1] to 31[n], and transistor 32, it is preferable to use transistors with an extremely low off-current. Thereby, the potential of node N1 can be held for an extremely long period. Also, the potential of node N2 can be held for an extremely long period. As a result, although details will be described later, circuit 20 can continue to output signal OUT1 with high accuracy, and circuit 30 can continue to output signal OUT2 with high accuracy.

[0072] Examples of transistors with an extremely low off-current include OS transistors. Specifically, the off-current per 1 μm of channel width is less than 1×10 -20 A, preferably less than 1×10 -22 A, more preferably less than 1×10 -24 A.

[0073] In addition, compared with a transistor having silicon in a channel formation region (hereinafter also referred to as an Si transistor), the OS transistor has excellent electrical characteristics in a high-temperature environment. By using the OS transistor for the transistors included in the semiconductor device 10, it is possible to realize a semiconductor device that operates stably and has good reliability even in a high-temperature environment. In particular, by using the OS transistor for all of the transistors 21[1] to 21[n], the transistor 22, the transistor 23, the transistors 31[1] to 31[n], the transistor 32, and the transistor 33, the semiconductor device 10 can operate stably and have high reliability even in a high-temperature environment.

[0074] Note that Si transistors may be used for the transistors 21[1] to 21[n], the transistor 22, the transistor 23, the transistors 31[1] to 31[n], the transistor 32, and the transistor 33. Examples of the Si transistor include a transistor having amorphous silicon, a transistor having crystalline silicon (typically, low-temperature polysilicon), and a transistor having single-crystalline silicon. For example, by using a transistor having single-crystalline silicon for the transistors 21[1] to 21[n], the transistor 22, the transistor 23, the transistors 31[1] to 31[n], the transistor 32, and the transistor 33, the on-current of these transistors can be increased. Therefore, the semiconductor device 10 can be driven at high speed.

[0075] Although details will be described later, the semiconductor device 10 can detect whether an event has occurred in a circuit that generates, for example, signals IN[1] to IN[n]. For example, assuming that the first reference potential is higher than the second reference potential, the semiconductor device 10 can detect that at least one of the potentials of signals IN[1] to IN[n] is higher than the first reference potential and is equal to or lower than the second reference potential. Alternatively, it can detect that all of the potentials of signals IN[1] to IN[n] are higher than the second reference potential and are equal to or lower than the first reference potential. For example, when at least one of the potentials of signals IN[1] to IN[n] is higher than the first reference potential or is equal to or lower than the second reference potential, it can be assumed that an event has occurred in the circuit that generates signals IN[1] to IN[n]. Here, the detection result by the semiconductor device 10 can be output as signals OUT1 and OUT2.

[0076] <An example of a driving method for a semiconductor device> Next, an example of a driving method for the semiconductor device 10 will be described. FIG. 2 is a timing chart showing an example of a driving method for the semiconductor device 10 having the configuration shown in FIG. 1. In FIG. 2, “H” indicates a high potential and “L” indicates a low potential. The same description will be made for other timing charts. Also, in FIG. 2, potential fluctuations due to wiring resistance and the resistance between the drain and source of a transistor are not considered. The same applies to other timing charts and the like.

[0077] In FIG. 2, an example of the driving method for the semiconductor device 10 is shown divided into periods T11[1] to T11[7] and periods T12[1] to T12[7]. An example of the driving method for the semiconductor device 10 in periods T12[1] to T12[7] is also shown in FIGS. 3 to 9.

[0078] In the following description, it is assumed that the threshold voltages of transistors 21[1] to 21[n] and transistors 31[1] to 31[n] are all equal to “Vth”.

[0079] Hereinafter, assuming that all of transistor 21[1] to transistor 21[n], transistor 22, transistor 23, transistor 31[1] to transistor 31[n], transistor 32, and transistor 33 are n-channel transistors, an example of the driving method of semiconductor device 10 will be described. Even if all or some of transistor 21[1] to transistor 21[n], transistor 22, transistor 23, transistor 31[1] to transistor 31[n], transistor 32, and transistor 33 are p-channel transistors, the following description can be referred to by appropriately changing the magnitude relationship of the potentials, etc.

[0080] The potential VC shall be higher than the potential VDET1 and the potential VDET2. Also, the potential VDET1 shall be higher than the potential VDET2. That is, the relationship of "VC > VDET1 > VDET2" shall hold.

[0081] During period T11[1], the signal PRE is set to a high potential. As a result, transistor 22 and transistor 32 are turned on. When transistor 22 is turned on, the potential of node N1 becomes the potential VC. Also, when transistor 32 is turned on, the potential of node N2 becomes the potential VC.

[0082] During period T12[1], the signal PRE is set to a low potential. As a result, transistor 22 and transistor 32 are turned off. Also, the signal EVA is set to a high potential. As a result, transistor 23 and transistor 33 are turned on.

[0083] During period T12[1], assume that the potentials of signals IN[1] to IN[n] are higher than the potential "VDET2 + Vth" and equal to or lower than the potential "VDET1 + Vth". Here, when the difference between the potential of the gate of the transistor and the potential of the source is greater than the threshold voltage of the transistor, a current flows between the drain and the source of the transistor. On the other hand, when the difference between the potential of the gate of the transistor and the potential of the source is equal to or lower than the threshold voltage of the transistor, no current flows between the drain and the source of the transistor.

[0084] When transistor 23 is turned on, the potential of one of the source or drain of transistors 21[1] to 21[n] becomes the potential VDET1. Here, the potential of the other of the source or drain of transistors 21[1] to 21[n] is the potential VC. Also, when transistor 33 is turned on, the potential of one of the source or drain of transistor 31[1] becomes the potential VDET2. Here, the potential of the other of the source or drain of transistor 31[n] is the potential VC.

[0085] As described above, transistors 21[1] to 21[n] and transistors 31[1] to 31[n] are n-channel transistors, and the potential VC is higher than the potential VDET1 and the potential VDET2. Also, transistors 31[1] to 31[n] are connected in series. Therefore, one of the source or drain of transistors 21[1] to 21[n] and transistors 31[1] to 31[n] is the source, and the other of the source or drain of transistors 21[1] to 21[n] and transistors 31[1] to 31[n] is the drain.

[0086] From the above, during period T12[1], the difference between the potential of the gates of transistors 21[1] to 21[n] and the potential of the sources becomes equal to or less than the threshold voltage Vth. Therefore, in any of transistors 21[1] to 21[n], no current flows between the drain and the source. Therefore, the potential of node N1 remains at potential VC, and the potential of signal OUT1 becomes potential VC.

[0087] On the other hand, the difference between the potential of the gates of transistors 31[1] to 31[n] and the potential of the sources becomes higher than the threshold voltage Vth. Therefore, a current flows between the drain and the source of transistor 33 from node N2 through transistors 31[1] to 31[n]. Accordingly, the potential of node N2 changes to potential VDET2, and the potential of signal OUT2 becomes potential VDET2.

[0088] Figure 3 is a circuit diagram showing the state of semiconductor device 10 at time T12[1]. In Figure 3, transistors that cannot pass a current between the drain and the source are indicated with an 'x' mark. Specifically, transistors in which the difference between the potential of the gates and the potential of the sources is equal to or less than the threshold voltage are indicated with an 'x' mark. On the other hand, transistors that can pass a current between the drain and the source are not marked with an 'x' mark. Specifically, transistors in which the difference between the potential of the gates and the potential of the sources is higher than the threshold voltage are not marked with an 'x' mark. Also, the current is indicated by an arrow. Similar descriptions may be made in other figures.

[0089] During period T11[2], signal PRE is set to a high potential. As a result, transistors 22 and 32 are turned on. When transistor 22 is turned on, the potential of node N1 becomes potential VC. Also, when transistor 32 is turned on, the potential of node N2 becomes potential VC.

[0090] During period T12[2], set signal PRE to a low potential. As a result, transistors 22 and 32 are turned off. Also, set signal EVA to a high potential. As a result, transistors 23 and 33 are turned on.

[0091] During period T12[2], assume that the potential of signal IN[n] is higher than the potential "VDET1 + Vth". Also, assume that the potentials of signals IN[1] to IN[n - 1] are higher than the potential "VDET2 + Vth" and equal to or lower than the potential "VDET1 + Vth". Since the potential of signal IN[n] is higher than the potential "VDET1 + Vth", the difference between the potential of the gate and the potential of the source of transistor 21[n] becomes higher than the threshold voltage Vth. As described above, transistors 21[1] to 21[n] are connected in parallel. From the above, a current flows between the drain and the source of transistor 23 from node N1 through transistor 21[n]. Therefore, the potential of node N1 changes to the potential VDET1, and the potential of signal OUT1 becomes the potential VDET1.

[0092] Also, similar to period T12[1], the difference between the potential of the gate and the potential of the source of transistors 31[1] to 31[n] becomes higher than the threshold voltage Vth. Therefore, a current flows between the drain and the source of transistor 33 from node N2 through transistors 31[1] to 31[n]. Therefore, similar to period T12[1], the potential of node N2 changes to the potential VDET2, and the potential of signal OUT2 becomes the potential VDET2.

[0093] Figure 4 is a circuit diagram showing the state of semiconductor device 10 during period T12[2]. In Figure 4, that the potential of signal OUT1 during period T12[2] is different from the potential of signal OUT1 during period T12[1] is shown by enclosing signal OUT1 with a dashed line.

[0094] During period T11[3], set signal PRE to a high potential. As a result, transistors 22 and 32 turn on. When transistor 22 turns on, the potential of node N1 becomes potential VC. Also, when transistor 32 turns on, the potential of node N2 becomes potential VC.

[0095] During period T12[3], set signal PRE to a low potential. As a result, transistors 22 and 32 turn off. Also, set signal EVA to a high potential. As a result, transistors 23 and 33 turn on.

[0096] During period T12[3], assume that the potential of signal IN[n] is equal to or lower than the potential "VDET2 + Vth". Also, assume that the potentials of signals IN[1] to IN[n - 1] are higher than the potential "VDET2 + Vth" and equal to or lower than the potential "VDET1 + Vth". Since the potential of signal IN[n] is equal to or lower than the potential "VDET2 + Vth", the difference between the potential of the gate and the source of transistor 31[n] becomes equal to or lower than the threshold voltage Vth. As described above, transistors 31[1] to 31[n] are connected in series. From the above, no current flows from node N2 towards transistor 33, the potential of node N2 remains at potential VC, and the potential of signal OUT2 becomes potential VC.

[0097] Also, similar to period T12[1], the difference between the potential of the gate and the source of transistors 21[1] to 21[n] becomes equal to or lower than the threshold voltage Vth. Therefore, no current flows between the drain and the source of any of transistors 21[1] to 21[n]. Thus, similar to period T12[1], the potential of node N1 remains at potential VC, and the potential of signal OUT1 becomes potential VC.

[0098] FIG. 5 is a circuit diagram showing the state of the semiconductor device 10 in the period T12[3]. In FIG. 5, the potential of the signal OUT2 in the period T12[3] is different from the potential of the signal OUT2 in the period T12[1], and this is shown by surrounding the signal OUT2 with a dashed line.

[0099] In the period T11[4], the signal PRE is set to a high potential. As a result, the transistors 22 and 32 are turned on. When the transistor 22 is turned on, the potential of the node N1 becomes the potential VC. Also, when the transistor 32 is turned on, the potential of the node N2 becomes the potential VC.

[0100] In the period T12[4], the signal PRE is set to a low potential. As a result, the transistors 22 and 32 are turned off. Also, the signal EVA is set to a high potential. As a result, the transistors 23 and 33 are turned on.

[0101] In the period T12[4], similar to the period T12[1], it is assumed that the potentials of the signals IN[1] to IN[n] are higher than the potential "VDET2 + Vth" and equal to or lower than the potential "VDET1 + Vth". In this case, similar to the period T12[1], the potential of the signal OUT1 is the potential VC and the potential of the signal OUT2 is the potential VDET2.

[0102] FIG. 6 is a circuit diagram showing the state of the semiconductor device 10 at the time T12[4]. FIG. 6 shows the same state as FIG. 3.

[0103] In the period T11[5], the signal PRE is set to a high potential. As a result, the transistors 22 and 32 are turned on. When the transistor 22 is turned on, the potential of the node N1 becomes the potential VC. Also, when the transistor 32 is turned on, the potential of the node N2 becomes the potential VC.

[0104] During period T12[5], set signal PRE to a low potential. As a result, transistors 22 and 32 are turned off. Also, set signal EVA to a high potential. As a result, transistors 23 and 33 are turned on.

[0105] During period T12[5], assume that the potential of signal IN[1] is higher than the potential "VDET1 + Vth". Also, assume that the potentials of signals IN[2] to IN[n] are higher than the potential "VDET2 + Vth" and equal to or lower than the potential "VDET1 + Vth". Since the potential of signal IN[1] is higher than the potential "VDET1 + Vth", the difference between the potential of the gate and the potential of the source of transistor 21[1] becomes higher than the threshold voltage Vth. As described above, transistors 21[1] to 21[n] are connected in parallel. From the above, a current flows between the drain and the source of transistor 23 from node N1 through transistor 21[1]. Therefore, the potential of node N1 changes to the potential VDET1, and the potential of signal OUT1 becomes the potential VDET1.

[0106] Also, similar to period T12[4], the difference between the potential of the gate and the potential of the source of transistors 31[1] to 31[n] becomes higher than the threshold voltage Vth. Therefore, a current flows between the drain and the source of transistor 33 from node N2 through transistors 31[1] to 31[n]. Therefore, similar to period T12[4], the potential of node N2 changes to the potential VDET2, and the potential of signal OUT2 becomes the potential VDET2.

[0107] FIG. 7 is a circuit diagram showing the state of the semiconductor device 10 during period T12[5]. In FIG. 7, the fact that the potential of signal OUT1 during period T12[5] is different from the potential of signal OUT1 during period T12[4] is shown by surrounding signal OUT1 with a dashed line.

[0108] During period T11[6], set signal PRE to a high potential. As a result, transistors 22 and 32 turn on. When transistor 22 turns on, the potential of node N1 becomes potential VC. Also, when transistor 32 turns on, the potential of node N2 becomes potential VC.

[0109] During period T12[6], set signal PRE to a low potential. As a result, transistors 22 and 32 turn off. Also, set signal EVA to a high potential. As a result, transistors 23 and 33 turn on.

[0110] During period T12[6], assume that the potential of signal IN[1] is equal to or lower than potential “VDET2 + Vth”. Also assume that the potentials of signals IN[2] to IN[n] are higher than potential “VDET2 + Vth” and equal to or lower than potential “VDET1 + Vth”. Since the potential of signal IN[1] is equal to or lower than potential “VDET2 + Vth”, the difference between the potential of the gate and the source of transistor 31[1] becomes equal to or lower than the threshold voltage Vth. As described above, transistors 31[1] to 31[n] are connected in series. From the above, no current flows from node N2 towards transistor 33, the potential of node N2 remains at potential VC, and the potential of signal OUT2 becomes potential VC.

[0111] Also, similar to period T12[4], the difference between the potential of the gate and the source of transistors 21[1] to 21[n] becomes equal to or lower than the threshold voltage Vth. Therefore, no current flows between the drain and the source in any of transistors 21[1] to 21[n]. Thus, similar to period T12[4], the potential of node N1 remains at potential VC, and the potential of signal OUT1 becomes potential VC.

[0112] FIG. 8 is a circuit diagram showing the state of the semiconductor device 10 in period T12[6]. In FIG. 8, the potential of signal OUT2 in period T12[6] is different from the potential of signal OUT2 in period T12[4], which is indicated by enclosing signal OUT2 with a dashed line.

[0113] In period T11[7], signal PRE is set to a high potential. As a result, transistors 22 and 32 are turned on. When transistor 22 is turned on, the potential of node N1 becomes potential VC. Also, when transistor 32 is turned on, the potential of node N2 becomes potential VC.

[0114] In period T12[7], signal PRE is set to a low potential. As a result, transistors 22 and 32 are turned off. Also, signal EVA is set to a high potential. As a result, transistors 23 and 33 are turned on.

[0115] In period T12[7], assume that the potential of signal IN[n] is higher than potential “VDET1 + Vth” and the potential of signal IN[1] is equal to or lower than potential “VDET2 + Vth”. Also, assume that the potentials of signals IN[2] to IN[n - 1] are higher than potential “VDET2 + Vth” and equal to or lower than potential “VDET1 + Vth”. Since the potential of signal IN[n] is higher than potential “VDET1 + Vth”, the difference between the potential of the gate and the source of transistor 21[n] becomes higher than the threshold voltage Vth. As described above, transistors 21[1] to 21[n] are connected in parallel. From the above, a current flows from node N1, through transistor 21[n], between the drain and source of transistor 23. Therefore, the potential of node N1 changes to potential VDET1, and the potential of signal OUT1 becomes potential VDET1.

[0116] Also, when the potential of signal IN[1] is equal to or lower than the potential "VDET2 + Vth", the difference between the potential of the gate and the potential of the source of transistor 31[1] becomes equal to or lower than the threshold voltage Vth. As described above, transistors 31[1] to 31[n] are connected in series. From the above, no current flows from node N2 toward transistor 33, the potential of node N2 remains at potential VC, and the potential of signal OUT2 becomes potential VC.

[0117] FIG. 9 is a circuit diagram showing the state of semiconductor device 10 during period T12[7]. In FIG. 9, that the potential of signal OUT1 during period T12[7] is different from the potentials of signal OUT1 during periods T12[1] and T12[4] is indicated by enclosing signal OUT1 with a dashed line. Also, that the potential of signal OUT2 during period T12[7] is different from the potentials of signal OUT2 during periods T12[1] and T12[4] is indicated by enclosing signal OUT2 with a dashed line.

[0118] From the above, it can be said that circuit 20 has a function of detecting whether at least one of the potentials of signals IN[1] to IN[n] is higher than the potential "VDEF1 + Vth" or whether all of signals IN[1] to IN[n] are equal to or lower than the potential "VDEF1 + Vth", and outputting the detection result as signal OUT1. Therefore, when the potential "VDEF1 + Vth" is used as reference potential VREF1, it can be said that circuit 20 has a function of detecting whether at least one of the potentials of signals IN[1] to IN[n] is higher than reference potential VREF1 or whether all of signals IN[1] to IN[n] are equal to or lower than reference potential VREF1. Here, since the potential VDET1 can be expressed as the potential "VREF1 - Vth", it can be said that the potential VDET1 is a potential corresponding to reference potential VREF1.

[0119] Further, circuit 30 can be said to have a function of detecting whether at least one of the potentials of signals IN[1] to IN[n] is equal to or lower than the potential “VDEF2 + Vth”, or whether all of signals IN[1] to IN[n] are higher than the potential “VDEF2 + Vth”, and outputting the detection result as signal OUT2. Therefore, when the potential “VDEF2 + Vth” is used as the reference potential VREF2, circuit 30 can be said to have a function of detecting whether at least one of the potentials of signals IN[1] to IN[n] is equal to or lower than the reference potential VREF2, or whether all of signals IN[1] to IN[n] are higher than the reference potential VREF2. Here, since the potential VDET2 can be expressed as the potential “VREF2 - Vth”, it can be said that the potential VDET2 is a potential corresponding to the reference potential VREF2.

[0120] As described above, the potential VDET1 is higher than the potential VDET2. Also, it is assumed that the threshold voltages of transistors 21[1] to 21[n] and transistors 31[1] to 31[n] are all equal to “Vth”. Therefore, the reference potential VREF1 becomes higher than the reference potential VREF2.

[0121] From the above, semiconductor device 10 can detect that at least one of the potentials of signals IN[1] to IN[n] is higher than the reference potential VREF1 and equal to or lower than the reference potential VREF2. Alternatively, it can detect that all of the potentials of signals IN[1] to IN[n] are higher than the reference potential VREF2 and equal to or lower than the reference potential VREF1. Thereby, for example, it can be detected whether an event has occurred in a circuit that generates signals IN[1] to IN[n]. For example, when at least one of the potentials of signals IN[1] to IN[n] is higher than the reference potential VREF1 or equal to or lower than the reference potential VREF2, it can be assumed that an event has occurred in the circuit that generates signals IN[1] to IN[n].

[0122] The above detection result can be output as signal OUT1 and signal OUT2. Specifically, in period T11, transistors 22 and 32 are turned on, transistors 23 and 33 are turned off, and the potentials of node N1 and node N2 are set to potential VC. Next, in period T12, by turning off transistors 22 and 32 and turning on transistors 23 and 33, semiconductor device 10 can output signals of potentials corresponding to the potentials of signals IN[1] to IN[n] as signal OUT1 and signal OUT2. For example, when the potential of signal OUT1 is potential VC and the potential of signal OUT2 is potential VDET2, it can be assumed that no event has occurred in the circuit that generates signals IN[1] to IN[n], and that an event has occurred for other potentials. Note that after setting the potentials of node N1 and node N2 to potential VC in period T11, signal OUT1 and signal OUT2 are output in period T12. Therefore, in period T11, it can be said that precharge is performed. Also, potential VC can be said to be a precharge potential.

[0123] From the above, it can be said that semiconductor device 10 has a function of detecting the potential levels of signals IN[1] to IN[n]. Here, as shown in FIG. 1, no comparator is provided in semiconductor device 10. As described above, if the function of detecting the potential levels of signals IN[1] to IN[n] is to be provided by a comparator, particularly when n is large, many comparators are required. On the other hand, in semiconductor device 10, by simply increasing the number of transistors 21 and the number of transistors 31, it is possible to cope with an increase in n. For example, by simply increasing the number of transistors 21 and transistors 31 by one each, n can be increased by 1. As a result, even if n increases, a significant increase in the circuit scale of the semiconductor device can be suppressed. Therefore, according to one aspect of the present invention, the circuit scale of the semiconductor device can be reduced. Thereby, the semiconductor device can be miniaturized and the power consumption of the semiconductor device can be reduced.

[0124] Further, as described above, when the comparator is configured by transistors of the same polarity, the characteristics of the comparator are significantly degraded. On the other hand, even if all the transistors included in the semiconductor device 10 are transistors of the same polarity, the characteristics of the semiconductor device 10 do not vary significantly compared to the case where the semiconductor device 10 is configured by CMOS. Therefore, all the transistors included in the semiconductor device 10 can be transistors of the same polarity. For example, all of the transistors 21[1] to 21[n], the transistor 22, the transistor 23, the transistors 31[1] to 31[n], the transistor 32, and the transistor 33 can be n-channel transistors. By making all the transistors included in the semiconductor device 10 transistors of the same polarity, it is no longer necessary to separately fabricate n-channel transistors and p-channel transistors. As a result, the semiconductor device 10 can be fabricated by a simple method. Therefore, the manufacturing cost of the semiconductor device 10 can be reduced, and the semiconductor device 10 can be made inexpensive.

[0125] In addition, since all the transistors included in the semiconductor device 10 can be n-channel transistors, all the transistors included in the semiconductor device 10 can be OS transistors. As described above, the OS transistor has the characteristic that the off-current is extremely low. Therefore, for example, by making all the transistors included in the semiconductor device 10 OS transistors, when the potential of the node N1 does not become the potential VDET1 during the period T12, the potential of the node N1 can be held at the potential VC for a long time. Also, when the potential of the node N2 does not become the potential VDET2 during the period T12, the potential of the node N2 can be held at the potential VC for a long time. From the above, even if the period T12 is lengthened, the circuit 20 can continue to output the signal OUT1 with high accuracy, and the circuit 30 can continue to output the signal OUT2 with high accuracy.

[0126] <Configuration Example of Semiconductor Device_2> FIG. 10 is a diagram showing a configuration example of the semiconductor device 10, which is a modified example of the configuration shown in FIG. 1. The semiconductor device 10 shown in FIG. 10 is different from the semiconductor device 10 shown in FIG. 1 in that the transistors 21[1] to 21[n], the transistor 22, the transistor 23, the transistors 31[1] to 31[n], the transistor 32, and the transistor 33 have back gates in addition to gates.

[0127] In this specification and the like, the term "gate" may indicate a front gate. Note that the terms "gate" and "back gate" may be used interchangeably. Further, when a transistor has a gate and a back gate, one of the gate or the back gate may be referred to as a first gate, and the other of the gate or the back gate may be referred to as a second gate.

[0128] A potential VBG1 can be supplied to the back gates of the transistors 21[1] to 21[n]. A potential VBG2 can be supplied to the back gates of the transistors 31[1] to 31[n].

[0129] By controlling the potential of the back gate of a transistor, the threshold voltage of the transistor can be controlled. Specifically, in an n-channel type transistor, the higher the potential of the back gate, the smaller the threshold voltage can be. Therefore, even if the potential of the other of the source or drain of the transistor 23 and the potential of the other of the source or drain of the transistor 33 are the same potential, the reference potential VREF1 and the reference potential VREF2 can be made different. Specifically, by making the potential VBG1 lower than the potential VBG2, the reference potential VREF1 can be made higher than the reference potential VREF2.

[0130] In FIG. 10, the potential of the other of the source or drain of transistor 23 and the other of the source or drain of transistor 33 is defined as potential VDET. Here, when potential VBG1 is supplied to the back gates of transistors 21[1] to 21[n], the threshold voltage of transistors 21[1] to 21[n] is defined as Vth1. Also, when potential VBG2 is supplied to the back gates of transistors 31[1] to 31[n], the threshold voltage of transistors 31[1] to 31[n] is defined as Vth2. In this case, reference potential VREF1 becomes the potential "VDET + Vth1", and reference potential VREF2 becomes the potential "VDET + Vth2". By making threshold voltage Vth1 higher than threshold voltage Vth2, reference potential VREF1 can be made higher than reference potential VREF2.

[0131] The back gate of transistor 22 is electrically connected to the gate of transistor 22. The back gate of transistor 23 is electrically connected to the gate of transistor 23. The back gate of transistor 32 is electrically connected to the gate of transistor 32. The back gate of transistor 33 is electrically connected to the gate of transistor 33. Thus, by electrically connecting the gate and the back gate of the transistor functioning as a switch, the on-current of the transistor can be increased. Thereby, semiconductor device 10 can be driven at high speed. Note that even when transistors 21[1] to 21[n] and transistors 31[1] to 31[n] do not have back gates, back gates may be provided for transistors 22, 23, 32, and 33. Also, instead of electrically connecting the back gate and the gate, the potential of the back gate and the potential of the gate may be controlled separately.

[0132] An example of the driving method of the semiconductor device 10 shown in FIG. 10 is to replace the potential VDET1 and the potential VDET2 with the potential VDET, assume that the reference potential VREF1 is the potential "VDET + Vth1", and the reference potential VREF2 is the potential "VDET + Vth2", and reference the description according to FIGS. 2 to 9.

[0133] FIG. 11 is a diagram showing a configuration example of the semiconductor device 10 and is a modified example of the configuration shown in FIG. 10. The semiconductor device 10 shown in FIG. 11 is different from the semiconductor device 10 shown in FIG. 10 in that the potential supplied to the back gate of the transistors 21[1] to 21[n] is individually controlled, and the potential supplied to the back gate of the transistors 31[1] to 31[n] is individually controlled.

[0134] In the semiconductor device 10 shown in FIG. 11, not only the other potential of the source or drain of the transistor 23 and the other potential of the source or drain of the transistor 33 are set to the same potential (for example, the potential VDET), but also the variation in the threshold voltage between the transistors 21[1] to 21[n] and between the transistors 31[1] to 31[n] can be corrected. Therefore, in the semiconductor device 10 shown in FIG. 11, the potential levels of the signals IN[1] to IN[n] can be detected with high accuracy.

[0135] <Configuration Example of Signal IN Generation Circuit> Next, the generation of the signals IN[1] to IN[n] will be described. The signals IN[1] to IN[n] can be signals corresponding to the signals output by the pixels of the imaging device, for example. FIG. 12A is a diagram showing a configuration example of a circuit having a function of generating the signal IN[i]. In FIG. 12A, a pixel circuit 50 and a circuit 40 are shown. Also, a specific configuration example of the circuit 40 is shown. The circuit 40 includes a capacitor 41 and a transistor 42.

[0136] The pixel circuit 50 has a function of outputting a signal OUTPX. The signal OUTPX can be a signal representing imaging data acquired by the pixel circuit 50. The signal OUTPX is supplied to one electrode of the capacitor 41. Also, the other electrode of the capacitor 41 and one of the source or drain of the transistor 42 are electrically connected at a node N3. A signal IN[i] is output from the node N3. A potential VR is supplied to the other of the source or drain of the transistor 42. A signal RES is supplied to the gate of the transistor 42. The signal RES has a function of controlling the on / off of the transistor 42. The transistor 42 has a function as a switch whose on / off is switched by the signal RES.

[0137] Hereinafter, an example of the driving method of the circuit 40 will be described with reference to FIGS. 12B1 and 12B2. FIG. 12B1 shows the state of the circuit 40 in the period T01, and FIG. 12B2 shows the state of the circuit 40 in the period T02. In FIGS. 12B1 and 12B2, the off-state transistors are indicated with an × mark. On the other hand, the on-state transistors are not marked with an × mark.

[0138] First, in the period T01, as shown in FIG. 12B1, the transistor 42 is turned on. As a result, regardless of the potential of the signal OUTPX, the potential of the signal IN[i] becomes the potential VR. That is, it can be said that the potential of the signal IN[i] is reset to the potential VR. Therefore, the transistor 42 can be said to be a reset transistor, and the signal RES can be said to be a reset signal. Note that the potential of the signal OUTPX in the period T01 is set to the potential VD1.

[0139] Next, in period T02, as shown in FIG. 12B2, transistor 42 is turned off. As a result, node N3 becomes a floating state, and the potential of node N3 electrically connected to the other electrode of capacitor 41 varies according to the variation in the potential of signal OUTPX supplied to one electrode of capacitor 41. Therefore, the potential of signal IN[i] varies according to the variation in the potential of signal OUTPX. In FIG. 12B2, it is assumed that the potential of signal OUTPX varies from potential VD1 to potential VD2 in period T02. In FIG. 12B2, the fact that the potential of signal OUTPX in period T02 is different from the potential of signal OUTPX in period T01 is indicated by enclosing signal OUTPX with a dashed line. Also, the fact that the potential of signal IN[i] in period T02 is different from the potential of signal IN[i] in period T01 is indicated by enclosing signal IN[i] with a dashed line.

[0140] Here, when the capacitance of capacitor 41 is sufficiently larger than the parasitic capacitance of node N3, such as the gate capacitance of transistor 42, the capacitive coupling coefficient of node N3 can be regarded as 1. Assuming that the capacitive coupling coefficient of node N3 is 1, when transistor 42 is turned off, the variation range of the potential of signal IN[i] is equal to the variation range of the potential of signal OUTPX. From the above, in period T02, if the potential of signal OUTPX varies from potential VD1 to potential VD2 and the capacitive coupling coefficient of node N3 is 1, the potential of signal IN[i] becomes the potential “VR + VD2 - VD1”.

[0141] The potential VR shall be equal to or higher than the reference potential VREF2 and equal to or lower than the reference potential VREF1. For example, the potential VR shall be the potential “(VREF1 + VREF2) / 2”. Then, after the period T02, the operations in the period T11 and the operation in the period T12 shown in FIG. 2 and the like are performed. Thereby, the semiconductor device 10 can detect that at least one of the potentials of the signals IN[1] to IN[n] is higher than the reference potential VREF1 and equal to or lower than the reference potential VREF2. Alternatively, it can be detected that all of the potentials of the signals IN[1] to IN[n] are higher than the reference potential VREF2 and equal to or lower than the reference potential VREF1. Therefore, it is possible to detect in the period T12 whether or not there is a signal among the signals IN[1] to IN[n] whose potential has changed by a specified value or more in the period T02.

[0142] <Configuration example of pixel circuit> FIG. 13A is a diagram showing a configuration example of the pixel circuit 50. In FIG. 13A, for convenience of explanation, the circuit 40 having the configuration shown in FIG. 12A is also shown.

[0143] The pixel circuit 50 includes a photoelectric conversion device 60, a transistor 61, a transistor 62, a transistor 63, a transistor 64, and a capacitor 66.

[0144] Hereinafter, description will be made on the assumption that the transistor 42 and the transistors 61 to 64 are all n-channel transistors. Even if all or some of the transistor 42 and the transistors 61 to 64 are p-channel transistors, the following description can be referred to by appropriately changing the magnitude relationship of the potentials.

[0145] One electrode of the photoelectric conversion device 60 is electrically connected to one of the source or drain of the transistor 61. In FIG. 13A, one electrode of the photoelectric conversion device 60 is an anode, and the other electrode of the photoelectric conversion device 60 is a cathode.

[0146] The other of the source or drain of transistor 61 is electrically connected to the gate of transistor 62. The gate of transistor 62 is electrically connected to one of the source or drain of transistor 64. One of the source or drain of transistor 64 is electrically connected to one electrode of capacitor 66. One of the source or drain of transistor 62 is electrically connected to one of the source or drain of transistor 63.

[0147] Let the node where one electrode of the photoelectric conversion device 60 and one of the source or drain of transistor 61 are electrically connected be node NA. Also, let the node where the other of the source or drain of transistor 61, the gate of transistor 62, one of the source or drain of transistor 64, and one electrode of capacitor 66 are electrically connected be node FD. Note that if the gate capacitance of transistor 62 or the like is large enough and the capacitance of node FD can be sufficiently ensured even without capacitor 66, then capacitor 66 may not be provided.

[0148] Signal TX is supplied to the gate of transistor 61. Signal SEL is supplied to the gate of transistor 63. Signal RESPX is supplied to the gate of transistor 64. Signal OUTPX is output from the other of the source or drain of transistor 63.

[0149] As shown in FIG. 13A, when one electrode of the photoelectric conversion device 60 is an anode and the other electrode of the photoelectric conversion device 60 is a cathode, a potential VDD can be supplied to the other electrode of the photoelectric conversion device 60 and the other of the source or drain of the transistor 62. On the other hand, a potential VSS can be supplied to the other of the source or drain of the transistor 64 and the other electrode of the capacitor 66. Here, the potential VDD can be a high potential, and the potential VSS can be a low potential. Note that when one electrode of the photoelectric conversion device 60 is a cathode and the other electrode of the photoelectric conversion device 60 is an anode, a potential VDD can be supplied to the other of the source or drain of the transistor 62 and the other of the source or drain of the transistor 64. Also, a potential VSS can be supplied to the other electrode of the photoelectric conversion device 60 and the other electrode of the capacitor 66.

[0150] The other of the source or drain of the transistor 63 is electrically connected to one of the source or drain of the transistor 69. A potential VSS can be supplied to the other of the source or drain of the transistor 69. A potential Vbias can be supplied to the gate of the transistor 69. The potential Vbias is a potential that causes the transistor 69 to function as a current source. For example, the potential Vbias is a potential such that the transistor 69 operates in the saturation region. The potential Vbias can be referred to as a bias potential, and the transistor 69 can be referred to as a bias transistor.

[0151] FIG. 13B is a timing chart for explaining an example of a driving method of the pixel circuit 50 and the circuit 40 having the configuration shown in FIG. 13A. FIG. 13B shows the operation in the period T01 shown in FIG. 12B1 and the operation in the period T02 shown in FIG. 12B2. Here, in FIG. 13B, the period T01 is divided into periods 71_1 to 75_1, and the period T02 is divided into periods 71_2 to 75_2.

[0152] First, an example of the operation in period T01 will be described. In period 71_1, set the potentials of signal TX, signal RESPX, and signal RES to high potential, and set the potential of signal SEL to low potential. As a result, transistors 61, 64, and 42 turn on, and transistor 63 turns off. When transistor 64 turns on, the potential of node FD becomes the potential VSS. Also, in addition to transistor 64, when transistor 61 turns on, the potential of node NA also becomes the potential VSS. Furthermore, by turning on transistor 42, the potential of signal IN[i] becomes the potential VR. Here, the potential VR is set to be equal to or higher than the reference potential VREF2 and equal to or lower than the reference potential VREF1.

[0153] In period 72_1, set the potentials of signal TX and signal RESPX to low potential. As a result, transistors 61 and 64 turn off. When the photoelectric conversion device 60 is irradiated with light in this state, charges corresponding to the illuminance of the light are accumulated in node NA.

[0154] In period 73_1, set the potential of signal TX to high potential. As a result, transistor 61 turns on, and the charges accumulated in node NA are transferred to node FD. Thereby, the potential of node FD rises.

[0155] In period 74_1, set the potential of signal TX to low potential. As a result, transistor 61 turns off, and the transfer of charges from node NA to node FD ends. Thus, the pixel circuit 50 can acquire imaging data.

[0156] During period 75_1, set the potential of signal SEL to a high potential. As a result, transistor 63 turns on, and the imaging data acquired by pixel circuit 50 is read out as signal OUTPX. Specifically, the potential of signal OUTPX becomes a potential corresponding to the potential of node FD. In FIG. 13B, it is assumed that the potential of signal OUTPX becomes potential VD1. Since transistor 42 is on, the potential of signal IN[i] becomes potential VR regardless of the height of potential VD1. The above is an example of the operations of pixel circuit 50 and circuit 40 configured as shown in FIG. 13A during period T01.

[0157] In FIG. 13B, signal RES is set to a high potential during period 71_1, but signal RES may be set to a high potential at any time as long as it is until the start point of period 75_1. That is, during periods 71_1 to 74_1, signal RES may be switched from a low potential to a high potential at any time.

[0158] Next, an example of the operation during period T02 will be described. The potentials of signal TX, signal SEL, and signal RESPX during periods 71_2 to 75_2 are the same as those during periods 71_1 to 75_1. Also, during periods 71_2 to 74_2, switch the potential of signal RES from a high potential to a low potential. As a result, during period 75_2, signal OUTPX with potential VD2 is output from pixel circuit 50. Thereby, the imaging data acquired by pixel circuit 50 during periods 71_2 to 74_2 is read out from pixel circuit 50 during period 75_2.

[0159] Here, during period 75_2, since signal RES is at a low potential, transistor 42 is off. Therefore, assuming that the capacitive coupling coefficient of node N3 is 1, the potential of signal IN[i] becomes potential “VR + VD2 - VD1”. The above is an example of the operations of pixel circuit 50 and circuit 40 configured as shown in FIG. 13A during period T02.

[0160] As described above, after the period T02, the operations in the period T11 shown in FIG. 2 and the like and the operation in the period T12 are performed. In the case shown in FIG. 13B, the potential of the signal IN[i] at the end of the period T02 is assumed to be higher than the reference potential VREF1. Therefore, in the period T12, the semiconductor device 10 outputs the potential VDET1 as the signal OUT1.

[0161] Here, the pixel circuit 50 acquires and reads out imaging data in the period T01 and acquires and reads out imaging data again in the period T02. Therefore, it can be said that the periods T01 and T02 are each one frame period. And when the period T01 is the first frame period and the period T02 is the second frame period, the semiconductor device 10 can detect whether the difference between the imaging data acquired by the imaging device having the pixel circuit 50 in the first frame period and the imaging data acquired in the second frame period is equal to or greater than a specified value.

[0162] <Configuration example of imaging device> FIG. 14 is a block diagram showing a configuration example of an imaging device 80 which is an imaging device having a semiconductor device 10, a circuit 40, and a pixel circuit 50. The imaging device 80 includes a pixel unit 81, a gate driver circuit 82, a data driver circuit 83, and a transistor 69 in addition to the semiconductor device 10 and the circuit 40. In the pixel unit 81, pixel circuits 50 of m rows and n columns (m and n are integers of 1 or more) are arranged in a matrix. In this specification and the like, for example, the pixel circuit 50 at the h-th row and i-th column (h is an integer of 1 or more and m or less, and i is an integer of 1 or more and n or less) is described as the pixel circuit 50[h,i].

[0163] In this specification and the like, an imaging device having a semiconductor device according to an aspect of the present invention may be referred to as an imaging device according to an aspect of the present invention. For example, since the imaging device 80 includes the semiconductor device 10 which is a semiconductor device according to an aspect of the present invention, it can be referred to as an imaging device according to an aspect of the present invention.

[0164] The gate driver circuit 82 has a function of generating a signal SEL. Here, the same signal SEL can be supplied to the pixel circuits 50 in the same row. In this specification and the like, for example, the signal SEL supplied to the pixel circuit 50 in the h-th row is described as signal SEL[h]. Note that the gate driver circuit 82 may have a function of generating a signal RESPX. Also, the gate driver circuit 82 may have a function of generating a signal TX.

[0165] The data driver circuit 83 has a function of outputting the imaging data read from the pixel circuit 50 to the outside of the imaging device 80. Specifically, it has a function of outputting the imaging data to the outside of the imaging device 80 based on the signal OUTPX output from the pixel circuit 50. Here, the data driver circuit 83 can read the imaging data for each column of the pixel circuit 50. In this specification and the like, for example, the signal OUTPX output from the pixel circuit 50 in the i-th column is described as signal OUTPX[i].

[0166] The transistor 69 and the circuit 40 can be provided for each column of the pixel circuit 50. Therefore, in the imaging device 80, for example, the same number of transistors 69 and circuits 40 as the number of columns of the pixel circuit 50 can be provided. Thus, in the imaging device 80, the transistors 69 and the circuits 40 can be provided, for example, n pieces each. In this specification and the like, for example, the transistor 69 electrically connected to the pixel circuit 50 in the i-th column is described as transistor 69[i]. Also, for example, the circuit 40 to which the signal OUTPX[i] is supplied is described as circuit 40[i]. Here, it is assumed that, for example, a signal IN[i] is output from the circuit 40[i]. Then, the signals IN[1] to IN[n] can be supplied to the semiconductor device 10.

[0167] By configuring the imaging device 80 as shown in FIG. 14, the semiconductor device 10 can detect whether there is a signal OUTPX having a potential higher than the reference potential VREF1 or a signal OUTPX having a potential equal to or lower than the reference potential VREF2 among the signals OUTPX[1] to OUTPX[n] output from the pixel circuits 50[h,1] to 50[h,n]. Therefore, by driving the pixel circuit 50 and the circuit 40 in the manner shown in FIG. 13B and the like, the semiconductor device 10 can detect whether there is a pixel circuit 50 in which the difference between the imaging data acquired in the first frame period and the imaging data acquired in the second frame period is equal to or greater than a specified value, for each row of the pixel circuits 50. For example, it is possible to detect whether there is a pixel circuit 50 in which the difference between the imaging data acquired in the first frame period and the imaging data acquired in the second frame period is equal to or greater than a specified value, among the pixel circuits 50[h,1] to 50[h,n]. Note that, for example, it can be said that an event has occurred in the second frame period when there is a pixel circuit 50 in which the difference between the imaging data acquired in the first frame period and the imaging data acquired in the second frame period is equal to or greater than a specified value.

[0168] The configurations, structures, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.

[0169] (Embodiment 2) In the present embodiment, a configuration example of a transistor applicable to the semiconductor device described in the above embodiment will be described with reference to the drawings.

[0170] <Configuration Example of Transistor_1> FIGS. 15A, 15B, and 15C are diagrams showing a configuration example of a transistor 500, which is a transistor applicable to the semiconductor device described in the above embodiment. FIG. 15A is a top view of the transistor 500. Further, FIG. 15B is a cross-sectional view of a portion indicated by a one-dot chain line L1-L2 in FIG. 15A, and is also a cross-sectional view in the channel length direction of the transistor 500. Further, FIG. 15C is a cross-sectional view of a portion indicated by a one-dot chain line W1-W2 in FIG. 15A, and is also a cross-sectional view in the channel width direction of the transistor 500. Note that, in the top view of FIG. 15A, some elements are omitted for clarity of the drawing.

[0171] As shown in FIGS. 15A to 15C, the transistor 500 includes an insulating layer 524 disposed on a substrate (not shown), an oxide 530a disposed on the insulating layer 524, an oxide 530b disposed on the oxide 530a, conductive layers 542a and 542b disposed apart from each other on the oxide 530b, an insulating layer 580 disposed on the conductive layer 542a and on the conductive layer 542b and having an opening formed by overlapping between the conductive layer 542a and the conductive layer 542b, an insulating layer 545 disposed on the bottom surface and the side surface of the opening, and a conductive layer 560 disposed on the formation surface of the insulating layer 545.

[0172] Further, as shown in FIGS. 15B and 15C, it is preferable that an insulating layer 544 is disposed between the oxide 530a, the oxide 530b, the conductive layer 542a, and the conductive layer 542b and the insulating layer 580. Further, as shown in FIGS. 15B and 15C, the conductive layer 560 preferably includes a conductive layer 560a provided inside the insulating layer 545 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a. Further, as shown in FIGS. 15B and 15C, it is preferable that an insulating layer 574 is disposed on the insulating layer 580, the conductive layer 560, and the insulating layer 545.

[0173] Note that, in this specification and the like, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0174] Note that in the transistor 500, a configuration is shown in which two layers of the oxide 530a and the oxide 530b are laminated in the region where the channel is formed and in its vicinity, but the present invention is not limited to this. For example, a single layer of the oxide 530b or a laminated configuration of three or more layers may be provided.

[0175] Also, in the transistor 500, the conductive layer 560 is shown as a two-layer laminated configuration, but the present invention is not limited to this. For example, the conductive layer 560 may have a single-layer configuration or a laminated configuration of three or more layers.

[0176] Here, the conductive layer 560 functions as the gate electrode of the transistor 500. Also, the conductive layer 542a functions as one of the source electrode or the drain electrode of the transistor 500, and the conductive layer 542b functions as the other of the source electrode or the drain electrode of the transistor 500. As described above, the conductive layer 560 is formed so as to be embedded in the opening of the insulating layer 580 formed in the region sandwiched between the conductive layer 542a and the conductive layer 542b. The arrangement of the conductive layer 560, the conductive layer 542a, and the conductive layer 542b is self-aligned with respect to the opening of the insulating layer 580. That is, in the transistor 500, the gate electrode can be self-aligned and arranged between the source electrode and the drain electrode. Therefore, since the conductive layer 560 can be formed without providing an alignment margin, the occupied area of the transistor 500 can be reduced. As a result, miniaturization and high integration of the semiconductor device can be achieved.

[0177] Here, when miniaturizing a semiconductor device, it is required to shorten the gate length. On the other hand, it is necessary to prevent the conductivity of the conductive layer 560 from decreasing. If the film thickness of the conductive layer 560 is increased to prevent the conductivity of the conductive layer 560 from decreasing, the conductive layer 560 may have a shape with a high aspect ratio. As described above, in the transistor 500, the conductive layer 560 is provided so as to be embedded in the opening of the insulating layer 580. Thereby, even if the conductive layer 560 has a shape with a high aspect ratio, the transistor 500 can be formed without collapsing the conductive layer 560 during the process.

[0178] In addition, since the conductive layer 560 is self-alignedly formed in the region between the conductive layer 542a and the conductive layer 542b, the conductive layer 560 does not have a region overlapping with the conductive layer 542a or the conductive layer 542b. Thereby, the parasitic capacitance formed between the conductive layer 560 and the conductive layer 542a and the conductive layer 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved and the frequency characteristics can be enhanced.

[0179] The transistor 500 uses a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. Note that the oxide semiconductor preferably contains at least one of In or Zn. For example, as the oxide 530, a metal oxide such as an In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used.

[0180] The formation of the metal oxide that functions as an oxide semiconductor may be performed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.

[0181] In addition, as the metal oxide that functions as the channel formation region in the oxide 530, it is preferable to use a metal oxide having a band gap of 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0182] By having the oxide 530a under the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the constituent formed below the oxide 530a to the oxide 530b.

[0183] Note that the oxide 530 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0184] In addition, it is preferable that the energy of the lower end of the conduction band of the oxide 530a is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.

[0185] Here, at the junction of the oxide 530a and the oxide 530b, the energy level of the lower end of the conduction band changes smoothly. In other words, it can also be said that the energy level of the lower end of the conduction band at the junction of the oxide 530a and the oxide 530b changes continuously or forms a continuous junction. To achieve this, it is advisable to lower the density of defect energy levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0186] Specifically, by having the oxide 530a and the oxide 530b have a common element (as the main component) other than oxygen, a mixed layer with a low density of defect levels can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. may be used as the oxide 530a.

[0187] At this time, the main path of carriers becomes the oxide 530b. By configuring the oxide 530a as described above, the density of defect levels at the interface between the oxide 530a and the oxide 530b can be lowered. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

[0188] As shown in FIGS. 15B and 15C, the insulating layer 524 can be provided so as to have a region in contact with the oxide 530. When the insulating layer 524 has a region in contact with the oxide 530, it is preferable to use an insulator containing more oxygen than oxygen that satisfies the stoichiometric composition as the insulating layer 524. The oxygen is likely to be released from the film by heating. In this specification and the like, the oxygen released by heating may be referred to as "excess oxygen". That is, it is preferable that a region containing excess oxygen (also referred to as an "excess oxygen region") is formed in the insulating layer 524. By providing such an insulating layer containing excess oxygen in contact with the oxide 530, the oxygen vacancies (V O : also referred to as oxygen vacancy) in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved. When hydrogen enters the oxygen vacancies in the oxide 530, the defect (hereinafter, V OIn some cases, it may be H. ) functions as a donor, and electrons that are carriers may be generated. Also, a part of hydrogen may combine with oxygen that binds to metal atoms to generate electrons that are carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Also, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate. In one aspect of the present invention, V in the oxide 530 O H is preferably reduced as much as possible to be highly pure intrinsic or substantially highly pure intrinsic. Thus, to obtain an oxide semiconductor in which V O H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen in the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment"), and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as "oxygen addition treatment"). By using an oxide semiconductor in which impurities such as V O H are sufficiently reduced in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0189] In this specification and the like, a low impurity concentration and a low defect level density are referred to as highly pure intrinsic or substantially highly pure intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0190] As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which some oxygen is desorbed by heating. An oxide that desorbs oxygen by heating means that in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3The above is the oxide film. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0191] Further, the insulator having the above excess oxygen region and the oxide 530 may be brought into contact with each other and subjected to one or more of heat treatment, microwave treatment, or RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction occurs in which the bond of VoH is broken. In other words, dehydrogenation can be achieved by the reaction of "V O H → Vo + H". A part of the hydrogen generated at this time may combine with oxygen and be removed as H2O from the oxide 530 or the insulating layer in the vicinity of the oxide 530. Also, a part of the hydrogen may be gettered by the conductive layer 542a or the conductive layer 542b.

[0192] Further, the above microwave treatment is preferably performed using, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated. Then, by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulating layer in the vicinity of the oxide 530. Also, the above microwave treatment may be performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, more preferably 400 Pa or higher. As the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow rate ratio (O2 / (O2 + Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0193] Also, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment in a state where the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 530 to reduce oxygen vacancies (V O O

[0194] ). Also, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an atmosphere of nitrogen gas or an inert gas. Alternatively, after heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas. O O

[0195] Note that by performing an oxygen addition treatment on the oxide 530, the oxygen vacancies in the oxide 530 can be repaired with the supplied oxygen. In other words, the reaction of "Vo + O → null" can be promoted. Furthermore, by reacting the hydrogen remaining in the oxide 530 with the supplied oxygen, the hydrogen can be removed (dehydrated) as H2O. Thereby, it is possible to suppress the recombination of the hydrogen remaining in the oxide 530 with oxygen vacancies to form VH O O

[0195] On the oxide 530b, a conductive layer 542a and a conductive layer 542b that function as a source electrode and a drain electrode are provided. As the conductive layer 542a and the conductive layer 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Furthermore, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.

[0196] Also, in FIG. 15, the conductive layer 542a and the conductive layer 542b are shown as a single-layer structure, but a laminated structure of two or more layers may also be used. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Also, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0197] In addition, there are three-layer structures such as a titanium film or a titanium nitride film, an aluminum film or a copper film laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film further formed thereon; a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0198] Also, as shown in FIG. 15B, in the interface between the oxide 530 and the conductive layer 542a and in the vicinity thereof, a region 543a may be formed as a low-resistance region. Also, in the interface between the oxide 530 and the conductive layer 542b and in the vicinity thereof, a region 543b may be formed as a low-resistance region. At this time, the region 543a functions as one of the source region or the drain region, and the region 543b functions as the other of the source region or the drain region. Also, a channel formation region is formed in the region sandwiched between the region 543a and the region 543b.

[0199] By providing the conductive layer 542a and the conductive layer 542b so as to be in contact with the oxide 530, the oxygen concentration in the region 543a and the region 543b may be reduced. Also, a metal compound layer containing the metal contained in the conductive layer 542a and the component of the oxide 530 may be formed in the region 543a. Further, a metal compound layer containing the metal contained in the conductive layer 542b and the component of the oxide 530 may be formed in the region 543b. In such a case, the carrier density in the region 543a and the region 543b increases, and the electrical resistance in the region 543a and the region 543b decreases.

[0200] The insulating layer 544 is provided so as to cover the conductive layer 542a and the conductive layer 542b, and has a function of suppressing the oxidation of the conductive layer 542a and the conductive layer 542b. At this time, the insulating layer 544 may cover the side surface of the oxide 530 and be provided so as to be in contact with the insulating layer 524.

[0201] As the insulating layer 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used. Further, as the insulating layer 544, silicon oxynitride, silicon nitride, etc. can also be used.

[0202] In particular, as the insulating layer 544, it is preferable to use aluminum oxide or hafnium oxide, which is an insulator containing one or both oxides of aluminum or hafnium. Alternatively, it is preferable to use an oxide containing aluminum and hafnium (hafnium aluminate), etc. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent process. When the conductive layers 542a and 542b are made of a material having oxidation resistance, or a material that does not significantly reduce conductivity even when absorbing oxygen, the insulating layer 544 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0203] By having the insulating layer 544, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulating layer 580 into the oxide 530b. Further, it is possible to suppress the oxidation of the conductive layer 560 by the excess oxygen of the insulating layer 580.

[0204] The insulating layer 545 functions as a gate insulating film for the conductive layer 560. The insulating layer 545 is preferably formed using an insulator that contains oxygen excessively and releases oxygen by heating, similar to the above-described insulating layer 524.

[0205] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0206] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Further, in this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0207] By providing an insulator containing excess oxygen as the insulating layer 545, oxygen can be effectively supplied from the insulating layer 545 to the channel formation region of the oxide 530b. Further, it is preferable that the concentration of impurities such as water or hydrogen in the insulating layer 545 is reduced. The film thickness of the insulating layer 545 is preferably 1 nm or more and 20 nm or less.

[0208] Further, in order to efficiently supply the excess oxygen contained in the insulating layer 545 to the oxide 530, a metal oxide may be provided between the insulating layer 545 and the conductive layer 560. The metal oxide preferably has a composition that suppresses the diffusion of oxygen from the insulating layer 545 to the conductive layer 560. By providing a metal oxide that suppresses the diffusion of oxygen between the insulating layer 545 and the conductive layer 560, the diffusion of excess oxygen from the insulating layer 545 to the conductive layer 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Further, oxidation of the conductive layer 560 by excess oxygen can be suppressed.

[0209] Note that the insulating layer 545 may have a laminated structure. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by forming the insulating layer that functions as the gate insulating film into a laminated structure of a high-k material and a thermally stable material, the gate potential during transistor operation can be reduced while maintaining the physical film thickness.

[0210] The conductive layer 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 15B and 15C, but it may be a single-layer structure or a laminated structure of three or more layers.

[0211] For the conductive layer 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). Since the conductive layer 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductive layer 560b by oxygen contained in the insulating layer 545 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. In addition, an oxide semiconductor applicable to the oxide 530 can be used as the conductive layer 560a. In that case, by forming the conductive layer 560b by sputtering, the electrical resistance value of the conductive layer 560a can be decreased. This can be referred to as an OC (Oxide Conductor) electrode.

[0212] Also, for the conductive layer 560b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Further, since the conductive layer 560b also functions as a wiring, it is preferable to use a conductor having a low electrical resistance. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductive layer 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0213] The insulating layer 580 can be provided on the conductive layer 542a and on the conductive layer 542b via the insulating layer 544. The insulating layer 580 preferably has an excess oxygen region. For example, as the insulating layer 580, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with pores, or resin, etc. preferably can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Also, silicon oxide and silicon oxide with pores are preferable because an excess oxygen region can be easily formed in a later process.

[0214] The insulating layer 580 preferably has an excess oxygen region. By providing the insulating layer 580 from which oxygen is released by heating, oxygen in the insulating layer 580 can be efficiently supplied to the oxide 530. Note that it is preferable that the concentration of impurities such as water or hydrogen in the insulating layer 580 is reduced.

[0215] The insulating layer 574 is preferably provided so as to have a region in contact with the upper surface of the insulating layer 580, the upper surface of the conductive layer 560, and the upper surface of the insulating layer 545. By forming the insulating layer 574 by a sputtering method, an excess oxygen region can be provided in the insulating layer 545 and the insulating layer 580. Thereby, oxygen can be supplied from the excess oxygen region into the oxide 530.

[0216] For example, as the insulating layer 574, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used.

[0217] In particular, aluminum oxide has a high barrier property, and even a thin film of 0.5 nm or more and 3.0 nm or less can suppress the diffusion of hydrogen and nitrogen. Therefore, aluminum oxide formed by a sputtering method can function as an oxygen supply source and also as a barrier film for impurities such as hydrogen.

[0218] Further, it is preferable to provide an insulating layer 581 that functions as an interlayer film on the insulating layer 574. The insulating layer 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

[0219] Further, conductive layers 540a and 540b are disposed in openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 544. The conductive layers 540a and 540b are provided to face each other with the conductive layer 560 interposed therebetween.

[0220] As the substrate that can be used in the semiconductor device according to one aspect of the present invention, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), a resin substrate, and the like. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or a compound semiconductor substrate made of gallium nitride, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, such as a SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, and the like. Or, there is a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like.

[0221] <Configuration Example of Transistor_2> FIGS. 16A, 16B, and 16C are diagrams showing a configuration example of a transistor 500A, which is a modified example of the transistor 500. FIG. 16A is a top view of the transistor 500A. FIG. 16B is a cross-sectional view of a portion indicated by a one-dot chain line L3-L4 in FIG. 16A, and is also a cross-sectional view in the channel length direction of the transistor 500A. FIG. 16C is a cross-sectional view of a portion indicated by a one-dot chain line W3-W4 in FIG. 16A, and is also a cross-sectional view in the channel width direction of the transistor 500A. Note that in the top view of FIG. 16A, some elements are omitted for clarity of the drawing.

[0222] The transistor 500A is different from the transistor 500 in that an insulating layer 514, an insulating layer 516, an insulating layer 520, and an insulating layer 522 are provided between a substrate (not shown) and the insulating layer 524, and a conductive layer 503 is arranged so as to be embedded in the insulating layer 514 and the insulating layer 516. Here, the insulating layer 520 is arranged on the insulating layer 516 and the conductive layer 503, the insulating layer 522 is arranged on the insulating layer 520, and the insulating layer 524 is arranged on the insulating layer 522.

[0223] The conductive layer 503 functions as a back gate electrode. The conductive layer 503 is arranged so as to have a region overlapping with the oxide 530 and the conductive layer 560. Thereby, when a potential is supplied to the conductive layer 560 and the conductive layer 503, the electric field generated from the conductive layer 560 and the electric field generated from the conductive layer 503 are connected, and the channel formation region formed in the oxide 530 can be electrically surrounded.

[0224] In this specification and the like, a configuration of a transistor in which a channel formation region is electrically surrounded by an electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is referred to as a surrounded channel (s-channel) configuration. Further, in this specification and the like, the s-channel configuration has a feature that the side surfaces and peripheries of the oxide 530 in contact with the conductive layers 542a and 542b that function as source and drain electrodes are of the same I-type as the channel formation region. Also, since the side surfaces and peripheries of the oxide 530 in contact with the conductive layers 542a and 542b are in contact with the insulating layer 544, they can be of the I-type similar to the channel formation region. Note that in this specification and the like, the I-type can be treated in the same manner as high-purity intrinsic. Also, the s-channel configuration disclosed in this specification and the like is different from the Fin-type configuration and the planar-type configuration. By adopting the s-channel configuration, it is possible to enhance the resistance to the short-channel effect, in other words, to obtain a transistor in which the short-channel effect hardly occurs.

[0225] Further, the conductive layer 503 can be configured to include a conductive layer 503a and a conductive layer 503b. The conductive layer 503a is formed in contact with the inner walls of the openings of the insulating layer 514 and the insulating layer 516, and the conductive layer 503b is further formed inside. Note that in this embodiment, the conductive layer 503 is configured such that the conductive layer 503a and the conductive layer 503b are laminated, but one aspect of the present invention is not limited to this. For example, the conductive layer 503 may be a single layer or a laminated structure of three or more layers.

[0226] Here, it is preferable to use a conductive material in which the conductive layer 503a has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Or, it is preferable to use a conductive material in which the conductive layer 503a has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0227] For example, since the conductive layer 503a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductive layer 503b and the decrease in conductivity.

[0228] Further, when the conductive layer 503 also serves as a wiring, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductive layer 503b.

[0229] In the transistor 500A, the insulating layer 520, the insulating layer 522, and the insulating layer 524 have a function as a gate insulating film for the conductive layer 503. Here, as described above, the insulating layer 545 also has a function as a gate insulating film. Therefore, the insulating layer 545 can be referred to as a first gate insulating film, and the insulating layer 520, the insulating layer 522, and the insulating layer 524 can be referred to as a second gate insulating film.

[0230] As described above, the insulating layer 524 can have an excess oxygen region. In this case, it is preferable that the insulating layer 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate).

[0231] Since the insulating layer 522 has a function of suppressing the diffusion of oxygen and impurities, it is possible to suppress the diffusion of the oxygen contained in the oxide 530 to the insulating layer 520 side. Further, it is possible to suppress the reaction of the conductive layer 503 with the oxygen contained in the insulating layer 524 or the oxide 530.

[0232] The insulating layer 522 preferably uses, as a single layer or a laminate, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0233] In particular, it is preferable to use an insulator containing one or both of the oxides of aluminum and hafnium, which is an insulating material having a function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to permeate). As the insulator containing one or both of the oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the incorporation of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530.

[0234] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. The above insulators may be laminated with silicon oxide, silicon oxynitride, or silicon nitride and used.

[0235] Also, the insulating layer 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Further, by combining the insulator of the high-k material with silicon oxide or silicon oxynitride, an insulating layer 520 having a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0236] In the transistors 500 in FIGS. 16B and 16C, an insulating layer 520, an insulating layer 522, and an insulating layer 524 are shown as a second gate insulating film having a three-layer stacked structure. However, the second gate insulating film may have a single-layer, two-layer, or four-layer or more stacked structure. In that case, it is not limited to a stacked structure made of the same material, and a stacked structure made of different materials may also be used.

[0237] <Configuration Example of Transistor_3> FIGS. 17A, 17B, and 17C are diagrams showing a configuration example of a transistor 500B, which is a modified example of the transistor 500A. FIG. 17A is a top view of the transistor 500B. Further, FIG. 17B is a cross-sectional view of a portion indicated by a one-dot chain line L5-L6 in FIG. 17A, and is also a cross-sectional view of the transistor 500B in the channel length direction. Further, FIG. 17C is a cross-sectional view of a portion indicated by a one-dot chain line W5-W6 in FIG. 17A, and is also a cross-sectional view of the transistor 500B in the channel width direction. In the top view of FIG. 17A, some elements are omitted for clarity of the drawing.

[0238] The transistor 500B is different from the transistor 500A in that it has an insulating layer 552, an insulating layer 513, and an insulating layer 404. Further, the transistor 500B is different from the transistor 500A in that the insulating layer 552 is provided in contact with the side surfaces of the conductive layer 540a and the conductive layer 540b. Furthermore, the transistor 500B is different from the transistor 500A in that it does not have the insulating layer 520.

[0239] For the transistor 500B, the insulating layer 513 is provided on a substrate (not shown). Further, the insulating layer 404 is provided on the insulating layer 574 and on the insulating layer 513.

[0240] In transistor 500B, insulating layers 514, 516, 522, 524, 544, 580, and 574 are patterned, and insulating layer 404 is configured to cover them. That is, insulating layer 404 is in contact with the upper surface of insulating layer 574, the side surface of insulating layer 574, the side surface of insulating layer 580, the side surface of insulating layer 544, the side surface of insulating layer 524, the side surface of insulating layer 522, the side surface of insulating layer 516, the side surface of insulating layer 514, and the upper surface of insulating layer 513, respectively. Thereby, the oxide 530 and the like are isolated from the outside by the insulating layer 404 and the insulating layer 513.

[0241] It is preferable that the insulating layer 513 and the insulating layer 404 have a high function of suppressing the diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, etc.) or water molecules. For example, it is preferable to use silicon nitride or silicon oxynitride, which are materials with high hydrogen barrier properties, as the insulating layer 513 and the insulating layer 404. Thereby, since the diffusion of hydrogen or the like into the oxide 530 can be suppressed, the deterioration of the characteristics of the transistor 500B can be suppressed. Therefore, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.

[0242] The insulating layer 552 is provided so as to have a region in contact with the insulating layer 581, the insulating layer 404, the insulating layer 574, the insulating layer 580, and the insulating layer 544. The insulating layer 552 preferably has a function of suppressing the diffusion of hydrogen or water molecules. For example, as the insulating layer 552, it is preferable to use an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride, which is a material with high hydrogen barrier properties. In particular, since silicon nitride is a material with high hydrogen barrier properties, it is suitable for use as the insulating layer 552. By using a material with high hydrogen barrier properties as the insulating layer 552, the diffusion of impurities such as water or hydrogen from the insulating layer 580 or the like into the oxide 530 through the conductive layer 540a or the conductive layer 540b can be suppressed. Further, the absorption of oxygen contained in the insulating layer 580 by the conductive layer 540a and the conductive layer 540b can be suppressed. As described above, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.

[0243] <Configuration Example of Transistor_4> FIGS. 18A, 18B, and 18C are diagrams showing a configuration example of a transistor 500C, which is a modified example of the transistor 500. FIG. 18A is a top view of the transistor 500C. Further, FIG. 18B is a cross-sectional view of the portion indicated by the one-dot chain line L7 - L8 in FIG. 18A, and is also a cross-sectional view of the transistor 500C in the channel length direction. Further, FIG. 18C is a cross-sectional view of the portion indicated by the one-dot chain line W7 - W8 in FIG. 18A, and is also a cross-sectional view of the transistor 500C in the channel width direction. Note that in the top view of FIG. 18A, some elements are omitted for clarity of the drawing.

[0244] The conductive layer 560 that functions as the first gate electrode includes a conductive layer 560a and a conductive layer 560b on the conductive layer 560a. It is preferable to use a conductive material for the conductive layer 560a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0245] Since the conductive layer 560a has a function of suppressing the diffusion of oxygen, even if a material that is easily oxidized is used as the conductive layer 560b, it is possible to suppress the oxidation of the conductive layer 560b. Thereby, it is possible to suppress a decrease in the conductivity of the conductive layer 560.

[0246] Further, it is preferable to provide an insulating layer 544 so as to cover the upper surface and the side surface of the conductive layer 560 and the side surface of the insulating layer 545. Note that the insulating layer 544 may use an insulating material that has a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. Further, in addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can be used.

[0247] By providing the insulating layer 544, oxidation of the conductive layer 560 can be suppressed. Further, by having the insulating layer 544, diffusion of impurities such as water and hydrogen contained in the insulating layer 580 into the transistor 500C can be suppressed.

[0248] In the transistor 500C, since a part of the conductive layer 542a and a part of the conductive layer 542b overlap with the conductive layer 560, the parasitic capacitance is likely to be larger than that of the transistor 500. Therefore, the driving frequency tends to be lower than that of the transistor 500. However, since the process of providing an opening in the insulating layer 580 and filling the conductive layer 560 and the insulating layer 545, etc. is unnecessary, the productivity is high as compared with the transistor 500.

[0249] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.

[0250] (Embodiment 3) In this embodiment, an oxide semiconductor which is a kind of metal oxide will be described.

[0251] The metal oxide preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. Further, in addition to those, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Also, one or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0252] <Classification of crystal structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 19A. FIG. 19A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0253] As shown in Fig. 19A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "Amorphous" includes completely amorphous. Also, "Crystalline" includes CAAC (C-Axis-Aligned Crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Also, "Crystal" includes single crystal and poly crystal.

[0254] Note that the structure within the thick frame shown in Fig. 19A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous" and "Crystal".

[0255] Note that the crystal structure of a film or a substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, Fig. 19B shows the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of a CAAC-IGZO film classified as "Crystalline". Note that the GIXD method is also called the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Fig. 19B will be simply referred to as the XRD spectrum. The vertical axis of Fig. 19B is intensity and the horizontal axis is 2θ. Note that the composition of the CAAC-IGZO film shown in Fig. 19B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in Fig. 19B is 500 nm.

[0256] As shown in Fig. 19B, in the XRD spectrum of the CAAC-IGZO film, peaks indicating distinct crystallinity are detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak showing c-axis orientation is detected near 2θ = 31°. As shown in Fig. 19B, the peak near 2θ = 31° is asymmetric about the angle at which the peak intensity is detected.

[0257] Also, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Fig. 19C. Fig. 19C is the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in Fig. 19C is near In:Ga:Zn = 4:2:3 [atomic ratio]. Also, in the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0258] As shown in Fig. 19C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots showing c-axis orientation are observed.

[0259] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from Fig. 19A. For example, the oxide semiconductor can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Also, non-single-crystalline oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, etc.

[0260] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0261] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions have their c-axes oriented in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. The strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor with its c-axis oriented and no obvious orientation in the a-b plane direction.

[0262] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0263] Also, in In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. The In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0264] When performing a structural analysis on the CAAC-OS film using, for example, an XRD apparatus, in the out-of-plane XRD measurement using θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type, composition, etc. of the metal element constituting the CAAC-OS.

[0265] Also, for example, in the electron diffraction pattern of the CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0266] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, or the interatomic bond distance changes due to the substitution of metal atoms, etc.

[0267] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers, and there is a high possibility of causing a decrease in the on-current of the transistor and a decrease in the field-effect mobility due to the capture of carriers. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor of the transistor. Note that for constituting CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0268] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct crystal grain boundaries. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to crystal grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0269] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Also, nc-OS has no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS and amorphous oxide semiconductors. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as restricted view electron beam diffraction) using an electron beam with a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern like a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) is performed on the nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0270] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0271] [[Constitution of Oxide Semiconductor]] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0272] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0273] Furthermore, the CAC-OS is a configuration in which the material is separated into a first region and a second region to form a mosaic state, and the first region is a configuration (hereinafter also referred to as a cloud state) distributed in the film. That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0274] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0275] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0276] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0277] For example, in the CAC-OS of the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0278] When using CAC-OS in a transistor, the conductivity caused by the first region and the insulating property caused by the second region act complementarily, enabling the function of switching (on / off function) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on )、high field-effect mobility (μ), and good switching drive can be achieved.

[0279] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0280] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0281] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0282] It is preferable to use an oxide semiconductor with a low carrier concentration in the transistor. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, still more preferably 1×10 11 cm -3 or less, even more preferably 1×10 10 cm -3 less than, and 1×10 -9 cm-3 The above is the case. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced, and the density of defect levels may be reduced.

[0283] In addition, an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic may have a low trap level density because the density of defect levels is low.

[0284] In addition, the charge trapped in the trap level of the oxide semiconductor may take a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.

[0285] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0286] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0287] In the oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0288] In addition, when an alkali metal or an alkaline earth metal is contained in an oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is preferably 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0289] In addition, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, in an oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is 5×10 19 atoms / cm 3 or less, preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, still more preferably 5×10 17 atoms / cm 3 or less.

[0290] In addition, hydrogen contained in the oxide semiconductor may react with oxygen bonded to a metal atom to form water, and thus may form oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons as carriers may be generated. Also, a part of hydrogen may bond to oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is 1×10 20atoms / cm 3 less than, preferably 1×10 19 atoms / cm 3 less than, more preferably 5×10 18 atoms / cm 3 less than, even more preferably 1×10 18 atoms / cm 3 to less than.

[0291] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0292] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0293] (Embodiment 4) In this embodiment, a configuration example of an imaging device to which a semiconductor device according to one aspect of the present invention can be applied will be described with reference to the drawings.

[0294] FIG. 20A is a cross-sectional view showing a configuration example of an imaging device to which a semiconductor device according to one aspect of the present invention can be applied. Specifically, among the components of the pixel circuit 50 shown in FIG. 13A, a cross-sectional configuration example of the photoelectric conversion device 60, the transistor 61, and the transistor 64 is shown. In FIG. 20A, an example in which the pixel circuit 50 has a stacked structure of a layer 561 and a layer 562 is shown.

[0295] The layer 561 has a photoelectric conversion device 60. The photoelectric conversion device 60 can be a stack of a layer 565a, a layer 565b, and a layer 565c. In the layer 565b, a region 536 for electrically connecting the wiring provided in the layer 562 and the layer 565c is provided. For example, the region 536 can be a p + type region.

[0296] The photoelectric conversion device 60 shown in FIG. 20A is a pn junction type photodiode. For example, a p + type semiconductor in the layer 565a, an n-type semiconductor in the layer 565b, and an n+ A type semiconductor can be used. Alternatively, an n + type semiconductor for layer 565a, a p-type semiconductor for layer 565b, and a p + type semiconductor for layer 565c may be used. Alternatively, it may be a pin junction type photodiode with layer 565b being an i-type semiconductor.

[0297] The above pn junction type photodiode or pin junction type photodiode can be formed using single crystal silicon. Also, as the pin junction type photodiode, it can also be formed using thin films such as amorphous silicon, microcrystalline silicon, and polycrystalline silicon.

[0298] An Si transistor is provided in layer 562. The Si transistor shown in FIG. 20A is a fin type having a channel formation region on a silicon substrate 540, and a cross section in the channel width direction is shown in FIG. 20B. The Si transistor may be a planar type as shown in FIG. 20C.

[0299] Alternatively, as shown in FIG. 20D, it may be a transistor having a semiconductor layer 555 of a silicon thin film. The semiconductor layer 555 can be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 540.

[0300] FIG. 20A shows a configuration example in which the electrical connection between the elements of layer 561 and the elements of layer 562 is obtained by a bonding technique.

[0301] An insulating layer 542, a conductive layer 533, and a conductive layer 534 are provided in layer 561. The conductive layer 533 and the conductive layer 534 have regions embedded in the insulating layer 542. The conductive layer 533 is electrically connected to layer 565a. The conductive layer 534 is electrically connected to region 536. Also, the surfaces of the insulating layer 542, the conductive layer 533, and the conductive layer 534 are flattened so that their heights are the same, respectively.

[0302] The insulating layer 541, the conductive layer 531, and the conductive layer 532 are provided in the layer 562. The conductive layer 531 and the conductive layer 532 have regions embedded in the insulating layer 541. The conductive layer 531 is electrically connected to the source or drain of the transistor 61. Further, the surfaces of the insulating layer 541, the conductive layer 531, and the conductive layer 532 are flattened so that their heights are the same.

[0303] Here, it is preferable that the main components of the conductive layer 531 and the conductive layer 533 are the same metal element. It is preferable that the main components of the conductive layer 532 and the conductive layer 534 are the same metal element. Also, it is preferable that the insulating layer 541 and the insulating layer 542 are composed of the same components.

[0304] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au, etc. can be used for the conductive layer 531, the conductive layer 532, the conductive layer 533, and the conductive layer 534. From the viewpoint of ease of bonding, it is preferable to use Cu, Al, W, or Au. Also, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used for the insulating layer 541 and the insulating layer 542.

[0305] That is, it is preferable to use the same metal material shown above for each of the combination of the conductive layer 531 and the conductive layer 533 and the combination of the conductive layer 532 and the conductive layer 534. Also, it is preferable to use the same insulating material shown above for each of the insulating layer 541 and the insulating layer 542. With such a configuration, bonding can be performed with the boundary between the layer 561 and the layer 562 as the bonding position.

[0306] By this bonding, electrical connection can be obtained for each of the combination of the conductive layer 531 and the conductive layer 533 and the combination of the conductive layer 532 and the conductive layer 534. Also, a connection having the mechanical strength of the insulating layer 541 and the insulating layer 542 can be obtained.

[0307] For the bonding between metal layers, a surface activation bonding method can be used, in which the oxide film on the surface and the adsorbed layer of impurities are removed by sputtering or the like, and the cleaned and activated surfaces are brought into contact with each other for bonding. Alternatively, a diffusion bonding method or the like in which the surfaces are bonded together using a combination of temperature and pressure can be used. Since bonding occurs at the atomic level in both cases, excellent bonding can be obtained not only electrically but also mechanically.

[0308] In addition, for the bonding between insulating layers, after obtaining high flatness by polishing or the like, a hydrophilic bonding method or the like can be used, in which the surfaces subjected to hydrophilic treatment with oxygen plasma or the like are brought into contact with each other for temporary bonding, and permanent bonding is performed by dehydration by heat treatment. Since the hydrophilic bonding method also involves bonding at the atomic level, excellent mechanical bonding can be obtained.

[0309] When laminating layer 561 and layer 562, since the insulating layer and the metal layer are mixed on each bonding surface, for example, a combination of the surface activation bonding method and the hydrophilic bonding method can be used.

[0310] For example, a method can be used in which the surface is cleaned after polishing, an antioxidant treatment is performed on the surface of the metal layer, and then a hydrophilic treatment is performed for bonding. Also, the surface of the metal layer can be made of a metal with low oxidation resistance such as Au, and a hydrophilic treatment can be performed. In addition, a bonding method other than the methods described above may be used.

[0311] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.

[0312] (Embodiment 5) In this embodiment, an example of an electronic device that can use the semiconductor device of one aspect of the present invention will be described.

[0313] Examples of electronic devices that can use the semiconductor device according to one aspect of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with recording media, mobile phones, game machines including portable types, portable data terminals, electronic book terminals, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS. 21A to 21F.

[0314] FIG. 21A shows an example of a mobile phone 910, which has a housing 911, a display unit 912, operation buttons 913, an external connection port 914, a speaker 915, a slot 916, a camera 917, a headphone jack 918, and the like. The mobile phone 910 can be provided with a touch sensor on the display unit 912. Any operation such as making a call or inputting characters can be performed by touching the display unit 912 with a finger or a stylus. Also, various removable storage devices such as memory cards such as SD cards, USB memories, and SSDs (solid state drives) can be inserted into the slot 916.

[0315] The semiconductor device according to one aspect of the present invention can be applied to the mobile phone 910. For example, an imaging device having the semiconductor device according to one aspect of the present invention can be applied to elements for acquiring imaging data by the mobile phone 910, such as the camera 917. Thereby, the mobile phone 910 can be miniaturized.

[0316] FIG. 21B shows an example of a portable data terminal 920, which has a housing 921, a display unit 922, a speaker 923, a camera 924, and the like. Information can be input and output by the touch panel function of the display unit 922. Also, characters and the like can be recognized from the image acquired by the camera 924, and the characters can be output as audio by the speaker 923.

[0317] The semiconductor device according to an aspect of the present invention can be applied to the portable data terminal 920. For example, an imaging device having the semiconductor device according to an aspect of the present invention can be applied to an element for acquiring imaging data by the portable data terminal 920, such as the camera 924. Thereby, the portable data terminal 920 can be miniaturized.

[0318] FIG. 21C shows an example of the surveillance camera 960, which includes a fixture 961, a housing 962, a lens 963, etc. The surveillance camera 960 can be attached to a wall or a ceiling by the fixture 961. Note that the surveillance camera is a conventional name and does not limit the use. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

[0319] The semiconductor device according to an aspect of the present invention can be applied to the surveillance camera 960. For example, an imaging device having the semiconductor device according to an aspect of the present invention can be applied to an element for acquiring imaging data by the surveillance camera 960. Thereby, the surveillance camera 960 can be miniaturized.

[0320] FIG. 21D shows an example of the video camera 940, which includes a first housing 941, a second housing 942, a display unit 943, operation keys 944, a lens 945, a connection unit 946, a speaker 947, a microphone 948, etc. The operation keys 944 and the lens 945 can be provided on the first housing 941, and the display unit 943 can be provided on the second housing 942.

[0321] The semiconductor device according to an aspect of the present invention can be applied to the video camera 940. For example, an imaging device having the semiconductor device according to an aspect of the present invention can be applied to an element for acquiring imaging data by the video camera 940. Thereby, the video camera 940 can be miniaturized.

[0322] FIG. 21E is an example of a digital camera 950, which includes a housing 951, a shutter button 952, a light emitting unit 953, a lens 954, etc. The semiconductor device according to one aspect of the present invention can be applied to the digital camera 950. For example, an imaging device having the semiconductor device according to one aspect of the present invention can be applied to an element for acquiring imaging data by the digital camera 950. Thereby, the digital camera 950 can be miniaturized.

[0323] FIG. 21F is an example of a wristwatch-type information terminal 930, which includes a housing-cum-wristband 931, a display unit 932, an operation button 933, an external connection port 934, a camera 935, etc. The display unit 932 is provided with a touch panel for operating the information terminal 930. The housing-cum-wristband 931 and the display unit 932 have flexibility and excellent wearability on the body.

[0324] The semiconductor device according to one aspect of the present invention can be applied to the information terminal 930. For example, an imaging device having the semiconductor device according to one aspect of the present invention can be applied to an element for acquiring imaging data by the information terminal 930, such as the camera 935. Thereby, the information terminal 930 can be miniaturized.

[0325] The configurations, structures, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.

Description of Reference Numerals

[0326] 10: semiconductor device, 11: transmission path, 20: circuit, 21: transistor, 22: transistor, 23: transistor, 24: capacitor, 30: circuit, 31: transistor, 32: transistor, 33: transistor, 34: capacitor, 40: circuit, 41: capacitor, 42: transistor, 50: pixel circuit, 60: photoelectric conversion device, 61: transistor, 62: transistor, 63: transistor, 64: transistor, 66: capacitor, 69: transistor, 71: period, 72: period, 73: period, 74: period, 75: period, 80: imaging device, 81 : pixel portion, 82: gate driver circuit, 83: data driver circuit, 404: insulating layer, 500: transistor, 500A: transistor, 500B: transistor, 500C: transistor, 503: conductive layer, 503a: conductive layer, 503b: conductive layer, 513: insulating layer, 514: insulating layer, 516: insulating layer, 520: insulating layer, 522: insulating layer, 524: insulating layer, 530: oxide, 530a: oxide, 530b: oxide, 531: conductive layer, 532: conductive layer, 533: conductive layer, 534: conductive layer, 536: region, 540: silicon substrate, 540a: conductive layer, 540b: Conductive layer, 541: insulating layer, 542: insulating layer, 542a: conductive layer, 542b: conductive layer, 543a: region, 543b: region, 544: insulating layer, 545: insulating layer, 546: insulating layer, 552: insulating layer, 555: semiconductor layer, 560: conductive layer, 560a: conductive layer, 560b: conductive layer, 561: layer, 562: layer, 565a: layer, 565b: layer, 565c: layer, 574: insulating layer, 580: insulating layer, 581: insulating layer, 910: mobile phone, 911: housing, 912: display unit, 913: operation button, 914: external connection port, 915: speaker, 916: socket, 917: camera, 918: earphone jack, 920: portable data terminal, 921: housing, 922: display unit, 923: speaker, 924: camera, 930: information terminal, 931: housing and wristband, 932: display unit, 933: operation button, 934: external connection port, 935: camera, 940: video camera, 941: housing, 942: housing, 943: display unit, 944: operation key, 945: lens, 946: connection unit, 947: speaker, 948: microphone, 950: digital camera, 951: housing, 952: shutter button, 953: light emitting unit, 954: lens, 960: surveillance camera,961: Fixture, 962: Housing, 963: Lens,

Claims

【Claim 1】 having n sets of a first transistor and a second transistor whose gates are electrically connected to each other (n is an integer of 2 or more), one of the sources or drains of each of the n first transistors is electrically connected to each other, the other of the sources or drains of each of the n first transistors is electrically connected to each other, the n second transistors are electrically connected in series, the first circuit having the n first transistors has a function of outputting a first potential when any of the potentials input to the gates of the n first transistors is equal to or lower than a first reference potential, the first circuit has a function of outputting a second potential when at least one of the potentials input to the gates of the n first transistors is higher than the first reference potential, the second circuit having the n second transistors has a function of outputting a third potential when any of the potentials input to the gates of the n second transistors is higher than a second reference potential, the second circuit has a function of outputting the first potential when at least one of the potentials input to the gates of the n second transistors is equal to or lower than the second reference potential, a semiconductor device.

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