Liquid crystal display device

Abstract

To improve an element characteristic, and reliability in elements even when providing a semiconductor layer on a gate electrode layer, a source electrode layer and a drain electrode layer.SOLUTION: In a structure which includes: a gate electrode layer; a gate insulation layer provided on the gate electrode layer; a source electrode layer and a drain electrode layer provided so as to overlap with a part of the gate electrode layer via the gate insulation layer; and a semiconductor layer provided on the gate insulation layer, the source electrode layer, and the drain electrode layer, a film thickness of the gate insulation layer positioned in an area between the source electrode layer and the drain electrode layer is smaller than a film thickness of the gate insulation layer provided between the gate electrode layer and the source electrode layer, and a film thickness of the gate insulation layer provided between the gate electrode layer and the drain electrode layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] In recent years, techniques for fabricating thin film transistors (also referred to as TFTs) using oxide semiconductors and applying them to electronic devices such as etc. have attracted attention. For example, in Patent Document 1 and Patent Document 2, zinc oxide, an In-Ga-Zn-O based oxide semiconductor, etc. are used as the oxide semiconductor layer, and a technique for fabricating a switching element of an image display device is disclosed.

[0003] In addition, various structures have been proposed as the structure of a transistor using an oxide semiconductor layer. For example, in Patent Document 2 and Patent Document 3 described above, a bottom gate-bottom contact type structure in which an oxide semiconductor layer is formed on a source electrode layer and a drain electrode layer provided on a gate insulating layer is shown.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] Generally, in order to reduce the driving voltage of a transistor and perform high-speed operation, the It is effective to reduce the film thickness. However, in the case of a bottom gate-bottom contact type structure when the gate electrode layer, the source electrode layer, and the drain electrode layer partially overlap via the gate insulating layer as the film thickness of the gate insulating layer decreases, a parasitic capacitance is formed between the gate electrode layer and the source electrode layer and the drain electrode layer, which may affect the device characteristics. As a result, variations may occur in the device characteristics, and the reliability of the device may decrease.

[0006] Also, when the source electrode layer or the drain electrode layer is provided so as to cover the end portion of the gate electrode layer via the gate insulating layer if the thickness of the gate insulating layer covering the end portion of the gate electrode layer becomes small a problem occurs in that leakage easily occurs between the gate electrode layer and the source electrode layer or the drain electrode layer occurs.

[0007] In view of the above problems, even in the case where the semiconductor layer is provided on the gate electrode layer, the source electrode layer, and the drain electrode layer the purpose is to improve the device characteristics and the reliability of the device at the same time. is the first.

Means for Solving the Problems

[0008] In a structure having a gate electrode layer, a gate insulating layer provided on the gate electrode layer, a source electrode layer and a drain electrode layer provided so as to overlap a part of the gate electrode layer via the gate insulating layer, and a semiconductor layer provided on the gate insulating layer, the source electrode layer, and the drain electrode layer the film thickness of the gate insulating layer located in the region between the source electrode layer and the drain electrode layer is made smaller than the film thickness of the gate insulating layer provided between the gate electrode layer and the source electrode layer or the film thickness of the gate insulating layer provided between the gate electrode layer and the drain electrode layer. In this case, the source electrode layer and the drain electrode layer are provided so as to overlap a part of the gate electrode layer via the gate insulating layer, and a semiconductor layer is provided on the gate insulating layer, the source electrode layer, and the drain electrode layer. In the structure having a gate electrode layer, a gate insulating layer provided on the gate electrode layer, a source electrode layer and a drain electrode layer provided so as to overlap a part of the gate electrode layer via the gate insulating layer, and a semiconductor layer provided on the gate insulating layer, the source electrode layer, and the drain electrode layer the film thickness of the gate insulating layer located in the region between the source electrode layer and the drain electrode layer is made smaller than the film thickness of the gate insulating layer provided between the gate electrode layer and the source electrode layer or the film thickness of the gate insulating layer provided between the gate electrode layer and the drain electrode layer. is provided so as to be smaller than the film thickness of the gate insulating layer provided between the gate electrode layer and the source electrode layer or the film thickness of the gate insulating layer provided between the gate electrode layer and the drain electrode layer. In this case, the source Reduce the parasitic capacitance generated between the source electrode layer and the drain electrode layer and the gate electrode layer, and the device characteristics can be improved.

[0009] In addition, one aspect of the disclosed invention is a gate electrode layer provided on a substrate, and on the gate electrode layer a gate insulating layer provided, and a source electrode layer and a drain electrode layer provided so as to overlap a part of the gate electrode layer through the gate insulating layer, and on the gate electrode layer, between the source electrode layer and the drain electrode layer, provided in contact with the gate insulating layer located in the region therebetween, and having an oxide semiconductor layer provided on the source electrode layer and the drain electrode layer, characterized in that the film thickness of the gate insulating layer located in the region between the source electrode layer and the drain electrode layer on the gate electrode layer is smaller than the film thickness of the gate insulating layer provided between the gate electrode layer and the source electrode layer or the gate insulating layer provided between the gate electrode layer and the drain electrode layer.

[0010] In addition, one aspect of the disclosed invention is a gate electrode layer provided on a substrate, and on the gate electrode layer a first insulating layer provided, and on the first insulating layer, a second insulating layer provided so as to overlap a part of the gate electrode layer, and a source electrode layer and a drain electrode layer provided so as to overlap a part of the gate electrode layer through the first insulating layer and the second insulating layer, and on the gate electrode layer, provided in contact with the first insulating layer located in the region between the source electrode layer and the drain electrode layer therebetween, and characterized by having an oxide semiconductor layer provided on the source electrode layer and the drain electrode layer. Note that the film thickness of the first insulating layer located in the region between the source electrode layer and the drain electrode layer on the gate electrode layer is set to the first insulating layer provided between the gate electrode layer and the source electrode layer. The film thickness of the first insulating layer located in the region between the source electrode layer and the drain electrode layer on the gate electrode layer is set to the first insulating layer provided between the gate electrode layer and the source electrode layer. ​​​​​​​​Smaller than the film thickness of the first insulating layer provided between the edge layer or the gate electrode layer and the drain electrode layer It may be.

[0011] Further, one aspect of the disclosed invention is a gate electrode layer provided on a substrate, and on the gate electrode layer A first insulating layer and a second insulating layer provided by being laminated in order, and the first insulating layer and the second insulating layer A source electrode layer and a drain electrode layer provided so as to overlap a part of the gate electrode layer through And a second provided on the gate electrode layer and located in the region between the source electrode layer and the drain electrode layer An oxide semiconductor layer provided in contact with the insulating layer and provided on the source electrode layer and the drain electrode layer Having, located in the region between the source electrode layer and the drain electrode layer on the gate electrode layer The film thickness of the second insulating layer is smaller than the film thickness of the second insulating layer provided between the gate electrode layer and the source electrode layer And the film thickness of the second insulating layer provided between the gate electrode layer and the drain electrode layer It is characterized by that.

[0012] Further, one aspect of the disclosed invention is to form a gate electrode layer on a substrate, and a gate on the gate electrode layer Form an insulating layer, form a source electrode layer and a drain electrode layer on the gate insulating layer, and etch the upper layer portion of the gate insulating layer provided in the region between the source electrode layer and the drain electrode layer By doing so, the film thickness of the gate insulating layer located in the region between the source electrode layer and the drain electrode layer is Smaller than the film thickness of the gate insulating layer provided between the gate electrode layer and the source electrode layer or the gate insulating layer provided between the gate electrode layer and the drain An electrode layer, and an oxide semiconductor layer is formed on the gate insulating layer, the source electrode layer and the drain electrode layer. It is characterized by that. It is characterized by forming an oxide semiconductor layer on the gate insulating layer, the source electrode layer and the drain electrode layer.

[0013] In addition, one aspect of the disclosed invention is to form a gate electrode layer on a substrate, form a first insulating layer on the gate electrode layer, form a second insulating layer on the first insulating layer, form a source electrode layer and a drain electrode layer on the second insulating layer, and expose the first insulating layer by etching the second insulating layer provided in the region between the source electrode layer and the drain electrode layer, and form an oxide semiconductor layer on the first insulating layer, the source electrode layer, and the drain electrode layer.

[0014] Examples of the oxide semiconductor that can be used in this specification include those represented by InMO3(Zn O) m (m > 0, m is not necessarily an integer). Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co ). For example, when Ga is selected as M, in addition to the case of only Ga, cases where other metal elements such as Ga and Ni, or Ga and Fe are selected are included. In addition, in the above oxide semiconductor, in addition to the metal elements contained as M, there are those containing impurity elements such as Fe, Ni, and other transition metal elements, or oxides of the transition metals. In this specification, among the above oxide semiconductors, those containing at least gallium as M are called In-Ga-Zn-O-based oxide semiconductors, and a thin film using this material is called an In-Ga-Zn-O-based non-single crystal film.

[0015] Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all included in semiconductor devices. In addition, in this specification, a display device includes a light-emitting device and a liquid crystal display device. A light-emitting device emits light ​​​​​​ The light emitting element changes its brightness depending on a current or a voltage. The category includes elements that are controlled by inorganic EL (Electro Lu These include photoluminescence elements, organic electroluminescence elements, etc. Effect of the Invention

[0016] A gate electrode layer, a gate insulating layer provided on the gate electrode layer, and a gate insulating layer a source electrode layer and a drain electrode layer provided so as to overlap a part of the gate electrode layer; In a structure having a semiconductor layer provided on a gate insulating layer, a source electrode layer, and a drain electrode layer, The thickness of the gate insulating layer located between the source electrode layer and the drain electrode layer is set to be equal to the thickness of the gate insulating layer. A gate insulating layer or a gate electrode layer and a drain electrode layer are provided between the gate electrode layer and the source electrode layer. The thickness of the gate insulating layer provided between the electrode layers is set to be smaller than the thickness of the gate insulating layer. The parasitic capacitance between the source electrode layer and the drain electrode layer and the gate electrode layer is reduced, and As a result, the device characteristics can be improved. [Brief description of the drawings]

[0017]

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[0018] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the described embodiment, and various changes in form and details are possible without departing from the spirit of the invention. It is obvious to those skilled in the art that the configurations according to the different embodiments can be combined as appropriate. In the configuration of the invention described below, the same parts Alternatively, the same reference numerals are used for parts having similar functions, and repeated explanations thereof will be omitted.

[0019] (Embodiment 1) First, a structure of a thin film transistor shown in this embodiment mode will be described with reference to FIG. Reveal.

[0020] The thin film transistor 250 shown in this embodiment has a gate electrode layer 210 formed over a substrate 200. 202, a gate insulating layer 204 provided on the gate electrode layer 202 and the substrate 200, and a gate a source electrode layer 206a and a drain electrode layer 206b provided over the source insulating layer 204; The source electrode layer 206a and the drain electrode layer 206b are provided on the source electrode layer 206 a and the drain electrode layer 206b. Further, the source electrode layer 206a and the drain electrode layer 2 The gate electrode layer 202 is provided so as to overlap with a part of the gate electrode layer 202 via the gate insulating layer 204. and a gate insulating layer located in the region between the source electrode layer 206a and the drain electrode layer 206b. The thickness t2 of the gate electrode layer 204 is the thickness of the gate electrode layer 202 provided between the source electrode layer 206a. A gate provided between the gate insulating layer 204, the gate electrode layer 202, and the drain electrode layer 206b is provided so as to be smaller than the film thickness t1 of the gate insulating layer 204 (see Fig. 1(A)).

[0021] That is, in a region where the gate insulating layer 204 overlaps with the gate electrode layer 202, there is a concave portion (a depression (hereinafter referred to as "concave portion 207")), and an oxide semiconductor layer 210 is provided in the concave portion 207 of the gate insulating layer 204. Here, the concave portion 207 of the gate insulating layer 204 refers to a depression formed in the gate insulating layer 204 when observed from the cross-sectional direction connecting the source electrode layer and the drain electrode layer.

[0022] Thus, by adopting the configuration shown in Fig. 1(A), even when the source electrode layer 206a and the drain electrode layer 206b are provided so as to partially overlap with the gate electrode layer 202 via the gate insulating layer 204, and the oxide semiconductor layer 210 is provided on the source electrode layer 206a and the drain electrode layer 206b, the parasitic capacitance generated between the source electrode layer 206a and the drain electrode layer 206b and the gate electrode layer 202 can be reduced, and the driving voltage of the transistor can be reduced to improve the element characteristics.

[0023] In Fig. 1(A), a case where both the source electrode layer 206a and the drain electrode layer 206b overlap with a part of the gate electrode layer 202 via the gate insulating layer 204 is shown. However, the present embodiment is not limited to this. When either the source electrode layer 206a or the drain electrode layer 206b overlaps with the gate electrode layer 202 via the gate insulating layer 204, the film thickness t1 of the gate insulating layer 204 provided between the overlapping electrode layer and the gate electrode layer 202 is made smaller than the film thickness of the gate insulating layer 204 provided between the other electrode layer and the gate electrode layer 202. the gate electrode layer 202, and the film thickness t1 of the gate insulating layer 204 provided between the overlapping electrode layer and the gate electrode layer 202 is made smaller than the film thickness of the gate insulating layer 204 provided between the other electrode layer and the gate electrode layer 202. The thickness t2 of the gate insulating layer 204 located in the region between 06a and the drain electrode layer 206b may be provided to be thicker. It suffices to provide it so as to be thicker.

[0024] Next, with reference to FIG. 2, one embodiment of a method for manufacturing the thin film transistor 250 shown in FIG. 1(A) will be described. will be described.

[0025] First, a gate electrode layer 202 is formed on the substrate 200, and subsequently, a gate insulating layer 204 is formed on the gate electrode layer 202 (see FIG. 2(A)). is formed (see FIG. 2(A)).

[0026] The substrate 200 may be any substrate having an insulating surface. For example, a glass substrate can be used. The glass substrate is preferably a non-alkali glass substrate. As the non-alkali glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and lithium borosilicate glass are used. In addition, as the substrate 200, a ceramic substrate, an insulating substrate made of an insulator such as a quartz substrate or a sapphire substrate, a semiconductor substrate made of a semiconductor material such as silicon with its surface coated with an insulating material, or a conductive substrate made of a conductor such as metal or stainless steel with its surface coated with an insulating material can be used. Also, if it can withstand the heat treatment in the manufacturing process, a plastic substrate can be used. In addition, other than the above, a ceramic substrate, an insulating substrate made of an insulator such as a quartz substrate or a sapphire substrate, a semiconductor substrate made of a semiconductor material such as silicon with its surface coated with an insulating material, or a conductive substrate made of a conductor such as metal or stainless steel with its surface coated with an insulating material can be used. Also, if it can withstand the heat treatment in the manufacturing process, a plastic substrate can be used. In addition, other than the above, a ceramic substrate, an insulating substrate made of an insulator such as a quartz substrate or a sapphire substrate, a semiconductor substrate made of a semiconductor material such as silicon with its surface coated with an insulating material, or a conductive substrate made of a conductor such as metal or stainless steel with its surface coated with an insulating material can be used. Also, if it can withstand the heat treatment in the manufacturing process, a plastic substrate can be used. In addition, other than the above, a ceramic substrate, an insulating substrate made of an insulator such as a quartz substrate or a sapphire substrate, a semiconductor substrate made of a semiconductor material such as silicon with its surface coated with an insulating material, or a conductive substrate made of a conductor such as metal or stainless steel with its surface coated with an insulating material can be used. Also, if it can withstand the heat treatment in the manufacturing process, a plastic substrate can be used. In addition, other than the above, a ceramic substrate, an insulating substrate made of an insulator such as a quartz substrate or a sapphire substrate, a semiconductor substrate made of a semiconductor material such as silicon with its surface coated with an insulating material, or a conductive substrate made of a conductor such as metal or stainless steel with its surface coated with an insulating material can be used. Also, if it can withstand the heat treatment in the manufacturing process, a plastic substrate can be used. In addition, other than the above, a ceramic substrate, an insulating substrate made of an insulator such as a quartz substrate or a sapphire substrate, a semiconductor substrate made of a semiconductor material such as silicon with its surface coated with an insulating material, or a conductive substrate made of a conductor such as metal or stainless steel with its surface coated with an insulating material can be used. Also, if it can withstand the heat treatment in the manufacturing process, a plastic substrate can be used.

[0027] The gate electrode layer 202 can be formed by forming a conductive layer over the entire surface of the substrate 200 and then etching the conductive layer using photolithography. The gate electrode layer 202 includes electrodes and wirings formed by the above conductive layer, such as gate wirings. The gate electrode layer 202 can be formed by forming a conductive layer over the entire surface of the substrate 200 and then etching the conductive layer using photolithography. The gate electrode layer 202 includes electrodes and wirings formed by the above conductive layer, such as gate wirings. The gate electrode layer 202 includes electrodes and wirings formed by the above conductive layer, such as gate wirings.

[0028] The gate electrode layer 202 is made of aluminum (Al), copper (Cu), molybdenum (Mo), tantalum It is desirable to form it with a conductive material such as tungsten (W) or titanium (Ti). Note that for the wiring and electrodes, when aluminum is used, since aluminum alone has problems such as low heat resistance and being prone to corrosion , it is preferably formed in combination with a heat-resistant conductive material .

[0029] The heat-resistant conductive material can be formed of an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), an alloy containing the above-described elements as components, an alloy combining the above-described elements, or a nitride containing the above-described elements as components. A film made of these heat-resistant conductive materials and aluminum (or copper) may be laminated to form wiring or electrodes. In addition, the gate electrode layer 202 can also be selectively formed on the substrate 200 using a droplet discharge method, a screen printing method, or the like.

[0030] The gate insulating layer 204 can be formed of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or the like. Also , these films may be laminated and provided. These films can be formed to have a film thickness of 5

[0031] 0 nm or more and 250 nm or less using a sputtering method or the like. For example, as the gate insulating layer 204 , a silicon oxide film can be formed to a thickness of 200 nm by a sputtering method. , these films may be laminated and provided. These films can be formed to have a film thickness of 5 0 nm or more and 250 nm or less using a sputtering method or the like. For example, as the gate insulating layer 204 , a silicon oxide film can be formed to a thickness of 200 nm by a sputtering method.

[0032] In this specification, silicon oxynitride means that, in terms of its composition, the oxygen content is higher than the nitrogen content, and preferably, by the Rutherford backscattering spectrometry (RBS: Ruthe ford backscattering spectrometry (RBS: Ruthe Rutherford Backscattering Spectrometry) and hydrogen forward scattering method (HFS: Hydrogen Forwardscattering Spect ometry), when measured using, the concentration range is 50 to 70 atomic % oxygen, nitrogen is 0.5 to 15 atomic %, silicon is 25 to 35 atomic %, and hydrogen is 0.1 to 10 atomic %. The term "silicon oxynitride" refers to a material having a higher nitrogen content than oxygen in its composition, and preferably, when measured using RBS and HFS, the concentration range is 5 to 30 atomic % oxygen, 20 to 55 atomic % nitrogen, 25 to 3 5 atomic % silicon, and 10 to 30 atomic % hydrogen. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic %, the content ratios of nitrogen, oxygen, silicon, and hydrogen are within the above ranges.

[0033] Next, a source electrode layer 206a and a drain electrode layer 206b are formed on the gate insulating layer 204 (see FIG. 2(B)).

[0034] The source electrode layer 206a and the drain electrode layer 206b can be formed by forming a conductive layer on the gate insulating layer 204 and then etching the conductive layer using photolithography. Here, as an example, a case is shown where a part of the source electrode layer 206a and the drain electrode layer 2 06b overlaps the gate electrode layer 202 via the gate insulating layer 204.

[0035] The source electrode layer 206a and the drain electrode layer 206b can be formed using a sputtering method, a vacuum evaporation method, or the like. and can be formed of a metal containing an element selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), an alloy containing the above elements as components, or a material composed of a nitride or the like containing the above elements as components. For example, the source electrode layer 206a and the drain electrode layer 206b can be formed with a single-layer structure of a molybdenum film or a titanium film. Also, the source electrode layer 206a and the drain electrode layer 206b may be formed with a laminated structure. For example, a laminated structure of an aluminum film and a titanium film can be used. Further, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated in this order

[0036] may be used. Also, a three-layer structure in which a molybdenum film, an aluminum film, and a molybdenum film are laminated in this order may be used. As the aluminum film used in these laminated structures, an aluminum (Al-Nd) film containing neodymium may be used. Further, the source electrode layer 206a and the drain electrode layer 206b may have a single-layer structure of an aluminum film containing silicon.

[0037] Note that the source electrode layer 206a and the drain electrode layer 206b can also be selectively formed on the substrate 200 using a droplet discharge method, a screen printing method, or the like.

[0038] In FIG. 2(B), the formed source electrode layer 206a functions as the source of the transistor, and the drain electrode layer 206b functions as the drain of the transistor. Note that depending on the driving method of the transistor, the source electrode layer 206a may function as the drain, and the drain electrode layer 206b may function as the source. ​

[0039] Next, a gate insulating film is formed in the region between the source electrode layer 206a and the drain electrode layer 206b. By performing an etching process on the upper layer of the edge layer 204 (exposed gate insulating layer 204), A recess 207 is formed in the gate insulating layer 204 (see FIG. 2(C)).

[0040] By performing etching treatment, the source electrode layer 206a and the drain electrode layer 206b are The thickness t2 of the gate insulating layer 204 located in the region between the gate electrode layer 202 and the source electrode layer 203 is set to t1. The gate insulating layer 204 and the gate electrode layer 202 are disposed between the electrode layer 206a and the drain electrode layer 206b. The thickness t1 of the gate insulating layer 204 provided between the electrode layers 206b can be made smaller than the thickness t1 of the gate insulating layer 204 provided between the electrode layers 206b. Preferably, the thickness t2 of the gate insulating layer 204 is set to 1 / 5 to 4 / 5 (t2 =t1 / 5~4t1 / 5).

[0041] The etching process includes plasma treatment using inert gas and / or reactive gas, A hot etching process or the like can be used.

[0042] In addition, in the etching treatment, the source electrode layer 206a and the drain electrode layer 206b are In addition, the source electrode layer 206a and the drain electrode layer 20 The etching of the gate insulating layer 204 was performed using the photomask used in forming the gate insulating layer 6b (FIG. 2(B)). In this case, the source electrode layer 206a and the drain electrode layer 206 The gate insulating layer 204 that does not overlap with b is etched.

[0043] By performing an etching process, the thickness of the gate insulating layer 204 is made to have different values in each region. At the same time, impurities adhering to the surface of the exposed gate insulating layer 204 and the surface layer portion incorporating impurity elements can be removed (see FIG. 2(C)). (See FIG. 2(C)).

[0044] Next, an oxide semiconductor layer 209 is formed so as to cover the gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206b (see FIG. 2(D)). (See FIG. 2(D)).

[0045] The oxide semiconductor layer 209 can be formed of an In-Ga-Zn-O-based non-single crystal film. For example, the oxide semiconductor layer 209 can be formed by a sputtering method using an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O3 :ZnO = 1:1:1). As sputtering conditions, for example, the distance between the substrate 200 and the target is 30 mm to 500 mm, the pressure is 0.1 Pa to 2.0 Pa, the DC (direct current) power supply is 0.25 kW to 5. 0 kW, the temperature is 20°C to 100°C, and the atmosphere can be an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of argon and oxygen. (See FIG. 2(D)).

[0046] Note that using a pulsed DC (direct current) power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. Further, after performing the above-described plasma treatment, by forming the oxide semiconductor layer 209 without exposing it to the atmosphere, it is possible to suppress the adhesion of dust and moisture to the interface between the gate insulating layer 204 and the oxide semiconductor layer 209. Also, the film thickness of the oxide semiconductor layer 209 may be about 5 nm to 200 nm. (See FIG. 2(D)).

[0047] As the above-described sputtering method, an RF sputtering method using a high-frequency power supply for the sputtering power supply, a DC sputtering method using a direct current power supply, and a pulsed DC sputtering method in which a pulsed DC bias is applied can be used. etc. can be used.

[0048] Also, when plasma processing is used as the etching process, it is preferable to continuously perform the plasma processing and the formation of the oxide semiconductor layer 209 within the same chamber. By forming the oxide semiconductor layer 209 without exposing the surfaces of the gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206b to the atmosphere, the adhesion of impurities to the surfaces of the gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206b, and the formation of an oxide film or the like can be suppressed.

[0049] Note that in this embodiment, the case where an oxide semiconductor layer is used as the semiconductor layer that becomes the channel formation region of the thin film transistor 250 is shown, but the applicable semiconductor layer is not limited to this. Other semiconductor layers such as a semiconductor layer using an organic semiconductor material can also be used. In addition to the In-Ga-Zn-O-based amorphous film, as the semiconductor layer, an oxide semiconductor containing at least one of indium, gallium, and zinc, such as ZnO, IZO, ITO , or an oxide semiconductor such as SnO, or a compound semiconductor such as SiGe or GaAs may be used.

[0050] Next, the oxide semiconductor layer 209 is etched to form an island-shaped oxide semiconductor layer 210 ( see Fig. 2(E)).

[0051] Through the above steps, a thin film transistor 250 using the oxide semiconductor layer 210 as the channel formation region can be formed.

[0052] Also, after forming the oxide semiconductor layer 210, at 100°C to 600°C, typically 200°C to It is preferable to perform a heat treatment at 400 °C. For example, a heat treatment can be performed at 350 °C for 1 hour in a nitrogen atmosphere. By this heat treatment, atomic-level rearrangement of the In—Ga— Zn—O-based oxide semiconductor that constitutes the island-shaped oxide semiconductor layer 210 is carried out. This heat treatment (including photo annealing, etc.) is important in that it can release the strain that inhibits the movement of carriers in the island-shaped oxide semiconductor layer 210. Note that the timing of performing the above heat treatment is not particularly limited as long as it is after the formation of the oxide semiconductor layer 209.

[0053] In addition, an oxygen radical treatment may be performed on the island-shaped oxide semiconductor layer 210. By performing the oxygen radical treatment, a thin film transistor having the oxide semiconductor layer 210 as a channel formation region can be made normally off. Further, by performing the radical treatment, damage due to etching of the island-shaped oxide semiconductor layer 210 can be recovered. The radical treatment can be performed in an atmosphere such as O2, N2O, N2 containing oxygen, He, or Ar. Further, it may be performed in an atmosphere in which Cl2 or CF4 is added to the above atmosphere. Note that the radical treatment is preferably performed without applying a bias voltage to the substrate 200 side.

[0054] In addition, a protective insulating layer may be formed so as to cover the thin film transistor 250 including the oxide semiconductor layer 210, the source electrode layer 206a, the drain electrode layer 206b, and the like. As the protective insulating layer, a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film may be formed using a CVD method, a sputtering method, or the like.

[0055] After that, by forming various electrodes and wirings, a semiconductor device having the thin film transistor 250 is completed.

[0056] As described above, after forming the source electrode layer 206a and the drain electrode layer 206b, the exposed gate insulating layer 204 is subjected to an etching process, so that the film thickness t2 of the gate insulating layer 204 located between the source electrode layer 206a and the drain electrode layer 206b is made smaller than the film thickness t1 of the gate insulating layer 204 provided between the gate electrode layer 202 and the source electrode layer 206a and the film thickness t1 of the gate insulating layer 204 provided between the gate electrode layer 202 and the drain electrode layer 206b. As a result, the parasitic capacitance generated between the source electrode layer and the drain electrode layer and the gate electrode layer can be reduced, and the element characteristics can be improved.

[0057] (Embodiment 2) In this embodiment, a transistor configuration different from that of the above embodiment will be described with reference to FIG. 1(B).

[0058] The thin film transistor 260 shown in FIG. 1(B) is different from the thin film transistor 250 shown in FIG. 1(A) in that the source electrode layer 206a and the drain electrode layer 206b are tapered, and the upper ends of the source electrode layer 206a and the drain electrode layer 206b are provided with curved surfaces. Note that other structures (the positional relationship between the gate electrode layer 202, the gate insulating layer 204, the source electrode layer 206a, the drain electrode layer 206b, the oxide semiconductor layer 210, etc.) can be provided in the same manner as in FIG. 1 (A).

[0059] The source electrode layer 206a and the drain electrode layer 206b are tapered, and the source electrode layer 2 By providing the upper end portions of the drain electrode layer 206a and the drain electrode layer 206b to have curved surfaces, Oxides for the gate insulating layer 204, the source electrode layer 206a and the drain electrode layer 206b The coverage of the semiconductor layer 210 can be improved, and discontinuity can be suppressed. The thickness t of the gate insulating layer 204 located in the region between the drain electrode layer 206a and the drain electrode layer 206b 2 is a gate insulating layer provided below the source electrode layer 206a and the drain electrode layer 206b. Even if the thickness of the oxide semiconductor layer 210 is sufficiently small with respect to the thickness t1 of the oxide semiconductor layer 210, It can be effectively suppressed.

[0060] An example of a method for manufacturing the thin film transistor 260 shown in FIG. 1B will be described below with reference to FIG. Note that the manufacturing process in FIG. 3 is common to that in FIG. Therefore, in the following description, the overlapping parts will be omitted and only the differences will be explained. 3, the gate insulating layer 204 is etched using a plasma. This shows the case where processing is used.

[0061] First, a gate electrode layer 202 is formed on a substrate 200 having an insulating surface, and then the gate A gate insulating layer 204 is formed over the electrode layer 202 (see FIG. 3A). When the layer 202 is formed, the covering property of the gate insulating layer 204 to be formed later is improved and a step is prevented. In order to prevent this, the end of the gate electrode layer 202 is etched to have a tapered shape. For example, the taper angle θ1 is preferably 20° or more and less than 90°, and more preferably 30° or more. It is preferable that the taper angle be 80° or less. A layer having a perforated shape (here, the gate electrode layer 202) is formed in a cross-sectional direction (the surface of the substrate 200). When observed from a plane orthogonal to the plane), the inclination angle on the inner side of the layer formed by the side surface and the bottom surface of the layer is shown. That is, it corresponds to the angle of the lower end of the gate electrode layer 202 in contact with the substrate 200 when observed from the cross-sectional direction.

[0062] Regarding the materials and manufacturing methods of the gate electrode layer 202 and the gate insulating layer 204, reference can be made to Embodiment 1.

[0063] Next, a source electrode layer 206a and a drain electrode layer 206b are formed on the gate insulating layer 204 (see Fig. 3(B)). Regarding the materials and manufacturing methods of the source electrode layer 206a and the drain electrode layer 206b, reference can be made to Embodiment 1.

[0064] Next, an etching process is performed on the gate insulating layer 204. Here, plasma is generated in the chamber where the substrate 200 is installed, and the plasma 208 is applied to the surfaces of the exposed gate insulating layer 204, source electrode layer 206 a and drain electrode layer 206b to form recesses 207 in the gate insulating layer 204 (see Fig. 3(C)).

[0065] The plasma treatment can be performed, for example, by introducing an inert gas such as argon (Ar) gas into a chamber in a vacuum state and applying a bias voltage to the object to be processed (here, the substrate 200) to make it in a plasma state. When Ar gas is introduced into the chamber, electrons and Ar positive ions exist in the plasma, and the Ar positive ions are accelerated in the cathode direction (substrate 200 side). The accelerated Ar positive ions collide with the surfaces of the gate insulating layer 204, source electrode layer 2 06a and drain electrode layer 206b formed on the substrate 200, causing the surface to be sputtered. ​​​​​​​​Etched, the surfaces of the gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206 b can be etched. Such plasma processing is sometimes referred to as "reverse sputtering" .

[0066] By applying a bias voltage to the substrate 200 side and performing plasma processing, sputter etching of the surfaces of the gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206b can be effectively performed.

[0067] Also, when irregularities are formed on the surface of the gate insulating layer 204, by performing plasma processing , the convex portions of the gate insulating layer 204 are preferentially sputter-etched, and the flatness of the surface of the gate insulating layer 204 can be improved.

[0068] Also, as the gas used in the above plasma processing, helium gas may be used instead of argon gas. Also, it may be performed in an atmosphere in which oxygen, hydrogen, nitrogen, etc. are added to an argon atmosphere. Also, it may be performed in an atmosphere in which Cl2, CF4, etc. are added to an argon atmosphere.

[0069] For example, in this embodiment, plasma processing can be performed using a sputtering apparatus as shown in FIG. 4 .

[0070] The sputtering apparatus shown in FIG. 4 has a first electrode 191 for holding an object to be processed 195 (here, the substrate 2 00) and a second electrode 192 facing it provided in a chamber 190. Also , the first electrode 191 is connected to an RF power supply (high-frequency power supply) 197, and the second electrode 192 is connected to an RF power supply 198 and a DC power supply 199. The first electrode 191 and the RF power supply 19 ​​Between the first electrode 191 and the second electrode 192, and between the second electrode 192 and the RF power supply 198, matching boxes 193 and 194 for impedance matching are respectively provided. When performing plasma processing (also called reverse sputtering) on the object to be processed 195 using the sputtering apparatus shown in FIG. 4, an inert gas such as argon gas is introduced from the inlet 196, and a high-frequency voltage is applied to the first electrode 191 to generate an inert gas plasma between the first electrode 191 and the second electrode 192, and a negative self-bias is generated on the side of the object to be processed 195 provided on the first electrode 191 (in a state where a bias voltage is applied), so that the cations in the plasma are accelerated and collided with the object to be processed 195. At this time, if irregularities are formed on the surface of the gate insulating layer 204, the convex portions are preferentially sputter-etched, and the surface of the gate insulating layer 204 can be planarized.

[0071] When performing plasma processing (also called reverse sputtering) on the object to be processed 195 using the sputtering apparatus shown in FIG. 4, an inert gas such as argon gas is introduced from the inlet 196, and a high-frequency voltage is applied to the first electrode 191 to generate an inert gas plasma between the first electrode 191 and the second electrode 192, and a negative self-bias is generated on the side of the object to be processed 195 provided on the first electrode 191 (in a state where a bias voltage is applied), so that the cations in the plasma are accelerated and collided with the object to be processed 195. At this time, if irregularities are formed on the surface of the gate insulating layer 204, the convex portions are preferentially sputter-etched, and the surface of the gate insulating layer 204 can be planarized. When performing plasma processing (also called reverse sputtering) on the object to be processed 195 using the sputtering apparatus shown in FIG. 4, an inert gas such as argon gas is introduced from the inlet 196, and a high-frequency voltage is applied to the first electrode 191 to generate an inert gas plasma between the first electrode 191 and the second electrode 192, and a negative self-bias is generated on the side of the object to be processed 195 provided on the first electrode 191 (in a state where a bias voltage is applied), so that the cations in the plasma are accelerated and collided with the object to be processed 195. At this time, if irregularities are formed on the surface of the gate insulating layer 204, the convex portions are preferentially sputter-etched, and the surface of the gate insulating layer 204 can be planarized. 191 to generate an inert gas plasma between the first electrode 191 and the second electrode 192, and a negative self-bias is generated on the side of the object to be processed 195 provided on the first electrode 191 (in a state where a bias voltage is applied), so that the cations in the plasma are accelerated and collided with the object to be processed 195. At this time, if irregularities are formed on the surface of the gate insulating layer 204, the convex portions are preferentially sputter-etched, and the surface of the gate insulating layer 204 can be planarized. 191 to generate an inert gas plasma between the first electrode 191 and the second electrode 192, and a negative self-bias is generated on the side of the object to be processed 195 provided on the first electrode 191 (in a state where a bias voltage is applied), so that the cations in the plasma are accelerated and collided with the object to be processed 195. At this time, if irregularities are formed on the surface of the gate insulating layer 204, the convex portions are preferentially sputter-etched, and the surface of the gate insulating layer 204 can be planarized. 191 to generate an inert gas plasma between the first electrode 191 and the second electrode 192, and a negative self-bias is generated on the side of the object to be processed 195 provided on the first electrode 191 (in a state where a bias voltage is applied), so that the cations in the plasma are accelerated and collided with the object to be processed 195. At this time, if irregularities are formed on the surface of the gate insulating layer 204, the convex portions are preferentially sputter-etched, and the surface of the gate insulating layer 204 can be planarized. 191 to generate an inert gas plasma between the first electrode 191 and the second electrode 192, and a negative self-bias is generated on the side of the object to be processed 195 provided on the first electrode 191 (in a state where a bias voltage is applied), so that the cations in the plasma are accelerated and collided with the object to be processed 195. At this time, if irregularities are formed on the surface of the gate insulating layer 204, the convex portions are preferentially sputter-etched, and the surface of the gate insulating layer 204 can be planarized. 191 to generate an inert gas plasma between the first electrode 191 and the second electrode 192, and a negative self-bias is generated on the side of the object to be processed 195 provided on the first electrode 191 (in a state where a bias voltage is applied), so that the cations in the plasma are accelerated and collided with the object to be processed 195. At this time, if irregularities are formed on the surface of the gate insulating layer 204, the convex portions are preferentially sputter-etched, and the surface of the gate insulating layer 204 can be planarized. 191 to generate an inert gas plasma between the first electrode 191 and the second electrode 192, and a negative self-bias is generated on the side of the object to be processed 195 provided on the first electrode 191 (in a state where a bias voltage is applied), so that the cations in the plasma are accelerated and collided with the object to be processed 195. At this time, if irregularities are formed on the surface of the gate insulating layer 204, the convex portions are preferentially sputter-etched, and the surface of the gate insulating layer 204 can be planarized.

[0072] When forming a film (sputter deposition) on the object to be processed 195 using the sputtering apparatus shown in FIG. 4, a target composed of the material to be formed into a film is installed on the second electrode 192 side, and a DC voltage or a high-frequency voltage is applied to the second electrode 192 to generate a plasma between the first electrode 191 and the second electrode 192, and the cations in the plasma are accelerated and collided with the target. When forming a film (sputter deposition) on the object to be processed 195 using the sputtering apparatus shown in FIG. 4, a target composed of the material to be formed into a film is installed on the second electrode 192 side, and a DC voltage or a high-frequency voltage is applied to the second electrode 192 to generate a plasma between the first electrode 191 and the second electrode 192, and the cations in the plasma are accelerated and collided with the target. When forming a film (sputter deposition) on the object to be processed 195 using the sputtering apparatus shown in FIG. 4, a target composed of the material to be formed into a film is installed on the second electrode 192 side, and a DC voltage or a high-frequency voltage is applied to the second electrode 192 to generate a plasma between the first electrode 191 and the second electrode 192, and the cations in the plasma are accelerated and collided with the target. When forming a film (sputter deposition) on the object to be processed 195 using the sputtering apparatus shown in FIG. 4, a target composed of the material to be formed into a film is installed on the second electrode 192 side, and a DC voltage or a high-frequency voltage is applied to the second electrode 192 to generate a plasma between the first electrode 191 and the second electrode 192, and the cations in the plasma are accelerated and collided with the target.

[0073] Therefore, when forming a film on the object to be processed 195 after plasma processing, the object to be processed 195 can be continuously formed into a film on the object to be processed 195 using the sputtering method without exposing the object to be processed 195 to the atmosphere after plasma processing. Therefore, when forming a film on the object to be processed 195 after plasma processing, the object to be processed 195 can be continuously formed into a film on the object to be processed 195 using the sputtering method without exposing the object to be processed 195 to the atmosphere after plasma processing. Therefore, when forming a film on the object to be processed 195 after plasma processing, the object to be processed 195 can be continuously formed into a film on the object to be processed 195 using the sputtering method without exposing the object to be processed 195 to the atmosphere after plasma processing.

[0074] ​In addition, in this embodiment, the case where a bias voltage is applied to the substrate 200 side during plasma processing has been described. However, if a recess 207 can be formed in the gate insulating layer 204, plasma processing may be performed without applying a bias voltage. Also, since a recess 207 can be formed in the gate insulating layer 204, plasma processing may be performed without applying a bias voltage. In addition, by performing plasma processing, there is an advantage that impurities attached to the surface of the gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206b can be removed.

[0075] In addition, by performing plasma processing, there is an advantage that impurities attached to the surface of the gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206b can be removed. a and the surface of the drain electrode layer 206b have the advantage that impurities attached thereto can be removed. Yes.

[0076] Also, in FIG. 3, not only the gate insulating layer 204 but also the source electrode layer 206a and the drain electrode layer 206b are subjected to plasma processing, and the case where the ends of the source electrode layer 206a and the drain electrode layer 206b are tapered is shown. For example, it is preferable to form a shape such that the taper angle θ2 is 20° or more and less than 90°, preferably 30° or more and 80° or less. Here, the "taper angle θ2" refers to the inclination angle of the tip portion on the inner side of the layer formed by the side surface and the bottom surface of the layer having a tapered shape (here, the source electrode layer 206a or the drain electrode layer 206b) when observed from the cross-sectional direction (a plane perpendicular to the surface of the substrate 200). That is, it corresponds to the angle of the lower end portion of the source electrode layer 206a or the drain electrode layer 206b in contact with the gate insulating layer 204 when observed from the cross-sectional direction. By forming the ends of the source electrode layer 206a and the drain electrode layer 206b into a tapered shape, the covering property of the oxide semiconductor layer formed later can be improved, and step discontinuity can be suppressed. Also, in FIG. 3, not only the gate insulating layer 204 but also the source electrode layer 206a and the drain electrode layer 206b are subjected to plasma processing, and the case where the ends of the source electrode layer 206a and the drain electrode layer 206b are tapered is shown. For example, it is preferable to form a shape such that the taper angle θ2 is 20° or more and less than 90°, preferably 30° or more and 80° or less. Here, the "taper angle θ2" refers to the inclination angle of the tip portion on the inner side of the layer formed by the side surface and the bottom surface of the layer having a tapered shape (here, the source electrode layer 206a or the drain electrode layer 206b) when observed from the cross-sectional direction (a plane perpendicular to the surface of the substrate 200). That is, it corresponds to the angle of the lower end portion of the source electrode layer 206a or the drain electrode layer 206b in contact with the gate insulating layer 204 when observed from the cross-sectional direction. By forming the ends of the source electrode layer 206a and the drain electrode layer 206b into a tapered shape, the covering property of the oxide semiconductor layer formed later can be improved, and step discontinuity can be suppressed. layers 206b are shown to be tapered. For example, it is preferable to form a shape such that the taper angle θ2 is 20° or more and less than 90°, preferably 30° or more and 80° or less. It is preferable to form a shape such that the taper angle θ2 is 20° or more and less than 90°, preferably 30° or more and 80° or less. Note that the "taper angle θ2" refers to the inclination angle of the tip portion on the inner side of the layer having a tapered shape (here, the source electrode layer 206a or the drain electrode layer 206b) when observed from the cross-sectional direction (a plane perpendicular to the surface of the substrate 200). That is, it corresponds to the angle of the lower end portion of the source electrode layer 206a or the drain electrode layer 206b in contact with the gate insulating layer 204 when observed from the cross-sectional direction. When observed from the cross-sectional direction, the inclination angle of the tip portion on the inner side of the layer formed by the side surface and the bottom surface of the layer having a tapered shape (here, the source electrode layer 206a or the drain electrode layer 206b) is shown. That is, it corresponds to the angle of the lower end portion of the source electrode layer 206a or the drain electrode layer 206b in contact with the gate insulating layer 204 when observed from the cross-sectional direction. 06a or the drain electrode layer 206b. By forming the ends of the source electrode layer 206a and the drain electrode layer 206b into a tapered shape, the covering property of the oxide semiconductor layer formed later can be improved, and step discontinuity can be suppressed. By forming the ends of the source electrode layer 206a and the drain electrode layer 206b into a tapered shape, the covering property of the oxide semiconductor layer formed later can be improved, and step discontinuity can be suppressed.

[0077] Also, in FIG. 3, not only the gate insulating layer 204 but also the source electrode layer 206a and the drain electrode layer 206b are subjected to plasma processing. By performing plasma treatment on the top layer 206b, the source electrode layer 206a and the drain electrode shows a case where the upper end of the layer 206b is formed to have a curved surface (to have a curved surface shape). For example, the radius of curvature R of the upper ends of the source electrode layer 206a and the drain electrode layer 206b is 1 / 100 or more and 1 / 2 or less of the thickness of the source electrode layer 206a and the drain electrode layer 206b after plasma treatment, preferably 3 / 100 or more and 1 / 5 or less of the thickness of the source electrode layer 206a and the drain electrode layer 206b.

[0078] For example, when the thickness of the source electrode layer 206a and the drain electrode layer 206b after plasma treatment is 1 00 nm, the radius of curvature R of the upper ends of the source electrode layer 206a and the drain electrode layer 206b is set to 1 nm or more and 50 nm or less, preferably 3 nm or more and 20 nm or less. Also, the radius of curvature R of the upper ends of the source electrode layer 206a and the drain electrode layer 206b may have a shape that continuously changes within this range. By providing the upper ends of the source electrode layer 206a and the drain electrode layer 206 b with a curved surface, the coverage of the oxide semiconductor layer formed later can be improved, and steps can be suppressed. In particular, when the thickness of the oxide semiconductor layer is thinner than the combined length (step difference) of the thickness of the source electrode layer 206a or the drain electrode layer 206b and the depth of the recessed portion, the effect of suppressing steps becomes remarkable. Also, when the ends of the source electrode layer 206a and the drain electrode layer 206b are tapered, it is preferable to form the recess 207 of the gate insulating layer 204 to have a tapered shape as well. In this case, the gate insulating layer 204 and the source electrode layer 206a or the drain electrode layer 206

[0079] When the ends of the source electrode layer 206a and the drain electrode layer 206b are tapered, it is preferable to form the recess 207 of the gate insulating layer 204 to have a tapered shape as well. In this case, the gate insulating layer 204 and the source electrode layer 206a or the drain electrode layer 206 b, Improve the coverage of the oxide semiconductor layer formed at the portion where it contacts b, and effectively prevent step discontinuities This can be achieved. Note that making the recess 207 of the gate insulating layer 204 have a tapered shape means that the inclination angle θ3 on the recess side (or the inclination angle on the recess side formed by the side surface and the bottom surface of the recess portion of the gate insulating layer 204) between the side surface and the bottom surface of the recess portion of the gate insulating layer 204 (or the inclination angle on the recess side formed by the side surface of the recess portion and the surface of the substrate 200) is 90° or more is what is meant.

[0080] In this way, by performing plasma treatment not only on the gate insulating layer 204 but also on the source electrode layer 206a and the drain electrode layer 206b, a recess 207 is formed in the gate insulating layer 204 while making the source electrode layer 206a and the drain electrode layer 206b have a tapered shape, and the upper ends of the source electrode layer 206a and the drain electrode layer 206b are provided so as to have a curved surface This can be achieved.

[0081] Next, after forming an oxide semiconductor layer so as to cover the gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206b, the oxide semiconductor layer is selectively etched to form the oxide semiconductor layer 210 (see FIG. 3(D)). Note that for the material and manufacturing method of the oxide semiconductor layer 210 reference can be made to Embodiment 1.

[0082] According to this embodiment, a semiconductor device composed of transistors having high characteristics can be provided Note that this embodiment can be used in appropriate combination with other embodiments

[0083] (Embodiment 3) In this embodiment, with reference to FIG. 5, the configuration of a transistor different from that of the above embodiment will be described

[0084] ​​​​ The thin film transistor 270 shown in Fig. 5(A) includes a first insulating layer 2 51 provided on the substrate 200, a second insulating layer 252 provided on the first insulating layer 251, and a source electrode layer 206a and a drain electrode layer 206b provided so as to overlap a part of the gate electrode layer 202 through the first insulating layer 251 and the second insulating layer 252, and an oxide semiconductor layer 210 provided in contact with the first insulating layer 251 located in the region between the source electrode layer 206a and the drain electrode layer 206b and provided on the source electrode layer 206a and the drain electrode layer 206b. That is, the second insulating layer 252 is removed in a region where it does not overlap the source electrode layer 206a and the drain electrode layer 206b in the region overlapping the gate electrode layer 202.

[0085] In this case, the insulating layer located between the source electrode layer 206a and the drain electrode layer 206b is composed of the first insulating layer 251, and the insulating layer provided between the gate electrode layer 202 and the source electrode layer 206a and the insulating layer provided between the gate electrode layer 202 and the drain electrode layer 206b are composed of a stacked structure of the first insulating layer 251 and the second insulating layer 252. Also, the film thickness t 2 of the insulating layer located between the source electrode layer 206a and the drain electrode layer 206b is smaller than the film thickness t1 of the insulating layer provided between the gate electrode layer 202 and the source electrode layer 206a and the insulating layer provided between the gate electrode layer 202 and the drain electrode layer 206b. In Fig. 5(A), the film thickness t1 corresponds to the value obtained by adding the film thicknesses of the first insulating layer 251 and the second insulating layer 252, and the film thickness t2 corresponds to the value of the film thickness of the first insulating layer 251.

[0086]

[0087] Thus, by adopting the configuration shown in FIG. 5(A), even when the source electrode layer 206a and the drain electrode layer 206b are provided via the first insulating layer 251 and the second insulating layer 252 on the gate electrode layer 202, and the oxide semiconductor layer 210 is provided on the source electrode layer 206a and the drain electrode layer 206b, the parasitic capacitance generated between the source electrode layer 206a and the drain electrode layer 206b and the gate electrode layer 202 can be reduced, the driving voltage of the transistor can be reduced, and the element characteristics can be improved.

[0088] Further, in the configuration shown in FIG. 5(A), it is preferable to use different materials for the first insulating layer 251 and the second insulating layer 252. Preferably, the dielectric constant of the material used for the first insulating layer 251 is higher than the dielectric constant of the material used for the second insulating layer 252. By making the dielectric constant of the first insulating layer 251 higher than the dielectric constant of the second insulating layer 252, the driving voltage of the transistor can be reduced, so that the influence of the parasitic capacitance generated between the source electrode layer 206a and the drain electrode layer 206b and the gate electrode layer 202 can be effectively reduced.

[0089] By using different materials for the first insulating layer 251 and the second insulating layer 252, the etching selectivity can be easily obtained when etching the second insulating layer 252. Note that the ability to obtain an etching selectivity means that, for example, when etching layer A and layer B, there is a sufficient difference between the etching rate of layer A and the etching rate of layer B. Further, the "etching rate" means the amount of etching per unit time (the amount of material to be etched). Therefore, "a large etching rate" means that it is easier to be etched. ​​​​​​​​​​​​It means etching, and "low etching rate" means that it is more difficult to be etched. It means.

[0090] Also, the film thickness of the first insulating layer 251 and the film thickness of the second insulating layer 252 can be appropriately set according to the materials used. For example, as the first insulating layer 251, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, or an insulating layer combining these films can be formed with a film thickness of 5 nm to 20 0 nm, and as the second insulating layer 252, an aluminum oxide film, a polyimide film, or an insulating layer combining these films can be formed with a film thickness of 5 nm to 200 nm. Also, when reducing the driving voltage and reducing the parasitic capacitance generated between the source electrode layer 206a and the drain electrode layer 206b and the gate electrode layer 202, it is preferable to make the film thickness of the first insulating layer 251 smaller than the film thickness of the second insulating layer 252. Note that the transistor shown in this embodiment is not limited to the configuration of FIG. 5(A). Alternatively, it may have the structures shown in FIGS.

[0091] 5(B) and 5(C). The thin film transistor 271 shown in FIG. 5(B) includes a first insulating layer 2

[0092] 51 provided on a substrate 200, a second insulating layer 252 provided on the first insulating layer 251, and a source electrode layer 206a and a drain electrode layer 206b provided so as to overlap a part of the gate electrode layer 202 through the first insulating layer 251 and the second insulating layer 252, and an oxide semiconductor layer 210 provided on the source electrode layer 206a and the drain electrode layer 206b and in contact with the second insulating layer 252 located in the region between the source electrode layer 206a and the drain electrode layer 206b. The thin film transistor 271 shown in FIG. 5(B) includes a first insulating layer 2 51 provided on a substrate 200, a second insulating layer 252 provided on the first insulating layer 251, and a source electrode layer 206a and a drain electrode layer 206b provided so as to overlap a part of the gate electrode layer 202 through the first insulating layer 251 The upper portion of the second insulating layer 252 located in the region between the source electrode layer 206a and the drain electrode layer 206b is removed.

[0093] That is, the second insulating layer 252 has a recess 207 in the region overlapping with the gate electrode layer 202 and an oxide semiconductor layer 210 is provided in the recess 207 of the second insulating layer 252.

[0094] The transistor 272 shown in Fig. 5(C) has, in the configuration shown in Fig. 5(A), a region where the second insulating layer 252 overlaps with the gate electrode layer 202, and is located between the source electrode layer 206a and the drain electrode layer 206b. In this region, the first insulating layer 251 has a recess 207 and an oxide semiconductor layer 210 is provided in the recess 207 of the first insulating layer 251.

[0095] Even when the configuration shown in Fig. 5(B) or Fig. 5(C) is adopted, the film thickness t2 of the insulating layer located between the source electrode layer 206a and the drain electrode layer 206b can be made smaller than the film thickness t1 of the insulating layer provided between the gate electrode layer 202 and the source electrode layer 206a and the film thickness t1 of the insulating layer provided between the gate electrode layer 202 and the drain electrode layer 20 6b.

[0096] Also, in Fig. 5, an example of the manufacturing method of the transistor 270 shown in Fig. 5(A) is shown with a two-layer structure of the first insulating layer 251 and the second insulating layer 252 as the insulating layers provided between the gate electrode layer 202 and the source electrode layer 206a and between the gate electrode layer 202 and the drain electrode layer 20 6b. However, the present embodiment is not limited to the two-layer structure and may be a three-layer structure.

[0097] Next, with reference to Fig. 6, an example of the manufacturing method of the transistor 270 shown in Fig. 5(A) will be described. Note that many parts of the manufacturing process in Fig. 6 are common to Fig. 1. Therefore ... , in the following description, the description of overlapping parts will be omitted, and different points will be described in detail. to do.

[0098] First, a gate electrode layer 202 is formed on a substrate 200 having an insulating surface, and then a first insulating layer 251 and a second insulating layer 252 are sequentially stacked on the gate electrode layer 202 (see Fig. 6(A)).

[0099] The first insulating layer 251 and the second insulating layer 252 can be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a tantalum oxide film, a hafnium oxide film, etc.

[0100] Also, it is preferable that the first insulating layer 251 and the second insulating layer 252 are formed using different materials. In particular, it is preferable to determine the material and film thickness so that the dielectric constant of the first insulating layer 251 is higher than that of the second insulating layer 252. For example, as the first insulating layer 251, a film formed by sequentially stacking a silicon oxide film and a silicon nitride film is formed with a thickness of 5 nm to 200 nm, and as the second insulating layer 252, a silicon oxide film is formed with a thickness of 5 nm to 200 nm. can be.

[0101] Also, as described above, as the first insulating layer 251, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, or an insulating layer formed by combining these films is formed with a film thickness of 5 nm to 200 nm, and as the second insulating layer 252, an aluminum oxide film, a polyimide film, or an insulating layer formed by combining these films can be formed with a film thickness of 5 nm to 200 nm.

[0102] Note that for the material and manufacturing method of the gate electrode layer 202, refer to Embodiment 1.​​​ It is possible.

[0103] Next, a source electrode layer 206a and a drain electrode layer 206b are formed on the second insulating layer 252 (see Fig. 6(B)). Note that, for the materials and manufacturing methods of the source electrode layer 206a and the drain electrode layer 206b, reference can be made to Embodiment 1.

[0104] Next, an etching process is performed on the second insulating layer 252 (the exposed second insulating layer 252) formed between the source electrode layer 206a and the drain electrode layer 206b, thereby removing the second insulating layer 252 and exposing the first insulating layer 251 (see Fig. 6(C)).

[0105] By performing the etching process, the film thickness t2 of the insulating layer (here, the first insulating layer 251) located in the region between the source electrode layer 206a and the drain electrode layer 206b becomes smaller than the film thickness t1 of the insulating layer provided between the gate electrode layer 202 and the source electrode layer 206a and the insulating layer provided between the gate electrode layer 202 and the drain electrode layer 206b (here, the stacked film of the first insulating layer 251 and the second insulating layer 252).

[0106] As the etching process, dry etching or wet etching can be used. For example, by performing dry etching using a mixed gas of C4F8 and Ar as the etching process, the etching selectivity between the silicon oxide film and the silicon nitride film can be taken, and the second insulating layer 252 can be effectively removed.

[0107] Note that, by controlling the conditions of the etching process, a part of the second insulating layer 252 formed between the source electrode layer 206a and the drain electrode layer 206b may be left remaining (Fig. 5( ​​​​​​​​​​​​ (corresponding to FIG. 5(B)), the second formed between the source electrode layer 206a and the drain electrode layer 206b Remove the insulating layer 252 and etch the upper part of the first insulating layer 251 to form a concave portion in the first insulating layer 251 (corresponding to FIG. 5(C)).

[0108] Also, in the etching process, the source electrode layer 206a and the drain electrode layer 206b can be used as a mask. In addition, the etching of the second insulating layer 252 can also be performed using the photomask used when forming the source electrode layer 206a and the drain electrode layer 206b (FIG. 6(B)). Next, after forming the oxide semiconductor layer 209 so as to cover the first insulating layer 251, the second insulating layer 252, the source electrode layer 206a, and the drain electrode layer 206b (see FIG. 6(D)), the oxide semiconductor layer 209 is selectively etched to form the oxide semiconductor layer 210 (see FIG. 6(E)). Note that for the material and manufacturing method of the oxide semiconductor layer 209 (oxide semiconductor layer 210), reference can be made to Embodiment 1. (corresponding to FIG. 6(D)), and then the oxide semiconductor layer 209 is selectively etched to form the oxide semiconductor layer 210 (see FIG. 6(E)). Regarding the material and manufacturing method of the oxide semiconductor layer 209 (oxide semiconductor layer 210), reference can be made to Embodiment 1. By this embodiment, a semiconductor device composed of transistors having high characteristics can be provided. Note that this embodiment can be used in appropriate combination with other embodiments.

[0109] Next, after forming the oxide semiconductor layer 209 so as to cover the first insulating layer 251, the second insulating layer 252, the source electrode layer 206a, and the drain electrode layer 206b (see FIG. 6(D)), the oxide semiconductor layer 209 is selectively etched to form the oxide semiconductor layer 210 (see FIG. 6(E)). (See FIG. 6(D)), and then the oxide semiconductor layer 209 is selectively etched to form the oxide semiconductor layer 210 (see FIG. 6(E)). (See FIG. 6(D)), and then the oxide semiconductor layer 209 is selectively etched to form the oxide semiconductor layer 210 (see FIG. 6(E)). (See FIG. 6(D)), and then the oxide semiconductor layer 209 is selectively etched to form the oxide semiconductor layer 210 (see FIG. 6(E)). By this embodiment, a semiconductor device composed of transistors having high characteristics can be provided. Note that this embodiment can be used in appropriate combination with other embodiments.

[0110] By this embodiment, a semiconductor device composed of transistors having high characteristics can be provided. Note that this embodiment can be used in appropriate combination with other embodiments. By this embodiment, a semiconductor device composed of transistors having high characteristics can be provided. Note that this embodiment can be used in appropriate combination with other embodiments. can be.

[0111] (Embodiment 4) In this embodiment, with reference to FIG. 7, a transistor configuration different from the above embodiment will be described. will be described.

[0112] The thin film transistor 280 shown in FIG. 7(A) includes a gate insulating layer 2 provided on a substrate 200 04 and is provided so as to overlap a part of the gate electrode layer 202 via the gate insulating layer 204 a source electrode layer 206a and a drain electrode layer 206b provided so as to overlap, and the source electrode layer 206a and the drain electrode layer 206b are provided via buffer layers 217a, 217b thereon and are in contact with the gate insulating layer 204 positioned between the source electrode layer 206a and the drain electrode layer 206b and has an oxide semiconductor layer 210. Further, the film thickness t2 of the gate insulating layer 204 positioned in the region between the source electrode layer 206a and the drain electrode layer 206b is smaller than the film thickness t1 of the gate insulating layer 204 provided between the gate electrode layer 202 and the source electrode layer 206a and the film thickness of the gate insulating layer 204 provided between the gate electrode layer 202 and the drain electrode layer 206b (see FIG. 7(A)).

[0113] That is, the transistor shown in FIG. 7(A) has a configuration in which buffer layers 217a, 217b are added to the transistor shown in FIG. 1(A).

[0114] The buffer layers 217a, 217b suppress oxidation of the surfaces of the source electrode layer 206a and the drain electrode layer 206b in the manufacturing process, and function as a layer for favorably making electrical connection between the oxide semiconductor layer 210 functioning as a channel formation region and the source electrode layer 206a and the drain electrode layer 206b.

[0115] As the buffer layers 217a, 217b, an oxide semiconductor layer having the same conductivity as or higher conductivity than that of the oxide semiconductor layer 210 can be used for formation. For example, the buffer layers 217a, 217b are formed of an In-Ga-Zn-O-based polycrystalline film, and the oxide semiconductor layer 2 10 can be formed of an In-Ga-Zn-O based polycrystalline film having a lower conductivity than the buffer layers 217a and 217b.

[0116] Thus, by providing the buffer layers 217a and 217b between the source electrode layer 206a and the drain electrode layer 206b and the oxide semiconductor layer 21 0, the contact resistance can be reduced , and the device characteristics of the transistor can be improved.

[0117] Next, with reference to FIG. 8, an example of a method for manufacturing the thin film transistor 280 shown in FIG. 7(A) will be described. Note that many parts of the manufacturing process in FIG. 8 are common to FIG. 1. Therefore, in the following description, the description of the overlapping parts will be omitted, and the different points will be described in detail.

[0118] First, a gate electrode layer 202 is formed on a substrate 200 having an insulating surface, and then a gate insulating layer 204 is formed on the gate electrode layer 202 (see FIG. 8(A)). Note that for the materials and manufacturing methods of the gate electrode layer 202 and the gate insulating layer 204, reference can be made to Embodiment 1.

[0119] Next, after a conductive layer 206 is formed on the gate insulating layer 204, an oxide semiconductor layer 217 is formed on the conductive layer 206 (see FIG. 8(B)).

[0120] The conductive layer 206 is formed of a metal containing an element selected from aluminum (Al), copper (Cu ), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), an alloy containing the above-described elements as components, or a nitride or the like containing the above-described elements as components by a sputtering method, a vacuum evaporation method, or the like. ​​​​​​ It can be formed.

[0121] For example, the conductive layer 206 can be formed with a single-layer structure of a molybdenum film or a titanium film. Also, the conductive layer 206 may be formed with a laminated structure. For example, it can be a laminated structure of an aluminum film and a titanium film. Moreover, it may be a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated in sequence. Also, it may be a three-layer structure in which a molybdenum film, an aluminum film, and a molybdenum film are laminated in sequence. In addition, as the aluminum film used in these laminated structures, an aluminum (Al-Nd) film containing neodymium may be used. Furthermore, the conductive layer 206 may have a single-layer structure of an aluminum film containing silicon. The oxide semiconductor layer 217 can be formed of an In-Ga-Zn-O-based non-single crystal film.

[0122] For example, the oxide semiconductor layer 217 can be formed on the conductive layer 206 by a sputtering method using an oxide semiconductor target (In2O3:Ga2O3:ZnO = 1:1:1) containing In, Ga, and Zn. For example, as the sputtering conditions, the distance between the substrate 200 and the target is 30 mm to 500 mm, the pressure is 0.1 Pa to 2.0 Pa, the DC power supply is 0.25 kW to 5.0 kW, the temperature is 20°C to 100°C, and the atmosphere can be an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of argon and oxygen. The oxide semiconductor layer 217 suppresses the oxidation of the surfaces of the source electrode layer and the drain electrode layer to be formed later, and also functions as a buffer for favorably making electrical connection between the oxide semiconductor layer that functions as a channel formation region to be formed later and the source electrode layer and the drain electrode layer.

[0123] functions as the A layer.

[0124] Also, in the process of FIG. 8(B), after forming the conductive layer 206, it is preferable to continuously form the oxide semiconductor layer 217 without exposing the conductive layer 206 to the atmosphere. By forming the oxide semiconductor layer 217 without exposing the conductive layer 206 to the atmosphere, it is possible to suppress the adhesion of impurities and the formation of an oxide film on the surface of the conductive layer 206, and thus reduce the contact resistance between the conductive layer 206 and the oxide semiconductor layer 217.

[0125] Also, it is preferable to use a gas that is difficult to oxidize the surface of the conductive layer 206 as the gas used during the film formation of the oxide semiconductor layer 217. For example, in the film formation conditions of the oxide semiconductor layer 217, increase the ratio of the flow rate of argon gas to the flow rate of oxygen gas (preferably, do not introduce oxygen gas). Specifically, the film formation of the oxide semiconductor layer 217 is carried out in an atmosphere of a noble gas such as argon or helium, or in an atmosphere where the oxygen gas is 10% or less and the noble gas is 90% or more. By reducing the ratio of the flow rate of oxygen gas to the flow rate of argon gas, it is possible to suppress the formation of an oxide film on the surface of the conductive layer 206. As a result, the contact resistance between the conductive layer 206 and the oxide semiconductor layer 217 can be reduced.

[0126] Also, by reducing the ratio of the flow rate of oxygen gas to the flow rate of argon gas, the conductivity of the obtained oxide semiconductor layer can be increased. In this case, the electrical connection between the oxide semiconductor layer that functions as the channel formation region to be formed later, and the source electrode layer and the drain electrode layer can be performed well.

[0127] ​​​​​​Next, using a photolithography method, the conductive layer 206 and the oxide semiconductor layer 217 are etched to form a source electrode layer 206a and a drain electrode layer 206b, and a buffer layer 2 17a and a buffer layer 217b.

[0128] Next, an etching process is performed on the gate insulating layer 2 04 (the exposed gate insulating layer 204) to form a recess 207 in the gate insulating layer 204 (see FIG. 8(C)).

[0129] Next, after forming an oxide semiconductor layer 209 so as to cover the gate insulating layer 204, the source electrode layer 206a, the drain electrode layer 206b, the buffer layer 217a and the buffer layer 217b (see FIG. 8(D)), the oxide semiconductor layer 209 is selectively etched to form an oxide semiconductor layer 210 (see FIG. 8(E)). At this time, a part of the buffer layer 217a and the buffer layer 217b is also etched. Note that for the material and manufacturing method of the oxide semiconductor layer 209 (oxide semiconductor layer 210), reference can be made to Embodiment 1.

[0130] Note that in FIG. 7(A), a configuration in which buffer layers 217a and 217b are provided for the transistor shown in FIG. 1(A) is shown, but the present invention is not limited to this. For example, as shown in FIG. 7(B), buffer layers 217a and 217b may be provided for the transistor shown in FIG. 5( A). In addition, buffer layers 217a and 217b may be provided for the configurations shown in FIGS. 1 (B), 5(B), and 5(C). (B), 5(B), and 5(C). This is also possible.

[0131] According to the present embodiment, a semiconductor device including transistors having high characteristics is provided. It is possible. Note that this embodiment can be used in appropriate combination with other embodiments. It can be.

[0132] (Embodiment 5) In this embodiment, a display device, which is an example of the usage form of a semiconductor device including a transistor, will be described with reference to the drawings in terms of its manufacturing process. Note that many parts of the manufacturing process shown in this embodiment are common to Embodiment 1. Therefore, in the following, the description of the overlapping parts will be omitted, and the different points will be described in detail. Note that in the following description, FIGS. 9 and 1 0 show cross-sectional views, and FIGS. 11 to 14 show top views.

[0133] First, wirings and electrodes (gate wiring including gate electrode layer 202, capacitor wiring 308, first terminal 321) are formed on a substrate 200 having an insulating surface (see FIGS. 9(A) and 11). .

[0134] The capacitor wiring 308 and the first terminal 321 can be formed simultaneously using the same material as the gate electrode layer 202. Note that for the material and manufacturing method of the gate electrode layer 202, reference can be made to Embodiment 1.

[0135] Next, a gate insulating layer 204 is formed on the gate electrode layer 202, and then a conductive layer 206 is formed on the gate insulating layer 204 (see FIG. 9(B)).

[0136] The conductive layer 206 is made of a metal containing an element selected from aluminum (Al), copper (Cu ), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), using a sputtering method, a vacuum evaporation method, or the like. An alloy containing the above elements as components, or a material composed of a nitride or the like containing the above elements can be formed.

[0137] For example, the conductive layer 206 can be formed with a single-layer structure of a titanium film. Also, the conductive layer 2 06 may be formed with a laminated structure, for example, a laminated structure of an aluminum film and a titanium film can be used. Also, a three-layer structure of a titanium film, an aluminum (Al-Nd) film containing neodymium, and a titanium film may be used. Further, the conductive layer 206 may have a single-layer structure of an aluminum film containing silicon film.

[0138] In FIG. 9(B), after forming the gate insulating layer 204, a contact hole 213 is formed in the gate insulating layer 204, and then the conductive layer 206 is formed so that the first terminal 3 21 and the conductive layer 206 are electrically connected.

[0139] Next, by etching the conductive layer 206, a source electrode layer 206a, a drain electrode layer 206b, a connection electrode 320, and a second terminal 322 are formed (see FIGS. 9(C) and 12).

[0140] The second terminal 322 can be configured to be electrically connected to a source wiring (source wiring including the source electrode layer 206a). Also, the connection electrode 320 can be configured to be directly connected to the first terminal 321 through a contact hole 213 formed in the gate insulating layer 204

[0141] Next, by performing an etching process on the gate insulating layer 204 (exposed gate insulating layer 204) provided between the source electrode layer 206a and the drain electrode layer 206b, the gate insulating layer 04 ​​​​A recess 207 is formed in 204 (see FIG. 9(D)).

[0142] By performing an etching process, the film thickness t2 of the gate insulating layer 204 located in the region between the source electrode layer 206a and the drain electrode layer 206b becomes smaller than the film thickness t1 of the gate insulating layer 204 provided between the gate electrode layer 202 and the source electrode layer 206a and the film thickness t1 of the gate insulating layer 204 provided between the gate electrode layer 202 and the drain electrode layer 206b.

[0143] As the etching process, plasma processing using an inert gas and / or a reactive gas, wet etching process, or the like can be used.

[0144] Here, a case where plasma processing is performed on the surfaces of the gate insulating layer 204, the source electrode layer 206a, the drain electrode layer 206b, the connection electrode 320, and the second terminal 322 is shown. In this case, the ends of the source electrode layer 206a, the drain electrode layer 206b, the connection electrode 3 20, and the second terminal 322 can be formed in a tapered shape with the upper ends having a curved surface. For the method of plasma processing, reference can be made to the above-described Embodiment 2.

[0145] Also, by reducing the film thickness of the gate insulating layer 204 formed on the capacitance wiring 308, the capacitance of the capacitance element formed later can be increased.

[0146] Next, an oxide semiconductor layer 209 is formed so as to cover the gate insulating layer 204, the source electrode layer 206a, the drain electrode layer 206b, the connection electrode 320, and the second terminal 322 (see FIG. 10(A)).

[0147] ​​​​It is preferable to perform plasma treatment and the formation of the oxide semiconductor layer 209 continuously within the same chamber. By performing plasma treatment and the formation of the oxide semiconductor layer 209 continuously, the adhesion of impurities to the surfaces of the gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206b, and the formation of an oxide film or the like on the surfaces of the source electrode layer 206a and the drain electrode layer 206b can be suppressed. Note that, regarding the material and manufacturing method of the oxide semiconductor layer 209, reference can be made to Embodiment 1.

[0148] Next, the oxide semiconductor layer 209 is selectively etched to form an island-shaped oxide semiconductor layer 210, thereby forming the thin film transistor 290 (see FIGS. 10(B) and 13).

[0149] Next, it is preferable to perform a heat treatment at 100°C to 600°C, typically 200°C to 400°C. For example, a heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. By this heat treatment, atomic-level rearrangement of the In-Ga-Zn-O-based non-single crystal film constituting the island-shaped oxide semiconductor layer 210 is performed. Since the strain that inhibits the movement of carriers is released by this heat treatment, the heat treatment (including photo annealing) here is effective. Note that the timing of performing the heat treatment is not particularly limited as long as it is after the formation of the oxide semiconductor layer 209, and for example, it may be performed after the formation of the pixel electrode.

[0150] In addition, an oxygen radical treatment may be performed on the exposed island-shaped oxide semiconductor layer 210. By performing the oxygen radical treatment, the thin film transistor having the island-shaped oxide semiconductor layer 210 as the channel formation region can be made normally-off. Also, by performing the radical treatment, This can recover the damage caused by the etching of the island-shaped oxide semiconductor layer 210. The radical treatment is preferably performed in an atmosphere of O2, N2O, preferably N2, He, Ar containing oxygen. Alternatively, it may be performed in an atmosphere in which Cl2 or CF4 is added to the above atmosphere.

[0151] Next, a protective insulating layer 340 covering the thin film transistor 290 is formed, and contact holes 325 reaching the drain electrode layer 206b, contact holes 326 reaching the connection electrode 320, and contact holes 327 reaching the second terminal 322 are selectively etched in the protective insulating layer 340 (see FIG. 10(C)).

[0152] Next, a transparent conductive layer 310 electrically connected to the drain electrode layer 206b, a transparent conductive layer 328 electrically connected to the connection electrode 320, and a transparent conductive layer 329 electrically connected to the second terminal 322 are formed (see FIGS. 10(D) and 14).

[0153] The transparent conductive layer 310 functions as a pixel electrode, and the transparent conductive layers 328 and 329 serve as electrodes or wirings used for connection to the FPC. More specifically, the transparent conductive layer 328 formed on the connection electrode 320 is used as a connection terminal electrode functioning as an input terminal of the gate wiring, and the transparent conductive layer 329 formed on the second terminal 322 can be used as a connection terminal electrode functioning as an input terminal of the source wiring.

[0154] In addition, a holding capacitor can be formed by the capacitance wiring 308, the gate insulating layer 204, the protective insulating layer 340, and the transparent conductive layer 310. In this case, the capacitance wiring 308 and the transparent conductive layer 310 serve as electrodes, and the gate insulating layer 204 and the protective insulating layer 340 serve as dielectrics. ​​​​​​​​​​​​

[0155] The transparent conductive layers 310, 328, and 329 are made of indium oxide (In2O3), indium oxide tin oxide alloy (In2O3―SnO2, abbreviated as ITO), indium oxide zinc oxide alloy (In2O3―ZnO), etc., and can be formed by using a sputtering method, a vacuum evaporation method, or the like. . For example, after forming the transparent conductive layer, a resist mask is formed on the transparent conductive layer, and the unnecessary portions are removed by etching to form the transparent conductive layers 310, 328, and 329.

[0156] By the above steps, elements such as a bottom gate type n-channel thin film transistor and a holding capacitor can be completed. Then, by arranging these elements in a matrix corresponding to individual pixels, one substrate for manufacturing an active matrix type display device can be obtained. In this specification, for convenience, such a substrate is referred to as an active matrix substrate.

[0157] When manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate may be fixed.

[0158] In addition, the configuration shown in this embodiment is not limited to the pixel configuration of FIG. 14. An example of another configuration is shown in FIG. 15. FIG. 15 shows a configuration in which a capacitive wiring 308 is not provided, the transparent conductive layer 31 0 functioning as a pixel electrode and the gate wiring 302 of an adjacent pixel are used as electrodes, and a holding capacitor is formed using the protective insulating layer 340 and the gate insulating layer 204 as dielectrics.

[0159] Note that this embodiment can be used in appropriate combination with other embodiments.

[0160] (Embodiment 6) In this embodiment, a thin film transistor is fabricated, and a semiconductor device (also referred to as a display device) having a display function is fabricated by using the thin film transistor in a pixel portion and further in a driver circuit. The case will be described. Further, a part or all of the driver circuit fabricated by the thin film transistor can be integrally formed on the same substrate as the pixel portion to form a system-on-panel.

[0161] A display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage within its scope. Specifically, it includes inorganic EL (Electro Luminescence), organic EL, etc. Further, a display medium such as electronic ink, whose contrast changes by an electric action, can also be applied.

[0162] In addition, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Further, regarding the element substrate corresponding to a form before the display element is completed in the process of fabricating the display device, the element substrate includes means for supplying current to the display element in each of a plurality of pixels. The element substrate may specifically be in a state where only the pixel electrode of the display element is formed, or may be in a state after forming a conductive layer to be the pixel electrode and before etching to form the pixel electrode

[0163] ​​​​​Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a connector, for example, an FPC (Flexible pr inted circuit) or a TAB (Tape Automated Bon ding) tape or a TCP (Tape Carrier Package) attached module, a module with a printed wiring board provided at the tip of the TAB tape or TCP, or a module in which an IC (integrated circuit) is directly mounted on a display element by the COG (Chip On Glass) method shall all be included in the display device. In this embodiment, an example of a liquid crystal display device is shown as a semiconductor device which is one form of the present invention. First, the appearance and cross-section of a liquid crystal display panel corresponding to one form of the semiconductor device will be described with reference to FIG. 16. FIGS. 16(A1)(A2) are top views of the panel in which reliable thin film transistors 4010,

[0164] 4011, and a liquid crystal element 4013 including an In-G a-Zn-O based non-single crystal film formed on a first substrate 4001 as a semiconductor layer are sealed with a sealing material 4005 between the second substrate 4006, and FIG. 16(B) corresponds to a cross-sectional view at M -N of FIGS. 16(A1)(A2). A sealing material 4005 is provided so as to surround a pixel portion 4002 and a scanning line driving circuit 4004 provided on the first substrate 4001. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are between the first substrate 4001, the sealing material 4005, and the second substrate 4006. A sealing material 4005 is provided so as to surround a pixel portion 4002 and a scanning line driving circuit 4004 provided on the first substrate 4001. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are between the first substrate 4001, the sealing material 4005, and the second substrate 4006.

[0165] A sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Thus, the pixel portion 4002 and the scanning line driving circuit 4004 are between the first substrate 4001, the sealing material 4005, and the second substrate 4006. A sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Thus, the pixel portion 4002 and the scanning line driving circuit 4004 are between the first substrate 4001, the sealing material 4005, and the second substrate 4006. It is sealed together with the liquid crystal layer 4008. Also, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealant 4005 on the first substrate 4001. The signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealant 4005 on the first substrate 4001. The signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealant 4005 on the first substrate 4001.

[0166] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 16(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 16(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method.

[0167] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 have a plurality of thin film transistors. In FIG. 16(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 401 1 included in the scanning line driving circuit 4004 are exemplified. Insulating layers 4020 and 40 21 are provided on the thin film transistors 4010 and 4011. Insulating layers 4020 and 4021 are provided on the thin film transistors 4010 and 4011.

[0168] As the thin film transistors 4010 and 4011, highly reliable thin film transistors including an In-Ga-Zn-O based non-single crystal film as a semiconductor layer can be applied. In the present embodiment As the thin film transistors 4010 and 4011, highly reliable thin film transistors including an In-Ga-Zn-O based non-single crystal film as a semiconductor layer can be applied. In the present embodiment the thin film transistors 4010 and 4011 are n-channel type thin film transistors.

[0169] Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is the second substrate 40 It is formed on 06. The overlapping part of the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are each provided with insulating layers 4032 and 4033 that function as alignment films, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033. The overlapping part corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are each provided with insulating layers 4032 and 4033 that function as alignment films. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are each provided with insulating layers 4032 and 4033 that function as alignment films, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are each provided with insulating layers 4032 and 4033 that function as alignment films, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033.

[0170] Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used. Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used.

[0171] Also, 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that spherical spacers can also be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between the pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealing material 4005. Also, 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that spherical spacers can also be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between the pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealing material 4005. Also, 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that spherical spacers can also be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between the pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealing material 4005. Also, 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that spherical spacers can also be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between the pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealing material 4005. Also, 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that spherical spacers can also be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between the pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealing material 4005. Also, 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that spherical spacers can also be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between the pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealing material 4005. Also, 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that spherical spacers can also be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between the pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealing material 4005.

[0172] Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. Yes, when the cholesteric liquid crystal is heated, just before the transition from the cholesteric phase to the isotropic phase is the phase that appears first. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 is used. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed as short as 10 μs to 100 μs, is optically isotropic, so no alignment treatment is required, and the viewing angle dependence is small .

[0173] Note that the liquid crystal display device shown in this embodiment is an example of a transmissive liquid crystal display device, but the liquid crystal display device can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

[0174] Also, in the liquid crystal display device shown in this embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and an example is shown in which a coloring layer and an electrode layer used for the display element are provided in this order on the inside. However, the polarizing plate may be provided on the inside of the substrate. Also, the laminated structure of the polarizing plate and the coloring layer is not limited to this embodiment, and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the coloring layer. Also, a light-shielding film that functions as a black matrix may be provided.

[0175] Also, in this embodiment, in order to reduce the surface unevenness of the thin film transistor and improve the reliability of the thin film transistor, the thin film transistor is covered with an insulating layer (insulating layer 4020, insulating layer 4021) that functions as a protective layer or a planarizing insulating layer . Note that the protective layer is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the atmosphere , and a dense film is preferable. The protective layer is made of a silicon oxide film or a silicon nitride film using a sputtering method . A single layer or a laminate of a recon film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, aluminum nitride, an aluminum oxynitride film, or an aluminum nitride oxide film may be formed. In this embodiment, an example of forming the protective layer by a sputtering method is shown, but it is not particularly limited and may be formed by various methods. Here, an insulating layer 4020 having a laminated structure is formed as the protective layer. Here, a silicon oxide film is formed as the first layer of the insulating layer 4020 by using a sputtering method. When a silicon oxide film is used as the protective layer, it is effective in preventing the aluminum film used as the source electrode layer and the drain electrode layer from peeling. In this embodiment, an example of forming the protective layer by a sputtering method is shown, but it is not particularly limited and may be formed by various methods.

[0176] Here, an insulating layer 4020 having a laminated structure is formed as the protective layer. Here, a silicon oxide film is formed as the first layer of the insulating layer 4020 by using a sputtering method. When a silicon oxide film is used as the protective layer, it is effective in preventing the aluminum film used as the source electrode layer and the drain electrode layer from peeling. Here, a silicon oxide film is formed as the first layer of the insulating layer 4020 by using a sputtering method. When a silicon oxide film is used as the protective layer, it is effective in preventing the aluminum film used as the source electrode layer and the drain electrode layer from peeling. When a silicon oxide film is used as the protective layer, it is effective in preventing the aluminum film used as the source electrode layer and the drain electrode layer from peeling.

[0177] Also, an insulating layer is formed as the second layer of the protective layer. Here, a silicon nitride film is formed as the second layer of the insulating layer 4020 by using a sputtering method. When a silicon nitride film is used as the protective layer, it is possible to suppress the intrusion of mobile ions such as sodium into the semiconductor region and the change of the electrical characteristics of the TFT. Also, an insulating layer is formed as the second layer of the protective layer. Here, a silicon nitride film is formed as the second layer of the insulating layer 4020 by using a sputtering method. When a silicon nitride film is used as the protective layer, it is possible to suppress the intrusion of mobile ions such as sodium into the semiconductor region and the change of the electrical characteristics of the TFT. When a silicon nitride film is used as the protective layer, it is possible to suppress the intrusion of mobile ions such as sodium into the semiconductor region and the change of the electrical characteristics of the TFT.

[0178] Also, after forming the protective layer, annealing (300 ° C to 400 ° C) of the semiconductor layer may be performed.

[0179] Also, an insulating layer 4021 is formed as a planarizing insulating layer. As the insulating layer 4021, a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that by laminating a plurality of insulating layers formed of these materials, the insulating layer As the insulating layer 4021, a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. As the insulating layer 4021, a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that by laminating a plurality of insulating layers formed of these materials, the insulating layer ​​​​4021 may be formed.

[0180] The siloxane-based resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. As substituents, the siloxane-based resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group. Further, the organic group may have a fluoro group. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When forming the insulating layer 4021 using a material liquid, annealing of the semiconductor layer (300°C to 400°C) may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device. The pixel electrode layer 4030 and the counter electrode layer 4031 can use a light-transmissive conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide.

[0181]

[0182]

[0183] The formed pixel electrode preferably has a light transmittance of 70% or more at a wavelength of 550 nm. Also, it is preferred that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω·cm or less.

[0184] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned.

[0185] Also, various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4 002 are supplied from the FPC4018.

[0186] In this embodiment, the connection terminal electrode 4015 is formed from the same conductive layer as the pixel electrode layer 40 30 of the liquid crystal element 4013, and the terminal electrode 4016 is formed from the same conductive layer as the source electrode layer and the drain electrode layer of the thin film transistors 4010, 40 11.

[0187] The connection terminal electrode 4015 is electrically connected to the terminal of the FPC4018 via the anisotropic conductive film 4019.

[0188] Also, in FIG. 16, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0189] FIG. 17 shows a liquid crystal display module corresponding to one form of a semiconductor device using a TFT substrate 2600 An example of the configuration is shown.

[0190] FIG. 17 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and a counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including a TFT and the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display region. The coloring layer 2605 is necessary for performing color display. In the case of the RGB system, coloring layers corresponding to red, green, and blue are provided corresponding to each pixel. Outside the TFT substrate 2600 and the counter substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Further, it may be laminated in a state having a retardation plate between the polarizing plate and the liquid crystal layer.

[0191] Liquid crystal display modules include TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Bend) mode, FLC (Ferroelectric Liquid) mode. ​​​​​​​​​​​​d Crystal mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. Liquid Crystal) mode, etc. can be used.

[0192] Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device. .

[0193] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0194] (Embodiment 7) In this embodiment, an electronic paper is shown as an example of a semiconductor device which is one form of the present invention.

[0195] FIG. 18 shows an active matrix type electronic paper as an example of a semiconductor device. As the thin film transistor 581 used in the semiconductor device, it can be manufactured in the same manner as the thin film transistors shown in the above Embodiments 1 to 3. For the thin film transistor 581 used in the semiconductor device, it can be manufactured in the same manner as the thin film transistors shown in the above Embodiments 1 to 3. transistor and can be manufactured in the same manner as the thin film transistors shown in the above Embodiments 1 to 3.

[0196] The electronic paper in FIG. 18 is an example of a display device using the twist ball display method. The twist ball display method is a method in which spherical particles painted white and black are arranged between a first electrode layer and a second electrode layer which are electrode layers used in a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control the orientation of the spherical particles and perform display. The twist ball display method is an electrode layer that uses spherical particles painted white and black as a display element, It is arranged between the first electrode layer and the second electrode layer, and by generating a potential difference between the first electrode layer and the second electrode layer, the orientation of the spherical particles is controlled to perform display.

[0197] The thin film transistor 581 provided on the substrate 580 is a thin film transistor of a bottom gate structure, and the source electrode layer or the drain electrode layer is electrically connected to the first electrode layer 587 through contact holes formed in the insulating layers 583, 5 84, 585. The first electrode is electrically connected through contact holes formed in the insulating layers 583, 584, 585. The first electrode Between the layer 587 and the second electrode layer 588, there are provided black regions 590a and white regions 590b and spherical particles 589 including cavities 594 filled with liquid around them . Around the spherical particles 589, there is provided a filler 595 such as resin (see Fig. 18). In Fig. 18, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode . The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581 . Using the common connection portion shown in the above embodiment, the second electrode layer 588 provided on the substrate 596 and the common potential line can be electrically connected through conductive particles arranged between a pair of substrates .

[0198] Also, instead of the twist ball, it is also possible to use an electrophoretic element. In that case, a transparent liquid, positively charged white fine particles, and negatively charged black fine particles are encapsulated in microcapsules having a diameter of about 10 μm to 200 μm. The microcapsules provided between the first electrode layer and the second electrode layer can display white or black when an electric field is applied by the first electrode layer and the second electrode layer, causing the white fine particles and the black fine particles to move in opposite directions . A display element applying this principle is an electrophoretic display element, which is generally called electronic paper . Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, it does not require a backlight, has low power consumption, and can recognize the display portion even in a dim place . Also, even when no power is supplied to the display portion, it is possible to hold the image once displayed. Therefore, a semiconductor device with a display function (simply a display device or a display device) from a radio wave transmission source . ​​​​Even when the (also referred to as a semiconductor device having a device) is kept at a distance, the displayed image can be saved. It becomes possible to do so.

[0199] As described above, a highly reliable electronic paper can be manufactured as a semiconductor device.

[0200] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0201] (Embodiment 8) In this embodiment, an example of a light-emitting display device is shown as a semiconductor device which is one form of the present invention. As the display element of the display device, here, a light-emitting element using electroluminescence is shown. The light-emitting element using electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element. The organic EL element is such that when a voltage is applied to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element depending on its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism utilizes a donor-acceptor level using a donor level and an acceptor level. It is called.

[0202] When a voltage is applied to the light-emitting element, electrons and holes are respectively injected into a layer containing a light-emitting organic compound from a pair of electrodes, and a current flows. And when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. It is called.

[0203] The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism utilizes a donor-acceptor level using a donor level and an acceptor level. It is acceptor recombination type light emission. The thin film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers, and further sandwiched between electrodes, and the light emission mechanism is localized light emission that utilizes inner shell electron transition of metal ions. Here, an organic EL element is used as the light emitting element for explanation.

[0204] FIG. 19 is a diagram showing an example of a pixel configuration applicable to digital time gradation driving as an example of a semiconductor device according to an aspect of the present invention.

[0205] The configuration and operation of a pixel applicable to digital time gradation driving will be described. Here, an n-channel type transistor using an oxide semiconductor layer (In-Ga-Zn-O based non-single crystal film) in the channel formation region is used as an example of using two in one pixel.

[0206] Pixel 6400 has a switching transistor 6401, a driving transistor 6402, a light emitting element 6404, and a capacitive element 6403. The switching transistor 64 01 has its gate connected to the scanning line 6406, its first electrode (one of the source electrode and the drain electrode) connected to the signal line 6405, and its second electrode (the other of the source electrode and the drain electrode) connected to the gate of the driving transistor 6402. The driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitive element 6403, its first electrode connected to the power supply line 640 7, and its second electrode connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The second electrode of the light emitting element 6404 (common electrode 6408) is set to a low power supply potential.

[0207] ​​​​​Note that the low power supply potential is a potential lower than the high power supply potential set on the power supply line 6407, and examples of the low power supply potential may include GND, 0V, etc. The potential difference between this high power supply potential and the low power supply potential is applied to the light emitting element 6404 to cause a current to flow through the light emitting element 6404 and make the light emitting element 6404 emit light. Therefore, the potentials of the high power supply potential and the low power supply potential are set so that the potential difference therebetween is equal to or greater than the forward threshold voltage of the light emitting element 6404. The low power supply potential is a potential that satisfies the high power supply potential, and for example, GND, 0V, etc. may be set as the low power supply potential. The potential difference between this high power supply potential and the low power supply potential is applied to the light emitting element 6404 to cause a current to flow through the light emitting element 6404 and make the light emitting element 6404 emit light. Therefore, the potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404 to cause a current to flow through the light emitting element 6404 and make the light emitting element 6404 emit light. The potential difference between the high power supply potential and the low power supply potential is set so that it is equal to or greater than the forward threshold voltage of the light emitting element 6404. Note that the capacitor element 6403 can also be omitted by substituting for the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, a capacitance may be formed between the channel region and the gate electrode.

[0208] Note that the capacitor element 6403 can also be omitted by substituting for the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, a capacitance may be formed between the channel region and the gate electrode. It may be formed between the channel region and the gate electrode.

[0209] Here, in the case of the voltage input voltage driving method, a video signal that causes the driving transistor 6402 to be in one of two states, either fully on or off, is input to the gate of the driving transistor 6402. That is, the driving transistor 6402 operates in the linear region. A video signal that causes the driving transistor 6402 to be in one of two states, either fully on or off, is input to the gate of the driving transistor 6402. That is, the driving transistor 6402 operates in the linear region. Since the driving transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied to the signal line 6405. Since the driving transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. (The power supply line voltage + the Vth of the driving transistor 6402) or higher is applied.

[0210] Also, when performing analog gradation driving instead of digital time gradation driving, the same pixel configuration as in FIG. 19 can be used by changing the signal input. When performing analog gradation driving, the same pixel configuration as in FIG. 19 can be used by changing the signal input.

[0211] When performing analog gradation driving, the gate of the driving transistor 6402 is connected to the light emitting element 6404. Apply a voltage equal to or higher than the Vth of the forward voltage + driving transistor 6402. The forward voltage of the light-emitting element 64 04 refers to the voltage for a desired luminance and includes at least the forward threshold voltage. Note that a video signal is input so that the driving transistor 6402 operates in the saturation region, allowing current to flow through the light-emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be made to flow through the light-emitting element 6404, enabling analog gradation driving. Note that the pixel configuration shown in FIG. 19 is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, or logic circuit may be added to the pixel shown in FIG. 19.

[0212] Next, the configuration of the light-emitting element will be described with reference to FIG. 20. Here, the case where the driving TFT is of the n type will be taken as an example to describe the cross-sectional structure of the pixel. The TFTs 7001, 7011, and 7021, which are driving TFTs used in the semiconductor devices shown in FIGS. 20(A), (B), and (C), can be fabricated in the same manner as the thin-film transistors shown in the above-described embodiments and are highly reliable thin-film transistors including an In-Ga-Zn-O-based non-single-crystalline

[0213] film as the semiconductor layer. For the light-emitting element, at least one of the anode or cathode may be transparent for extracting light. Thus, a thin-film transistor and a light-emitting element are formed on the substrate, and top emission for extracting light from the surface opposite to the substrate, bottom emission for extracting light from the surface on the substrate side, or emission from both the substrate side and the side opposite to the substrate is possible.

[0214] ​​​​​There is a light-emitting element with a double-sided emission structure that extracts light from the side surfaces, and the pixel configuration can be applied to light-emitting elements of any emission structure. It can also be applied to the light-emitting element.

[0215] The light-emitting element with the top emission structure will be described with reference to FIG. 20(A).

[0216] FIG. 20(A) shows a cross-sectional view of a pixel when the TFT 7001, which is a driving TFT, is of the n-type and the light emitted from the light-emitting element 7002 escapes to the anode 7005 side. In FIG. 20(A), the cathode 7003 of the light-emitting element 7002 and the driving TFT 7001 are electrically connected, and the light-emitting layer 7004 and the anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film with a low work function and can reflect light. For example, Ca, Al, MgAg, AlLi, etc. are desirable. And the light-emitting layer 7 004 can be composed of a single layer or a plurality of stacked layers. When composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are sequentially stacked on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or a light-transmitting conductive layer such as indium tin oxide added with silicon oxide may be used. either way is fine. When composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are sequentially stacked on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or a light-transmitting conductive layer such as indium tin oxide added with silicon oxide may be used. lead oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or a light-transmitting conductive layer such as indium tin oxide added with silicon oxide may be used. The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002.

[0217] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. Corresponds. In the case of the pixel shown in Fig. 20(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 as indicated by the arrow.

[0218] Next, the light-emitting element with a bottom emission structure will be described with reference to Fig. 20(B). When the driving TFT 7 011 is of the n-type and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013, a cross-sectional view of the pixel is shown. In Fig. 20(B), the cathode 7013 of the light-emitting element 7012 is formed on the light-transmissive conductive layer 7017 electrically connected to the driving TFT 7011, and the light-emitting layer 7014 and the anode 7015 are sequentially laminated on the cathode 7013. When the anode 7 015 is light-transmissive, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode. The cathode 7013 can be made of various materials as long as it is a conductive material with a low work function, similar to the case of Fig. 20(A). However, its film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, an aluminum film with a film thickness of 20 nm can be used as the cathode 7013. And the light-emitting layer 7 014 may be composed of a single layer or a plurality of layers laminated as in the case of Fig. 20(A). The anode 7015 does not necessarily need to transmit light, but as in Fig. 20(A), it can be formed using a light-transmissive conductive material. And the shielding film 7016 can be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin added with a black pigment can also be used.

[0219] The region where the cathode 7013 and the anode 7015 sandwich the light-emitting layer 7014 is the light-emitting element 7012. ​​​Corresponds to. In the case of the pixel shown in Fig. 20(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow.

[0220] Next, the light-emitting element with a double-sided emission structure will be described with reference to Fig. 20(C). Fig. 20(C) shows that on the light-transmissive conductive layer 7027 electrically connected to the driving TFT 7021, the cathode 7023 of the light-emitting element 7022 is formed, and the light-emitting layer 7024 and the anode 7025 are sequentially laminated on the cathode 7023. The cathode 7023, similar to the case of Fig. 20(A), can use various materials as long as they are conductive materials with a small work function. However, its film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024, similar to Fig. 20(A), can be composed of a single layer or can be configured such that a plurality of layers are laminated. The anode 70 25, similar to Fig. 20(A), can be formed using a light-transmissive conductive material that transmits light.

[0221] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 70 22. In the case of the pixel shown in Fig. 20(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrow.

[0222] Here, although the organic EL element is described as the light-emitting element, it is also possible to provide an inorganic EL element as the light-emitting element.

[0223] In this embodiment, a thin-film transistor (driving TFT) that controls the driving of the light-emitting element and ​Although an example in which the light-emitting element is electrically connected has been shown, the current between the driving TFT and the light-emitting element is A control TFT may be connected.

[0224] Note that the semiconductor device described in this embodiment mode is not limited to the configuration shown in FIG. Many variations are possible.

[0225] Next, the appearance and structure of a light-emitting display panel (also called a light-emitting panel) which corresponds to one embodiment of a semiconductor device will be described. The cross section will be described with reference to FIG. 21. FIG. 21(A) shows a cross section of a semiconductor device formed on a first substrate 4501. A highly reliable thin film transistor containing a non-single crystal In-Ga-Zn-O-based semiconductor layer The resistors 4509 and 4510 and the light emitting element 4511 are sealed between the second substrate 4506. FIG. 21(B) is a top view of the panel sealed with a material 4505. This corresponds to the cross-sectional view in HI.

[0226] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0227] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 21B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0228] The thin film transistors 4509 and 4510 are made of In-Ga-Zn-O non-single crystal films as semiconductor layers. In this embodiment, a highly reliable thin film transistor including the above-mentioned The thin film transistors 4509 and 4510 are n-channel thin film transistors.

[0229] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent layer The first electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The light emitting element 4511 is not rotated in accordance with the direction of the light to be extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0230] The partition 4520 is formed using an organic resin layer, an inorganic insulating layer, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0231] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. Either may be used.

[0232] A protective layer may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not penetrate into the light-emitting element 4511. As the protective layer, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0233] In addition, various signals and potentials applied to the signal line drive circuits 4503a and 4503b, the scanning line drive circuits 4504a and 4504b, or the pixel section 4502 are supplied from the FPCs 4518a and 4518b. b.

[0234] In this embodiment, the connection terminal electrode 4515 is formed of the same conductive layer as the first electrode layer 4517 of the light-emitting element 4511, and the terminal electrode 4516 is formed of the same conductive layer as the source electrode layer and the drain electrode layer of the thin film transistors 4509 and 4510.

[0235] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519.

[0236] The second substrate 4506 located in the light extraction direction from the light-emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0237] In addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used as the filler 4507, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EV ​ A (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler 4507 and.

[0238] Also, if necessary, a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), an optical film such as a color filter, etc. may be appropriately provided. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface irregularities and can reduce reflections can be performed.

[0239] The signal line driving circuits 4503a, 4503b, and the scanning line driving circuits 4504a, 4504b are implemented by a driving circuit formed of a single-crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line driving circuit, or a part thereof, or only the scanning line driving circuit, or a part thereof may be separately formed and implemented, and this embodiment is not limited to the configuration of FIG. 21.

[0240] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device.

[0241] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0242] (Embodiment 9) A semiconductor device according to one embodiment of the present invention can be applied as an electronic paper. The electronic paper can be used in electronic devices in any field as long as it can display information. For example, using the electronic paper, electronic books (e-books), posters, trains, etc. ​​​It can be applied to in-vehicle advertisements of vehicles, displays on various cards such as credit cards, etc. An example of an electronic device is shown in FIGS. 22 and 23.

[0243] FIG. 22(A) shows a poster 2631 made of electronic paper. When the advertising medium is a paper printout, the advertisement is replaced manually, but if electronic paper is used the advertisement display can be changed in a short time. Also, a stable image can be obtained without the display being distorted. Note that the poster may be configured to be able to wirelessly transmit and receive information.

[0244] Also, FIG. 22(B) shows an in-vehicle advertisement 2632 in a vehicle such as a train. When the advertising medium is a paper printout, the advertisement is replaced manually, but if electronic paper is used the advertisement display can be changed in a short time without much manpower. Also, a stable image can be obtained without the display being distorted. Note that the in-vehicle advertisement may be configured to be able to wirelessly transmit and receive information.

[0245] Also, FIG. 23 shows an example of an electronic book 2700. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and opening and closing operations can be performed with the shaft portion 2711 as an axis. With such a configuration, it is possible to perform operations like those of a paper book

[0246] A display portion 2705 is incorporated in the housing 2701, and a display portion 2707 is incorporated in the housing 2703. The display portion 2705 and the display portion 2707 are configured to display consecutive screens ​​It may also be configured to display different screens. By configuring it to display different screens, for example, text can be displayed on the display unit on the right side (display unit 2705 in FIG. 23), and an image can be displayed on the display unit on the left side (display unit 2707 in FIG. 23).

[0247] In addition, FIG. 23 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, in the housing 2 701, a power supply 2721, operation keys 2723, a speaker 2725, and the like are provided. Pages can be sent by the operation keys 2723. Note that a key board, a pointing device, or the like may be provided on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (such as headphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion part, and the like may be provided. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary.

[0248] In addition, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is also possible to purchase and download desired book data and the like from an electronic book server.

[0249] (Embodiment 10) A semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (including gaming machines). As the electronic devices, for example, a television device (also referred to as a TV or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a mobile device, etc. (also referred to as a TV receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a mobile device, etc. Examples include large game machines such as game consoles, mobile information terminals, audio playback devices, and pachinko machines. are mentioned.

[0250] FIG. 24(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display an image. Here, a configuration is shown in which the housing 9601 is supported by a stand 9605.

[0251] The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control unit 9610. The operation keys 9609 provided in the remote control unit 9610 can be used to operate the channel and volume, and to operate the image displayed on the display unit 9603. It is also possible to provide a display unit 9607 for displaying information output from the remote control unit 9610 on the remote control unit 9610.

[0252] Note that the television device 9600 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts, and further, by connecting to a communication network via a modem, either wired or wirelessly, one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication can also be performed.

[0253] FIG. 24(B) shows an example of a digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and for example, images taken with a digital camera, etc. By displaying the acquired image data, it can function in the same way as a normal photo frame.

[0254] Note that the digital photo frame 9700 includes an operation unit, external connection terminals (such as USB terminals, terminals connectable to various cables such as USB cables), a recording medium insertion part, etc. It may be configured to include. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface because it improves the design. For example, an image data memory captured by a digital camera can be inserted into the recording medium insertion part of the digital photo frame to capture image data, and the captured image data can be displayed on the display unit 9703.

[0255] Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It can also be configured to capture and display desired image data wirelessly.

[0256] FIG. 25(A) shows a portable game machine, which is composed of two housings, a housing 9881 and a housing 9891, and is connected by a connecting part 9893 so as to be openable and closable. A display unit 9882 is incorporated in the housing 9881, and a display unit 9883 is incorporated in the housing 9891. Also, the portable game machine shown in FIG. 25(A) further includes a speaker unit 9884, a recording medium insertion part 988 6, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. ​​​Of course, the configuration of the portable gaming machine is not limited to the above, and it suffices to have a configuration including at least a semiconductor device, and other accessory equipment can be appropriately provided. The portable gaming machine shown in Fig. 25(A) has functions of reading programs or data recorded on a recording medium and displaying them on a display unit, and performing wireless communication with other portable gaming machines to share information. Note that the functions of the portable gaming machine shown in Fig. 25(A) are not limited to this, and it can have various functions.

[0257] Fig. 25(B) shows an example of a slot machine 9900 which is a large gaming machine. The slot machine 9900 has a display unit 9903 incorporated in a housing 9901. Also, the slot machine 9900 is provided with other operating means such as a start lever and a stop switch, a coin insertion slot, a speaker, etc.

[0258] Of course, the configuration of the slot machine 9900 is not limited to the above, and it suffices to have a configuration including at least a semiconductor device related to one embodiment of the present invention, and other accessory equipment can be appropriately provided.

[0259] Fig. 26(A) shows an example of a mobile phone 1000. The mobile phone 1000 includes, in addition to a display unit 1002 incorporated in a housing 1001, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, etc. The mobile phone 1000 shown in Fig. 26(A) can input information by touching the display unit 1002 with a finger or the like. Also, operations such as making a phone call or sending an email can be performed by touching the display unit 1002 with a finger or the like.

[0260] ​​​​​​​​​The screen of the display unit 1002 mainly has three modes. The first is the display mode mainly for displaying images, the second is the input mode mainly for inputting information such as characters. The third is the display + input mode in which the two modes of the display mode and the input mode are mixed.

[0261] For example, when making a call or creating an email, the display unit 1002 may be set to the character input mode mainly for character input, and an input operation on the characters displayed on the screen may be performed. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002.

[0262] Also, by providing a detection device having sensors for detecting inclination such as a gyro and an acceleration sensor inside the mobile phone 1000, the orientation (vertical or horizontal) of the mobile phone 1000 can be determined, and the screen display of the display unit 1002 can be automatically switched.

[0263] Also, the switching of the screen mode is performed by touching the display unit 1002 or operating the operation button 1003 of the housing 1001. Also, it can be switched according to the type of image displayed on the display unit 1002. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0264] Also, in the input mode, the signal detected by the optical sensor of the display unit 1002 is detected, and when there is no touch operation on the display unit 1002 for a certain period, the mode of the screen may be controlled to be switched from the input mode to the display mode.

[0265] The display unit 1002 can also function as an image sensor. For example, the display unit 10​​​​ By touching the palm or fingers on 02 and imaging palm prints, fingerprints, etc., personal authentication can be performed. In addition, if a backlight that emits near-infrared light or a light source for a sensor that emits near-infrared light is used for the display unit, finger veins, palm veins, etc. can also be imaged.

[0266] Figure 26(B) is also an example of a mobile phone. The mobile phone in Figure 26(B) has a display device 9410 including a housing 9411, a display unit 9412, and operation buttons 9413, and a communication device 9400 including operation buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light-emitting unit 9406 that emits light when receiving an incoming call in a housing 9401. The display device 9410 having a display function is detachably attachable to the communication device 9400 having a telephone function in two directions of the arrow. Therefore, it is possible to attach the short axes of the display device 9410 and the communication device 9400 to each other, or to attach the long axes of the display device 9410 and the communication device 9400 to each other. Further, when only the display function is required, the display device 9410 can be removed from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery.

Explanation of Reference Numerals

[0267] 190 Chamber 191 Electrode 192 Electrode 193 Matching Box 194 Matching Box 195 Object to be Processed 196 Inlet 197 RF Power Supply 198 RF Power Supply 199 DC Power Supply 200 Substrate 202 Gate electrode layer 204 Gate insulating layer 206 Conductive layer 207 Recess 208 Plasma 209 Oxide semiconductor layer 210 Oxide semiconductor layer 213 Contact hole 217 Oxide semiconductor layer 250 Thin film transistor 251 Insulating layer 252 Insulating layer 260 Thin film transistor 270 Thin film transistor 271 Thin film transistor 272 Thin film transistor 280 Thin film transistor 290 Thin film transistor 302 Gate wiring 308 Capacitance wiring 310 Transparent conductive layer 320 Connection electrode 321 Terminal 322 Terminal 325 Contact hole 326 Contact hole 327 Contact hole 328 Transparent conductive layer 329 Transparent conductive layer 340 Protective insulating layer 580 Substrate 581 Thin film transistor 583 Insulating layer 584 Insulating layer 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material 596 Substrate 1000 Mobile phone 1001 Housing 1002 Display unit 1003 Operation Button 1004 External Connection Port 1005 Speaker 1006 Microphone 206a Source Electrode Layer 206b Drain Electrode Layer 217a Buffer Layer 217b Buffer Layer 2600 TFT Substrate 2601 Opposite Substrate 2602 Sealing Material 2603 Pixel Section 2604 Display Element 2605 Coloring Layer 2606 Polarizing Plate 2607 Polarizing Plate 2608 Wiring Circuit Section 2609 Flexible Wiring Substrate 2610 Cold Cathode Tube 2611 Reflector 2612 Circuit Substrate 2613 Diffuser 2631 Poster 2632 In-vehicle Advertisement 2700 E-book 2701 Housing 2703 Housing 2705 Display Section 2707 Display Section 2711 Shaft Section 2721 Power Supply 2723 Operation Key 2725 Speaker 4001 Substrate 4002 Pixel Section 4003 Signal Line Driving Circuit 4004 Scanning Line Driving Circuit 4005 Sealing Material 4006 Substrate 4008 Liquid Crystal Layer 4010 Thin Film Transistor 4011 Thin Film Transistor 4013 Liquid Crystal Element 4015 Connection Terminal Electrode 4016 Terminal Electrode 4018 FPC 4019 Anisotropic Conductive Film 4020 Insulating Layer 4021 Insulating Layer 4030 Pixel Electrode Layer 4031 Counter Electrode Layer 4032 Insulating Layer 4033 Insulating Layer 4501 Substrate 4502 Pixel Portion 4505 Sealing Material 4506 Substrate 4507 Filling Material 4509 Thin Film Transistor 4510 Thin Film Transistor 4511 Light Emitting Element 4512 Electroluminescent Layer 4513 Electrode Layer 4515 Connection Terminal Electrode 4516 Terminal Electrode 4517 Electrode Layer 4519 Anisotropic Conductive Film 4520 Partition Wall 590a Black Region 590b White Region 6400 Pixel 6401 Switching Transistor 6402 Driving Transistor 6403 Capacitive Element 6404 Light Emitting Element 6405 Signal Line 6406 Scanning Line 6407 Power Supply Line 6408 Common Electrode 7001 TFT 7002 Light Emitting Element 7003 Cathode 7004 Light Emitting Layer 7005 Anode 7011 Driving TFT 7012 Light Emitting Element 7013 Cathode 7014 Light Emitting Layer 7015 Anode 7016 Masking Film 7017 Conductive Layer 7021 TFT for driving 7022 Light-emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive layer 9400 Communication device 9401 Housing 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting unit 9410 Display device 9411 Housing 9412 Display unit 9413 Operation button 9600 Television device 9601 Housing 9603 Display unit 9605 Stand 9607 Display unit 9609 Operation key 9610 Remote control operation unit 9700 Digital photo frame 9701 Housing 9703 Display unit 9881 Housing 9882 Display unit 9883 Display unit 9884 Speaker unit 9885 Operation key 9886 Recording medium insertion part 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Housing 9893 Connecting part 9900 Slot machine 9901 Housing 9903 Display unit 4503a Signal line drive circuit 4503b Signal line drive circuit 4504a Scanning line drive circuit 4504b Scanning line drive circuit 4518a FPC 4518b FPC

Claims

1. A liquid crystal display device having a first substrate, a second substrate, liquid crystal, and spacers, wherein the liquid crystal and the spacers are disposed between the first substrate and the second substrate, and having a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a third insulating layer, and a fourth conductive layer, wherein the first conductive layer has a region that functions as a gate electrode of a transistor, the first insulating layer has a region disposed above the first conductive layer, the second insulating layer has a region disposed above the first insulating layer, the second conductive layer has a region disposed above the second insulating layer, the second conductive layer has a region that functions as one of a source electrode or a drain electrode of the transistor, the third conductive layer has a region disposed above the second insulating layer, the third conductive layer has a region that functions as the other of the source electrode or the drain electrode of the transistor, the oxide semiconductor layer has a channel formation region of the transistor, the third insulating layer has a region disposed above the second conductive layer, a region disposed above the oxide semiconductor layer, and a region disposed above the third conductive layer, the fourth conductive layer has a region disposed above the third insulating layer, the fourth conductive layer has a region that functions as a pixel electrode, the second insulating layer has a first region, a second region, and a third region, wherein the first region does not overlap with the second conductive layer and does not overlap with the third conductive layer, the second region overlaps with the second conductive layer, the third region overlaps with the third conductive layer, the film thickness of the first region is thinner than the film thickness of the second region, the film thickness of the first region is thinner than the film thickness of the third region, in plan view, the first conductive layer has an overlap with the entire oxide semiconductor layer, and in plan view, the spacer has an overlap with the oxide semiconductor layer. A liquid crystal display device.

2. A liquid crystal display device having a first substrate, a second substrate, liquid crystal, and spacers, wherein the liquid crystal and the spacers are disposed between the first substrate and the second substrate, and having a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a third insulating layer, and a fourth conductive layer, The first conductive layer has a region that functions as a gate electrode of a transistor. The first insulating layer has a region disposed above the first conductive layer. The second insulating layer has a region disposed above the first insulating layer. The dielectric constant of the first insulating layer is higher than the dielectric constant of the second insulating layer. The second conductive layer has a region disposed above the second insulating layer. The second conductive layer has a region that functions as one of a source electrode or a drain electrode of the transistor. The third conductive layer has a region disposed above the second insulating layer. The third conductive layer has a region that functions as the other of the source electrode or the drain electrode of the transistor. The oxide semiconductor layer has a channel formation region of the transistor. The third insulating layer has a region disposed above the second conductive layer, a region disposed above the oxide semiconductor layer, and a region disposed above the third conductive layer. The fourth conductive layer has a region disposed above the third insulating layer. The fourth conductive layer has a region that functions as a pixel electrode. The second insulating layer has a first region, a second region, and a third region. The first region does not overlap with the second conductive layer and does not overlap with the third conductive layer. The second region overlaps with the second conductive layer. The third region overlaps with the third conductive layer. The film thickness of the first region is thinner than the film thickness of the second region. The film thickness of the first region is thinner than the film thickness of the third region. In plan view, the first conductive layer has an overlap with the entire oxide semiconductor layer. A liquid crystal display device, wherein in plan view, the spacer has an overlap with the oxide semiconductor layer.

3. A liquid crystal display device having a first substrate, a second substrate, liquid crystal, and spacers, wherein the liquid crystal and the spacers are disposed between the first substrate and the second substrate. The liquid crystal display device has a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a third insulating layer, and a fourth conductive layer. The first conductive layer has a region that functions as a gate electrode of a transistor. The first insulating layer has a region disposed above the first conductive layer. The second insulating layer has a region disposed above the first insulating layer. The second conductive layer has a region disposed above the second insulating layer. The second conductive layer has a region that functions as one of a source electrode or a drain electrode of the transistor. The third conductive layer has a region disposed above the second insulating layer. The third conductive layer has a region that functions as the other of the source electrode or the drain electrode of the transistor. The oxide semiconductor layer has a channel formation region of the transistor. The third insulating layer has a region disposed above the second conductive layer, a region disposed above the oxide semiconductor layer, and a region disposed above the third conductive layer. The fourth conductive layer has a region disposed above the third insulating layer. The fourth conductive layer has a region that functions as a pixel electrode. The second insulating layer has a first region, a second region, and a third region. The first region does not overlap with the second conductive layer and does not overlap with the third conductive layer. The second region overlaps with the second conductive layer. The third region overlaps with the third conductive layer. The film thickness of the first region is thinner than the film thickness of the second region. The film thickness of the first region is thinner than the film thickness of the third region. In plan view, the first conductive layer has an overlap with the entire oxide semiconductor layer. The fourth conductive layer is electrically connected to the third conductive layer through a contact hole provided in the third insulating layer. In plan view, the contact hole does not have an overlap with the first conductive layer. In plan view, the spacer has an overlap with the oxide semiconductor layer. A liquid crystal display device.

4. A liquid crystal display device having a first substrate, a second substrate, liquid crystal, and spacers, wherein the liquid crystal and the spacers are disposed between the first substrate and the second substrate. The liquid crystal display device has a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a third insulating layer, and a fourth conductive layer. The first conductive layer has a region that functions as a gate electrode of a transistor. The first insulating layer has a region disposed above the first conductive layer. The second insulating layer has a region disposed above the first insulating layer. The dielectric constant of the first insulating layer is higher than the dielectric constant of the second insulating layer. The second conductive layer has a region disposed above the second insulating layer. The second conductive layer has a region that functions as one of the source electrode or the drain electrode of the transistor. The third conductive layer has a region disposed above the second insulating layer. The third conductive layer has a region that functions as the other of the source electrode or the drain electrode of the transistor. The oxide semiconductor layer has a channel formation region of the transistor. The third insulating layer has a region disposed above the second conductive layer, a region disposed above the oxide semiconductor layer, and a region disposed above the third conductive layer. The fourth conductive layer has a region disposed above the third insulating layer. The fourth conductive layer has a region that functions as a pixel electrode. The second insulating layer has a first region, a second region, and a third region. The first region does not overlap with the second conductive layer and does not overlap with the third conductive layer. The second region overlaps with the second conductive layer. The third region overlaps with the third conductive layer. The film thickness of the first region is thinner than the film thickness of the second region. The film thickness of the first region is thinner than the film thickness of the third region. In plan view, the first conductive layer has an overlap with the entire oxide semiconductor layer. The fourth conductive layer is electrically connected to the third conductive layer through a contact hole provided in the third insulating layer. In plan view, the contact hole does not have an overlap with the first conductive layer. A liquid crystal display device in which, in plan view, the spacer has an overlap with the oxide semiconductor layer.

5. In any one of Claims 1 to 4, A liquid crystal display device in which the fourth conductive layer does not have an overlap with the oxide semiconductor layer.

Images