Circuit substrate

Abstract

To provide a printed circuit substrate.SOLUTION: A printed circuit substrate includes a first isolation layer, a second isolation layer that is provided over the first isolation layer and has cavities, and a pad that is provided over the first isolation layer and has an upper surface exposed through the cavities. The cavities each has a first part including a first inner wall and a second part including a second inner wall under the first part. The tilt angle of the first inner wall is different from the tilt angle of the second inner wall.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The embodiments relate to printed circuit boards.

Background Art

[0002] A printed circuit board (PCB) is a board in which a printed circuit is printed with a conductive material on an electrical insulating substrate.

[0003] A printed circuit board is configured in a structure where the mounting positions of each element are determined and a circuit pattern for connecting the elements is printed and fixed on the surface of the flat plate in order to densely mount various types of elements on the flat plate, or is configured in an embedded structure in which elements are embedded inside the printed circuit board.

[0004] Recently, in order to achieve miniaturization and multifunctionality of electronic parts, printed circuit boards are used as multilayer structures capable of high-density integration.

[0005] Generally, a conventional embedded printed circuit board forms a cavity for internally mounting elements using a drill bit, uses auxiliary materials such as a release film for mounting the elements, or forms a cavity for internally mounting the elements using sand blast.

[0006] However, when a conventional embedded printed circuit board uses a drill bit as described above, large tolerances in the position and depth of the processing area occur, making high-density integration difficult, and thus a protective layer that is finally removed had to be formed.

[0007] Also, when a conventional embedded printed circuit board uses sand blast as described above, it is difficult to form a cavity only to a desired depth, and thus a stop layer had to be formed.

[0008] In addition, since manual work is required to use auxiliary materials such as release films, it is not easy to miniaturize the cavity size, and there is a problem that the manufacturing cost increases.

[0009] On the other hand, when using the protection layer or the stop layer, after the cavity is formed, the removal process must be performed essentially, and there is a problem that the process becomes complicated due to this. Further, the protection layer and the stop layer are formed of metal, and the etching process was performed to remove this.

[0010] However, for the sandblasting or laser process, the protection layer and the stop layer should have a thickness of at least 3 to 10 μm. Thus, when removing the protection layer and the stop layer, there is a problem that a part of the pad exposed through the cavity is also removed together.

Summary of the Invention

Problems to be Solved by the Invention

[0011] In an embodiment, a printed circuit board, a package board, and a manufacturing method thereof having a new structure are provided.

[0012] Further, in an embodiment, a printed circuit board, a package board, and a manufacturing method thereof are provided, which can solve the reliability problem of the printed circuit board by forming a cavity through a plurality of steps.

[0013] Further, in an embodiment, a printed circuit board, a package board, and a manufacturing method thereof are provided, in which a part of the insulating layer including the cavity remains with roughness on the surface, so that the adhesive force with the mold layer to be laminated later can be improved.

[0014] In the proposed embodiment, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those having ordinary knowledge in the technical field to which the embodiment belongs from the following description.

Means for Solving the Problem

[0015] The printed circuit board according to the embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer and including a cavity, and a pad disposed on the first insulating layer and having an upper surface exposed through the cavity. The cavity includes a first part including a first inner wall and a second part including a second inner wall below the first part, and an inclination angle of the first inner wall is different from an inclination angle of the second inner wall.

[0016] Also, the cavity includes an inflection point between the first inner wall and the second inner wall.

[0017] Also, the inflection point is located higher than the upper surface of the pad.

[0018] Also, the inclination angle of the first inner wall is smaller than the inclination angle of the second inner wall.

[0019] Also, the inclination angle of the first inner wall has a range of 50° to 60°, and the inclination angle of the second inner wall has a range of 60° to 80°.

[0020] Also, the second insulating layer includes a first portion disposed on the upper surface of the first insulating layer in a region where the cavity is formed and a second portion other than the first portion, and a thickness of the first portion is smaller than a thickness of the second portion.

[0021] Also, the upper surface of the first portion of the second insulating layer is located lower than the upper surface of the pad.

[0022] Also, an upper width of the first part of the cavity is larger than a lower width of the second part of the cavity.

[0023] Also, the cavity is connected to the second inner wall and includes a bottom surface located higher than the upper surface of the first insulating layer.

[0024] Further, the first inner wall, the second inner wall, and the bottom surface have surface buckles.

[0025] Also, the surface buckle of the first inner wall is different from the surface buckle of at least one of the second inner wall and the bottom surface.

[0026] On the other hand, the package substrate according to the embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer and including a cavity, a pad disposed on the first insulating layer and having an upper surface exposed through the cavity, a connection portion disposed on the pad, and an electronic element disposed on the connection portion. The cavity includes a first part including a first inner wall, and a second part including a second inner wall connected to the first inner wall under the first part and a bottom surface connected to the second inner wall. The first inner wall, the second inner wall, and the bottom surface each have a surface buckle, and the surface buckle of the first inner wall is different from the surface buckle of at least one of the second inner wall and the bottom surface.

[0027] Also, the cavity includes an inflection point located higher than the upper surface of the pad between the first inner wall and the second inner wall, and based on the inflection point, the inclination angle of the first inner wall is smaller than the inclination angle of the second inner wall.

[0028] Also, it includes a molding layer disposed in the cavity and covering at least a part of the electronic element, and the molding layer is in contact with the first inner wall, the second inner wall, and the bottom surface.

[0029] On the one hand, the manufacturing method of a printed circuit board according to an embodiment includes preparing a first insulating layer, forming pads on the upper surface of the first insulating layer, forming a second insulating layer covering the pads on the upper surface of the first insulating layer, forming a mask having an opening on the second insulating layer, performing a laser process through the opening of the mask to form a first part of a cavity that opens a part of the second insulating layer, and performing a plasma process on the second insulating layer under the first part to form a second part of the cavity that exposes the upper surface of the pads while opening a part of the second insulating layer. Before forming the second part, the upper surface of the pads is covered by the second insulating layer.

[0030] Further, the first part includes a first inner wall having a first inclination angle, and the second part includes a second inner wall having a second inclination angle different from the first inclination angle.

[0031] Also, the second part includes a bottom surface connected to the second inner wall and located higher than the upper surface of the first insulating layer. The first inner wall, the second inner wall, and the bottom surface have surface buckles, and the surface buckle of the first inner wall is different from the surface buckle of at least one of the second inner wall and the bottom surface.

Advantages of the Invention

[0032] According to the embodiment, the printed circuit board includes a cavity. At this time, the cavity 160 has a non-penetrating structure rather than a structure penetrating the second insulating layer 120. At this time, the cavity 160 exposes the pad 141a disposed on the first insulating layer 110. And the bottom surface of the cavity 160 is located lower than the upper surface of the pad 141a. Thereby, in the embodiment, it is not necessary to form an additional layer to form the cavity 160, and the number of processes can be reduced accordingly. Also, in the embodiment, losses due to thickness changes and shape changes of the pad 141a generated in the process of removing the additional layer can be solved, and the reliability of the product can be improved accordingly.

[0033] Also, according to the embodiment, the first part of the cavity is formed through a laser process, and then the remaining second part of the cavity is formed through a plasma process. By forming the first part through the laser process in this way, the overall process time for forming the cavity can be shortened, and by forming the second part through the plasma process, precise space can be ensured.

[0034] Also, according to the embodiment, the cavity 160 of the printed circuit board includes a first inner wall 161 having a first inclination angle centered on the inflection point 163, and a second inner wall 162 having a second inclination angle, and includes a bottom surface 164 extending from the second inner wall 163. At this time, the first inner wall 161, the second inner wall 162, and the bottom surface 164 of the cavity 160 can have a certain surface roughness instead of being flat. Also, an electronic element can be mounted on the pad 141a in the cavity 160. Further, the molding layer 190 can be disposed in the cavity 160 to cover the electronic element. At this time, by having a certain surface roughness on the inner wall and the bottom surface 164 of the cavity 160, the surface area in contact with the molding layer 190 can be increased, and thereby the bonding force during molding of the molding layer 190 can be improved.

Brief Description of the Drawings

[0035]

Figure 1

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Figure 10

Embodiments for Carrying Out the Invention

[0036] Hereinafter, with reference to the attached drawings, preferred embodiments of the present invention will be described in detail.

[0037] However, the technical idea of the present invention is not limited to some of the described embodiments, but is realized in various different forms, and within the scope of the technical idea of the present invention, one or more of the components between the embodiments can be selectively combined and replaced for use.

[0038] In addition, the terms (including technical and scientific terms) used in the embodiments of the present invention can be interpreted as the meaning generally understood by those having ordinary knowledge in the technical field to which the present invention belongs, unless specifically defined and described otherwise, and terms generally used like pre-defined terms can be interpreted in consideration of their meaning in the context of the related technology. Also, the terms used in the embodiments of the present invention are for explaining the embodiments and do not limit the present invention.

[0039] In this specification, the singular form can include the plural form as well, unless otherwise specifically mentioned in a phrase, and when described as "at least one (or one or more) of A and (or) B, C", it can include one or more of all the combinations that can be combined with A, B, C. Also, when explaining the components of the present invention, terms such as first, second, A, B, (a), (b), etc. can be used.

[0040] Such terms are only for distinguishing their components from other components, and are not intended to limit the essence, order or sequence of such components. When a component is described as being "connected", "coupled" or "joined" to another component, that component can include not only the case where it is directly connected, coupled or joined to the other component, but also the case where it is "connected", "coupled" or "joined" to the other component by another component between the component and the other component.

[0041] In addition, when it is described that something is formed or arranged "above or below" each component, "above or below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or arranged between the two components. Also, when expressed as "above or below", it can include not only the upward direction but also the downward direction with respect to one component.

[0042] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings as follows.

[0043] FIG. 1 is a diagram showing a printed circuit board according to an embodiment, and FIG. 2 is an enlarged view of the cavity region of FIG. 1.

[0044] Referring to FIGS. 1 and 2, the printed circuit board 100 includes a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, circuit patterns 141, 141, 143, 144, 145, 146, 147, 148, vias V1, V2, V3, V4, V5, V6, V7, and protective layers 151, 152.

[0045] The first insulating layer 110 can be an insulating layer disposed at the center of the printed circuit board 100.

[0046] The second insulating layer 120 is disposed above the first insulating layer 110.

[0047] Further, a third insulating layer 130 is disposed below the first insulating layer 110.

[0048] At this time, in the drawing, the first insulating layer 110 is shown to be disposed in the central layer in the overall laminated structure of the printed circuit board 100, but it is not limited thereto. That is, the first insulating layer 110 may be disposed at a position biased to the upper side in the overall laminated structure of the printed circuit board 100, and conversely, it may be disposed at a position biased to the lower side.

[0049] A second insulating layer 120 is disposed above the first insulating layer 110. At this time, the second insulating layer 120 has a plurality of layer structures. For example, the second insulating layer 120 may include a second-1 insulating layer 121 disposed on the upper surface of the first insulating layer 110, a second-2 insulating layer 122 disposed on the upper surface of the second-1 insulating layer 121, and a second-3 insulating layer 123 disposed on the upper surface of the second-2 insulating layer 122. At this time, in the drawing, the second insulating layer 120 is shown to have a three-layer structure, but it is not limited thereto. That is, the second insulating layer 120 may be composed of two layers or less, and differently, it may be configured to have a structure of four layers or more.

[0050] Further, a third insulating layer 130 is disposed below the first insulating layer 110. At this time, the third insulating layer 130 has a plurality of layer structures. For example, the third insulating layer 130 may include a third-1 insulating layer 131 disposed below the lower surface of the first insulating layer 110, a third-2 insulating layer 132 disposed below the lower surface of the third-1 insulating layer 131, and a third-3 insulating layer 133 disposed below the lower surface of the third-2 insulating layer 132. At this time, in the drawing, the third insulating layer 130 is shown to have a three-layer structure, but it is not limited thereto. That is, the second insulating layer 130 may be composed of two layers or less, and differently, it may be configured to have a structure of four layers or more.

[0051] Also, although the printed circuit board 100 is shown in the drawing as having a seven-layer structure based on the insulating layer, it is not limited thereto. For example, the printed circuit board 100 may have a number of layers of six or less based on the insulating layer, and conversely, may have a number of layers of eight or more.

[0052] The first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 are substrates in which an electric circuit capable of changing wiring is formed, and can include all of a print, a wiring board, and an insulating substrate made of an insulating material capable of forming a circuit pattern on the surface.

[0053] For example, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 can be rigid or flexible. For example, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 can include glass or plastic. Specifically, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 includes chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or includes a reinforced or ductile plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or can include sapphire.

[0054] Also, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 can include an optically isotropic film. As an example, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 can include cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0055] Further, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may be curved while partially having a curved surface. That is, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may partially have a flat surface and may be curved while partially having a curved surface. Specifically, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may be curved with an end having a curved surface or may be curved with a surface including a random curvature.

[0056] Further, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may be a flexible substrate having flexible characteristics. Also, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 may be a curved or bended substrate. At this time, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 can represent the electrical wiring connecting circuit components in a wiring pattern based on the circuit design and reproduce the electrical conductor on the insulator. Further, at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130 can mount electrical components and form wiring for connecting them circuitously, and can mechanically fix components other than the electrical connection function of the components.

[0057] On the other hand, the second - 1 insulating layer 121 disposed at the lowermost portion of the second insulating layer 120 in the embodiment may be an insulating layer that does not contain glass fiber. Preferably, the second - 1 insulating layer 121 may be any one of RCC (Resin Coated Copper), PPG (PREPER; Glass Fabric), and ABF (Akinomoto Build - up Film). This is because a part of the second - 1 insulating layer 121 may be removed by a plasma process. At this time, if glass fiber is included in the second - 1 insulating layer 121, it may affect the plasma process, and thus, the second - 1 insulating layer 121 can include an insulating substance that does not contain glass fiber.

[0058] Circuit patterns may be disposed on the surfaces of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130.

[0059] For example, on the upper surface of the first insulating layer 110, a first circuit pattern 141 may be disposed. At this time, the first circuit patterns 141 may be arranged in a plurality on the upper surface of the first insulating layer 110 while being spaced apart from each other at a certain interval.

[0060] On the lower surface of the first insulating layer 110, a second circuit pattern 142 may be disposed. The second circuit patterns 142 may be arranged in a plurality on the lower surface of the first insulating layer 110 while being spaced apart from each other at a certain interval.

[0061] Also, circuit patterns may be disposed on the surface of the second insulating layer 120. For example, on the upper surface of the second - 1 insulating layer 121, a plurality of third circuit patterns 143 may be disposed while being spaced apart from each other at a certain interval. Also, on the upper surface of the second - 2 insulating layer 122, a plurality of fourth circuit patterns 144 may be disposed while being spaced apart from each other at a certain interval. Also, on the upper surface of the second - 3 insulating layer 123, a plurality of fifth circuit patterns 145 may be disposed while being spaced apart from each other at a certain interval.

[0062] Also, circuit patterns can be arranged on the surface of the third insulating layer 130. For example, a plurality of sixth circuit patterns 146 can be arranged on the lower surface of the third-1 insulating layer 131, spaced apart from each other at regular intervals. Also, a plurality of seventh circuit patterns 147 can be arranged on the lower surface of the third-2 insulating layer 132, spaced apart from each other at regular intervals. Also, a plurality of eighth circuit patterns 148 can be arranged on the lower surface of the third-3 insulating layer 133, spaced apart from each other at regular intervals.

[0063] On the other hand, the first to eighth circuit patterns 141, 142, 143, 144, 145, 146, 147, 148 as described above are wirings for transmitting electrical signals and can be formed of a metallic substance with high electrical conductivity. For this purpose, the first to eighth circuit patterns 141, 142, 143, 144, 145, 146, 147, 148 can be formed of at least one metallic substance selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Also, the first to eighth circuit patterns 141, 142, 143, 144, 145, 146, 147, 148 can be formed of a paste or solder paste containing at least one metallic substance selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) which have excellent bonding force. Preferably, the first to eighth circuit patterns 141, 142, 143, 144, 145, 146, 147, 148 can be formed of copper (Cu) which has high electrical conductivity and is relatively inexpensive.

[0064] The first to eighth circuit patterns 141, 142, 143, 144, 145, 146, 147, 148 can be formed by an additive process, a subtractive process, an MSAP (Modified Semi Additive Process), an SAP (Semi Additive Process), etc., which are the manufacturing processes of a normal printed circuit board. Here, detailed descriptions are omitted.

[0065] On the one hand, the first circuit pattern 141 can be disposed on the upper surface of the first insulating layer 110 and include pads 141a that are exposed through the cavity 160. The pads 141a can be electrically connected to electronic elements (described later) mounted in the cavity 160. For example, the pads 141a can be wire bonding pads connected to the electronic elements mounted in the cavity 160 via wires. Alternatively, the pads 141a can be flip chip bonding pads directly connected to the terminals of the electronic elements mounted in the cavity 160. This will be described in more detail below.

[0066] On the one hand, the first to eighth circuit patterns 141, 142, 143, 144, 145, 146, 147, 148 can each include a pattern connected to a via for interlayer conduction, a pattern for signal transmission, and pads connected to electronic elements or the like.

[0067] In the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130, vias V1, V2, V3, V4, V5, V6, V7 for electrically connecting circuit patterns disposed in different layers to each other can be disposed. The vias V1, V2, V3, V4, V5, V6, V7 can be disposed to penetrate at least one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130. Both ends of the vias V1, V2, V3, V4, V5, V6, V7 are respectively connected to circuit patterns disposed in different insulating layers, thereby enabling the transmission of electrical signals.

[0068] The first via V1 can be disposed in the first insulating layer 110. The first via V1 can be disposed to penetrate the upper and lower surfaces of the first insulating layer 110. The first via V1 can electrically connect the first circuit pattern 141 disposed on the upper surface of the first insulating layer 110 and the second circuit pattern 142 disposed on the lower surface of the first insulating layer 110.

[0069] A plurality of vias may be disposed in the second insulating layer 120. That is, a second via V2 may be disposed in the second - 1 insulating layer 121. The second via V2 can electrically connect the first circuit pattern 141 disposed on the upper surface of the first insulating layer 110 and the third circuit pattern 143 disposed on the upper surface of the second - 1 insulating layer 121.

[0070] Also, a third via V3 may be disposed in the second - 2 insulating layer 122. The third via V3 can electrically connect the fourth circuit pattern 144 disposed on the upper surface of the second - 2 insulating layer 122 and the third circuit pattern 143 disposed on the upper surface of the second - 1 insulating layer 121.

[0071] Also, a fourth via V4 may be disposed in the second - 3 insulating layer 123. The fourth via V4 can electrically connect the fifth circuit pattern 145 disposed on the upper surface of the second - 3 insulating layer 123 and the fourth circuit pattern 144 disposed on the upper surface of the second - 2 insulating layer 122.

[0072] A plurality of vias may be disposed in the third insulating layer 130. That is, a fifth via V5 may be disposed in the third - 1 insulating layer 131. The fifth via V5 can electrically connect the second circuit pattern 142 disposed on the lower surface of the first insulating layer 110 and the sixth circuit pattern 146 disposed on the lower surface of the third - 1 insulating layer 131.

[0073] Also, a sixth via V6 may be disposed in the third - 2 insulating layer 132. The sixth via V6 can electrically connect the seventh circuit pattern 147 disposed on the lower surface of the third - 2 insulating layer 132 and the sixth circuit pattern 146 disposed on the lower surface of the third - 1 insulating layer 131.

[0074] Also, a seventh via V7 may be disposed in the third - 3 insulating layer 133. The seventh via V7 can electrically connect the eighth circuit pattern 148 disposed on the lower surface of the third - 3 insulating layer 133 and the seventh circuit pattern 147 disposed on the lower surface of the third - 2 insulating layer 132.

[0075] On the one hand, the vias V1, V2, V3, V4, V5, V6, and V7 may penetrate only one of the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130. In contrast, they may be arranged to penetrate a plurality of insulating layers in common. As a result, the vias V1, V2, V3, V4, V5, V6, and V7 can connect circuit patterns arranged on the surfaces of insulating layers that are at least two or more layers apart from each other, rather than adjacent insulating layers.

[0076] On the other hand, the vias V1, V2, V3, V4, V5, V6, and V7 can be formed by filling the inside of a through-hole (not shown) that penetrates at least one of the plurality of insulating layers with a conductive material.

[0077] The through-hole can be formed by any one of machining methods such as mechanical, laser, and chemical processing. When the through-hole is formed by mechanical processing, methods such as milling, drill, and routing can be used. When it is formed by laser processing, UV or CO2 laser methods can be used. When it is formed by chemical processing, at least one of the plurality of insulating layers can be opened using chemicals containing aminosilane, ketones, etc.

[0078] On the other hand, the laser processing is a cutting method that concentrates optical energy on the surface to melt and evaporate a part of the material to form a desired shape. It can be easily processed even for complex formations by a computer program, and can also process composite materials that are difficult to cut by other methods.

[0079] In addition, the laser processing has the advantages that the cutting diameter can be as small as 0.005 mm at minimum, and the range of processable thickness is wide.

[0080] As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, and the CO2 laser is a laser that can process only the insulating layer.

[0081] When the through hole is formed, the inside of the through hole can be filled with a conductive material to form the vias V1, V2, V3, V4, V5, V6, V7. The metallic material for forming the vias V1, V2, V3, V4, V5, V6, V7 can be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the filling of the conductive material can use any one of electroless plating, electroplating, screen printing, sputtering, evaporation method, inkjetting, and dispensing, or a combination of these methods.

[0082] On the other hand, protective layers 151 and 152 can be disposed on the surface of the insulating layer disposed on the outermost periphery among the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130. For example, the first protective layer 151 can be disposed on the upper surface of the insulating layer disposed at the uppermost part among the plurality of insulating layers. For example, the first protective layer 151 can be disposed on the upper surface of the second - 3 insulating layer 123 disposed at the uppermost part of the second insulating layer 120. Also, the second protective layer 152 can be disposed on the lower surface of the insulating layer disposed at the lowermost part among the plurality of insulating layers. For example, the second protective layer 152 can be disposed on the lower surface of the third - 3 insulating layer 133 disposed at the lowermost part of the third insulating layer 130.

[0083] The first protective layer 151 and the second protective layer 152 can each have an opening. For example, the first protective layer 151 can have an opening that exposes the surface of the fifth circuit pattern to be exposed among the fifth circuit patterns 145 disposed on the upper surface of the second - 3 insulating layer 123.

[0084] Further, the second protective layer 152 can have an opening that exposes the surface of the eighth circuit pattern to be exposed among the eighth circuit patterns 148 disposed on the lower surface of the third - third insulating layer 133.

[0085] Such first protective layer 151 and second protective layer 152 can contain an insulating material. The first protective layer 151 and the second protective layer 152 can contain various substances that can be heated and cured after being applied to protect the surface of the circuit pattern. The first protective layer 151 and the second protective layer 152 can be a resist layer. For example, the first protective layer 151 and the second protective layer 152 can be a solder resist layer containing an organic polymer material. As an example, the first protective layer 151 and the second protective layer 152 can contain an epoxy acrylate - based resin. Specifically, the first protective layer 151 and the second protective layer 152 can contain a resin, a curing agent, a photo - initiator, a pigment, a solvent, a filler, an additive, an acrylic - based monomer, etc. However, the embodiments are not limited thereto, and it goes without saying that the first protective layer 151 and the second protective layer 152 can be any one of a photo - solder resist layer, a coverlay, and a polymer material.

[0086] The thickness of the first protective layer 151 and the second protective layer 152 can be 1 μm to 20 μm. The thickness of the first protective layer 151 and the second protective layer 152 can be 1 μm to 15 μm. For example, the thickness of the first protective layer 151 and the second protective layer 152 can be 5 μm to 20 μm. When the thickness of the first protective layer 151 and the second protective layer 152 exceeds 20 μm, the thickness of the printed circuit board 100 may increase. When the thickness of the first protective layer 151 and the second protective layer 152 is less than 1 μm, the reliability of the circuit pattern included in the printed circuit board 100 may decrease.

[0087] On the other hand, a cavity 160 may be formed in the second insulating layer 120. At this time, the cavity 160 may be disposed within the second insulating layer 120 composed of a plurality of layers. At this time, the cavity 160 may be disposed so as to penetrate at least one of the insulating layers among the second insulating layers 120 composed of the plurality of layers and not penetrate at least one other insulating layer.

[0088] That is, a general cavity 160 is disposed to penetrate the insulating layer. As a result, at the position where the cavity 160 is disposed, there is no insulating layer that overlaps the cavity 160 in the horizontal direction. For example, the cavity in the comparative example is disposed to penetrate the entire second insulating layer 120. For example, the cavity in the comparative example is disposed to penetrate the lower surface of the second - 1 insulating layer 121 and the upper surface of the second - 3 insulating layer 123.

[0089] In contrast, in the embodiment, the cavity, at the position where the cavity is disposed, at least one of the insulating layers that overlap the cavity 160 vertically penetrates, while at least one other insulating layer does not penetrate.

[0090] That is, the cavity 160 in the embodiment is disposed in the second insulating layer 120. That is, the cavity 160 is disposed within the second - 1 insulating layer 121, the second - 2 insulating layer 122, and the second - 3 insulating layer 123.

[0091] At this time, the cavity in the structure of the printed circuit board of the comparative example is disposed to penetrate all of the second - 1 insulating layer 121, the second - 2 insulating layer 122, and the second - 3 insulating layer 123. As a result, on the printed circuit board of the comparative example, the upper surface of the first insulating layer in the region that overlaps the cavity vertically is exposed. That is, on the upper surface of the first insulating layer that overlaps the cavity vertically in the printed circuit board of the comparative example, there is no second insulating layer (more specifically, the second - 1 insulating layer).

[0092] In contrast, the cavity 160 in the printed circuit board 100 in the embodiment can be disposed so as to penetrate through the second-1 insulating layer 121 and the second-2 insulating layer 122 while not penetrating through the second-3 insulating layer 123.

[0093] That is, the cavity 160 can include a first portion disposed in the second-1 insulating layer 121, a second portion disposed in the second-2 insulating layer 122, and a third portion disposed in the second-3 insulating layer 123. Here, since the second insulating layer 122 in the embodiment has a three-layer structure, the cavity 160 is shown as being composed of the first to third portions, but it is not limited thereto. For example, when the second insulating layer 120 has a two-layer structure, the cavity 160 can include only the first and second portions. For example, when the second insulating layer 122 has a five-layer structure, the cavity 160 can include the first to fifth portions. However, the cavity 160 in the embodiment is characterized in that the part disposed at the lowermost part has a groove shape instead of a through-hole shape.

[0094] The first portion can be disposed in the second-1 insulating layer 121. At this time, the first portion is disposed in the second-1 insulating layer 121 and can be a groove that forms the lower region of the cavity 160.

[0095] The second portion can be disposed in the second-2 insulating layer 122. The second portion is disposed in the second-2 insulating layer 122 and can be a through-hole that forms the central region of the cavity 160.

[0096] The third portion can be disposed in the second-3 insulating layer 123. The third portion is disposed in the second-3 insulating layer 123 and can be a through-hole that forms the upper region of the cavity 160.

[0097] That is, the cavity 160 can be composed of a combination of the first part, the second part, and the third part. At this time, the thickness of the first part may be smaller than the thickness of the second - 1 insulating layer 121. Therefore, the cavity 160 can be formed without penetrating the second - 1 insulating layer 121.

[0098] In other words, the second - 1 insulating layer 121 can include a first region R1 disposed on a region overlapping the cavity 160 in the vertical direction and a second region R2 excluding the first region R1. And the thickness of the first region R1 may be different from the thickness of the second region R2.

[0099] Preferably, the thickness H1 of the second region R2 can be the thickness of the second - 1 insulating layer 121.

[0100] The thickness H1 of the second region R2 can be 20μm to 100μm. For example, the thickness H1 of the second region R2 can have a thickness of 25μm to 50μm. For example, the thickness H1 of the second region R2 can have a thickness of 30μm to 40μm. When the thickness H1 of the second region R2 exceeds 100μm, the thickness of the entire printed circuit board 100 may increase. When the thickness H1 of the second region R2 is less than 20μm, the pad 141a and the first circuit pattern cannot be stably protected. Also, when the thickness H1 of the second region R2 is less than 20μm, the second - 1 insulating layer 121 may be vulnerable to heat / pressure, etc. in the process of mounting electronic elements.

[0101] The thickness H2 of the first region R1 may be smaller than the thickness H1 of the second region. The thickness H2 of the first region R1 can be determined by the thickness H3 of the pad 141a. Preferably, the thickness H2 of the first region R1 may be smaller than the thickness H3 of the pad 141a.

[0102] Preferably, the thickness H3 of the pad 141a may be smaller than the thickness H1 of the second region R2. For example, the thickness H3 of the pad 141a can be 5μm to 30μm.

[0103] And the thickness H2 of the first region R1 may be smaller than the thickness H3 of the pad 141a. For example, the thickness H2 of the first region R1 of the first region R1 may be 3 μm to 25 μm. Therefore, the first region R1 of the second first insulating layer 121 is disposed on the first insulating layer 110. At this time, the first region R1 of the second first insulating layer 121 may expose the upper surface of the pad 141a disposed on the first insulating layer 110.

[0104] That is, in the embodiment, in order to mount the electronic element, the cavity 160 is not formed by penetrating the second insulating layer 120, and the cavity 160 is formed in a state where at least a part of the second insulating layer 120 (the first region of the second first insulating layer 121) remains on the first insulating layer 110.

[0105] At this time, the thickness H2 of the remaining part of the second insulating layer 120 is smaller than the thickness H3 of the pad 141a to be exposed on the cavity 160. Thereby, in the embodiment, the cavity 160 can be formed without affecting the mounting of the electronic element on the pad 141a and while maintaining the shape of the pad 141a.

[0106] That is, conventionally, in order to form cavities in a plurality of insulating layers as described above, the cavity forming process was performed with a protective layer or a stop layer disposed on the first insulating layer. As a result, conventionally, cavities could be formed to a desired depth (a depth that penetrates the entire second insulating layer). However, conventionally, after the cavities were formed, an etching process for removing the protective layer and the stop layer had to be performed. As a result, conventionally, a part of the pad disposed on the first insulating layer was also removed together during the etching process for removing the protective layer and the stop layer, which could cause a problem in the reliability of the pad. At this time, the thickness of the protective layer and the stop layer required during the sandblasting or laser process was at the level of 3 μm to 10 μm. As a result, there was a problem that only the thickness corresponding to the protective layer and the stop layer in the total thickness of the pad during the etching process was removed.

[0107] Accordingly, in the embodiment, the cavities can be easily formed without forming the protective layer and the stop layer, thereby solving the reliability problems that occur during the removal process of the protective layer and the stop layer.

[0108] And this is to form the cavity 160 in a state where the second - 1 insulating layer 121 is not penetrated through control of the process conditions for forming the cavity.

[0109] At this time, the cavity 160 can be formed by a plurality of processes.

[0110] That is, the cavity 160 can be divided into a first part formed by a first process and a second part formed by a second process.

[0111] The first part can be formed in the entire region of the second - 3 insulating layer 123, the entire region of the second - 2 insulating layer 122, and a partial region of the second - 1 insulating layer 121. The first process can be a laser process.

[0112] That is, in the embodiment, when forming the cavity 160, the entire region of the second-third insulating layer 123, the entire region of the second-second insulating layer 122, and a partial region of the second-first insulating layer 121 can be removed through a laser process first to form the first part 160a of the cavity 160.

[0113] At this time, the first inner wall 161 of the first part 160a can have a first inclination angle θ1. Preferably, the first inclination angle θ1 can be 50° to 60°. The first inner wall 161 of the first part 160a can be a laser cut surface formed by a laser process.

[0114] The first part 160a can have a first depth. At this time, the first depth of the first part 160a may be greater than the second depth of the second part 160b formed by a plasma process with respect to the total thickness of the second insulating layer 120. The first depth of the first part 160a may be greater than 1 / 2 of the thickness of the second insulating layer 120.

[0115] A second part 160b can be formed under the first part 160a. The second part 160b can communicate with the first part 160a. For example, the second part 160b can be connected to the first part 160a to form one cavity 160.

[0116] An inflection point 163 can be formed between the first inner wall 161 of the first part 160a and the second inner wall 162 of the second part 160b. The inflection point 163 can mean a portion where the inclination angles of the inner walls 161 and 162 of the cavity 160 are changed. For example, the inflection point 163 can be a point where the lowermost end of the first inner wall 161 of the first part 160a meets the uppermost end of the second inner wall 162 of the second part 160b.

[0117] That is, the first part 160a is formed by a laser process, and the second part 160b is formed by a plasma process. As a result, an inflection point 163 where the inclination angle (or curvature) is changed may be located at the point where the first part 160a and the second part 160b meet.

[0118] At this time, the inflection point 163 may be located higher than the pad 141a. In other words, the lowermost end of the first part 160a may be located higher than the upper surface of the pad 141a. In other words, the uppermost end of the second part 160b may be located higher than the upper surface of the pad 141a.

[0119] That is, the first part 160a may be formed by a laser process to a point higher than the upper surface of the pad 141a. At this time, when the first part 160a is formed to the point where the pad 141a is located, the pad 141a may be damaged by the laser in the process of forming the first part 160a. Thus, in the embodiment, the first part 160a can be formed only to a point higher than the upper surface of the pad 141a.

[0120] And the second part 160b has a second depth and may be formed under the first part 160a. The second depth may be smaller than the first depth that the first part 160a has.

[0121] The second part 160b may include a second inner wall 162 connected to the first inner wall 161 and a bottom surface 164 connected to the second inner wall 162. The second inner wall 162 and the bottom surface 164 may be plasma-treated surfaces formed by a plasma process.

[0122] The bottom surface 164 may be positioned lower than the upper surface of the pad 141a. That is, when the bottom surface 164 is positioned higher than the pad 141a, a part of the upper surface of the pad 141a may be covered by the second insulating layer, which may affect the reliability of the product. Therefore, in the embodiment, the bottom surface 164 is positioned lower than the upper surface of the pad 141a.

[0123] The second inner wall 162 of the second part 160b can have a second inclination angle θ2. At this time, the second inclination angle θ2 of the second inner wall 162 of the second part 160b may be different from the first inclination angle θ1 of the first inner wall 161 of the first part 160a. For example, the second inclination angle θ2 of the second inner wall 162 of the second part 160b may be larger than the first inclination angle θ1 of the first inner wall 161 of the first part 160a. For example, the second inclination angle θ2 may be 60° to 80°.

[0124] On the other hand, in the process of forming the second part 160b, the upper surface of the pad 141a covered by the second insulating layer 120 may be exposed. At this time, the second part 160b is formed by a plasma process, so that in the process of forming the second part 160b, the second part 160b can be precisely formed without damaging the surface of the pad 141a.

[0125] As described above, the maximum depth of the cavity 160 including the first part 160a and the second part 160b may be smaller than the total thickness of the second insulating layer 120. Also, the minimum depth of the cavity 160 may be larger than the depth obtained by subtracting the thickness of the pad 141a from the total thickness of the second insulating layer 120. Thereby, in the embodiment, the upper surface of the first region R1 of the second - 1 insulating layer 121 of the second insulating layer 120 is higher than the upper surface of the first insulating layer 110 and lower than the upper surface of the pad 141a.

[0126] On the one hand, referring to FIG. 2, the cavity 160 may include a first inner wall 161 of the first part 160a, a second inner wall 162 and a bottom surface 164 of the second part 160b.

[0127] At this time, the first inner wall 161 of the first part 160a, the second inner wall 162 and the bottom surface 164 of the second part 160b may have a certain surface roughness.

[0128] At this time, the surface roughness of the first inner wall 161 of the first part 160a may be different from the surface roughness of the second inner wall 162 of the second part 160b. For example, the surface roughness of the first inner wall 161 of the first part 160a may be greater than the surface roughness of the second inner wall 162 of the second part 160b. Also, the surface roughness of the second inner wall 162 of the second part 160b may be the same as the surface roughness of the bottom surface 164.

[0129] At this time, in the embodiment, instead of performing an additional process so that the first inner wall 161 of the first part 160a of the cavity 160, the second inner wall 162 and the bottom surface 164 of the second part 160b have a certain surface roughness, during the laser process and the plasma process for forming the cavity 160, different surface roughnesses as described above can be formed.

[0130] In other words, the bottom surface 164 of the cavity 160 may mean the upper surface of the first region R1 of the second - 1 insulating layer 121. And the height of the upper surface of the first region R1 of the second - 1 insulating layer 121 is not constant and may have a deviation depending on the position.

[0131] On the one hand, as described above, the first inner wall 161 of the first part 160a and the second inner wall 162 of the second part 160b may have a first inclination angle θ1 and a second inclination angle θ2.

[0132] At this time, the inner walls 161 and 162 may be curves having a certain surface roughness instead of straight lines. Thereby, the first inclination angle θ1 may be an interior angle between a virtual first line connecting the uppermost end and the lowermost end of the first part 160a and a virtual second line corresponding to the upper surface of the second insulating layer 120.

[0133] Also, the second inclination angle θ2 may be an interior angle between a virtual third line connecting the uppermost end and the lowermost end of the second part 160b and a virtual second line corresponding to the upper surface of the second insulating layer 120.

[0134] FIG. 3 is a diagram showing a package substrate according to the first embodiment.

[0135] Referring to FIG. 4, the package substrate 200 in the embodiment includes the printed circuit board 100 shown in FIG. 1 and an electronic component 180 mounted in the cavity 160 of the printed circuit board 100.

[0136] The printed circuit board 100 described with reference to FIG. 1 can be used as the package substrate 200 for mounting the electronic component 180.

[0137] At this time, since the printed circuit board 100 has already been described in detail with reference to FIG. 1, the description thereof will be omitted.

[0138] The printed circuit board 100 includes a cavity 160, and pads 141a may be exposed in the cavity 160. At this time, the second insulating layer 121 may be disposed in the remaining area of the cavity 160 excluding the area where the pads 141a are formed. However, the height of the first region R1 of the second insulating layer 121 is lower than the height of the pads 141a. Thereby, the electronic component 180 can be stably mounted on the pads 141a without being affected by the second insulating layer 121 on the first region R1. That is, if the height of the first region R1 of the second insulating layer 121 is higher than the height of the pads 141a, the electronic component 180 may be mounted in an inclined state on the pads 141a, and further, a poor electrical connection state with the pads 141a may occur.

[0139] At this time, the electronic component 180 may be an electronic component disposed in the cavity 160 of the printed circuit board 100, and this can be classified into an active component and a passive component. The active component is a component that actively utilizes a non-linear portion, and the passive component means a component that does not utilize non-linear characteristics even if both linear and non-linear characteristics exist. The passive component may include a transistor, an IC semiconductor chip, etc., and the passive component may include a capacitor, a resistor, an inductor, etc. The passive component is mounted on a normal printed circuit board in order to increase the signal processing speed of a semiconductor chip that is an active component or to perform a filtering function or the like.

[0140] On one hand, a connection part 170 can be arranged on the pad 141a. The planar shape of the connection part 170 can be a quadrilateral shape. The connection part 170 is arranged on the pad 141a to electrically connect between the electronic element 180 and the pad 141a while fixing the electronic element 180. For this purpose, the pad 141a can be formed of a conductive material. As an example, the connection part 170 can be a solder ball. The connection part 170 can contain a substance of a different component in the solder. The solder can be composed of at least any one of SnCu, SnPb, and SnAgCu. And the substance of the different component can contain any one of Al, Sb, Bi, Cu, Ni, In, Pb, Ag, Sn, Zn, Ga, Cd, and Fe.

[0141] On one hand, the upper surface of the electronic element 180 can be located higher than the surface of the uppermost layer of the printed circuit board 100. However, the embodiment is not limited thereto. Depending on the type of the electronic element 180, the upper surface of the electronic element 180 may be arranged at the same height as the surface of the uppermost layer of the printed circuit board 100, or differently, may be arranged lower.

[0142] FIG. 4 is a diagram showing a package substrate according to a second embodiment.

[0143] Referring to FIG. 4, the package substrate 200A in the embodiment includes the printed circuit board 100 shown in FIG. 1 and an electronic element 180a mounted in the cavity 160 of the printed circuit board 100.

[0144] In addition, the package substrate 200A further includes a molding layer 190 arranged in the cavity 160 to cover the electronic element 180a.

[0145] The molding layer 190 is selectively arranged in the cavity 160 and can protect the electronic element 180a mounted in the cavity 160.

[0146] The molding layer 190 may be made of a molding resin, for example, it may be an EMC (Epoxy molding compound). However, the embodiments are not limited thereto, and the molding layer 190 may also be made of various other molding resins other than EMC.

[0147] The printed circuit board 100 described with reference to FIG. 1 can be used as a package substrate 200A for mounting the electronic element 180a.

[0148] The printed circuit board 100 includes a cavity 160, and pads 141a may be exposed in the cavity 160. At this time, the second first insulating layer 121 may be disposed in the remaining area of the cavity 160 excluding the area where the pads 141a are formed. However, the height of the first region R1 of the second first insulating layer 121 is lower than the height of the pads 141a. Thereby, the electronic element 180a can be stably mounted on the pads 141a without being affected by the second first insulating layer 121 on the first region R1. In other words, if the height of the first region R1 of the second first insulating layer 121 is higher than the height of the pads 141a, the electronic element 180a may be mounted in an inclined state on the pads 141a, and furthermore, a defect may occur in the electrical connection state with the pads 141a.

[0149] On the other hand, the inner walls 161, 162 and the bottom surface 164 of the cavity 160 in the embodiment may not be flat and may have a certain bend. In other words, the inner walls 161, 162 and the bottom surface 164 of the cavity 160 may have a surface roughness above a certain level. That is, the inner walls 161, 162 and the bottom surface 164 of the cavity 160 may have roughness.

[0150] In the embodiment, the molding layer 190 is disposed in contact with the inner walls 161, 162 and the bottom surface 164 of the cavity 160. At this time, the inner walls 161, 162 and the bottom surface 164 of the cavity 160 are not flat but have a certain degree of bending. Such a structure of the cavity 160 can increase the surface area in contact with the molding layer 190, thereby improving the bonding force between the molding layer 190 and the printed circuit board 100.

[0151] According to the embodiment, the printed circuit board includes a cavity. At this time, the cavity 160 has a non-penetrating structure rather than a structure that penetrates the second insulating layer 120. At this time, the cavity 160 exposes the pad 141a disposed on the first insulating layer 110. And the bottom surface of the cavity 160 is positioned lower than the upper surface of the pad 141a. Thus, in the embodiment, it is not necessary to form an additional layer to form the cavity 160, and the number of processes can be reduced thereby. Also, in the embodiment, losses due to changes in the thickness and shape of the pad 141a generated in the process of removing the additional layer can be solved, and the reliability of the product can be improved thereby.

[0152] Also, according to the embodiment, the cavity 160 of the printed circuit board includes inner walls 161, 162 and a bottom surface 164. At this time, the inner walls 161, 162 and the bottom surface 164 of the cavity 160 can have a certain surface roughness rather than being flat. Also, an electronic element can be mounted on the pad 141a in the cavity 160. Also, the molding layer 190 may be disposed in the cavity 160 to cover the electronic element. At this time, by having a certain surface roughness on the inner walls and the bottom surface of the cavity 160, the surface area in contact with the molding layer 190 can be increased, thereby improving the bonding force during molding of the molding layer 190.

[0153] Hereinafter, a method for manufacturing a printed circuit board according to an embodiment will be described with reference to the accompanying drawings.

[0154] FIGS. 5 to 9 are diagrams showing the manufacturing method of the printed circuit board shown in FIG. 1 in the order of steps, and FIG. 10 is a micrograph showing an enlarged cavity of the printed circuit board according to the embodiment.

[0155] Referring to FIG. 5, a first insulating layer 110 can be prepared, first and second circuit patterns 141 and 142 can be formed on the surface of the first insulating layer 110, and a first via V1 that penetrates the first insulating layer 110 and electrically connects the first and second circuit patterns 141 and 142 can be formed.

[0156] The first insulating layer 110 can be a prepreg. The prepreg (PPG) has good fluidity and adhesiveness in a semi-cured state and is used as an intermediate base material for a fiber-reinforced composite material used as an adhesive layer and an insulating material layer, but is a molding material in which reinforcing fibers are impregnated with a matrix resin in advance. By laminating such prepregs and heating / pressing to cure the resin, a molded product is formed. That is, prepreg refers to a material in which glass fiber is impregnated with a resin (such as BT / Epoxy, FR4, FR5) and cured to the B-stage.

[0157] That is, the first insulating layer 110 can be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an inorganic-organic composite material substrate, or a glass fiber impregnated substrate. When including a polymer resin, it can include an epoxy-based insulating resin, and alternatively, it can also include a polyimide-based resin.

[0158] That is, the first insulating layer 110 is a board in which an electric circuit capable of changing wiring is formed, and can include all of a print, a wiring board, and an insulating substrate made of an insulating material capable of forming a conductor pattern on the surface of the insulating substrate.

[0159] A metal layer (not shown) is laminated on the surface of the first insulating layer 110. The metal layer can be formed by electroless plating a metal containing copper on the first insulating layer 110. Also, unlike forming the metal layer by performing electroless plating on the first insulating layer 110, a CCL (Copper Clad Laminate) can be used.

[0160] When forming the metal layer by performing electroless plating, roughness can be imparted to the upper surface of the first insulating layer 110 so that the plating can be performed smoothly. Then, the metal layer is patterned to form first and second circuit patterns 141 and 142 on the upper and lower surfaces of the first insulating layer 110, respectively. At this time, the first circuit pattern 141 can include pads 141a connected to electronic elements 180 and 180a to be mounted on the first insulating layer 110 later via connection portions 170.

[0161] The first and second circuit patterns 141 and 142 as described above are possible by an additive process, a subtractive process, an MSAP (Modified Semi Additive Process), an SAP (Semi Additive Process), etc., which are manufacturing processes of a normal printed circuit board. Here, detailed descriptions are omitted.

[0162] Next, referring to FIG. 6, a step of laminating a second insulating layer 120 and a third insulating layer 130 on the upper and lower portions of the first insulating layer 110, respectively, can be performed.

[0163] At this time, the second insulating layer 120 has a plurality of layer structures. For example, the second insulating layer 120 can include a second-1 insulating layer 121 disposed on the upper surface of the first insulating layer 110, a second-2 insulating layer 122 disposed on the upper surface of the second-1 insulating layer 121, and a second-3 insulating layer 123 disposed on the upper surface of the second-2 insulating layer 122.

[0164] In addition, the third insulating layer 130 has a plurality of layer structures. For example, the third insulating layer 130 can include a third-1 insulating layer 131 disposed under the lower surface of the first insulating layer 110, a third-2 insulating layer 132 disposed under the lower surface of the third-1 insulating layer 131, and a third-3 insulating layer 133 disposed under the lower surface of the third-2 insulating layer 132.

[0165] Further, a step of forming a circuit pattern on the surface of the second insulating layer 120 can be performed. For example, a step of forming a plurality of third circuit patterns 143 spaced apart from each other at a constant interval on the upper surface of the second-1 insulating layer 121 can be performed. Also, a step of forming a plurality of fourth circuit patterns 144 spaced apart from each other at a constant interval on the upper surface of the second-2 insulating layer 122 can be performed. Further, a step of forming a plurality of fifth circuit patterns 145 arranged spaced apart from each other at a constant interval on the upper surface of the second-3 insulating layer 123 can be performed.

[0166] Also, a step of forming a circuit pattern on the surface of the third insulating layer 130 can be performed. For example, a step of forming a plurality of sixth circuit patterns 146 arranged spaced apart from each other at a constant interval on the lower surface of the third-1 insulating layer 131 can be performed. Also, a step of forming a plurality of seventh circuit patterns 147 arranged spaced apart from each other at a constant interval on the lower surface of the third-2 insulating layer 132 can be performed. Further, a step of forming a plurality of eighth circuit patterns 148 arranged spaced apart from each other at a constant interval on the lower surface of the third-3 insulating layer 133 can be performed.

[0167] Also, a step of forming vias V1, V2, V3, V4, V5, V6, V7 for electrically connecting circuit patterns arranged in different layers to each other can be performed in the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130.

[0168] Next, referring to FIG. 7, a step of forming a cavity 160 on the cavity region in the second insulating layer 120 can be performed. At this time, the cavity 160 can be formed in the second insulating layer 120 composed of a plurality of layers.

[0169] At this time, the cavity 160 can be formed through a plurality of different processes.

[0170] That is, as a first cavity forming step for forming the cavity 160, a laser process can be performed.

[0171] At this time, before the first cavity forming step, a mask 310 can be formed on the remaining region of the upper surface of the second insulating layer 120 excluding the region where the cavity 160 is to be formed. The mask 310 can be a metal layer. For example, the mask 310 can be formed of a metal material containing copper.

[0172] That is, the mask 310 can be formed of a material that is not etched during the laser and plasma processes, and as an example, it can be a metal layer containing copper.

[0173] The mask 310 can have a thickness between 0.1 μm and 12 μm. When the mask 310 is smaller than 0.1 μm, the role of the mask cannot be performed normally, and thus a cavity may be formed in a region where a cavity should not be formed. Also, when the mask 310 is larger than 12 μm, damage to other circuit patterns may occur during the removal process of the mask 310.

[0174] Next, as shown in FIG. 8, a first cavity forming step is performed using a laser on the second insulating layer 120 to form a first part 160a of the cavity 160. Then, as shown in FIG. 9, a second cavity forming step is performed through a plasma process to form a second part 160b of the cavity 160 under the first part 160a.

[0175] As a result, the cavity 160 can include a first portion disposed in the second first insulating layer 121, a second portion disposed in the second second insulating layer 122, and a third portion disposed in the second third insulating layer 123. Here, although the second insulating layer 122 in the embodiment has a three-layer structure and it is shown that the cavity 160 is composed of the first to third portions, it is not limited thereto. For example, when the second insulating layer 120 has a two-layer structure, the cavity 160 can include only the first and second portions. For example, when the second insulating layer 122 has a five-layer structure, the cavity 160 can include the first to fifth portions. However, the cavity 160 in the embodiment is characterized in that the part disposed at the lowermost part has a groove shape instead of a through-hole shape. As a result, as shown in FIG. 10, the cavity 160 is formed through a plurality of processes and can be divided into a plurality of portions having different inclination angles from each other.

[0176] Next, as shown in FIG. 9, after removing the mask 310 used for forming the cavity 160, protective layers 151 and 152 are formed on the outermost contours of the second insulating layer 120 and the third insulating layer 130.

[0177] For example, a first protective layer 151 can be disposed on the upper surface of the insulating layer disposed at the uppermost part among the plurality of insulating layers. For example, a first protective layer 151 can be disposed on the upper surface of the second third insulating layer 123 disposed at the uppermost part of the second insulating layer 120. Also, a second protective layer 152 can be disposed on the lower surface of the insulating layer disposed at the lowermost part among the plurality of insulating layers. For example, a second protective layer 152 can be disposed on the lower surface of the third third insulating layer 133 disposed at the lowermost part of the third insulating layer 130.

[0178] The first protective layer 151 and the second protective layer 152 can each have an opening. For example, the first protective layer 151 can have an opening that exposes the surface of the fifth circuit pattern to be exposed among the fifth circuit patterns 145 disposed on the upper surface of the second third insulating layer 123.

[0179] Further, the second protective layer 152 can have an opening that exposes the surface of the eighth circuit pattern to be exposed among the eighth circuit patterns 148 disposed on the lower surface of the third - third insulating layer 133.

[0180] As described above, the features, structures, effects, etc. described in the embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Further, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified and implemented for other embodiments by those with ordinary knowledge in the field to which the embodiments belong. Therefore, the content related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0181] As described above, the description has been centered on the embodiments, but this is merely an illustration and does not limit the embodiments. It can be understood that those with ordinary knowledge in the field to which the embodiments belong can make various modifications and applications not exemplified above without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be implemented with modifications. And the differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined by the appended claims.

Claims

1. A base insulating layer, an upper insulating layer disposed on the base insulating layer and including a cavity, a circuit pattern embedded in the upper insulating layer, and an electronic element disposed in the cavity of the upper insulating layer, wherein the upper insulating layer includes an inner wall surface forming the cavity, the inner wall surface includes a first surface having a first inclination angle with respect to the upper surface of the base insulating layer, and a second surface disposed on the first surface and having a second inclination angle different from the first inclination angle with respect to the upper surface of the base insulating layer, the circuit pattern includes a via electrode overlapping with the first surface of the cavity along a horizontal direction parallel to the upper surface of the base insulating layer, and a wiring portion disposed on the via electrode and not overlapping with the first surface along the horizontal direction but overlapping with the second surface along the horizontal direction, the electronic element is a circuit board overlapping with the via electrode and the wiring portion along the horizontal direction.

2. The circuit board according to claim 1, further including a protective insulating layer disposed on the upper insulating layer.

3. The circuit board further includes a circuit layer embedded in the base insulating layer, the circuit layer includes a base via electrode penetrating at least a partial region of the base insulating layer, and a base wiring layer connected to the base via electrode, wherein the thickness of the wiring portion in a vertical direction perpendicular to the horizontal direction is the same as the thickness of the base wiring layer in the vertical direction. The circuit board according to claim 2.

4. The circuit pattern further includes an upper via electrode disposed on the via electrode, wherein the upper via electrode does not overlap with the first surface along the horizontal direction but overlaps with the second surface along the horizontal direction. The circuit board according to claim 3.

5. The electronic element is spaced apart from the first surface and the second surface along the horizontal direction. The circuit board according to claim 4.

6. The cavity of the upper insulating layer includes a contact portion where the first surface and the second surface are in direct contact, wherein the electronic element overlaps with the contact portion along the horizontal direction. The circuit board according to claim 5.

7. The via electrode is disposed adjacent to the base insulating layer rather than the contact portion. The circuit board according to claim 6.

8. The first inclination angle has an inclination angle between 60° and 80°, and the second inclination angle has an inclination angle between 50° and 60°. The circuit board according to claim 1.

9. The protective insulating layer includes a through hole, The circuit board according to claim 2, wherein at least a part of the through hole of the protective insulating layer overlaps with the cavity along a vertical direction perpendicular to the horizontal direction.

10. The circuit board according to claim 1, wherein the base insulating layer and the upper insulating layer are made of the same material.

11. The circuit board according to claim 3, wherein the thickness of the electronic element in the vertical direction is greater than the thickness of the via electrode in the vertical direction.

12. The circuit board according to claim 4, wherein the upper via electrode and the via electrode gradually decrease in width toward the base insulating layer.

13. A base insulating layer, an upper insulating layer disposed on the base insulating layer and including a cavity, a circuit pattern embedded in the upper insulating layer, an electronic element disposed in the cavity of the upper insulating layer, and a protective insulating layer disposed on the upper insulating layer, wherein the upper insulating layer includes an inner wall surface forming the cavity, the inner wall surface includes a first surface having a first inclination angle with respect to the upper surface of the base insulating layer, and a second surface disposed on the first surface and having a second inclination angle smaller than the first inclination angle with respect to the base insulating layer, the circuit pattern includes a via electrode overlapping with the first surface of the cavity along a horizontal direction parallel to the upper surface of the base insulating layer, and a wiring portion disposed on the via electrode and not overlapping with the first surface along the horizontal direction and overlapping with the second surface along the horizontal direction, the electronic element overlaps with the via electrode, the wiring portion, the first surface, the second surface, and the circuit pattern embedded in the upper insulating layer along the horizontal direction, the circuit board.

14. The cavity of the upper insulating layer includes a contact portion where the first surface and the second surface are in direct contact, the electronic element overlaps with the contact portion along the horizontal direction, the circuit board according to claim 13.

15. The circuit board according to claim 14, wherein the thickness of the electronic element in the vertical direction perpendicular to the horizontal direction is greater than the thickness of the via electrode in the vertical direction.

16. The first inclination angle has an inclination angle between 60° and 80°, the second inclination angle has an inclination angle between 50° and 60°, the circuit board according to claim 13.

17. further includes a circuit layer embedded in the base insulating layer, the circuit layer includes a base via electrode penetrating at least a partial region of the base insulating layer, and a base wiring layer connected to the base via electrode, The circuit board according to claim 15, wherein the thickness of the wiring portion in the vertical direction is the same as the thickness of the base wiring layer in the vertical direction.

18. The circuit pattern further includes an upper via electrode disposed on the via electrode, The circuit board according to claim 17, wherein the upper via electrode does not overlap with the first surface along the horizontal direction and overlaps with the second surface along the horizontal direction.

19. The circuit board according to claim 14, wherein the via electrode is disposed adjacent to the base insulating layer rather than the contact portion.

20. The protective insulating layer includes a through hole penetrating the upper surface and the lower surface, The circuit board according to claim 13, wherein at least a part of the through hole of the protective insulating layer overlaps with the cavity along a vertical direction perpendicular to the horizontal direction.

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