Filter circuit

Abstract

To provide a filter circuit capable of having a wide passband with simple constitution.SOLUTION: A filter circuit 1 comprises: an inductor L3 which is provided between a signal path 5 and the ground, and has a first end L3a electrically connected to the ground; a resonator 32 which is provided between the signal path 5 and the ground, and has a first end L32a electrically connected to the ground; and a capacitor C5 which is provided on the signal path 5, and electrically connected to a second end L3b of the inductor L3 and a second end L32b of the resonator 32. The inductor L3 is constituted using an inductor element. The resonator 32 is constituted without using any inductor element.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a filter circuit including a resonator.

Background Art

[0002] Various filters such as low-pass filters, high-pass filters, and band-pass filters are configured using a plurality of resonators. Examples of the resonators used in these filters include LC resonators configured using an inductor and a capacitor, stripline resonators configured using a conductor line (distributed constant line), and surface acoustic wave resonators configured using a surface acoustic wave element. A surface acoustic wave element is an element that utilizes a surface acoustic wave. Surface acoustic wave elements include surface acoustic wave elements that utilize surface acoustic waves and bulk acoustic wave elements that utilize bulk acoustic waves.

[0003] Patent Document 1 discloses a band-pass filter including a plurality of stripline resonators, a first notch circuit including a series circuit of an inductor and a capacitor disposed between a signal input terminal and a ground, and a second notch circuit including a series circuit of an inductor and a capacitor disposed between a signal output terminal and a ground. The first and second notch circuits have a function of increasing the out-of-band attenuation amount of the band-pass filter.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Generally, a filter configured using an elastic wave resonator is suitable for realizing a passing attenuation characteristic that sharply changes in a frequency region near the cutoff frequency, but there is a problem that it is not suitable for realizing a wide passing band. The above problem is not limited to a filter configured using an elastic wave resonator, but applies to all filters configured using a resonator having steep resonance characteristics.

[0006] By the way, in recent years, miniaturization and space saving of small mobile communication devices have been demanded by the market, and miniaturization of filters used in such communication devices has also been demanded. In order to miniaturize a filter, it is desirable to be able to realize desired characteristics with a simple configuration.

[0007] The present invention has been made in view of such problems, and an object thereof is to provide a filter circuit capable of realizing a wide passing band with a simple configuration.

Means for Solving the Problems

[0008] The filter circuit of the present invention includes an input port, an output port, a signal path connecting the input port and the output port, a first inductor provided between the signal path and the ground and having a first end electrically connected to the ground and a second end opposite to the first end, a resonator provided between the signal path and the ground and having a third end electrically connected to the ground and a fourth end opposite to the third end, and a first capacitor provided on the signal path and electrically connected to the second end of the first inductor and the fourth end of the resonator. The first inductor is configured using an inductor element. The resonator is configured without using an inductor element.

Effects of the Invention

[0009] In the filter circuit of the present invention, the first inductor is configured using an inductor element, and the resonator is configured without using an inductor element. One end of each of the first inductor and the resonator is electrically connected to the ground. The first capacitor is electrically connected to the second end of the first inductor and the fourth end of the resonator. Thus, according to the present invention, there is an effect that it is possible to provide a filter circuit capable of realizing a wide passband with a simple configuration.

Brief Description of the Drawings

[0010]

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[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, the schematic configuration of the filter circuit 1 according to one embodiment of the present invention will be described. The filter circuit 1 according to the present embodiment is a band-pass filter that selectively passes signals having frequencies within a predetermined passband.

[0012] The filter circuit 1 according to this embodiment includes at least one resonator configured without using an inductor element. The at least one resonator can be configured using, for example, an elastic wave element. The elastic wave element may be, for example, a bulk elastic wave element or a surface acoustic wave element.

[0013] Next, with reference to FIG. 1, an example of the circuit configuration of the filter circuit 1 will be described. FIG. 1 is a circuit diagram showing the circuit configuration of the filter circuit 1. The filter circuit 1 includes an input port 2 to which a signal is input, an output port 3 that outputs a signal, and a signal path 5 that connects the input port 2 and the output port 3.

[0014] The filter circuit 1 further includes inductors L1, L2, L3, L5, L6, L7 and capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11. The inductors L1 to L3, L5 to L7 and the capacitors C1 to C11 are provided between the input port 2 and the output port 3 in terms of circuit configuration. In this application, the expression "in terms of circuit configuration" is used to refer to the arrangement on the circuit diagram rather than the arrangement in the physical configuration.

[0015] The inductors L1, L2, L7 and the capacitors C1, C4 to C9, C11 are provided on the signal path 5. One end of the inductor L1 is connected to the input port 2. One end of the inductor L2 is connected to the other end of the inductor L1.

[0016] One end of the capacitor C4 is connected to the other end of the inductor L2. One end of the capacitor C5 is connected to the other end of the capacitor C4. One end of the capacitor C6 is connected to the other end of the capacitor C5. One end of the capacitor C7 is connected to the other end of the capacitor C6. One end of the capacitor C8 is connected to the other end of the capacitor C7.

[0017] One end of capacitor C11 is connected to the other end of capacitor C8. One end of inductor L7 is connected to the other end of capacitor C11. The other end of inductor L7 is connected to output port 3.

[0018] Capacitor C1 is connected in parallel to inductor L1. One end of capacitor C9 is connected to one end of capacitor C5. The other end of capacitor C9 is connected to the other end of capacitor C8.

[0019] Inductors L3, L5, L6 and capacitors C2, C3, C10 are provided between signal path 5 and ground. One end of capacitor C2 is connected to the connection point of inductors L1, L2. One end of capacitor C3 is connected to the connection point of inductor L2 and capacitor C4. Each other end of capacitors C2, C3 is connected to ground.

[0020] Inductor L3 has a first end L3a electrically connected to ground and a second end L3b on the opposite side of the first end L3a. L5 has a first end L5a electrically connected to ground and a second end L5b on the opposite side of the first end L5a. The second end L3b of inductor L3 is connected to the connection point of capacitors C4, C5, C9 on signal path 5. The second end L5b of inductor L5 is connected to the connection point of capacitors C6, C7 on signal path 5. In this application, the expression "electrically connected" includes the case of being electrically connected via a metal conductor (including an inductor), but does not include the case of being connected via a capacitor.

[0021] One end of inductor L6 is connected to the connection point of capacitors C8, C9, C11. One end of capacitor C10 is connected to the other end of inductor L6. The other end of capacitor C10 is connected to ground.

[0022] The filter circuit 1 further includes a resonator 31 provided in the signal path 5, a resonator 32 provided between the signal path 5 and the ground, and signal ports 81, 82, 83, 84. The resonator 31 is provided between the signal port 81 and the signal port 82 in terms of circuit configuration. The resonator 32 is provided between the signal port 83 and the signal port 84 in terms of circuit configuration. Each of the resonators 31 and 32 is configured without using an inductor element. In particular, in the present embodiment, each of the resonators 31 and 32 is a surface acoustic wave resonator configured using at least one surface acoustic wave element.

[0023] The filter circuit 1 further includes signal ports 11, 12, 13, 14 respectively connected to the signal ports 81, 82, 83, 84. In FIG. 1, for the sake of convenience, the signal port 12 is depicted as being interposed between one end of the capacitor C9 and one end of the capacitor C5. However, the signal port 12 does not necessarily have to be interposed between one end of the capacitor C9 and one end of the capacitor C5.

[0024] The capacitor C4 is connected in parallel to the resonator 31. The other end of the inductor L2 and one end of each of the capacitors C3 and C4 are connected to one end of the resonator 31 via the signal ports 11 and 81 in sequence. The second end L3b of the inductor L3, the other end of the capacitor C4, and one end of the capacitor C5 are connected to the other end of the resonator 31 via the signal ports 12 and 82 in sequence.

[0025] The resonator 32 has a first end 32a electrically connected to the ground and a second end 32b on the side opposite to the first end 32a. The other end of the capacitor C5 and one end of the capacitor C6 are connected to the second end 32b of the resonator 32 via the signal ports 13 and 83 in sequence. The filter circuit 1 further includes an inductor L4. One end of the inductor L4 is connected to the first end 32a of the resonator 32 via the signal ports 14 and 84 in sequence. The other end of the inductor L4 is connected to the ground.

[0026] The first end 32a of resonator 32 is electrically connected to ground via inductor L4. Capacitor C5 is provided on signal path 5 and is electrically connected to the second end L3b of inductor L3 and the second end 32b of resonator 32. Capacitor C6 is provided on signal path 5 and is electrically connected to the second end L5b of inductor L5 and the second end 32b of resonator 32.

[0027] Filter circuit 1 includes a main body 10 for integrating input port 2, output port 3, signal path 5, signal ports 11 to 14, 81 to 84, resonators 31 and 32, inductors L1 to L7, and capacitors C1 to C11. Hereinafter, the configuration of main body 10 will be described with reference to FIGS. 2 to 4. FIG. 2 is a perspective view showing main body 10. FIGS. 3 and 4 are perspective views showing the element portion of main body 10.

[0028] Main body 10 includes an element portion 50. Element portion 50 is a laminate including a plurality of stacked dielectric layers and a plurality of conductors (a plurality of conductor layers and a plurality of through holes). The inductors L1 to L7 and capacitors C1 to C11 shown in FIG. 1 are constituted by a plurality of dielectric layers and a plurality of conductors. Each of the plurality of dielectric layers is made of a dielectric material. In the present embodiment, low-temperature co-fired ceramics (LTCC) is used as the dielectric material.

[0029] Element portion 50 has a first surface 50A and a second surface 50B located at both ends in the stacking direction T of the plurality of dielectric layers, and four side surfaces 50C to 50F connecting the first surface 50A and the second surface 50B. Side surfaces 50C and 50D face opposite sides, and side surfaces 50E and 50F also face opposite sides. Side surfaces 50C to 50F are perpendicular to the first surface 50A and the second surface 50B.

[0030] Here, as shown in FIGS. 2 to 4, the X direction, Y direction, and Z direction are defined. The X direction, Y direction, and Z direction are orthogonal to each other. In the present embodiment, one direction parallel to the stacking direction T is defined as the Z direction. The Z direction is also one direction parallel to the direction in which the element portion 50 and the mounted component 80 are arranged. Further, the direction opposite to the X direction is defined as the -X direction, the direction opposite to the Y direction is defined as the -Y direction, and the direction opposite to the Z direction is defined as the -Z direction. Further, the expression "when viewed from a predetermined direction (for example, the Z direction)" means viewing an object from a position separated by a predetermined direction or one direction parallel to the predetermined direction.

[0031] As shown in FIGS. 3 and 4, the first surface 50A is located at the Z-direction end of the element portion 50. The first surface 50A is also the upper surface of the element portion 50 and is also a mounting surface for mounting a mounted component described later. The second surface 50B is located at the -Z-direction end of the element portion 50. The second surface 50B is also the bottom surface of the element portion 50. FIG. 3 shows the element portion 50 viewed from the first surface 50A side. FIG. 4 shows the element portion 50 viewed from the second surface 50B side.

[0032] The side surface 50C is located at the -X-direction end of the element portion 50. The side surface 50D is located at the X-direction end of the element portion 50. The side surface 50E is located at the -Y-direction end of the element portion 50. The side surface 50F is located at the Y-direction end of the element portion 50.

[0033] The element portion 50 further includes a plurality of electrodes 111, 112, 113, 114, 115, 116, 117, 118, 119 provided on the second surface 50B of the element portion 50. The electrodes 111, 112, 113 are arranged in this order in the X direction at a position closer to the side surface 50E than the side surface 50F. The electrodes 115, 116, 117 are arranged in this order in the -X direction at a position closer to the side surface 50F than the side surface 50E.

[0034] Electrode 114 is disposed between electrode 113 and electrode 115. Electrode 118 is disposed between electrode 111 and electrode 117. Electrode 119 is disposed between electrode 112 and electrode 116. Also, electrode 119 is disposed substantially at the center of the second surface 50B.

[0035] Electrode 118 corresponds to input port 2. Electrode 114 corresponds to output port 3. Accordingly, input port 2 and output port 3 are provided on the second surface 50B of the element portion 50. Each of electrodes 111, 112, 113, 115, 116, 117, 119 is connected to ground.

[0036] The element portion 50 further includes a plurality of electrodes 121, 122, 123, 124 provided on the first surface 50A of the element portion 50. Electrodes 121 and 122 are arranged in this order in the X direction at a position closer to the side surface 50E than the side surface 50F. Electrodes 123 and 124 are arranged in this order in the -X direction at a position closer to the side surface 50F than the side surface 50E.

[0037] Electrode 121 corresponds to signal port 11. Electrode 122 corresponds to signal port 12. Electrode 123 corresponds to signal port 13. Electrode 124 corresponds to signal port 14. Accordingly, signal ports 11 to 14 are provided on the first surface 50A of the element portion 50.

[0038] The main body 10 further includes a mounted component 80 mounted on the first surface 50A of the element portion 50. The mounted component 80 includes resonators 31 and 32 among the filter circuits shown in FIG. 1.

[0039] The mounted component 80 further includes four electrodes corresponding to the signal ports 81, 82, 83, and 84 respectively. In FIG. 2, for the sake of convenience, the four electrodes are shown with reference numerals 81 to 84 attached. When the mounted component 80 is mounted on the element part 50, the four electrodes with reference numerals 81 to 84 face the electrodes 121 to 124 of the element part 50 respectively. The four electrodes with reference numerals 81 to 84 are physically connected to the electrodes 121 to 124 by, for example, solder bumps 7.

[0040] The main body 10 further includes a sealing portion 90 for sealing the mounted component 80. The sealing portion 90 covers at least a part of the periphery of the mounted component 80 and the first surface 50A of the element part 50. The sealing portion 90 may further cover the side surfaces 50C to 50F of the element part 50. The sealing portion 90 is made of, for example, resin.

[0041] Next, with reference to FIGS. 5(a) to 10(c), an example of a plurality of dielectric layers, a plurality of conductor layers, and a plurality of through holes constituting the element part 50 will be described. In this example, the element part 50 includes 19 stacked dielectric layers. Hereinafter, these 19 dielectric layers will be referred to as the first to 19th dielectric layers in order from the bottom. Also, the first to 19th dielectric layers are represented by reference numerals 51 to 69.

[0042] In FIGS. 5(a) to 10(b), the plurality of circles represent a plurality of through holes. A plurality of through holes are formed in each of the dielectric layers 51 to 69. The plurality of through holes are each formed by filling a conductor paste into a hole for the through hole. Each of the plurality of through holes is connected to an electrode, a conductor layer, or another through hole.

[0043] In FIGS. 5(a) to 10(b), a plurality of specific through holes among the plurality of through holes are labeled. The connection relationship between each of the plurality of specific through holes and an electrode, a conductor layer, or another through hole is described with respect to the connection relationship in the state where the first to 19th dielectric layers 51 to 69 are stacked.

[0044] Figure 5(a) shows the pattern formation surface of the first dielectric layer 51. Electrodes 111 to 119 are formed on the pattern formation surface of the dielectric layer 51. In Figure 5(a), the five through-holes marked with reference numeral 51T1 are connected to electrodes 112, 113, 115, 116, and 119. In the following description, the through-holes marked with reference numeral 51T1 will be simply referred to as through-holes 51T1. Also, one or more through-holes marked with reference numerals other than 51T1 will be described in the same manner as through-holes 51T1.

[0045] Figure 5(b) shows the pattern formation surface of the second dielectric layer 52. Conductor layers 521, 522, 523, 524, and 525 are formed on the pattern formation surface of the dielectric layer 52. The conductor layer 525 is connected to the conductor layer 523. In Figure 5(b), the boundary between the conductor layer 523 and the conductor layer 525 is indicated by a dotted line. One of the five through-holes 51T1 is connected to the conductor layer 523. The other four of the five through-holes 51T1 and the through-holes 52T3, 52T4, and 52T5 shown in Figure 5(b) are connected to the conductor layer 525.

[0046] Figure 5(c) shows the pattern formation surface of the third dielectric layer 53. Conductor layers 531, 532, and 533 are formed on the pattern formation surface of the dielectric layer 53. The through-hole 53T1a shown in Figure 5(c) is connected to the conductor layer 531. The through-holes 52T3 and 52T5 are connected to the through-holes 53T3 and 53T5 shown in Figure 5(c), respectively. The through-hole 52T4 and the through-hole 53T4 shown in Figure 5(c) are connected to the conductor layer 533.

[0047] FIG. 6(a) shows the pattern formation surface of the fourth dielectric layer 54. A conductor layer 541 is formed on the pattern formation surface of the dielectric layer 54. The through hole 54T1b shown in FIG. 6(a) is connected to the conductor layer 541. The through holes 53T1a, 53T3, 53T4, 53T5 are connected to the through holes 54T1a, 54T3, 54T4, 54T5 shown in FIG. 6(a), respectively.

[0048] FIG. 6(b) shows the pattern formation surfaces of the fifth and sixth dielectric layers 55, 56. The through holes 54T1a, 54T1b, 54T3, 54T4, 54T5 are connected to the through holes 55T1a, 55T1b, 55T3, 55T4, 55T5 formed in the dielectric layer 55, respectively. Also, in the dielectric layers 55, 56, the through holes with the same reference numerals adjacent to each other vertically are connected to each other.

[0049] FIG. 6(c) shows the pattern formation surface of the seventh dielectric layer 57. A conductor layer 571 is formed on the pattern formation surface of the dielectric layer 57. The through holes 55T1a, 55T1b, 55T3, 55T5 formed in the dielectric layer 56 are connected to the through holes 57T1a, 57T1b, 57T3, 57T5 shown in FIG. 6(c), respectively. The through hole 55T4 formed in the dielectric layer 56 and the through hole 57T4 shown in FIG. 6(c) are connected to the conductor layer 571.

[0050] FIG. 7(a) shows the pattern formation surfaces of the eighth and ninth dielectric layers 58, 59. The through holes 57T1a, 57T1b, 57T3, 57T4, 57T5 are connected to the through holes 58T1a, 58T1b, 58T3, 58T4, 58T5 formed in the dielectric layer 58, respectively. Also, in the dielectric layers 58, 59, the through holes with the same reference numerals adjacent to each other vertically are connected to each other.

[0051] FIG. 7(b) shows the pattern formation surface of the tenth dielectric layer 60. Conductor layers 602, 606, and 607 for inductors are formed on the pattern formation surface of the dielectric layer 60. Through holes 58T1a, 58T1b, 58T3, 58T4, and 58T5 formed in the dielectric layer 59 are connected to through holes 60T1a, 60T1b, 60T3, 60T4, and 60T5 shown in FIG. 7(b), respectively.

[0052] FIG. 7(c) shows the pattern formation surface of the eleventh dielectric layer 61. Conductor layers 612, 614, 616, and 617 for inductors are formed on the pattern formation surface of the dielectric layer 61. Through holes 60T1a, 60T1b, 60T3, and 60T5 are connected to through holes 61T1a, 61T1b, 61T3, and 61T5 shown in FIG. 7(c), respectively. Through hole 60T4 and through hole 61T4 shown in FIG. 7(c) are connected to the conductor layer 614.

[0053] FIG. 8(a) shows the pattern formation surface of the twelfth dielectric layer 62. Conductor layers 622, 623, 626, and 627 for inductors are formed on the pattern formation surface of the dielectric layer 62. Through holes 61T1a, 61T1b, 61T4, and 61T5 are connected to through holes 62T1a, 62T1b, 62T4, and 62T5 shown in FIG. 8(a), respectively. Through hole 61T3 and the two through holes 62T3 shown in FIG. 8(a) are connected to the conductor layer 623.

[0054] FIG. 8(b) shows the pattern formation surface of the thirteenth dielectric layer 63. Conductor layers 632, 633, 635, 636, and 637 for inductors are formed on the pattern formation surface of the dielectric layer 63. Through holes 62T1a, 62T1b, and 62T4 are connected to through holes 63T1a, 63T1b, and 63T4 shown in FIG. 8(b), respectively. The two through holes 62T3 and through hole 63T3 shown in FIG. 8(b) are connected to the conductor layer 633. Through hole 62T5 and the two through holes 63T5 shown in FIG. 8(b) are connected to the conductor layer 635.

[0055] Figure 8(c) shows the pattern formation surface of the 14th dielectric layer 64. On the pattern formation surface of the dielectric layer 64, conductor layers 641a, 641b, 642, 643, 644, 646, 647, 648, and a conductor layer 645 for an inductor are formed. The conductor layer 646 is connected to the conductor layer 644. In Figure 8(c), the boundary between the conductor layer 644 and the conductor layer 646 is indicated by a dotted line. The through-hole 63T1a and the through-hole 64T1a shown in Figure 8(c) are connected to the conductor layer 641a. The through-hole 63T1b and the through-hole 64T1b shown in Figure 8(c) are connected to the conductor layer 641b. The through-holes 63T3 and 63T4 are connected to the through-holes 64T3 and 64T4 shown in Figure 8(c), respectively. The two through-holes 63T5 and the through-hole 64T5 shown in Figure 8(c) are connected to the conductor layer 645.

[0056] Figure 9(a) shows the pattern formation surface of the 15th dielectric layer 65. On the pattern formation surface of the dielectric layer 65, conductor layers 651, 652, 653, 654 are formed. The conductor layer 654 is connected to the conductor layer 653. In Figure 9(a), the boundary between the conductor layer 653 and the conductor layer 654 is indicated by a dotted line. The through-holes 64T1a, 64T1b, 64T3, 64T4, 64T5 are connected to the through-holes 65T1a, 65T1b, 65T3, 65T4, 65T5 shown in Figure 9(a), respectively. The through-holes 65T7 and 65T8 shown in Figure 9(a) are connected to the conductor layers 651 and 652, respectively.

[0057] FIG. 9(b) shows the pattern formation surface of the 16th dielectric layer 66. Conductor layers 661, 662, and 663 are formed on the pattern formation surface of the dielectric layer 66. The conductor layer 662 is connected to the conductor layer 661. In FIG. 9(b), the boundary between the conductor layer 661 and the conductor layer 662 is indicated by a dotted line. The through holes 65T1a, 65T1b, 65T3, 65T4, 65T5, 65T7, and 65T8 are respectively connected to the through holes 66T1a, 66T1b, 66T3, 66T4, 66T5, 66T7, and 66T8 shown in FIG. 9(b). The through hole 66T6 shown in FIG. 9(b) is connected to the conductor layer 661.

[0058] FIG. 9(c) shows the pattern formation surface of the 17th dielectric layer 67. Conductor layers 671, 672, 673, 675, 676, and 677 for inductors are formed on the pattern formation surface of the dielectric layer 67. The conductor layer 671 has a first end and a second end that are located on opposite sides of each other in the longitudinal direction of the conductor layer 671. The through hole 66T1a and the through hole 67T1a shown in FIG. 9(c) are connected to the vicinity of the first end of the conductor layer 671. The through hole 66T1b and the through hole 67T1b shown in FIG. 9(c) are connected to the vicinity of the second end of the conductor layer 671. The through holes 66T3, 66T7 and the two through holes 67T3 shown in FIG. 9(c) are connected to the conductor layer 673. The through holes 66T4, 66T6 are respectively connected to the through holes 67T4, 67T6 shown in FIG. 9(c). The through holes 66T5, 66T8 and the two through holes 67T5 shown in FIG. 9(c) are connected to the conductor layer 675.

[0059] Figure 10(a) shows the pattern formation surface of the 18th dielectric layer 68. On the pattern formation surface of the dielectric layer 68, conductor layers 681, 682, 683, 684, 685, 686, 687 for inductors are formed. The conductor layer 681 has a first end and a second end that are located on opposite sides in the longitudinal direction of the conductor layer 681. The through-hole 67T1a is connected to a vicinity portion of the first end of the conductor layer 681. The through-hole 67T1b is connected to a vicinity portion of the second end of the conductor layer 681. The through-hole 68T1 shown in FIG. 10(a) is connected to the conductor layer 682. The two through-holes 67T3 and the through-hole 68T2 shown in FIG. 10(a) are connected to the conductor layer 683. The through-hole 67T4 and the through-hole 68T4 shown in FIG. 10(a) are connected to the conductor layer 684. The two through-holes 67T5 are connected to the conductor layer 685. The through-hole 67T6 is connected to the through-hole 68T3 shown in FIG. 10(a).

[0060] Figure 10(b) shows the pattern formation surface of the 19th dielectric layer 69. On the pattern formation surface of the dielectric layer 69, conductor layers 691, 692, 693, 694 are formed. The through-hole 68T1 and the through-hole 69T1 shown in FIG. 10(b) are connected to the conductor layer 691. The through-hole 68T2 and the through-hole 69T2 shown in FIG. 10(b) are connected to the conductor layer 692. The through-hole 68T3 and the through-hole 69T3 shown in FIG. 10(b) are connected to the conductor layer 693. The through-hole 68T4 and the through-hole 69T4 shown in FIG. 10(b) are connected to the conductor layer 694.

[0061] Figure 10(c) shows the surface opposite to the pattern formation surface of the 19th dielectric layer 69. Hereinafter, the surface opposite to the pattern formation surface of the dielectric layer 69 is referred to as the electrode formation surface of the dielectric layer 69. Electrodes 121, 122, 123, 124 are formed on the electrode formation surface of the dielectric layer 69. The through-holes 69T1, 69T2, 69T3, 69T4 are connected to the electrodes 121, 122, 123, 124, respectively.

[0062] The element section 50 is configured by laminating the dielectric layers 51 to 69 of the first layer to the 19th layer such that the pattern formation surface of the first layer dielectric layer 51 becomes the second surface 50B of the element section 50 and the electrode formation surface of the 19th layer dielectric layer 69 becomes the first surface 50A of the element section 50.

[0063] Each of the plurality of through-holes shown in FIGS. 5(a) to 10(b) is connected to a conductor layer overlapping in the stacking direction T or another through-hole overlapping in the stacking direction T when the dielectric layers 51 to 69 of the first layer to the 19th layer are laminated. Further, among the plurality of through-holes shown in FIGS. 5(a) to 10(b), the through-holes located within the electrode or the conductor layer are connected to that electrode or that conductor layer.

[0064] FIG. 11 shows the inside of the element section 50 configured by laminating the dielectric layers 51 to 69 of the first layer to the 19th layer. As shown in FIG. 11, inside the element section 50, a plurality of conductor layers and a plurality of through-holes shown in FIGS. 5(a) to 10(c) are laminated.

[0065] Hereinafter, the correspondence between the components of the filter circuit 1 shown in FIG. 1 and the components inside the element section 50 shown in FIGS. 5(a) to 10(c) will be described. The inductor L1 is composed of conductor layers 671 and 681 for the inductor, conductor layers 641a and 641b, and through-holes 53T1a, 54T1a, 54T1b, 55T1a, 55T1b, 57T1a, 57T1b, 58T1a, 58T1b, 60T1a, 60T1b, 61T1a, 61T1b, 62T1a, 62T1b, 63T1a, 63T1b, 64T1a, 64T1b, 65T1a, 65T1b, 66T1a, 66T1b, 67T1a, 67T1b.

[0066] The inductor L2 is composed of conductor layers 602, 612, 622, 632, 672, and 682 for the inductor and a plurality of through-holes connecting these conductor layers. The conductor layer 682 is connected to the electrode 121 via the through-hole 68T1, the conductor layer 691, and the through-hole 69T1.

[0067] Inductor L3 is composed of conductor layers 623, 633, 673, 683 for the inductor and through holes 62T3, 63T3, 64T3, 65T3, 66T3, 67T3. Conductor layer 683 is connected to electrode 122 via through hole 68T2, conductor layer 692, and through hole 69T2.

[0068] Inductor L4 is composed of conductor layers 614, 684 for the inductor, conductor layers 533, 571, and through holes 52T4, 53T4, 54T4, 55T4, 57T4, 58T4, 60T4, 61T4, 62T4, 63T4, 64T4, 65T4, 66T4, 67T4.

[0069] Inductor L5 is composed of conductor layers 635, 645, 675, 685 for the inductor and through holes 63T5, 64T5, 65T5, 66T5, 67T5.

[0070] Inductor L6 is composed of conductor layers 606, 616, 626, 636, 676, 686 for the inductor and a plurality of through holes connecting these conductor layers. Inductor L7 is composed of conductor layers 607, 617, 627, 637, 677, 687 for the inductor and a plurality of through holes connecting these conductor layers.

[0071] Capacitor C1 is composed of conductor layers 521, 522, 531, 541 and dielectric layers 52, 53 between these conductor layers. Capacitor C2 is composed of electrodes 111, 117, conductor layers 521, 522, and dielectric layer 51 between electrodes 111, 117 and conductor layers 521, 522.

[0072] Capacitor C3 is composed of conductor layers 633, 642 and dielectric layer 63 between these conductor layers. Capacitor C4 is composed of conductor layers 643, 651 and dielectric layer 64 between these conductor layers.

[0073] The capacitor C5 is composed of conductor layers 651 and 661 and a dielectric layer 65 between these conductor layers. The capacitor C6 is composed of conductor layers 652 and 662 and a dielectric layer 65 between these conductor layers.

[0074] The capacitor C7 is composed of conductor layers 644 and 652 and a dielectric layer 64 between these conductor layers. The capacitor C8 is composed of conductor layers 646 and 653 and a dielectric layer 64 between these conductor layers. The capacitor C9 is composed of conductor layers 636 and 647 and a dielectric layer 63 between these conductor layers.

[0075] The capacitor C10 is composed of conductor layers 523 and 532 and a dielectric layer 52 between these conductor layers. The capacitor C11 is composed of conductor layers 648, 654, and 663 and dielectric layers 64 and 65 between these conductor layers.

[0076] Next, with reference to FIGS. 2 to 12, the structural features of the filter circuit 1 according to the present embodiment will be described. FIG. 12 is a plan view showing the inside of the element section 50.

[0077] First, two regions of the element section 50 defined by the mounted component 80 will be described. As described above, the mounted component 80 is mounted on the first surface 50A of the element section 50. The element section 50 includes a first region R1 that overlaps the mounted component 80 when viewed in the stacking direction T and a second region R2 that does not overlap the mounted component 80 when viewed in the stacking direction T. The first region R1 is defined as a three-dimensional region whose Z-direction end exists on the first surface 50A and whose -Z-direction end exists on the second surface 50B. In FIG. 12, the outer edge of the first region R1 including the X-direction end, -X-direction end, Y-direction end, and -Y-direction end of the first region R1 is shown by a two-dot chain line of a rectangle labeled R1.

[0078] The second region R2 is defined as the region obtained by removing the first region R1 from a three-dimensional region substantially surrounded by the outer peripheral surface of the element portion 50. The second region R2 covers at least a part of the outer peripheral portion of the first region R1. In particular, in the present embodiment, the second region R2 covers a portion of the outer peripheral portion of the first region R1 excluding the end in the Z direction (the first surface 50A) and the end in the -Z direction (the second surface 50B). In FIG. 12, the outer edge portion of the second region R2 including the end in the X direction, the end in the -X direction, the end in the Y direction, and the end in the -Y direction of the second region R2 is indicated by a two-dot chain line of a rectangle with the symbol R2. Note that, in FIG. 12, for the sake of convenience, the outer edge portion of the second region R2 is drawn away from the side surfaces 50C to 50F of the element portion 50.

[0079] The planar shape of the mounted component 80 (the shape as viewed from the stacking direction T) may be the same as the shape of the first region R1. Alternatively, the mounted component 80 may include a first portion having the same planar shape as the shape of the first region R1 and a second portion having a planar shape size different from the planar shape size of the first region R1. In this case, the mounted component 80 is mounted on the element portion 50 in a posture such that the first portion is located between the element portion 50 and the second portion.

[0080] Next, the characteristics regarding the inductors L2, L3, L5, L6, L7 will be described. The inductor L2 is wound around an axis extending in a direction parallel to the stacking direction T so that an opening surrounded by the inductor L2 is formed. Hereinafter, the opening surrounded by the inductor L2 will be referred to as the opening of the inductor L2. The opening of the inductor L2 faces the first surface 50A of the element portion 50. Further, the entire opening of the inductor L2 exists in the second region R2. Hereinafter, for the inductors other than the inductor L2, the opening surrounded by the inductor will also be referred to as the opening of the inductor.

[0081] Similarly, each of the inductors L3, L5, L6, and L7 is wound around an axis extending in a direction parallel to the stacking direction T such that an opening surrounded by each of the inductors L3, L5, L6, and L7 is formed. The opening of each of the inductors L3, L5, L6, and L7 faces the first surface 50A of the element portion 50. Most of the opening of each of the inductors L3 and L5 exists in the second region R2. The entire opening of each of the inductors L6 and L7 exists in the second region R2.

[0082] The inductor L2 includes a plurality of conductor layers 602, 612, 622, 632, 672, and 682 for inductors arranged at a predetermined interval in the stacking direction T. Each of the conductor layers 602, 612, 622, 632, 672, and 682 is wound around an axis extending in a direction parallel to the stacking direction T so as to surround the opening of the inductor L2.

[0083] The inductor L3 includes a plurality of conductor layers 623, 633, 673, and 683 for inductors arranged at a predetermined interval in the stacking direction T. Each of the conductor layers 623, 633, 673, and 683 is wound around an axis extending in a direction parallel to the stacking direction T so as to surround the opening of the inductor L3.

[0084] The inductor L5 includes a plurality of conductor layers 635, 645, 675, and 685 for inductors arranged at a predetermined interval in the stacking direction T. Each of the conductor layers 635, 645, 675, and 685 is wound around an axis extending in a direction parallel to the stacking direction T so as to surround the opening of the inductor L5.

[0085] The inductor L6 includes a plurality of conductor layers 606, 616, 626, 636, 676, and 686 for inductors arranged at a predetermined interval in the stacking direction T. Each of the conductor layers 626, 636, 676, and 686 is wound around an axis extending in a direction parallel to the stacking direction T so as to surround the opening of the inductor L6. Each of the conductor layers 606 and 616 extends along the opening of the inductor L6.

[0086] Inductor L7 includes a plurality of conductor layers 607, 617, 627, 637, 677, 687 for inductors arranged at a predetermined interval in the stacking direction T. Each of the conductor layers 627, 637, 677, 687 is wound around an axis extending in a direction parallel to the stacking direction T so as to surround the opening of the inductor L7. Each of the conductor layers 607, 617 extends along the opening of the inductor L7.

[0087] Next, the characteristics regarding inductors L1 and L4 will be described. Inductor L1 is wound around an axis extending in a direction orthogonal to the stacking direction T such that an opening surrounded by the inductor L1 is formed. The opening of the inductor L1 faces the side surface 50C of the element portion 50.

[0088] Inductor L4 has a shape such that an opening surrounded by the inductor L4 is not formed.

[0089] Next, with reference to FIGS. 1, 5 to 12, the characteristics regarding the connection of inductors L3, L4, L5, capacitors C5, C6 and resonator 32 will be described. As described above, each of the inductors L3, L4, L5 is configured using an inductor element configured using a plurality of conductors of the element portion 50. On the other hand, the resonator 32 is configured without using an inductor element.

[0090] The resonator 32 is provided between the signal port 83 and the signal port 84. The conductor layer 684 constituting the inductor L4 is connected to the electrode corresponding to the signal port 84 via the through hole 68T4, the conductor layer 694, the through hole 69T4 and the electrode 124. The through hole 52T4 constituting the inductor L4 is connected to the electrodes 112, 113, 115, 116, 119 connected to the ground via a plurality of through holes 51T1 and the conductor layer 525.

[0091] The first end 32a of the resonator 32 is electrically connected to the signal port 84. Accordingly, the first end 32a of the resonator 32 is electrically connected to the ground via a plurality of through holes 51T1, conductor layer 525, inductor L4, through hole 68T4, conductor layer 694, through hole 69T4, and electrode 124. The inductor L4 electrically connects the first end 32a of the resonator 32 to the ground.

[0092] The conductor layer 661 forming the capacitor C5 is connected to the electrode corresponding to the signal port 83 via through holes 66T6, 67T6, 68T3, conductor layer 693, through hole 69T3, and electrode 123. The conductor layer 662 forming the capacitor C6 is connected to the electrode corresponding to the signal port 83 via the conductor layer 661, through holes 66T6, 67T6, 68T3, conductor layer 693, through hole 69T3, and electrode 123.

[0093] The second end 32b of the resonator 32 is electrically connected to the signal port 83. Accordingly, the second end 32b of the resonator 32 is electrically connected to the capacitor C5 via through holes 66T6, 67T6, 68T3, conductor layer 693, through hole 69T3, and electrode 123, and is also electrically connected to the capacitor C6 via the conductor layer 661, through holes 66T6, 67T6, 68T3, conductor layer 693, through hole 69T3, and electrode 123.

[0094] The portion where the through hole 61T3 contacts the conductor layer 623 for the inductor forming the inductor L3 corresponds to the first end L3a of the inductor L3. The first end L3a of the inductor L3 is electrically connected to the electrodes 112, 113, 115, 116, 119 connected to the ground via a plurality of through holes 51T1, conductor layer 525, and through holes 52T3, 53T3, 54T3, 55T3, 57T3, 58T3, 60T3, 61T3.

[0095] The portion where the through-hole 66T7 contacts the conductor layer 673 for the inductor constituting the inductor L3 corresponds to the second end L3b of the inductor L3. The second end L3b of the inductor L3 is electrically connected to the conductor layer 651 constituting the capacitor C5 via the through-holes 65T7, 66T7. The capacitor C5 is electrically connected to the second end L3b of the inductor L3 and the second end 32b of the resonator 32.

[0096] The portion where the through-hole 62T5 contacts the conductor layer 635 for the inductor constituting the inductor L5 corresponds to the first end L5a of the inductor L5. The first end L5a of the inductor L5 is electrically connected to the electrodes 112, 113, 115, 116, 119 connected to the ground via a plurality of through-holes 51T1, the conductor layer 525, and the through-holes 52T5, 53T5, 54T5, 55T5, 57T5, 58T5, 60T5, 61T5, 62T5.

[0097] The portion where the through-hole 66T8 contacts the conductor layer 675 for the inductor constituting the inductor L5 corresponds to the second end L5b of the inductor L5. The second end L5b of the inductor L5 is electrically connected to the conductor layer 652 constituting the capacitor C6 via the through-holes 65T8, 66T8. The capacitor C6 is electrically connected to the second end L5b of the inductor L5 and the second end 32b of the resonator 32.

[0098] Next, with reference to FIGS. 2 to 4 and FIG. 12, the characteristics regarding the arrangement of the inductors L3, L5, the capacitors C5, C6, and the resonator 32 will be described. The mounting component 80 includes the resonator 32. Therefore, when viewing the main body 10 from the Z direction, the resonator 32 overlaps with the first region R1. As shown in FIG. 12, the inductor L3 and the inductor L5 are arranged so as to sandwich most of the first region R1 when viewing the main body 10 from the Z direction. From these facts, the inductor L3 and the inductor L5 are arranged so as to sandwich at least a part of the resonator 32 when viewing the main body 10 from the Z direction.

[0099] Also, as shown in FIG. 12, the entire capacitor C5 is present in the first region R1. A part of the capacitor C6 is present in the first region. The inductors L3 and L5 are arranged so as to sandwich the capacitors C5 and C6 when the main body 10 is viewed from the Z direction.

[0100] Next, the operation and effects of the filter circuit 1 according to the present embodiment will be described. The filter circuit 1 according to the present embodiment includes inductors L3 and L5 configured using inductor elements, and a resonator 32 configured without using an inductor element. The first end L3a of the inductor L3, the first end L5a of the inductor L5, and the first end 32a of the resonator 32 are electrically connected to the ground. The capacitor C5 is electrically connected to the second end L3b of the inductor L3 and the second end 32b of the resonator 32. The capacitor C6 is electrically connected to the second end L5b of the inductor L5 and the second end 32b of the resonator 32. With such a configuration, according to the present embodiment, the passband of the filter circuit 1 can be widened. Hereinafter, this effect will be described with reference to the results of simulation. Note that the following description assumes that the passband of the filter circuit 1 is 5.15 to 7.125 GHz. Hereinafter, this passband will be referred to as the assumed passband.

[0101] First, a first circuit including a resonator 132 corresponding to the resonator 32 will be described. FIG. 13 is a circuit diagram showing the first circuit. The first circuit includes an input port 102, an output port 103, a signal path 105 connecting the input port 102 and the output port 103, a resonator 132 provided between the signal path 105 and the ground, and resistors R101 and R102 provided in the signal path 105. One end of the resonator 132 is electrically connected to the ground. The other end of the resonator 132 is connected to the connection point of the resistors R101 and R102 and is also electrically connected to the input port 102 and the output port 103. In the simulation, the resistance values of the resistors R101 and R102 are each set to 0 Ω.

[0102] FIG. 14 is a characteristic diagram showing the characteristics of the first circuit obtained by simulation. In FIG. 14, the horizontal axis represents frequency, and the vertical axis represents attenuation. Also, in FIG. 14, the curve marked with reference numeral 91 shows the transmission attenuation characteristic between the input port 102 and the output port 103, and the curve marked with reference numeral 92 shows the reflection attenuation characteristic at the input port 102. Note that the reflection attenuation characteristic at the output port 103 is almost the same as the reflection attenuation characteristic at the input port 102. In the first circuit, the attenuation amount of the reflection attenuation characteristic at 5.15 GHz (hereinafter referred to as the reflection attenuation amount) is -9.221 dB, and the reflection attenuation amount at 5.9 GHz is -6.518 dB.

[0103] As shown in FIG. 14, in the reflection attenuation characteristic of the first circuit, it can be seen that an attenuation pole is formed in the assumed passband, and the absolute value of the reflection attenuation amount rapidly decreases as the frequency increases from the attenuation pole.

[0104] Next, a second circuit including an inductor L103, a capacitor C105, and a resonator 132 corresponding to the inductor L3, the capacitor C5, and the resonator 32 will be described. FIG. 15 is a circuit diagram showing the second circuit. The second circuit includes an inductor L103 and a capacitor C105 instead of the resistors R101 and R102 in the first circuit. The inductor L103 is provided between the signal path 105 and the ground. One end of the inductor L103 is electrically connected to the ground.

[0105] The capacitor C105 is provided in the signal path 105 and is electrically connected to the other end of the inductor L103 and the other end of the resonator 132. Note that in the second circuit, the other end of the inductor L103 is electrically connected to the input port 102, and the other end of the resonator 132 is electrically connected to the output port 103.

[0106] In the simulation, the inductance of the inductor L103 is set to 1 nH, and the capacitance of the capacitor C105 is set to 1.3 pF.

[0107] FIG. 16 is a characteristic diagram showing the characteristics of the second circuit obtained by simulation. In FIG. 16, the horizontal axis represents frequency, and the vertical axis represents attenuation. Also, in FIG. 16, the curve labeled 93 shows the transmission attenuation characteristic between the input port 102 and the output port 103, the curve labeled 94 shows the reflection attenuation characteristic at the input port 102, and the curve labeled 95 shows the reflection attenuation characteristic at the output port 103. In the second circuit, the reflection attenuation amount at 5.15 GHz is -5.233 dB, and the reflection attenuation amount at 5.9 GHz is -6.234 dB.

[0108] As shown in FIG. 16, in the second circuit, in the assumed passband, as the frequency increases, the absolute value of the reflection attenuation amount increases. From this result, it can be seen that the bandpass filter including the second circuit can widen the passband to the high-frequency side compared to the bandpass filter including the first circuit. That is, according to the present embodiment, by adopting a relatively simple configuration of providing the inductor L3 and the capacitor C5, a wide passband can be realized.

[0109] Next, a third circuit including inductors L3, L5, capacitors C5, C6, and resonators 32 corresponding inductors L103, L105, capacitors C105, C106, and resonator 132 will be described. FIG. 17 is a circuit diagram showing the third circuit. The third circuit includes an inductor L105 and a capacitor C106 in addition to the components of the second circuit. The inductor L105 is provided between the signal path 105 and the ground. One end of the inductor L105 is electrically connected to the ground.

[0110] The capacitor C106 is provided on the signal path 105 and is electrically connected to the other end of the inductor L105 and the other end of the resonator 132. In the third circuit, the other end of the inductor L103 is electrically connected to the input port 102, and the other end of the inductor L105 is electrically connected to the output port 103.

[0111] In the simulation, the inductance of each of inductors L103 and L105 is set to 1 nH, and the capacitance of each of capacitors C105 and C106 is set to 1.3 pF.

[0112] Figure 18 is a characteristic diagram showing the characteristics of the third circuit obtained by simulation. In Figure 18, the horizontal axis represents the frequency, and the vertical axis represents the attenuation amount. Also, in Figure 18, the curve marked with reference numeral 96 shows the transmission attenuation characteristic between input port 102 and output port 103, and the curve marked with reference numeral 97 shows the reflection attenuation characteristic at input port 102. Note that the reflection attenuation characteristic at output port 103 almost coincides with the reflection attenuation characteristic at input port 102. In the third circuit, the reflection attenuation amount at 5.15 GHz is -26.88 dB, and the reflection attenuation amount at 5.9 GHz is -35.31 dB.

[0113] As shown in Figure 18, in the third circuit, the absolute value of the reflection attenuation amount is larger in a wider frequency band including the assumed passband than in the second circuit. From this result, it can be seen that the bandpass filter including the third circuit can widen the passband to the high-frequency side compared to the bandpass filter including the second circuit. That is, according to the present embodiment, by adopting a relatively simple configuration of providing inductors L5 and capacitors C6 in addition to inductor L3 and capacitor C5, a wider passband can be realized.

[0114] Next, a fourth circuit in which inductors L103 and L105 in the third circuit are inductively coupled will be described. Figure 19 is a circuit diagram showing the fourth circuit. The fourth circuit includes an inductor L104 in addition to the components of the third circuit. Inductor L104 electrically connects one end of each of inductors L103, L105, and resonator 132 to the ground.

[0115] In the simulation, the inductance of each of inductors L103, L104, and L105 is set to 1 nH, and the capacitance of each of capacitors C105 and C106 is set to 1.3 pF.

[0116] FIG. 20 is a characteristic diagram showing the characteristics of the fourth circuit obtained by simulation. In FIG. 20, the horizontal axis represents the frequency, and the vertical axis represents the attenuation amount. Also, in FIG. 20, the curve labeled 98 shows the transmission attenuation characteristic between the input port 102 and the output port 103, and the curve labeled 99 shows the reflection attenuation characteristic at the input port 102. Note that the reflection attenuation characteristic at the output port 103 is almost the same as the reflection attenuation characteristic at the input port 102.

[0117] As shown in FIG. 20, in the transmission attenuation characteristic of the fourth circuit, an attenuation pole is formed in the frequency region lower than the assumed transmission band. As can be understood from this result, according to the present embodiment, by inductively coupling the inductors L3 and L5, the absolute value of the attenuation amount of the transmission attenuation characteristic in the frequency region lower than the transmission band can be increased. Note that the inductive coupling of the inductors L3 and L5 can be realized, for example, by the conductor layer 525 and the plurality of through holes 51T1.

[0118] Next, a fifth circuit in which the inductors L103 and L105 in the third circuit are capacitively coupled will be described. FIG. 21 is a circuit diagram showing the fifth circuit. The fifth circuit includes a capacitor C100 in addition to the components of the third circuit. The capacitor C100 is electrically connected to the other ends of the inductors L103 and L105.

[0119] In the simulation, the inductance of each of the inductors L103 and L105 is set to 1 nH, the capacitance of each of the capacitors C105 and C106 is set to 1.3 pF, and the capacitance of the capacitor C100 is set to 0.1 pF.

[0120] FIG. 22 is a characteristic diagram showing the characteristics of the fifth circuit obtained by simulation. In FIG. 22, the horizontal axis represents frequency, and the vertical axis represents attenuation. Also, in FIG. 22, the curve labeled 100 shows the transmission attenuation characteristic between the input port 102 and the output port 103, and the curve labeled 101 shows the reflection attenuation characteristic at the input port 102. Note that the reflection attenuation characteristic at the output port 103 is almost the same as the reflection attenuation characteristic at the input port 102.

[0121] As shown in FIG. 22, in the reflection attenuation characteristic of the fifth circuit, the absolute value of the reflection attenuation amount in the frequency region lower than the assumed passband is small. Therefore, in the band-pass filter including the fifth circuit, due to the capacitive coupling of the inductors L103 and L105, the characteristics in the frequency region lower than the passband deteriorate. In the present embodiment, in order to suppress the capacitive coupling between the inductors L3 and L5, the inductors L3 and L5 are arranged apart from each other. Thereby, according to the present embodiment, it is possible to suppress the deterioration of the characteristics in the frequency region lower than the passband.

[0122] Next, an example of the characteristics of the filter circuit 1 according to the present embodiment will be shown. FIG. 23 is a characteristic diagram showing the transmission attenuation characteristic of the filter circuit 1. In FIG. 23, the horizontal axis represents frequency, and the vertical axis represents attenuation. It can be seen from FIG. 23 that the filter circuit 1 has practically sufficient characteristics as a band-pass filter.

[0123] Next, other effects of the filter circuit 1 according to the present embodiment will be described. In the present embodiment, most of each opening of the inductors L3 and L5 exists in the second region R2. Thereby, according to the present embodiment, it is possible to suppress the electromagnetic field from acting on each of the inductors L3 and L5 and the mounted component 80, and to realize desired characteristics.

[0124] Similarly, in the present embodiment, the entire opening of each of the inductors L2, L6, and L7 is present in the second region R2. Thus, according to the present embodiment, it is possible to suppress the electromagnetic field from acting on each of the inductors L2, L6, and L7 and the mounted component 80 and to realize desired characteristics.

[0125] Note that the present invention is not limited to the above-described embodiment, and various modifications are possible. For example, the filter circuit of the present invention is not limited to a band-pass filter, and can be applied to other filters such as a low-pass filter and a high-pass filter, and electronic components including a plurality of resonators such as a demultiplexer that separates a plurality of signals having different frequency bands.

[0126] As described above, the filter circuit of the present invention includes an input port, an output port, a signal path connecting the input port and the output port, a first inductor provided between the signal path and the ground and having a first end electrically connected to the ground and a second end opposite to the first end, a resonator provided between the signal path and the ground and having a third end electrically connected to the ground and a fourth end opposite to the third end, and a first capacitor provided on the signal path and electrically connected to the second end of the first inductor and the fourth end of the resonator. The first inductor is configured using an inductor element. The resonator is configured without using an inductor element.

[0127] The filter circuit of the present invention may further include a third inductor that electrically connects the third end of the resonator and the ground.

[0128] Further, the filter circuit of the present invention may further include a second inductor provided between the signal path and the ground and having a fifth end electrically connected to the ground and a sixth end opposite to the fifth end, and a second capacitor provided on the signal path and electrically connected to the sixth end of the second inductor and the fourth end of the resonator. The second inductor may be configured using an inductor element.

[0129] When the filter circuit of the present invention includes a second inductor and a second capacitor, the filter circuit of the present invention may further include a main body for integrating an input port, an output port, a first inductor, a second inductor, a resonator, a first capacitor, and a second capacitor. The first inductor and the second inductor may be arranged so as to sandwich the first capacitor and the second capacitor when viewed from a predetermined one direction with respect to the main body. Also, the first inductor and the second inductor may be arranged so as to sandwich at least a part of the resonator when viewed from a predetermined one direction with respect to the main body. The main body may include an element portion including the first inductor, the second inductor, the first capacitor, and the second capacitor, and a mounted component including the resonator and mounted on the element portion.

[0130] In the filter circuit of the present invention, the resonator may be configured using an elastic wave element.

Explanation of Reference Numerals

[0131] 1... Filter circuit, 2... Input port, 3... Output port, 5... Signal path, 7... Solder bump, 10... Main body, 11 - 14... Signal ports, 31, 32... Resonators, 50... Element portion, 50A... First surface, 50B... Second surface, 50C - 50F... Side surfaces, 51 - 69... Dielectric layers, 80... Mounted component, 81 - 84... Signal ports, 90... Sealing portion, 111 - 119, 121 - 124... Electrodes, C1 - C11... Capacitors, L1 - L7... Inductors.

Claims

1. An input port, an output port, a signal path connecting the input port and the output port, a first inductor provided between the signal path and ground, having a first end electrically connected to ground and a second end opposite to the first end, a resonator provided between the signal path and ground, having a third end electrically connected to ground and a fourth end opposite to the third end, a first capacitor provided on the signal path and electrically connected to the second end of the first inductor and the fourth end of the resonator, the first inductor is configured using an inductor element, the resonator is configured without using an inductor element, a filter circuit characterized by this.

2. Furthermore, a filter circuit according to claim 1, characterized by further comprising a third inductor that electrically connects the third end of the resonator and ground.

3. Furthermore, a second inductor provided between the signal path and ground, having a fifth end electrically connected to ground and a sixth end opposite to the fifth end, a second capacitor provided on the signal path and electrically connected to the sixth end of the second inductor and the fourth end of the resonator, the second inductor is configured using an inductor element, a filter circuit according to claim 1, characterized by this.

4. Furthermore, a main body for integrating the input port, the output port, the first inductor, the second inductor, the resonator, the first capacitor, and the second capacitor is provided, a filter circuit according to claim 3, characterized in that the first inductor and the second inductor are arranged so as to sandwich the first capacitor and the second capacitor when viewing the main body from a predetermined one direction.

5. Furthermore, a main body for integrating the input port, the output port, the first inductor, the second inductor, the resonator, the first capacitor, and the second capacitor is provided, a filter circuit according to claim 3, characterized in that the first inductor and the second inductor are arranged so as to sandwich at least a part of the resonator when viewing the main body from a predetermined one direction.

6. The filter circuit according to claim 5, wherein the main body includes an element section including the first inductor, the second inductor, the first capacitor, and the second capacitor, and a mounted component including the resonator and mounted on the element section.

7. The filter circuit according to any one of claims 1 to 6, wherein the resonator is configured using an elastic wave element.

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