Circuit device

Abstract

To provide a circuit device or the like capable of reducing a detection error for current flowing through an inductor.SOLUTION: A circuit device 100 includes an amplifier circuit 160, a target value correction circuit 170, a D / A conversion circuit 190, a comparison circuit 115, and a control circuit 120. The amplifier circuit 160 amplifies an input voltage VIP corresponding to a sense resistor current IS. The target value correction circuit 170 outputs a correction setting value SDAC by correcting a target setting value TS of current. The D / A conversion circuit 190 performs D / A conversion for the correction setting value SDAC. The comparison circuit 115 compares an output voltage VOUT of the amplifier 160 with an output voltage VDAC of the D / A conversion circuit 190. The control circuit 120 controls a switch element based on an output signal COUT of the comparison circuit 115. The target value correction circuit 170 corrects the target setting value TS so that the output signal COUT of the comparison circuit 115 changes if the sense resistor current IS is a current corresponding to the target setting value TS.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a circuit device and the like.

Background Art

[0002] Patent Document 1 discloses a circuit device that drives a motor by a bridge circuit. The circuit device includes a detection circuit, a control circuit, and a bridge circuit. The detection circuit includes a differential amplifier circuit that amplifies the voltage difference between both ends of a sense resistor, a D / A conversion circuit that converts digital data specifying a current value into a reference voltage, and a comparator that compares the voltage output from the differential amplifier circuit with the reference voltage. The control circuit controls the bridge circuit based on the output of the comparator.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, control is performed so that the current flowing through the sense resistor becomes the target current value. However, the detection circuit compares the current flowing through the sense resistor with the target current value by voltage comparison. For this reason, when there are errors due to manufacturing variations, aging deterioration, or the like in the conversion from current or digital data to voltage, the current may not be accurately detected. For example, if there are offsets or the like in the differential amplifier circuit, comparator, or D / A conversion circuit, they will become factors of error in current detection.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a circuit device that controls a switch element, a sense resistor, and an inductor connected in series between a first power supply node and a second power supply node, the circuit device including: an amplification circuit that amplifies an input voltage corresponding to a sense resistor current, which is a current flowing through the sense resistor; a target value correction circuit to which a target set value of a current is input and that outputs a corrected set value by correcting the target set value; a D / A conversion circuit that performs D / A conversion on the corrected set value; a comparison circuit that compares an output voltage of the amplification circuit and an output voltage of the D / A conversion circuit; and a control circuit that controls the switch element based on an output signal of the comparison circuit. The target value correction circuit outputs the corrected set value by correcting the target set value such that an output signal of the comparison circuit changes when the sense resistor current is a current corresponding to the target set value.

Brief Description of the Drawings

[0006]

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MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, preferred embodiments of the present disclosure will be described in detail. It should be noted that the embodiments described below do not unduly limit the content described in the claims, and not all of the configurations described in the embodiments are essential constituent elements. [

[0008] 1. Electronic device and circuit device FIG. 1 shows a first configuration example of an electronic device and a circuit device. The electronic device 300 includes a processing device 200, a circuit device 100, a motor 10, and a sense resistor RS. The sense resistor RS is also called a shunt resistor. Hereinafter, an example in which the circuit device 100 drives the motor 10 will be mainly described. The motor is a DC motor, a stepping motor, or the like. FIG. 1 shows an example in which the circuit device 100 includes a single-phase drive circuit, but when driving a stepping motor or the like, it may include a two-phase drive circuit. Note that the drive target of the circuit device 100 may be an inductor. The inductor is a coil, a solenoid, or the like, and is not limited to a single coil, but may be a coil included in a device such as a motor.

[0009] The processing device 200 transmits the target set value TS of the current IS flowing through the sense resistor RS to the circuit device 100. Hereinafter, the current IS will be referred to as the sense resistor current. The target set value TS is a set value for controlling the drive current of the motor 10, that is, the torque or rotational speed of the motor 10. An example of the processing device 200 is a processor. The processor includes, for example, one or more of a CPU, GPU, microcomputer, DSP, ASIC, or FPGA. CPU is the abbreviation of Central Processing Unit. GPU is the abbreviation of Graphics Processing Unit. DSP is the abbreviation of Digital Signal Processor. ASIC is the abbreviation of Application Specific Integrated Circuit. FPGA is the abbreviation of Field Programmable Gate Array.

[0010] The circuit device 100 controls the drive of the motor 10 so that the sense resistor current IS becomes the current value indicated by the target set value TS. The circuit device 100 includes an interface circuit 105, a current detection circuit 110, a control circuit 120, a drive circuit 150, a terminal TVD, a terminal TSA, a terminal TSB, a terminal TD1, and a terminal TD2. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. Each terminal is, for example, a pad provided on the semiconductor substrate or a terminal provided on a package housing the semiconductor substrate.

[0011] The terminal TD1 is connected to one end of the motor 10, and the terminal TD2 is connected to the other end of the motor 10. The terminal TVD is connected to the power supply node NVD to which the power supply voltage VDD is supplied. One end of the sense resistor RS is connected to the terminals TSA and TSB. The other end of the sense resistor RS is connected to the ground node NGN to which the ground voltage GND is supplied. Note that the power supply node NVD is also referred to as the first power supply node, and the ground node NGN is also referred to as the second power supply node. The voltage supplied to the second power supply node is not limited to the ground voltage GND, and may be a constant voltage lower than the power supply voltage VDD.

[0012] The interface circuit 105 receives the target set value TS from the processing device 200. The interface circuit 105 is a serial communication circuit such as, for example, an SPI, I2C, or UART circuit. SPI is the abbreviation of Serial Peripheral Interface. I2C is the abbreviation of Inter-Integrated Circuit. UART is the abbreviation of Universal Asynchronous Receiver / Transmitter.

[0013] The current detection circuit 110 detects whether the input voltage VIP from the terminal TSB exceeds the voltage corresponding to the current value set by the target set value TS, and outputs the output signal COUT, which is the detection result. The input voltage VIP is the voltage corresponding to the sense resistor current IS, and VIP = RS × IS. Note that the terminal TSB may be omitted from the circuit device 100, and the input voltage VIP from the terminal TSA may be input to the current detection circuit 110.

[0014] The control circuit 120 outputs pre-drive signals CSA to CSD for switching the switch elements of the drive circuit 150 based on the output signal COUT of the current detection circuit 110. The control circuit 120 includes an arithmetic circuit 130 and a switch control circuit 140. The arithmetic circuit 130 generates a switching control signal CSW from the output signal COUT of the current detection circuit 110. The switch control circuit 140 generates pre-drive signals CSA to CSD from the switching control signal CSW.

[0015] The drive circuit 150 includes switch elements SWA to SWD. One end of the switch element SWA is connected to the terminal TVD, and the other end is connected to the terminal TD1. One end of the switch element SWB is connected to the terminal TVD, and the other end is connected to the terminal TD2. One end of the switch element SWC is connected to the terminal TD1, and the other end is connected to the terminal TSA. One end of the switch element SWD is connected to the terminal TD2, and the other end is connected to the terminal TSA. The switch element SWA is controlled to be turned on or off by the pre-drive signal CSA. Similarly, the switch elements SWB to SWD are controlled to be turned on or off by the pre-drive signals CSB to CSD. The switch elements SWA and SWB are so-called high-side transistors, which are P-type MOS transistors or N-type MOS transistors. The switch elements SWC and SWD are so-called low-side transistors, which are N-type MOS transistors.

[0016] The control circuit 120 turns on the switch elements SWA and SWD and turns off the switch elements SWB and SWC during the charge period. The control circuit 120 turns off the switch elements SWA and SWD and turns on the switch elements SWB and SWC during the decay period. Taking the charge period and the decay period together as the drive cycle, the sense resistor current IS is controlled by the duty ratio of the charge period with respect to the cycle. The control circuit 120 controls the drive based on the output signal COUT of the current detection circuit 110, and controls the duty ratio of the charge period so that the sense resistor current IS corresponds to the target set value TS.

[0017] Figure 2 shows a first configuration example of the current detection circuit. The current detection circuit 110 includes an amplifier circuit 160, a target value correction circuit 170, a D / A conversion circuit 190, a comparison circuit 115, and a storage unit 180.

[0018] The amplifier circuit 160 amplifies the input voltage VIP and outputs the amplified voltage as the output voltage VOUT. The amplifier circuit 160 includes an operational amplifier 161, a first resistor RIP, a second resistor RFP, a third resistor RIN, and a fourth resistor RFN.

[0019] One end of the first resistor RIP is connected to the first input terminal of the operational amplifier 161, and the other end is connected to the terminal TSB. The input voltage VIP is input from the terminal TSB to the other end of the first resistor RIP. One end of the second resistor RFP is connected to the first input terminal of the operational amplifier 161, and the other end is connected to the ground node. A reference voltage may be input to the other end of the second resistor RFP. Here, an example where the reference voltage is the ground voltage is shown. One end of the third resistor RIN is connected to the second input terminal of the operational amplifier 161, and the other end is connected to the ground node. One end of the fourth resistor RFN is connected to the second input terminal of the operational amplifier 161, and the other end is connected to the output terminal of the operational amplifier 161. The output voltage VOUT is output from the output terminal of the operational amplifier 161. In the example of FIG. 2, the first input terminal of the operational amplifier 161 is the positive input terminal, and the second input terminal is the negative input terminal.

[0020] When RIP = RIN and RFP = RFN, and the gain of the amplifier circuit 160 is K, then K = RFP / RIP, and VOUT = K × VIP. Since the voltage difference across both ends of the sense resistor RS is VIP - 0V, the amplifier circuit 160 amplifies the voltage difference across both ends of the sense resistor RS.

[0021] The storage unit 180 stores correction data TRM used for correcting the target set value TS. The correction data TRM includes a lower limit set value for setting the lower limit value of the correction set value SDAC. Further, the correction data TRM may include an upper limit set value for setting the upper limit value of the correction set value SDAC. The storage unit 180 is a register or a memory. The memory is a volatile memory such as a RAM, or a non-volatile memory such as an OTP memory or an EEPROM. RAM is the abbreviation of Random Access Memory. OTP is the abbreviation of One Time Programmable. EEPROM is the abbreviation of Electrically Erasable Programmable Read Only Memory.

[0022] The target value correction circuit 170 corrects the target set value TS using the correction data TRM, and outputs the result as the corrected set value SDAC. Details of the correction will be described later.

[0023] The D / A conversion circuit 190 D / A-converts the corrected set value SDAC and outputs the result as the output voltage VDAC. The D / A conversion circuit 190 includes, for example, a ladder resistor circuit and a selection circuit. The ladder resistor circuit divides the power supply voltage VDD into a plurality of voltages. The selection circuit selects a voltage corresponding to the corrected set value SDAC from the plurality of voltages and outputs the selected voltage as the output voltage VDAC.

[0024] The output voltage VOUT of the amplifier circuit 160 is input to the first input terminal of the comparison circuit 115, and the output voltage VDAC of the D / A conversion circuit 190 is input to the second input terminal. The comparison circuit 115 compares the output voltage VOUT of the amplifier circuit 160 and the output voltage VDAC of the D / A conversion circuit 190, and outputs the result as the output signal COUT. The comparison circuit 115 is also called a comparator. In the example of FIG. 2, the first input terminal is the positive input terminal and the second input terminal is the negative input terminal, but it is not limited thereto.

[0025] FIG. 3 is a waveform example for explaining the operation in the first configuration example of the circuit device. Here, it is assumed that the arithmetic circuit 130 outputs a low-level switching control signal CSW during the charge period and a high-level switching control signal CSW during the decay period.

[0026] When the switch elements SWA and SWD are turned on during the charge period, energy is supplied from the power supply to the coil of the motor 10, the sense resistor current IS increases, and the input voltage VIP and the output voltage VOUT of the amplifier circuit 160 increase. When the output voltage VOUT of the amplifier circuit 160 reaches the output voltage VDAC of the D / A conversion circuit 190, the output signal COUT of the comparison circuit 115 changes from low level to high level.

[0027] During the decay period, when the switching elements SWB and SWC are turned on, the coil of the motor 10 releases energy, the sense resistor current IS becomes negative and its absolute value decreases. Since the sense resistor current IS is negative, the input voltage VIP and the output voltage VOUT of the amplifier circuit 160 become 0V. When the output voltage VOUT of the amplifier circuit 160 becomes 0V, the output signal COUT of the comparison circuit 115 changes from a high level to a low level.

[0028] The arithmetic circuit 130 incorporates a timer. At the rising edge of the output signal COUT, the arithmetic circuit 130 changes the switching control signal CSW from a low level to a high level and starts the timer. When the measured time of the timer reaches a predetermined time, the arithmetic circuit 130 changes the switching control signal CSW from a high level to a low level and stops the timer. As a result, the operation during the charge period is performed again, and thereafter, the charge period and the decay period are repeated in the same manner.

[0029] Ideally, when the sense resistor current IS corresponding to the target set value TS flows, the output signal COUT of the comparison circuit 115 changes from a low level to a high level. However, due to manufacturing variations in circuits such as the offset of the amplifier circuit 160, the D / A conversion circuit 190, or the comparison circuit 115, or an increase in the offset due to aging deterioration, the sense resistor current IS when the output signal COUT of the current detection circuit 110 changes may be different from the sense resistor current IS corresponding to the target set value TS. Then, the drive current of the motor 10 will be different from the target value, and the torque or rotational speed of the motor will not be properly controlled.

[0030] According to the present embodiment, the target value correction circuit 170 corrects the target set value TS to output a corrected set value SDAC so that the output signal COUT of the current detection circuit 110 changes when the sense resistor current IS corresponding to the target set value TS flows. As a result, the output voltage VDAC of the D / A conversion circuit 190 is corrected, and when the sense resistor current IS corresponding to the target set value TS flows, the output signal COUT of the comparison circuit 115 changes from a low level to a high level.

[0031] 2. Target Value Correction Circuit Figures 4 and 5 are explanatory diagrams of the process for correcting the target set value.

[0032] Figure 4 shows the relationship between the target set value and the correction set value. FR means the full range of the target set value TS and the correction set value SDAC, that is, the maximum value within the settable range.

[0033] Line B1 shows the relationship between the target set value TS and the correction set value SDAC when no correction is performed. SDAC = TS. The target value correction circuit 170 performs the correction shown by line B2 or the correction shown by line B3 as follows.

[0034] Line B2 shows the relationship between the target set value TS and the correction set value SDAC when only the lower limit set value TLL is used. SDAC = TS / (FR / (FR - TLL)) + TLL. The lower limit set value TLL is the correction set value SDAC when the target set value TS indicates a current of 0 A, and is stored in the storage unit 180 as correction data TRM. The lower limit set value TLL is 0 or more and less than FR. For example, the lower limit set value TLL is less than FR / 2.

[0035] Line B3 shows the relationship between the target set value TS and the correction set value SDAC when the lower limit set value TLL and the upper limit set value TLU are used. SDAC = TS / (FR / (TLU - TLL)) + TLL. The upper limit set value TLU is a value set for reducing the calculation load, and is stored in the storage unit 180 as correction data TRM. The upper limit set value TLU is larger than the lower limit set value TLL and less than FR. The upper limit set value TLU is, for example, larger than FR / 2.

[0036] The upper limit setting value TLU is set such that the lower bits of TLU - TLL become zero. For example, assume that the correction setting value SDAC is 10 bits and the setting range of the lower limit setting value TLL is from "00 0000 0000" to "00 0000 1111". For example, if TLL = 00 0000 1001 is set and the lower 2 bits of TLU - TLL are zero, then the upper 8 bits of TLL are inverted and TLU = 11 1111 0101 is set.

[0037] FIG. 5 shows the relationship between the correction setting value and the output voltage of the D / A conversion circuit. The D / A conversion circuit 190 linearly D / A converts, for example, the correction setting value SDAC into the output voltage VDAC. The D / A conversion circuit 190 outputs VDAC = 0V when SDAC = 0, outputs VDAC = VTLL when SDAC = TLL, outputs VDAC = VTLU when SDAC = TLU, and outputs VDAC = VDD when SDAC = FR. It is 0V < VTLL < VTLU < VDD.

[0038] FIG. 6 is a configuration example of the target value correction circuit. Here, a configuration example is shown when performing the correction shown by line B3 in FIG. 4. The target value correction circuit 170 includes a gain calculation unit 171, a gain multiplication unit 172, and an offset addition unit 173. The storage unit 180 stores the lower limit setting value TLL and the upper limit setting value TLU.

[0039] The gain calculation unit 171 obtains the gain using the lower limit setting value TLL and the upper limit setting value TLU read from the storage unit 180. The gain is 1 / (FR / (TLU - TLL)). Note that the gain calculation unit 171 may obtain the reciprocal of the gain, that is, (FR / (TLU - TLL)).

[0040] The gain multiplication unit 172 multiplies the target setting value TS by the gain. That is, the gain multiplication unit 172 obtains TS / (FR / (TLU - TLL)). Note that the gain multiplication unit 172 may divide the target setting value TS by the reciprocal of the gain.

[0041] The offset addition unit 173 adds the lower limit setting value TLL read from the storage unit 180 to the output of the gain multiplication unit 172, and outputs the result as the correction setting value SDAC. That is, the offset addition unit 173 obtains SDAC = TS / (FR / (TLU - TLL)) + TLL.

[0042] When performing the correction shown by line B2 in FIG. 4, the storage unit 180 stores the full range FR instead of the upper limit setting value TLU. The gain calculation unit 171 obtains 1 / (FR / (FR - TLL)) as the gain.

[0043] FIG. 7 is an example flowchart of the procedure for determining the lower limit setting value. This flow is executed, for example, using an inspection device in the manufacturing inspection of the circuit device 100 or in the electronic device 300 including the circuit device 100. The upper limit setting value TLU is set by the above-described method based on the lower limit setting value TLL determined in this flow.

[0044] In step S1, the inspection device sets the input voltage VIP of the amplifier circuit 160 to 0V. For example, the inspection device sets the input voltage VIP to 0V by applying 0V to the terminal TSB. Alternatively, the inspection device turns off the switch elements SWA to SWD of the drive circuit 150 by register setting or the like. As a result, since IS = 0A, VIP = 0V.

[0045] In this flow, the correction by the target value correction circuit 170 is set to be invalid, or although the correction is valid, TLL = 0 and TLU = FR are set, and SDAC = TS is input to the D / A conversion circuit 190. In step S2, the inspection device initializes the target setting value TS to 0, thereby initializing the correction setting value SDAC input to the D / A conversion circuit 190 to 0.

[0046] In step S3, the inspection device determines whether or not the output signal COUT of the comparison circuit 115 is at a high level. For example, the output signal COUT of the comparison circuit 115 is output from the test terminal of the circuit device 100.

[0047] If COUT is at a low level in step S3, in step S4, the inspection device increments the target set value TS and returns to step S3. If COUT is at a high level in step S3, in step S5, the inspection device sets the lower limit set value TLL as the target set value TS, and writes the lower limit set value TLL and the upper limit set value TLU set based on the lower limit set value TLL into the storage unit 180.

[0048] Figure 8 is a first configuration example of the subtraction circuit included in the gain calculation unit. This configuration example is a configuration example when performing the correction shown by line B2 in FIG. 4. Hereinafter, an example where the input / output data of the subtraction circuit 175 is 10 bits will be shown. The subtraction circuit 175 includes a 1-bit subtractor DFA0 without carry input and 1-bit subtractors DFB1 to DFB9 with carry input. Let the output data of the subtraction circuit 175 be DF[10:0]. The subtraction circuit 175 calculates DF[10:0]=FR[9:0]-TLL[9:0]. In the example of FIG. 8, 1-bit subtractors are provided for all 10 bits of the 10-bit input.

[0049] Figure 9 is a second configuration example of the subtraction circuit included in the gain calculation unit. This configuration example is a configuration example when performing the correction shown by line B3 in FIG. 4. The subtraction circuit 175 includes a 1-bit subtractor DFA2 without carry input and 1-bit subtractors DFB3 to DFB9 with carry input. The subtraction circuit 175 outputs DF[1:0]=00 and calculates DF[10:2]=TLU[9:2]-TLL[9:2]. In the example of FIG. 9, the 1-bit subtractors for the lower 2 bits can be omitted. Here, an example where the lower 2 bits of the upper limit set value TLU and the lower limit set value TLL are the same is shown, but the lower 3 bits or more of the upper limit set value TLU and the lower limit set value TLL may be the same, and the larger the number of bits, the more the number of 1-bit subtractors can be reduced.

[0050] FIG. 10 is a configuration example of a 1-bit subtractor with a carry input. The 1-bit subtractor DFB includes a 1-bit subtractor DFa and DFa without a carry input and an OR circuit. A and B are bits to be subtracted, and C is a carry input. X0 is a subtraction result, and X1 is a carry output.

[0051] FIG. 11 is a configuration example of a 1-bit subtractor without a carry input. The 1-bit subtractor DFA includes an AND circuit in which one of two inputs is an inverted input and an exclusive OR circuit XOR. A and B are bits to be subtracted, X0 is a subtraction result, and X1 is a carry output.

[0052] FIGS. 12 and 13 are waveform examples for explaining the operation of the comparison circuit in the first configuration example of the current detection circuit. In FIG. 13, although the output voltage VOUT of the arithmetic circuit 130 usually does not become negative, for the sake of illustration, the case where the output voltage VOUT of the arithmetic circuit 130 becomes negative is included.

[0053] As shown by line A1 in FIG. 12, the ideal comparison circuit 115 outputs a high-level output signal COUT when the difference VOUT - VDAC between the two inputs is positive, and outputs a low-level output signal COUT when the difference VOUT - VDAC is negative.

[0054] However, when the two inputs are near 0V, the gain of the comparison circuit 115 is low, so the output signal COUT of the comparison circuit 115 does not invert until at least one of the two inputs rises to a certain voltage. Specifically, the minimum value of the sense resistor current IS is 0A, but when detecting a value close to it, the output voltage VDAC of the D / A conversion circuit 190 becomes almost 0V. Lines A2 in Fig. 12 and Fig. 13 show an example where the output voltage VDAC of the D / A conversion circuit 190 is 0V. In this case, when the output voltage VOUT of the amplifier circuit 160 is lower than a certain positive voltage VER, the output signal COUT of the comparison circuit 115 is at a low level, and when the output voltage VOUT is equal to or higher than the voltage VER, the output signal COUT of the comparison circuit 115 is at a high level. That is, the output signal COUT of the comparison circuit 115 inverts at the boundary of VOUT - VDAC = VER.

[0055] As shown in Fig. 13, when VDAC = 0V, the output signal COUT of the comparison circuit 115 inverts at the boundary of VOUT = VER, resulting in errors TER1 and TER2 in the edge timing of the output signal COUT. As explained in Fig. 3, since the length of the charge period is determined by the edge timing of the output signal COUT, if there are errors TER1 and TER2 in the edge timing of the output signal COUT, the drive current of the motor 10 will be different from the target value.

[0056] Considering the voltage error VER as an offset, the influence of the voltage error VER can be canceled by the correction by the target value correction circuit 170. That is, in the flow of Fig. 7, the lower limit setting value TLL corresponding to the voltage error VER is determined, and the target value correction circuit 170 outputs a corrected setting value SDAC obtained by adding the lower limit setting value TLL as an offset. As a result, an offset corresponding to the voltage error VER is added to the output voltage VDAC of the D / A conversion circuit 190, and the output signal COUT of the comparison circuit 115 inverts at the boundary of VOUT - VDAC = 0V.

[0057] In this embodiment, a switch element, a sense resistor RS, and an inductor are connected in series between a first power supply node and a second power supply node. The circuit device 100 controls the switch element. The circuit device 100 includes an amplifier circuit 160, a target value correction circuit 170, a D / A conversion circuit 190, a comparison circuit 115, and a control circuit 120. The amplifier circuit 160 amplifies an input voltage VIP corresponding to a sense resistor current IS which is a current flowing through the sense resistor RS. The target value correction circuit 170 receives a target set value TS of the current, corrects the target set value TS, and outputs a corrected set value SDAC. The D / A conversion circuit 190 performs D / A conversion on the corrected set value SDAC. The comparison circuit 115 compares an output voltage VOUT of the amplifier circuit 160 and an output voltage VDAC of the D / A conversion circuit 190. The control circuit 120 controls the switch element based on an output signal COUT of the comparison circuit 115. The target value correction circuit 170 corrects the target set value TS to output a corrected set value SDAC such that the output signal COUT of the comparison circuit 115 changes when the sense resistor current IS is a current corresponding to the target set value TS.

[0058] Due to manufacturing variations of circuits such as offsets in the amplifier circuit 160, the D / A conversion circuit 190, or the comparison circuit 115, or an increase in offsets due to aging degradation, there is a problem that the detected current value deviates from the target value and the drive of the inductor is not properly controlled. According to this embodiment, the target set value TS is corrected such that the output signal COUT of the comparison circuit 115 changes when the sense resistor current IS is a current corresponding to the target set value TS. Thereby, even when there are manufacturing variations or when offsets etc. increase due to aging degradation, it is correctly detected that the sense resistor current IS has reached the target value, and the drive of the inductor is properly controlled.

[0059] Note that in the example of FIG. 1, the first power supply node corresponds to the power supply node NVD, and the second power supply node corresponds to the ground node NGN. The switch element, the sense resistor RS, and the inductor connected in series between the first power supply node and the second power supply node correspond to any one of the switch elements SWA to SWD, the sense resistor RS, and the coil of the motor 10.

[0060] Also, in the present embodiment, the target value correction circuit 170 may correct the target set value TS such that the output signal COUT of the comparison circuit 115 changes when the lower limit value of the target set value TS is input and the sense resistance current IS is a current corresponding to the lower limit value.

[0061] The lower limit value of the target set value TS corresponds to the lower limit value of the sense resistance current IS. According to the present embodiment, when the lower limit value of the target set value TS is input, the target set value TS is corrected so that it is correctly detected that the sense resistance current IS has become a current corresponding to the lower limit value. This means that the offset due to manufacturing variations or aging deterioration is corrected. By correcting the offset at the lower limit value, the offset is also corrected at any current value.

[0062] In the example of FIG. 4, the lower limit value of the target set value TS is zero, and the lower limit value of the sense resistance current IS is 0 A. The offset is corrected by outputting the correction set value SDAC = TLL for the target set value TS = 0.

[0063] Also, in the present embodiment, the circuit device 100 may include a storage unit 180. The storage unit 180 stores the correction set value SDAC at which the output signal COUT of the comparison circuit 115 changes when the sense resistance current IS is a current corresponding to the lower limit value, as the lower limit set value TLL. The target value correction circuit 170 may output the lower limit set value TLL as the correction set value SDAC when the lower limit value of the target set value TS is input.

[0064] According to the present embodiment, when the lower limit value of the target set value TS is input, by outputting the lower limit set value TLL as the correction set value SDAC, the output signal COUT of the comparison circuit 115 changes when the sense resistance current IS is a current corresponding to the lower limit value.

[0065] Also, in the present embodiment, the storage unit 180 may store the upper limit setting value TLU of the correction setting value SDAC. The target value correction circuit 170 may correct the target setting value TS based on the gain value obtained based on the lower limit setting value TLL and the upper limit setting value TLU.

[0066] The range of the target setting value TS is 0 to FR, while the range of the correction setting value SDAC is TLL to TLU. According to the present embodiment, by correcting the target setting value TS based on the gain value obtained based on the lower limit setting value TLL and the upper limit setting value TLU, the target setting value TS in the range of 0 to FR is corrected to the correction setting value SDAC in the range of TLL to TLU.

[0067] Also, in the present embodiment, the storage unit 180 may be a non-volatile memory.

[0068] According to the present embodiment, the lower limit setting value TLL determined by the flow of FIG. 7 is stored in the non-volatile memory in advance. The target value correction circuit 170 can correct the target setting value TS based on the lower limit setting value TLL stored in the non-volatile memory.

[0069] Also, in the present embodiment, the circuit device 100 may include an interface circuit 105 that receives the target setting value TS from the outside.

[0070] According to the present embodiment, the target setting value TS is corrected inside the circuit device 100. As a result, the external processing device 200 may transmit the target setting value TS corresponding to the target current to the circuit device 100 without considering the manufacturing variation or the current detection error due to aging deterioration.

[0071] 3. Second Configuration Example of Current Detection Circuit As described below, it is also possible to reduce the voltage error VER itself in the comparison circuit 115.

[0072] FIG. 14 shows a second configuration example of the current detection circuit. Hereinafter, mainly the parts different from the first configuration example of FIG. 2 will be described, and the description of the parts similar to the first configuration example will be omitted.

[0073] The D / A conversion circuit 190 D / A-converts the reference voltage set value SVR and outputs the resulting reference voltage VR.

[0074] The reference voltage VR from the D / A conversion circuit 190 is input to the other end of the second resistor RFP of the amplifier circuit 160. The reference voltage VR is added as an offset to the output voltage VOUT of the amplifier circuit 160, and VOUT = K × VIP + VR, where K = RFP / RIP.

[0075] FIG. 15 is a waveform example for explaining the operation of the comparison circuit in the second configuration example of the current detection circuit. Here, an example where VR = 0.25 V is shown. When detecting a value close to the minimum value 0 A of the sense resistor current IS, the output voltage VDAC of the D / A conversion circuit 190 becomes approximately VR = 0.25 V. FIG. 15 shows an example where the output voltage VDAC of the D / A conversion circuit 190 is VR = 0.25 V. In this case, when VOUT - VDAC = 0 V, both inputs of the comparison circuit 115 are 0.25 V, not 0 V. Therefore, the voltage error VER described in FIGS. 12 and 13 does not occur, and the output signal COUT of the comparison circuit 115 is inverted with VOUT - VDAC = 0 V as the boundary.

[0076] In this configuration example, in the flow of FIG. 7, the lower limit set value TLL corresponding to the reference voltage VR is determined, and the target value correction circuit 170 outputs a correction set value SDAC obtained by adding the lower limit set value TLL as an offset. As a result, an offset corresponding to the reference voltage VR is added to the output voltage VDAC of the D / A conversion circuit 190, and VDAC = 0.25 V is output with respect to the target set value TS = 0. Here, although the explanation has been made ignoring the offsets of the amplifier circuit 160, the D / A conversion circuit 190, or the comparison circuit 115, actually, the lower limit set value TLL for correcting these offsets and the reference voltage VR is determined.

[0077] Figure 16 shows a configuration example of a D / A conversion circuit in a second configuration example of a current detection circuit. The D / A conversion circuit 190 includes a first selection circuit 181, a second selection circuit 182, a ladder resistor circuit 185, a first decoder 187, and a second decoder 188. Here, an example is shown in which the correction setting value SDAC is 6 bits and the reference voltage setting value SVR is 2 bits.

[0078] The ladder resistor circuit 185 includes resistors R1 to R63 connected in series between a ground node and a power supply node. The ladder resistor circuit 185 outputs voltages V0 to V63 by dividing the power supply voltage VDD with the resistors R1 to R63.

[0079] The first selection circuit 181 selects one of the voltages V0 to V63 based on the control signals SD0 to SD63 from the first decoder 187, and outputs the selected voltage as the output voltage VDAC. The first selection circuit 181 includes switch elements SA0 to SA63. Each switch element is an analog switch composed of one or more transistors. Any one of the switch elements SA0 to SA63 is turned on and the rest are turned off. When the switch element SA0 is on, the voltage V0 is output as the output voltage VOUT. Similarly, when the switch elements SA1 to SA63 are on, the voltages V1 to V63 are output as the output voltage VOUT.

[0080] The first decoder 187 decodes the correction setting value SDAC and outputs control signals SD0 to SD63 for controlling the first selection circuit 181. The control signal SD0 controls the switch element SA0 to be on or off. Similarly, the control signals SD1 to SD63 control the switch elements SA1 to SA63 to be on or off.

[0081] The second selection circuit 182 selects one of the voltages V0 to V3 based on the control signals SV0 to SV3 from the second decoder 188, and outputs the selected voltage as the reference voltage VR. The second selection circuit 182 includes switch elements SB0 to SB3. Each switch element is an analog switch composed of one or more transistors. Any one of the switch elements SB0 to SB3 is turned on, and the rest are turned off. When the switch element SB0 is on, the voltage V0 is output as the reference voltage VR. Similarly, when the switch elements SB1 to SB3 are on, the voltages V1 to V3 are output as the reference voltage VR.

[0082] The second decoder 188 decodes the reference voltage setting value SVR and outputs control signals SV0 to SV3 for controlling the second selection circuit 182. The control signal SV0 controls the switch element SB0 to be on or off. Similarly, the control signals SV1 to SV3 control the switch elements SB1 to SB63 to be on or off.

[0083] In this embodiment, the amplifier circuit 160 includes an operational amplifier 161, a first resistor RIP, a second resistor RFP, a third resistor RIN, and a fourth resistor RFN. One end of the first resistor RIP is connected to the first input terminal of the operational amplifier 161, and the input voltage VIP is input to the other end. One end of the second resistor RFP is connected to the first input terminal of the operational amplifier 161. One end of the third resistor RIN is connected to the second input terminal of the operational amplifier 161, and the other end is connected to the ground node. One end of the fourth resistor RFN is connected to the second input terminal of the operational amplifier 161, and the other end is connected to the output terminal of the operational amplifier 161. The reference voltage VR is input to the other end of the second resistor RFP.

[0084] According to this embodiment, the reference voltage VR is added as an offset to the output voltage VOUT of the amplifier circuit 160. As described with reference to FIGS. 12, 13, and 15, by adding an offset to the output voltage VOUT of the amplifier circuit 160, the two inputs of the comparison circuit 115 do not both become 0V. Thereby, even when VOUT - VDAC is near 0V, the gain of the comparison circuit 115 is high, and the output signal COUT of the comparison circuit 115 is inverted with VOUT - VDAC = 0V as a boundary.

[0085] Also, in this embodiment, the D / A conversion circuit 190 may include a ladder resistor circuit 185, a first selection circuit 181, and a second selection circuit 182. The ladder resistor circuit 185 may output a plurality of voltages V0 to V63. The first selection circuit 181 may select, as the output voltage VDAC of the D / A conversion circuit 190, the voltage corresponding to the correction setting value SDAC among the plurality of voltages V0 to V63. The second selection circuit 182 may select the reference voltage VR from the plurality of voltages V0 to V3.

[0086] According to this embodiment, using the common ladder resistor circuit 185, D / A conversion of the correction setting value SDAC and generation of the reference voltage VR are performed. Thereby, while saving the circuit scale, the reference voltage VR can be supplied to the amplifier circuit 160.

[0087] 4. Second Configuration Example of Electronic Device and Circuit Device FIG. 17 shows a second configuration example of an electronic device and a circuit device. The inductor 20 driven by the circuit device 100 in this configuration example is, for example, an inductor of a switching regulator or a solenoid used for an actuator or the like. Hereinafter, mainly the parts different from the first configuration example in FIG. 1 will be described, and the description of the parts similar to the first configuration example will be omitted.

[0088] The terminal TD1 is connected to one end of the inductor 20. The terminal TD2 is connected to the other end of the inductor 20.

[0089] The drive circuit 150 includes a switching element SWE. One end of the switching element SWE is connected to the terminal TVD, and the other end is connected to the terminal TD1. The terminal TD2 is connected to the terminal TSA. The switching element SWE is controlled to be turned on or off by a pre-drive signal CSE. The switching element SWE is a P-type MOS transistor or an N-type MOS transistor. Note that the switching element SWE may be connected between the terminal TD2 and the terminal TSA, and the terminal TVD and the terminal TD1 may be connected.

[0090] The control circuit 120 outputs a pre-drive signal CSE for switching the switching element SWE of the drive circuit 150 based on the output signal COUT of the current detection circuit 110. Specifically, the arithmetic circuit 130 generates a switching control signal CSW from the output signal COUT of the current detection circuit 110. The switch control circuit 140 generates a pre-drive signal CSE from the switching control signal CSW. The period during which the switching element SWE is on is called the on-period, and the period during which the switching element SWE is off is called the off-period. When the on-period and the off-period are combined to form a drive cycle, the sense resistor current IS is controlled by the duty ratio of the on-period with respect to the cycle. The control circuit 120 controls the drive based on the output signal COUT of the current detection circuit 110, and controls the duty ratio of the on-period so that the sense resistor current IS corresponds to the target set value TS.

[0091] The configuration of the current detection circuit 110 and the correction method of the target set value TS are the same as the configurations and methods described in FIGS. 1 to 16.

[0092] FIG. 18 is an example of waveforms for explaining the operation in the second configuration example of the circuit device. Here, it is assumed that the arithmetic circuit 130 outputs a low-level switching control signal CSW during the on-period and a high-level switching control signal CSW during the off-period.

[0093] During the on-period, when the switch element SWE turns on, energy is supplied from the power source to the inductor 20, the sense resistor current IS increases, and the input voltage VIP and output voltage VOUT of the amplifier circuit 160 increase. When the output voltage VOUT of the amplifier circuit 160 reaches the output voltage VDAC of the D / A conversion circuit 190, the output signal COUT of the comparison circuit 115 changes from a low level to a high level.

[0094] During the off-period, when the switch element SWE turns off, the inductor 20 releases energy and the sense resistor current IS decreases. Although FIG. 17 does not show the discharge path from the inductor 20, for example, the anode of a diode may be connected to the ground node NGN and the cathode of the diode may be connected to the terminal TD1. The comparison circuit 115 has a hysteresis of the voltage difference VHIS. When the output voltage VOUT of the amplifier circuit 160 decreases to VDAC - VHIS, the output signal COUT of the comparison circuit 115 changes from a high level to a low level.

[0095] The arithmetic circuit 130 outputs a switching control signal CSW having the same logic level as the output signal COUT of the comparison circuit 115. The switch control circuit 140 outputs a pre-drive signal CSE obtained by inverting the logic level of the switching control signal CSW. Here, an example where the switch element SWE is an N-type MOS transistor is shown.

[0096] Although the present embodiment has been described in detail as above, those skilled in the art will easily understand that many modifications can be made without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, in the specification or drawings, a term described at least once together with a broader or synonymous different term can be replaced with that different term at any location in the specification or drawings. Also, all combinations of the present embodiment and the modifications are included within the scope of the present disclosure. Further, the configurations and operations of the amplifier circuit, memory unit, target value correction circuit, D / A conversion circuit, comparison circuit, current detection circuit, control circuit, drive circuit, motor, inductor, circuit device, processing device, electronic device, etc. are not limited to those described in the present embodiment, and various modified implementations are possible.

Explanation of Reference Numerals

[0097] 10... motor, 20... inductor, 100... circuit device, 105... interface circuit, 110... current detection circuit, 115... comparison circuit, 120... control circuit, 130... arithmetic circuit, 140... switch control circuit, 150... drive circuit, 160... amplifier circuit, 161... operational amplifier, 170... target value correction circuit, 171... gain arithmetic unit, 172... gain multiplication unit, 173... offset addition unit, 175... subtraction circuit, 180... memory unit, 181... first selection circuit, 182... second selection circuit, 185... ladder resistance circuit, 187... first decoder, 188... second decoder, 190... D / A conversion circuit, 200... processing device, 300... electronic device, IS... sense resistor current, RFN... fourth resistor, RFP... second resistor, RIN... third resistor, RIP... first resistor, RS... sense resistor, SWA~SWE... switch element, TLL... lower limit set value, TLU... upper limit set value, TS... target set value, VIP... input voltage, VR... reference voltage

Claims

1. A circuit device for controlling the switch element among a switch element, a sense resistor, and an inductor connected in series between a first power supply node and a second power supply node, comprising: an amplifier circuit that amplifies an input voltage corresponding to a sense resistor current which is a current flowing through the sense resistor; a target value correction circuit to which a target set value of current is input and which corrects the target set value to output a corrected set value; a D / A conversion circuit that D / A-converts the corrected set value; a comparison circuit that compares the output voltage of the amplifier circuit and the output voltage of the D / A conversion circuit; a control circuit that controls the switch element based on the output signal of the comparison circuit; and wherein the target value correction circuit corrects the target set value to output the corrected set value such that the output signal of the comparison circuit changes when the sense resistor current is a current corresponding to the target set value.

2. In the circuit device according to Claim 1, the target value correction circuit corrects the target set value such that the output signal of the comparison circuit changes when the lower limit value of the target set value is input and the sense resistor current is a current corresponding to the lower limit value.

3. In the circuit device according to Claim 2, comprising a storage unit that stores, as a lower limit set value, the corrected set value at which the output signal of the comparison circuit changes when the sense resistor current is a current corresponding to the lower limit value, wherein the target value correction circuit outputs the lower limit set value as the corrected set value when the lower limit value of the target set value is input.

4. In the circuit device according to Claim 3, the storage unit stores an upper limit set value of the corrected set value, and the target value correction circuit corrects the target set value based on a gain value obtained based on the lower limit set value and the upper limit set value.

5. In the circuit device according to Claim 4, the storage unit is a non-volatile memory.

6. In the circuit device according to any one of Claims 1 to 5, the amplifier circuit includes an operational amplifier, a first resistor having one end connected to a first input terminal of the operational amplifier and the input voltage input to the other end, a second resistor having one end connected to the first input terminal of the operational amplifier, and a third resistor having one end connected to a second input terminal of the operational amplifier and the other end connected to a ground node. A fourth resistor having one end connected to the second input terminal of the operational amplifier and the other end connected to the output terminal of the operational amplifier, comprising a circuit device characterized in that a reference voltage is input to the other end of the second resistor.

7. In the circuit device according to claim 6, the D / A conversion circuit a ladder resistor circuit that outputs a plurality of voltages, a first selection circuit that selects, as the output voltage of the D / A conversion circuit, a voltage corresponding to the correction setting value among the plurality of voltages, a second selection circuit that selects the reference voltage from the plurality of voltages, a circuit device characterized by including.

8. In the circuit device according to any one of claims 1 to 5, a circuit device characterized by including an interface circuit that receives the target setting value from the outside.

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