Semiconductor device

Abstract

To reduce the on-resistance while ensuring short-circuit resistance in a trench MOSFET with a vertical channel fin structure.SOLUTION: A trench MOSFET has a vertical channel fin structure and includes a plurality of first trenches 2 extending longitudinally in a first direction and arranged in a second direction, includes a first JFET region 8A of a first conductivity type disposed below a channel region 5 and sandwiched with a first body regions 9A of a second conductivity type, and a second JFET region 8B of the first conductivity type disposed in contact with a lower surface of the first JFET region 8A and sandwiched with a second body region 9B of the second conductivity type, the length of the second JFET region 8B in the first direction is longer than that of the first JFET region 8A, the impurity concentration of the first JFET region 8A is higher than that of the second JFET region 8B, and the impurity concentration of the second JFET region 8B is higher than that of the drift region 10, and the dimensions of the first body region 9A and the first JFET region 8A in the depth direction from the bottom of the first trenches 2 are both greater than 0.5 μm.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] As a type of trench MOSFET, a trench MOSFET with a vertical channel fin structure has been proposed.

[0003] FIG. 13 is a perspective view schematically showing a conventional trench MOSFET with a vertical channel fin structure. In FIG. 13, the gate electrode, gate insulating film, interlayer insulating film, source electrode, and drain electrode are not shown.

[0004] The conventional semiconductor device 1 shown in FIG. 13 has a plurality of first trenches 2 that have a longitudinal direction in a first direction and a short-side direction in a second direction when viewed in plan and are arranged in the second direction. Note that the first trench 2 indicated by the dotted line in the cross section in front of FIG. 13 shows a virtual position corresponding to the first trench 2 for explaining the positional relationship between the other components and the first trench 2.

[0005] The first source region 3 of the first conductivity type includes a region having a fin structure in which at least a part is partitioned by a plurality of first trenches 2. On the lower surface of the first source region 3, a channel region 5 of the second conductivity type having a fin structure partitioned by a plurality of first trenches 2 is formed in contact with the first source region 3. Below the channel region 5, a JFET region 8 of the first conductivity type is formed, and body regions 9 of the second conductivity type are formed on both sides of the JFET region 8. The channel region 5 is connected to the body region 9. Below the JFET region 8, a drift region 10 of the first conductivity type is formed, and below the drift region 10, a drain region 11 of the first conductivity type is formed.

[0006] The conventional semiconductor device 1 shown in FIG. 13 has a gate insulating film disposed inside the first trench 2 and a gate electrode including a region at least partially disposed inside the first trench 2, and a channel current flows in the channel region 5 in the vertical direction (depth direction). Note that the gate electrodes embedded inside the first trench 2 are connected to each other outside the first trench 2.

[0007] As a patent document related to such a technique, for example, there is Patent Document 1. Although the names and detailed structures of the respective components are different, paragraphs 0048 to 0052, FIGS. 3, and FIGS. 14 to 18 of Patent Document 1 describe a configuration similar to that of FIG. 13 described above.

Prior Art Document

Patent Document

[0008]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] According to the structure of the conventional semiconductor device 1 shown in FIG. 13, by reducing the trench pitch and increasing the channel density, the number of channels can be increased, so that the on-resistance when viewed over the entire semiconductor chip can be reduced. However, the conventional semiconductor device 1 shown in FIG. 13 has a problem that although the on-resistance is low due to the high channel density, the short-circuit withstand voltage is low accordingly.

[0010] In addition, in the conventional semiconductor device 1 shown in FIG. 13, since the thickness (dimension in the depth direction) of the JFET region 8 is thin, there is a problem that the short-circuit withstand voltage is low.

[0011] Furthermore, in the conventional semiconductor device 1 shown in FIG. 13, when the impurity concentration of the JFET region 8 is the same as that of the drift region 10, since the impurity concentration of the JFET region 8 is as low as that of the drift region 10, the resistance of the JFET region 8 becomes high, and there is a problem that the on-resistance cannot be sufficiently reduced.

[0012] The problem to be solved by the present invention is to provide a semiconductor device capable of reducing the on-resistance while ensuring the short-circuit withstand voltage in a trench MOSFET having a vertical channel fin structure.

Means for Solving the Problem

[0013] To solve the above problems, a semiconductor device according to the present invention has a plurality of first trenches that have a longitudinal direction in a first direction and a short-side direction in a second direction when viewed in a plan view, and are arranged in a plurality in the second direction; a first source region of a first conductivity type including a region having a fin structure at least partially delimited by the plurality of first trenches; a channel region of a second conductivity type of a fin structure delimited by the plurality of first trenches, in contact with the lower surface of the first source region; a gate insulating film disposed inside the first trench; a gate electrode including a region at least partially disposed inside the first trench; a first JFET region of the first conductivity type disposed below the channel region; a first body region of the second conductivity type disposed on both sides of the first JFET region; a second JFET region of the first conductivity type disposed in contact with the lower surface of the first JFET region; a second body region of the second conductivity type disposed in contact with the lower surface of the first body region on both sides of the second JFET region; a drift region of the first conductivity type disposed below the second JFET region; and a drain region of the first conductivity type disposed below the drift region and having a higher impurity concentration than the drift region. An end portion of the bottom surface of the plurality of first trenches in the first direction is disposed in the first body region, the channel region is connected to the first body region, and a channel current flows vertically in the channel region. The length of the second JFET region in the first direction is longer than the length of the first JFET region in the first direction, the impurity concentration of the first JFET region is higher than the impurity concentration of the second JFET region, the impurity concentration of the second JFET region is higher than the impurity concentration of the drift region, and the dimensions of the first body region and the first JFET region in the depth direction from the lower part of the first trench are both larger than 0.5 μm.

Advantages of the Invention

[0014] According to the present invention, in a trench MOSFET having a vertical channel fin structure, it is possible to reduce the on-resistance while ensuring the short-circuit withstand voltage.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

BEST MODE FOR CARRYING OUT THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and redundant explanations are omitted.

EXAMPLE

[0017] FIG. 1 is a top perspective view of the semiconductor device of Example 1. FIG. 2 is a cross-sectional view taken along line X1-X1' of FIG. 1. FIG. 3 is a cross-sectional view taken along line X2-X2' of FIG. 1. FIG. 4 is a cross-sectional view taken along line Y1-Y1' of FIG. 1. In FIG. 1, the gate electrode 7, the gate insulating film 6, the interlayer insulating film 14, the source electrode 12, and the barrier metal 18 are not shown. Also, in FIG. 1, the position where the source contact 17 is disposed is indicated by a dotted line.

[0018] The semiconductor device 1 of this embodiment includes a plurality of first trenches 2, a first source region 3 of a first conductivity type, a channel region 5 of a second conductivity type, a gate insulating film 6, a gate electrode 7, a JFET region 8 of the first conductivity type, a body region 9 of the second conductivity type, a drift region 10 of the first conductivity type, and a drain region 11 of the first conductivity type.

[0019] In this embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example, but it is not limited thereto, and the first conductivity type may be p-type and the second conductivity type may be n-type. Also, regarding the impurity concentration, an example is shown in the embodiment, but it is not limited thereto, and it may be changed within a range capable of realizing the intended operations and effects in the embodiment.

[0020] The plurality of first trenches 2 have a longitudinal direction in a first direction (the direction of X1-X1' in FIG. 1) and a short side direction in a second direction (the direction of Y1-Y1' in FIG. 1) when viewed in plan, and a plurality of them are arranged in the second direction. Also, the first trench group composed of the plurality of first trenches 2 arranged in the second direction is also arranged in the first direction. Note that the first trench 2 indicated by the dotted line in the cross-sectional view of FIG. 3 shows a position virtually corresponding to the first trench 2 for explaining the positional relationship between the other components and the first trench 2.

[0021] The first source region 3 of the first conductivity type includes a region having a fin structure in which at least a part is partitioned by the plurality of first trenches 2. The impurity concentration of the first source region 3 is, for example, a high concentration of n+.

[0022] On the lower surface of the first source region 3, a channel region 5 of a second conductivity type having a fin structure partitioned by a plurality of first trenches 2 is formed in contact with the first source region 3. The impurity concentration of the channel region 5 is, for example, medium concentration p.

[0023] Below the channel region 5, a JFET region 8 of a first conductivity type is formed, and body regions 9 of a second conductivity type are formed on both sides of the JFET region 8. In this embodiment, the JFET region 8 has a configuration including a first JFET region 8A of a first conductivity type disposed below the channel region 5 and a second JFET region 8B of a first conductivity type disposed in contact with the lower surface of the first JFET region 8A. And the body region 9 has a configuration including a first body region 9A of a second conductivity type disposed on both sides of the first JFET region 8A and a second body region 9B of a second conductivity type disposed on both sides of the second JFET region 8B and in contact with the lower surface of the first body region 9A. The width (length in the first direction) (WJ2 in FIG. 2) of the second JFET region 8B is set to be longer than the width (length in the first direction) (WJ1 in FIG. 2) of the first JFET region 8A. The dimensions in the depth direction (tJ1 in FIG. 2) of the first body region 9A and the first JFET region 8A from the lower part of the first trench 2 are both set to be larger than 0.5 μm. The impurity concentration of the first JFET region 8A is set to be higher than the impurity concentration of the second JFET region 8B. The impurity concentration of the second JFET region 8B is set to be higher than the impurity concentration of the drift region 10. The impurity concentration of the first JFET region 8A is, for example, medium concentration n. The impurity concentration of the second JFET region 8B is, for example, low concentration n-. The impurity concentrations of the first body region 9A and the second body region 9B are, for example, medium concentration p. The operations and effects of the JFET region 8 and the body region 9 in this embodiment will be described later.

[0024] As shown in FIG. 3, the channel region 5 is connected to the first body region 9A. Therefore, the width (length in the first direction) of the channel region 5 is the width obtained by subtracting the overlapping width between the first trench 2 and the body region 9 from the width (length in the first direction) of the first trench 2. Therefore, the width of the channel region 5 becomes substantially the same as the width (WJ1 in FIG. 2) of the first JFET region 8A.

[0025] Below the JFET region 8, a drift region 10 of the first conductivity type is disposed. The drift region 10 is also disposed below the body region 9. Further, below the drift region 10, a drain region 11 of the first conductivity type having an impurity concentration higher than that of the drift region 10 is disposed. The impurity concentration of the drift region 10 is, for example, a low concentration of n-. The impurity concentration of the drain region 11 is, for example, a high concentration of n+.

[0026] As shown in FIGS. 2 and 4, a gate insulating film 6 is disposed inside the first trench 2. Further, at least a part of the gate electrode 7 is disposed inside the first trench 2. Note that the gate electrodes 7 disposed inside the first trench 2 are connected to each other outside the first trench 2. The gate electrode 7 can be formed of, for example, polysilicon.

[0027] The semiconductor device 1 of this embodiment controls the input of a gate drive signal to the gate electrode 7 inside the first trench 2, so that a channel current flows in the longitudinal direction (depth direction) in the channel region 5 of the fin structure. That is, it is a trench MOSFET having a vertical channel fin structure. Therefore, by reducing the trench pitch and increasing the channel density, the number of channels can be increased, and thus the on-resistance when viewed over the entire semiconductor chip can be reduced.

[0028] Also, in the semiconductor device 1 of this embodiment, as shown in FIG. 2, the width (length in the first direction) (WTG) of the gate electrode 7 disposed inside the first trench 2 is longer than the width (length in the first direction) (WJ1) of the first JFET region 8A. Note that the width (WTG) of the gate electrode 7 is the size obtained by subtracting the thickness of the gate insulating film (for two locations on one side and the other side in the first direction) from the width (length in the first direction) (WTR) of the first trench 2. Due to WTR>WTG>WJ, the end portions in the first direction of the bottom surfaces of the plurality of first trenches 2 and the end portions in the first direction of the bottom surface of the gate electrode 7 in the first trench 2 are arranged in the first body region 9A. As a result, a structure is formed in which the three-dimensional corners of the first trench 2 and the gate electrode 7 are present in the first body region 9A. Therefore, at the three-dimensional corner portion of the first trench 2 where the electric field is likely to concentrate and the gate insulating film 6 is likely to be broken, the concentration of the electric field is alleviated even when a high voltage is applied, and the breakage of the gate insulating film 6 can be suppressed. As the voltage applied with a high breakdown voltage becomes higher, the electric field is more likely to concentrate at the three-dimensional corner portion of the first trench 2 and the gate insulating film 6 is more likely to be broken. Therefore, it is desirable to adopt such a configuration for a semiconductor device 1 with a higher breakdown voltage.

[0029] Next, the operations and effects of the JFET region 8 and the body region 9 in this embodiment will be described.

[0030] In the semiconductor device 1 of this embodiment, the impurity concentration of the JFET region 8 (the first JFET region 8A and the second JFET region 8B) is set higher than the impurity concentration of the drift region 10, and as shown in FIG. 3, the thickness (dimension in the depth direction) (tJ1 in FIG. 2) of the first body region 9A and the first JFET region 8A from the lower part of the first trench 2 is set to be larger than 0.5 μm. It is desirable that the thickness (tJ1) of the first body region 9A and the first JFET region 8A from the lower part of the first trench 2 be set to be approximately the same thickness.

[0031] When a high voltage is applied between the drain and the source, a depletion layer spreads in the JFET region 8 to ensure the breakdown voltage. Here, when the thickness (tJ1) of the JFET region 8 is thin as in the conventional structure shown in FIG. 13, the depletion layer mainly spreads in the depth direction. The depletion layer spreads more easily where the impurity concentration is lower. Therefore, the concentration of the JFET region 8 cannot be increased and is set to about 1×10 16 cm -3 or so, which is the same as the concentration of the general drift region 10.

[0032] On the other hand, in this embodiment, by increasing the thickness (tJ1) of the first JFET region 8A, when a high voltage is applied between the drain and the source, the depletion layer starts to spread laterally from the first body regions 9A on both sides of the first JFET region 8A, and when an even higher voltage is applied, the depletion layer closes and pinch-off occurs. As a result, only by spreading the depletion layer by half of the width (WJ1) of the first JFET region 8A, the depletion layer of the thickness (tJ1) of the first JFET region 8A can be obtained. As a result, the spread of the depletion layer required for complete depletion can be small, so that the impurity concentration of the first JFET region 8A can be increased while maintaining the breakdown voltage. And since the impurity concentration of the first JFET region 8A can be set high, the resistance of the first JFET region 8A can be reduced and the on-resistance can be reduced. Note that the impurity concentration of the first JFET region 8A can be made higher as the thickness (tJ1) of the first JFET region 8A is larger and the width (WJ1) of the first JFET region 8A is narrower. Also, although the temperature characteristic of the resistance of the first JFET region 8A is positive, if the impurity concentration is high, the increase rate of the resistance of the first JFET region 8A is low even in a high-temperature environment, so that the on-resistance when viewed from the entire semiconductor chip at high temperature can be maintained at a low level.

[0033] The second JFET region 8B of this embodiment also operates in the same manner as the first JFET region 8A. Also for the second JFET region 8B, the impurity concentration can be set higher than that of the drift region 10, so that the resistance of the second JFET region 8B can be reduced and the on-resistance can be reduced. As a result, the on-resistance can be further reduced as compared with the case where the second JFET region 8B is not present.

[0034] It is desirable that the thickness (tJ1) of both the first body region 9A and the first JFET region 8A from the bottom of the first trench 2 be 0.8 μm or more and 1.3 μm or less. The larger the thickness (tJ1) of the first JFET region 8A, the greater the above-described effect. The thickness (the dimension in the depth direction of the second JFET region 8B from the bottom of the first JFET region 8A) (tJ2) of the second JFET region 8B is desirably 0.5 μm or more and 1.0 μm or less.

[0035] The width (WTR) of the first trench 2 is desirably 0.8 μm or more and 1.8 μm or less.

[0036] The width (WJ1) of the first JFET region 8A is desirably 0.3 μm or more and 1.4 μm or less. The narrower the width (WJ1) of the first JFET region 8A, the greater the above-described effect. The width (WJ2) of the second JFET region 8B is desirably 2.0 μm or more and 3.5 μm or less.

[0037] The impurity concentration of the first JFET region 8A is 8×10 16 cm -3 or more and 1×10 18 cm -3 or less. The impurity concentration of the second JFET region 8B is 1×10 16 cm -3 or more and 5×10 17 cm -3 or less. The impurity concentration of the drift region 10 is 1×10 15 cm -3 or more and 1×10 16 cm -3 or less, which is the same as the impurity concentration of a general drift region 10.

[0038] As described above, according to this embodiment, in the trench MOSFET having a vertical channel fin structure, the semiconductor device 1 capable of reducing the on-resistance while ensuring the short-circuit withstand voltage can be realized.

[0039] Note that the semiconductor device 1 of this embodiment also has a source electrode 12, a drain electrode 13, an interlayer insulating film 14, a second source region 4 of the second conductivity type, a second trench 15, a buried film 16, a source contact 17, and a barrier metal 18.

[0040] The source electrode 12 is disposed on the surface side and is an electrode formed of a metal such as aluminum, for example.

[0041] The drain electrode 13 is disposed on the back surface side and is an electrode formed of a laminated metal film (for example, titanium / nickel / gold), for example, and is electrically connected to the drain region 11.

[0042] The interlayer insulating film 14 is formed between the connected portions of the gate electrodes 7 and the first source region 3. Further, the interlayer insulating film 14 is formed so as to cover the upper portion and the side portions of the connected portions of the gate electrodes 7.

[0043] The second source region 4 of the second conductivity type is provided in contact with at least a part of the upper surface of the first body region 9A. The impurity concentration of the second source region 4 is set higher than that of the first body region 9. The impurity concentration of the second source region 4 is, for example, a high concentration of p+. By providing the second source region 4, the second conductivity type first body region 9A and the source electrode 12 can be connected with a lower resistance than connecting through the first source region 3 of the first conductivity type or directly connecting to the first body region 9A.

[0044] The second trench 15 is disposed at a position overlapping the second body region 9B. When the second body region 9B is formed by ion implantation, impurity ions can be implanted at a deep position with low energy by ion implantation through the second trench 15. The second trench 15 is not essential, but it is desirable to provide it. If the depth of the second trench 15 is the same as the depth of the first trench 2, it is desirable because both can be formed simultaneously. However, the depth of the second trench 15 is not limited to this.

[0045] The embedded film 16 is embedded inside the second trench 15. As the embedded film 16, for example, a single or laminated insulating film can be used. As the embedded film 16, for example, a silicon oxide film, a silicon nitride film, or the like can be used. The embedded film 16 can be formed by, for example, a CVD method or the like. In this embodiment, an example is shown in which the upper surface of the embedded film 16 is positioned lower than the upper surface of the first source region 3, but the present invention is not limited to this. Further, the embedded film 16 may include a conductive film at least in part. Thereby, since the source potential from the source electrode 12 can be transmitted to a deep position by the conductive film, the potential fixing to the source potential of the body region 9 becomes more reliable.

[0046] The source contact 17 is a contact region that electrically connects between the source electrode 12 and the first source region 3 or between the source electrode 12 and the second source region 4. The source contact 17 is also formed by filling with a metal such as aluminum, similar to the source electrode 12. It is desirable to connect between the first source region 3 and the source contact 17 or between the second source region 4 and the source contact 17 via a barrier metal 18. As the barrier metal 18, for example, TiN, Ti, or the like can be used. By providing the source contact 17, the source electrode 12 can be connected to the first source region 3 or the second source region 4 via the source contact 17, and the connection between the source electrode 12 and the first source region 3 or the second source region 4 can be stabilized.

[0047] Note that the arrangement of the first source region 3, the second source region 4, and the source contact 17 may be such that, for example, as shown in FIG. 1, the source contact 17 has a longitudinal direction in the second direction, and the first source region 3 and the second source region 4 are alternately arranged at least in a region overlapping the source contact 17. The second source region 4 has a longitudinal direction in the first direction, a short direction in the second direction, and is arranged in a plurality in the second direction. Note that the arrangement of the first source region 3, the second source region 4, and the source contact 17 is not limited to this, and other arrangements may be used.

[0048] The semiconductor device 1 of this embodiment can be formed using, for example, an n+-type SiC substrate, but is not limited thereto, and an Si substrate or the like may also be used. Also, for parts of the manufacturing method not specifically described in this specification, for example, an n+-type drain region 11 can be formed on an n+-type SiC substrate, and an n−-type drift region 10 can be formed by epitaxial growth. Since it can be manufactured by a general semiconductor device manufacturing method, detailed description is omitted. The same applies to the formation method of the source contact 17 and the like.

[0049] As a method for adjusting the impurity concentrations of the first JFET region 8A and the second JFET region 8B, for example, using an n+-type SiC substrate, with the n+-type drain region 11 as a base, an n−-type drift region 10 is formed therefrom using the epitaxial growth method, and then, epitaxial layers with different impurity concentrations are stacked to form the second JFET region 8B and the first JFET region 8A. Also, since stacking epitaxial layers may sometimes incur manufacturing costs, an epitaxial layer with a low and uniform impurity concentration corresponding to the n−-type drift region 10 is formed, and then, the first JFET region 8A and the second JFET region 8B may be additionally formed using impurity ion implantation technology or the like on a part of the formed epitaxial layer.

[0050] Also, for example, in a pn structure using SiC, due to the influence of energization or the like, deterioration of the breakdown voltage or characteristics may occur. To suppress this, a buffer region (not shown) of the same conductivity type (first conductivity type) may be provided between the drift region 10 and the drain region 11. The impurity concentration of the buffer region is preferably higher than that of the drift region 10 and lower than that of the drain region 11. For example, 1×10 16 cm -3 or more and 1×10 19 cm -3 or less is desirable. The thickness of the buffer region may be arbitrarily determined according to purposes such as the breakdown voltage of the semiconductor device 1 and the degree of deterioration suppression.

[0051] The impurity concentration and thickness of the channel region 5 are related to the threshold voltage of MOS operation and the channel resistance (and thus the on-resistance). The impurity concentration of the channel region 5 is desirably 1×10 17 cm -3 or more and 1×10 19 cm -3 or less, and more desirably about 1×10 18 cm -3 . The impurity concentration profile of the channel region 5 may be a uniform profile or a non-uniform profile. Further, as an example of the non-uniform profile, for the purpose of reducing the channel depth, a gradient profile may be used. The gradient profile can be, for example, a profile in which the impurity concentration on the source side is set to a high peak value and the impurity concentration decreases in the depth direction, that is, toward the drain side. For example, in the case of a non-uniform profile such as a gradient profile, the peak value of the impurity concentration is desirably 1×10 17 cm -3 or more and 1×10 19 cm -3 or less, and more desirably about 1×10 18 cm -3 .

[0052] For example, when a high voltage is applied between the drain and the source, the first JFET region 8A is depleted, and at the same time, a depletion layer also extends to the body region 9 side. Therefore, from the viewpoint of promoting depletion and maintaining a high breakdown voltage, it is also important to set the impurity concentration on the body region 9 side in consideration of this.

[0053] The impurity concentration of the body region 9 is desirably set to 1×10 17 cm -3 or more and 1×10 19 cm -3 or less. The impurity concentration of the first body region 9A is desirably higher than the impurity concentration of the channel region 5 within the above-described range of the impurity concentration.

[0054] Also, the impurity concentration profile of the body region 9 may be a uniform profile or a non-uniform profile. For example, the impurity concentration of the first body region 9A and the impurity concentration of the second body region 9B may be the same, or as the target breakdown voltage design increases, the impurity concentration of the first body region 9A may be made higher than the impurity concentration of the second body region 9B.

[0055] Furthermore, in order for the breakdown point in the drain-source breakdown voltage characteristics not to affect the bottom of the first trench 2, for example, in order to have a breakdown point (avalanche point) inside the second body region 9B, a point with a higher impurity concentration than other parts in the second body region 9B may be provided inside the second body region 9B.

Example

[0056] FIG. 5 is a cross-sectional view taken along the line X1-X1' of the semiconductor device of Example 2. FIG. 6 is a cross-sectional view taken along the line X2-X2' of the semiconductor device of Example 2. FIG. 7 is a cross-sectional view taken along the line Y1-Y1' of the semiconductor device of Example 2.

[0057] Example 2 is a modification of Example 1. In Example 1, the JFET region 8 had a two-stage configuration, whereas Example 2 is an example in which the JFET region 8 has a three-stage or more configuration.

[0058] For example, when the JFET region 8 has a three-stage configuration, the semiconductor device 1 may have a first-conductivity-type third JFET region 8C disposed above the drift region 10 and in contact with the lower surface of the second JFET region 8B, and second-conductivity-type third body regions 9C disposed on both sides of the third JFET region 8C and in contact with the lower surface of the second body region 9B. The width (length in the first direction) (WJ3 in FIG. 5) of the third JFET region 8C is longer than the width (length in the first direction) (WJ2 in FIG. 5) of the second JFET region 8B. The impurity concentration of the third JFET region 8C is higher than the impurity concentration of the drift region 10. The impurity concentration of the third JFET region 8C may be the same as the impurity concentration of the second JFET region 8B, or may be set lower than the impurity concentration of the second JFET region 8B. The impurity concentration of the third JFET region 8C is, for example, low-concentration n-.

[0059] Also, when the JFET region 8 has a four-stage configuration, the semiconductor device 1 may have a first-conductivity-type fourth JFET region 8D disposed above the drift region 10 and in contact with the lower surface of the third JFET region 8C, and second-conductivity-type fourth body regions 9D disposed on both sides of the fourth JFET region 8D and in contact with the lower surface of the third body region 9C. The width (length in the first direction) (WJ4 in FIG. 5) of the fourth JFET region 8D is longer than the width (length in the first direction) (WJ3 in FIG. 5) of the third JFET region 8C. The impurity concentration of the fourth JFET region 8D is higher than the impurity concentration of the drift region 10. The impurity concentration of the fourth JFET region 8D may be the same as the impurity concentration of the third JFET region 8C, or may be set lower than the impurity concentration of the third JFET region 8C. The impurity concentration of the fourth JFET region 8D is, for example, low-concentration n-.

[0060] When the JFET region 8 has a four-stage configuration, it is desirable to have a stepped second trench 15 disposed at a position overlapping with the fourth body region 9D. Similar to Example 1, by performing ion implantation through the stepped second trench 15, impurity ions can be implanted at a low energy to a deep position. At this time, in addition to the implantation in the vertical direction (depth direction), by performing the implantation of impurity ions from an oblique direction with respect to the side wall of the second trench 15, the impurities can be spread also in the lateral direction of the second trench 15. Note that it is desirable that the bottom of the stepped second trench 15 is deeper than the bottom of the first body region 9A.

[0061] Note that when the JFET region 8 has a three-stage configuration, a stepped second trench 15 may be provided at a position overlapping with the third body region 9C, or a normal second trench 15 that is not stepped and has a bottom deeper than the bottom of the first body region 9A may be provided at a position overlapping with the third body region 9C.

[0062] When the JFET region 8 has a configuration of five or more stages, the number of stages may be increased with the same concept.

[0063] The thickness of the third JFET region 8C (the dimension in the depth direction from the lower part of the second JFET region 8B) (tJ3 in FIG. 5) is desirably 0.5 μm or more and 1.0 μm or less. The thickness of the fourth JFET region 8D (the dimension in the depth direction from the lower part of the third JFET region 8C) (tJ4 in FIG. 5) is desirably 0.5 μm or more and 1.0 μm or less. Note that regardless of the number of stages, the dimension in the depth direction from the lower part of the first trench 2 of the JFET region 8 is desirably 5.0 μm or less. Also, regardless of the number of stages, the width (the length in the first direction) of the JFET region 8 is desirably 3.5 μm or less.

[0064] According to this embodiment, by adding the third JFET region 8C and the fourth JFET region 8D in which the impurity concentration is higher than that of the drift region 10, for the same reason as the effect of adding the second JFET region 8B in Example 1, the on-resistance can be further reduced compared to Example 1.

Example

[0065] FIG. 8 is a cross-sectional view taken along the line X2-X2' of the semiconductor device of Example 3.

[0066] Example 3 is a modification of Example 1. The semiconductor device 1 of this example has a thin first source region 3A in which the first source region 3 has a smaller thickness (dimension in the depth direction) than other portions in the first source region 3 at least in a portion separated by a plurality of first trenches 2.

[0067] Since the thin first source region 3A has a smaller thickness than the first source region 3, it has a higher resistance. Further, the resistance increases at high temperatures such as when a short circuit occurs. As a result, the thin first source region 3A has a higher potential than the first source region 3, and the voltage of the JFET region 8 increases accordingly, thereby strengthening the reverse bias of the PN junction between the JFET region 8 and the body region 9 and further depleting the JFET region 8. Therefore, the saturation current can be reduced and the short-circuit withstand capacity can be improved as compared with Example 1.

[0068] In addition, since the thin first source region 3A has a smaller thickness than the first source region 3, the overlap capacitance between the gate electrode 7 extending in the depth direction of the first trench 2 and the thin first source region 3A is reduced, and the gate capacitance can be reduced. As a result, the switching speed can also be increased.

[0069] Therefore, according to the semiconductor device 1 of this example, in addition to the effects of Example 1, the short-circuit withstand capacity can be improved and the gate capacitance can be reduced while maintaining a high channel density, and the switching speed can also be increased.

[0070] Here, in order to sufficiently obtain the effect of improving the short-circuit withstand capacity, it is desirable that the sheet resistance of the thin first source region 3A is 10 times or more the sheet resistance of other portions in the first source region 3. In order to increase the sheet resistance, it is desirable that the thin first source region 3A has a lower impurity concentration than other portions in the first source region 3.

[0071] In addition, in this embodiment, since the thickness of the thin first source region 3A is reduced, the first trench 2 can be made shallower, and the dimension (tJ1) in the depth direction of the first JFET region 8A from the lower part of the first trench 2 can be increased.

Example

[0072] FIG. 9 is a cross-sectional view taken along the line X2-X2' of the semiconductor device of Example 4.

[0073] Example 4 is a modification of Example 3. In the semiconductor device 1 of this embodiment, only one end of the thin first source region 3A is connected to the other part in the first source region 3. In FIG. 9, an example is shown in which the left end of the thin first source region 3A is connected to the other part in the first source region 3, but the reverse may also be true. Also, the connecting end may be changed depending on the location, and both a structure for connecting the left end of the thin first source region 3A and a structure for connecting the right end of the thin first source region 3A may be provided.

[0074] In this way, a larger resistance can be added by thinning the connections, so the short-circuit tolerance is further improved.

[0075] Also, the thinning frequency may be adjusted within the chip surface. For example, at locations where it is likely to get hot during a short circuit, the thinning frequency may be increased to reduce the heat generation amount.

[0076] In this case, the thin first source region 3A may have two types: a first connection structure in which both ends of the thin first source region 3A are connected to the other part in the first source region 3 as shown in FIG. 8, and a second connection structure in which only one end of the thin first source region 3A is connected to the other part in the first source region 3 as shown in FIG. 9.

Example

[0077] FIG. 10 is a cross-sectional view taken along the line X2-X2' of the semiconductor device of Example 5.

[0078] Example 5 is a modification of Example 3. The semiconductor device 1 of this example has a punch-back region 19 of the first conductivity type with an impurity concentration higher than that of the first JFET region 8A between the channel region 5 and the first JFET region 8A. The impurity concentration of the punch-back region 19 is, for example, a medium-concentration n-type.

[0079] FIG. 11 is an impurity concentration profile with respect to the depth in the Z1-Z1' direction of FIG. 10 in the semiconductor device of Example 5. The vertical axis represents the impurity concentration IC, and the horizontal axis represents the depth DP.

[0080] When the channel region 5 is formed by ion implantation, for example, the profile of aluminum, which is a p-type dopant, is likely to have a trailing edge, and the channel region 5 becomes deeper than necessary. Accordingly, the first trench 2 also needs to be deeper, the gate capacitance increases, and the effective length of the first JFET region 8A becomes shorter, resulting in a decrease in the short-circuit withstand voltage.

[0081] Therefore, by using, for example, nitrogen as the ion species of the punch-back region 19 and arranging the punch-back region 19 of the first conductivity type with an impurity concentration higher than that of the first JFET region 8A between the channel region 5 and the first JFET region 8A, the channel region depth d1 in the case without the punch-back region can be made smaller than the channel region depth d2 in the case with the punch-back region, and the low-concentration region (trailing-edge region) of the channel region 5 can be reduced. Therefore, the depth of the channel region 5 can be made shallower while maintaining the necessary charge amount. As a result, the gate capacitance can be reduced, and the dimension of the first JFET region 8A in the depth direction can also be increased, so that the short-circuit withstand voltage is also improved.

[0082] Note that the punch-back region 19 may be applied to Example 1 or the like.

Example

[0083] FIG. 12 is a cross-sectional view of the semiconductor device of Example 6 taken along the X1-X1' plane.

[0084] Example 6 is a modification of Example 1. In the semiconductor device 1 of this example, the first source region 3 has a 3C-SiC region 20 provided on the outermost surface of the 4H-SiC region.

[0085] Normally, SiC used in power devices is a polytype of 4H-SiC, which has a wide bandgap and is suitable for high breakdown voltage, but it is difficult to form an ohmic contact and generally requires a heat treatment at 900 °C or higher. On the other hand, since 3C-SiC has a small bandgap, it is possible to form an ohmic contact at a low temperature. Applying a low-temperature ohmic contact can avoid the deterioration of the oxide film in a high-temperature process, improve the reliability of the oxide film, and also improve the short-circuit withstand capacity.

[0086] To make the surface of 4H-SiC into 3C-SiC, it can be realized by implanting ions with a large mass such as phosphorus at a high dose and then recrystallizing. Note that if the high-dose phosphorus implantation layer is near the channel region 5, the channel characteristics will deteriorate. Therefore, the 3C-SiC region 20 may not be provided near the channel region 5.

[0087] Also, for example, when applying to Example 3, since a thin first source region 3A is arranged near the channel region 5, the 3C-SiC region 20 may not be provided in the thin first source region 3A, and the 3C-SiC region 20 may be provided in other parts of the first source region 3.

[0088] As described above, the embodiments of the present invention have been described. However, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical idea of the present invention. Also, a part or all of the configurations described in each embodiment may be combined and applied.

Description of Reference Numerals

[0089] 1 Semiconductor device 2 First trench 3 First source region 3A Thin first source region 4 Second source region 5-channel region 6-gate insulating film 7-gate electrode 8-JFET region 8A-First JFET region 8B-Second JFET region 8C-Third JFET region 8D-Fourth JFET region 9-body region 9A-First body region 9B-Second body region 9C-Third body region 9D-Fourth body region 10-drift region 11-drain region 12-source electrode 13-drain electrode 14-interlayer insulating film 15-Second trench 16-embedded film 17-source contact 18-barrier metal 19-turnback region 20-3C-SiC region IC impurity concentration DP depth d1-Channel region depth without turnback region d2-Channel region depth with turnback region

Claims

1. A plurality of first trenches having a longitudinal direction in a first direction and a lateral direction in a second direction when viewed in plan view, and arranged in a plurality in the second direction; A first source region of a first conductivity type including a region having a fin structure at least partially delimited by the plurality of first trenches; A channel region of a second conductivity type having a fin structure delimited by the plurality of first trenches and in contact with the lower surface of the first source region; A gate insulating film disposed inside the first trench; A gate electrode including a region at least partially disposed inside the first trench; A first JFET region of a first conductivity type disposed below the channel region; First body regions of a second conductivity type disposed on both sides of the first JFET region; A second JFET region of a first conductivity type disposed in contact with the lower surface of the first JFET region; Second body regions of a second conductivity type disposed on both sides of the second JFET region and in contact with the lower surface of the first body region; A drift region of a first conductivity type disposed below the second JFET region; A drain region of a first conductivity type disposed below the drift region and having a higher impurity concentration than the drift region, The ends of the bottom surfaces of the plurality of first trenches in the first direction are disposed within the first body region; The channel region is connected to the first body region, and a channel current flows in the longitudinal direction in the channel region; The length of the second JFET region in the first direction is longer than the length of the first JFET region in the first direction; The impurity concentration of the first JFET region is higher than the impurity concentration of the second JFET region; The impurity concentration of the second JFET region is higher than the impurity concentration of the drift region; A semiconductor device, characterized in that the dimensions in the depth direction from the lower part of the first trench of the first body region and the first JFET region are both greater than 0.5 μm.

2. In claim 1, The dimension in the depth direction of the first JFET region from the lower part of the first trench is 0.8 μm or more and 1.3 μm or less; The dimension in the depth direction of the second JFET region from the lower part of the first JFET region is 0.5 μm or more and 1.0 μm or less. A semiconductor device characterized by this.

3. In claim 1, The length of the first trench in the first direction is 0.8 μm or more and 1.8 μm or less. A semiconductor device characterized by this.

4. In claim 1, the length of the first JFET region in the first direction is 0.3 μm or more and 1.4 μm or less, the length of the second JFET region in the first direction is 2.0 μm or more and 3.5 μm or less, and a semiconductor device characterized by this.

5. In claim 1, The impurity concentration of the first JFET region is 8×10 １６ cm －３ or more and 1×10 １８ cm －３ or less, The impurity concentration of the second JFET region is 1×10 １６ cm －３ or more and 5×10 １７ cm －３ or less, and The impurity concentration in the drift region is 1×10 １５ cm －３ or more and 1×10 １６ cm －３ or less, and the semiconductor device is characterized by this.

6. In claim 1, a semiconductor device characterized by having a buffer region of a first conductivity type between the drift region and the drain region, the impurity concentration of which is higher than that of the drift region and lower than that of the drain region.

7. In claim 6, The impurity concentration in the buffer region is 1 × 10 １６ cm －３ or more and 1 × 10 １９ cm －３ or less, and the semiconductor device is characterized by this.

8. In claim 1, The impurity concentration in the channel region is 1×10 １７ cm －３ or more and 1×10 １９ cm －３ or less, and the semiconductor device is characterized by this.

9. In claim 1, The impurity concentrations of the first body region and the second body region are 1×10 １７ cm －３ or more and 1×10 １９ cm －３ or less, and a semiconductor device characterized by this is provided.

10. In claim 1, a semiconductor device characterized by having a point with a higher impurity concentration than other parts in the second body region inside the second body region.

11. In claim 1, a semiconductor device characterized by having a second trench disposed at a position overlapping the second body region.

12. In claim 11, having an embedded film embedded inside the second trench, the semiconductor device characterized in that the embedded film is a single or laminated insulating film.

13. In claim 11, having an embedded film embedded inside the second trench, the semiconductor device characterized in that the embedded film includes a conductive film at least in part.

14. In claim 1, [[ID= ​ ​ ​ ​ ​ ​ ​ ​ ​ On both sides of the fourth JFET region, there is a fourth body region of the second conductivity type disposed in contact with the lower surface of the third body region. The length of the fourth JFET region in the first direction is longer than the length of the third JFET region in the first direction. A semiconductor device characterized in that the impurity concentration of the fourth JFET region is higher than the impurity concentration of the drift region.

17. In claim 16, A semiconductor device characterized by having a stepped second trench disposed at a position overlapping the fourth body region.

18. In claim 1, The first source region has a thin first source region in at least a portion separated by the plurality of first trenches, and the dimension in the depth direction of the thin first source region is smaller than that of other portions in the first source region. A semiconductor device characterized by this.

19. In claim 18, A semiconductor device characterized in that the thin first source region has a lower impurity concentration than other portions in the first source region.

20. In claim 18, A semiconductor device characterized in that the sheet resistance of the thin first source region is 10 times or more that of other portions in the first source region.

21. In claim 18, A semiconductor device characterized in that only one end of the thin first source region is connected to other portions in the first source region.

22. In claim 18, The thin first source region has two types of connection structures: a first connection structure in which both ends of the thin first source region are connected to other portions in the first source region, and a second connection structure in which only one end of the thin first source region is connected to other portions in the first source region. A semiconductor device characterized by this.

23. In claim 1, A semiconductor device characterized by having a punch-back region of the first conductivity type with an impurity concentration higher than that of the first JFET region between the channel region and the first JFET region.

24. In claim 1, The first source region has a 3C-SiC region provided on the outermost surface of the 4H-SiC region. A semiconductor device characterized by this.

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