Central processing unit

Abstract

To provide a central processing unit which increases processing speed by reducing the number of cycles.SOLUTION: A CPU 1 comprises an arithmetic circuit 4 to perform an operation specified by an instruction code and a data memory 5 capable of storing data for input of the arithmetic circuit 4 and data of an operational result of the arithmetic circuit 4. The CPU calculates a specified address in an address space including the data memory 5 as an executable instruction and calculates the specified address in the address space, and has a first instruction to store the result in the specified address in the address space. The data are directly input in the arithmetic circuit 4 from the data memory 5 without using other storage elements and the arithmetic circuit directly outputs the operational result to the data memory 5 without using other storage elements.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a central processing unit.

Background Art

[0002] Conventionally, in a central processing unit (also referred to as a microcomputer or a microprocessor), data input from the outside is once stored in an I / O port, then transferred to a general-purpose register, and then written from the general-purpose register to a data memory. Further, data to be output to the outside is transferred from the data memory to a general-purpose register and then stored in the I / O port from the general-purpose register.

[0003] As described above, in the conventional central processing unit, reading and writing to the I / O port are performed via a general-purpose register. Therefore, since it passes through the general-purpose register, the number of execution cycles increases during data transfer.

[0004] In response to the above problem, for example, Patent Document 1 describes that by mapping an I / O port to a specified general-purpose register or a flag register, the number of cycles required for reading or writing from the I / O port can be shortened.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, the invention described in Patent Document 1 switches whether to replace the I / O port with a general-purpose register or a flag register. For example, when the number of I / O ports to be switched increases, the number of registers that cannot be used as normal general-purpose registers or flag registers also increases. In addition, the circuit for switching also increases. Furthermore, the number of program steps such as the setting of the I / O map register also increases.

[0007] Also, the invention described in Patent Document 1 only shortens the number of cycles required for reading from or writing to the I / O port. However, for example, even in the case of a normal arithmetic instruction, conventionally, it is necessary to transfer data from the data memory to the general-purpose register, and there is room for shortening the number of cycles during the execution of the arithmetic instruction.

[0008] The present invention has been made in view of the above background, and an object thereof is to provide a central processing unit that shortens the number of cycles and speeds up the processing speed.

Means for Solving the Problems

[0009] The invention described in claim 1 made to solve the above-described problems is a central processing unit that executes an instruction code read from an instruction memory, including an arithmetic unit that executes an operation specified by the instruction code, and a data memory capable of storing data that is an input to the arithmetic unit and data that is an arithmetic result of the arithmetic unit. The central processing unit has a first instruction that calculates a specified address in an address space including the data memory as an executable instruction and the specified address in the address space, and stores the result in the specified address in the address space. When the first instruction is executed, the arithmetic unit directly inputs data from the data memory without passing through another storage element, and directly outputs the arithmetic result to the data memory without passing through another storage element.

Effects of the Invention

[0010] As described above, according to the present invention, the arithmetic unit having the first instruction is configured such that data is directly input from the data memory without passing through other storage elements, and the arithmetic result is directly written into the data memory without passing through other storage elements. Therefore, data can be directly read from the data memory without passing through a general-purpose register or the like, operated on, and the operation result can be directly written into the data memory. As a result, the number of cycles required for instruction execution can be reduced, and the processing speed can be increased.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Modes for Carrying Out the Invention

[0012] Hereinafter, a central processing unit (also referred to as a microcomputer or a microprocessor) of the present invention in an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a central processing unit (hereinafter, CPU) 1. As specific hardware, the CPU 1 is assumed to be configured on a semiconductor substrate in one chip, such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0013] The CPU 1 includes an instruction memory 2, a control circuit 3, an arithmetic circuit 4, a data memory 5, and an I / O port 6.

[0014] The instruction memory 2 is a memory for 16-bit data having an address space from an address of 0000H (hexadecimal) to an address of 7FFFH, for example. Program data consisting of a plurality of instruction codes to be executed by the CPU 1 is stored in the instruction memory 2.

[0015] The control circuit 3 reads an instruction code from the instruction memory 2 and causes the arithmetic circuit 4, the data memory 5, and the I / O port 6 to perform operations according to the instructions constituting the program. The control circuit 3 includes a program counter (PC) 3a and an instruction register (IR) 4.

[0016] The PC 3a is a register that indicates (points to) the address of the instruction to be read from the instruction memory 2. An increment value or a predetermined address value is stored in the PC 3a based on the result calculated within the control circuit 3. The PC 3a is configured with, for example, 16 bits.

[0017] The IR 3b is a register in which the instruction code stored at the address indicated by the PC 3a is stored. The instruction code stored in the IR 3b is output to an instruction decoder within the control circuit 3. Then, the instruction decoder decodes (decodes) the instruction code and outputs a control signal as a decoding result to the above address calculation, the arithmetic circuit 4, the data memory 5, and the I / O port 6.

[0018] The arithmetic circuit 4 includes an arithmetic logic unit (ALU), an input register, a flag register, etc., and performs various arithmetic operations and logical operations based on the control signals output from the instruction decoder. Also, the arithmetic unit 8 may include a multiplier, a divider, etc. in addition to the ALU. That is, the arithmetic circuit 4 functions as an arithmetic unit that executes the arithmetic operation specified by the instruction code.

[0019] The data memory 5 is a 32-bit data memory having an address space from address 0000H to 7FFFH (a different address space from the instruction memory 2). Based on the address calculated by the control circuit 3, the result calculated by the arithmetic circuit 4 or the data stored in the I / O port 6 is written via a data bus or the like. Also, based on the address calculated by the control circuit 3, the stored data is read out. The read data is output to the arithmetic circuit 4 or the I / O port 6 via a data bus or the like. That is, the data memory 5 can store the data that becomes the input of the arithmetic circuit 4 (arithmetic unit) and the data that becomes the operation result of the arithmetic circuit 4 (arithmetic unit).

[0020] Further, the data memory 5 has word lines and bit lines, and is configured by a well-known static RAM (Random Access Memory) that activates the word lines and bit lines at a predetermined timing based on an address to perform read / write operations on the memory cells.

[0021] FIG. 2 and FIG. 3 show circuit configuration examples of the static RAM configured as the data memory 5. FIG. 2 shows a well-known memory cell of a static RAM composed of six transistors (hereinafter referred to as an SRAM cell). In the circuit shown in FIG. 2, the access transistors N3 and N4 are switched ON / OFF according to the voltage level of the first word line WL. Also, data (stored data) is held by a latch composed of two CMOS (Complementary Metal Oxide Semiconductor) inverters.

[0022] FIG. 3 shows the overall structure of a well-known SRAM in which the SRAM cells shown in FIG. 2 are arranged two-dimensionally. In the circuit shown in FIG. 3, access to an arbitrary SRAM cell is performed by the first word line WL and the first bit line pair BL0, BL1. In the case of a read operation, the first word line WL corresponding to the low address signal RA is activated. As a result, the access transistors N3 and N4 provided in all the SRAM cells connected to the same first word line WL are turned on.

[0023] That is, the memory node pair (the nodes on the drain terminal side of N3 and N4 in FIG. 2) is connected to the first bit line pair BL0 and BL1 (the nodes on the source terminal side of N3 and N4) charged to the power supply voltage VDD, and the stored data is output to the first bit line pair BL0 and BL1. Next, the first bit line pair BL0 and BL1 corresponding to the column address signal CA are selected and output by the bit line pair selector SEL. Then, the signal output from the bit line pair selector SEL is input to the sense amplifier SA. The potential difference of the signal input to the sense amplifier SA is amplified and output as a read signal. The row address signal RA and the column address signal CA are signals generated based on the address input to the static RAM.

[0024] The I / O port 6 inputs and outputs data to and from the outside (for example, the external device 10). The I / O port 6 includes a register for holding data input from the outside, a register for holding data output to the outside, and the like.

[0025] The external device 10 is a device that inputs and outputs data to and from the CPU 1. Examples of the external device include other semiconductor integrated circuits and external memories.

[0026] Next, the operation of the CPU 1 according to the above-described configuration will be described with reference to FIGS. 4 to 6. First, in the present embodiment, storage elements (data memory 5, I / O port 6) for storing data necessary for the operation of the CPU 1 are all aggregated in the address space including the data memory 5. Here, the instruction memory 2 is not included in this address space. For example, as shown in FIG. 4, not only the data memory but also the I / O port 6 is assigned to the address space of the data memory 5 (the shaded portion is the I / O port 6). That is, specifying the address space including the data memory 5 may also specify the I / O port 6. That is, the I / O port 6 is mapped to an address continuous with the data memory 5 in the address space.

[0027] Then, as instructions executable by the CPU 1, an instruction to transfer the data at the specified address in the data memory 5 to the specified address in the data memory 5 and an instruction to calculate the specified address in the data memory 5 and the specified address in the data memory 5 and store the result in the specified address in the data memory 5 are added. Although these two instructions are described as the data memory 5, they actually indicate the addresses in the address space described above. Therefore, the former instruction is the second instruction that transfers the data at the specified address in the address space including the data memory 5 to the specified address in the address space as an executable instruction, and the latter instruction is the first instruction that calculates the specified address in the address space including the data memory 5 and the specified address in the address space and stores the result in the specified address in the address space.

[0028] By adding the above two instructions, for example, it becomes possible to transfer the data at the address "0003H" of the data memory 5 to the address "7FFDH" of the I / O port 6. Also, it becomes possible to add the data at the address "0003H" of the data memory 5 and the data at the address "0005H" and store the result in the address "7FFDH" of the I / O port 6.

[0029] Although the above data transfer and the like were possible in the past, it was necessary to go through general-purpose registers and the number of execution cycles was large. In the configuration of this embodiment, the general-purpose registers are deleted and the I / O port 6 is mapped to the address space of the data memory 5. Furthermore, the first instruction and the second instruction can be used. Therefore, it becomes possible to transfer between data memories and directly write the calculation result to the I / O port 6 without going through general-purpose registers, and the number of execution cycles can be reduced.

[0030] The above will be described in detail. FIG. 5 is an explanatory diagram showing the operation when an arithmetic instruction is executed. That is, FIG. 5 is an example of the operation of executing the first instruction. In FIG. 5, only the main parts necessary for the explanation are extracted.

[0031] The example in Fig. 5 is an example where the data at address "0003H" and the data at "0005H" in the above-described data memory 5 are calculated, and the result is stored in "7FFDH" of the I / O port 6.

[0032] This is to read the instruction code corresponding to the address specified by PC3a into IR3b, and based on the data specified by the instruction code, read data from predetermined addresses (0003H, 7FFDH) in the address space mapped by the data memory 5 and the I / O port 6 and supply it to the ALU4c (arithmetic unit). The control circuit 3 functions as a control unit.

[0033] First, transfer the data at address "0003H" of the data memory 5 to the input register 4A of the arithmetic circuit 4 (Fig. 5(1)). Next, transfer the data at address "0005H" of the data memory 5 to the input register 4B of the arithmetic circuit 4 (Fig. 5(2)). Next, activate the ALU of the arithmetic circuit 4 to perform an operation (Fig. 5(3)). Then, transfer the operation result data to the address "7FFDH" of the I / O port 6 (Fig. 5(4)).

[0034] In the case of a conventional CPU with general-purpose registers, for the above (1) and (2), it was necessary to execute an instruction for transferring data from the data memory 5 to the general-purpose register. Also, for the above (4), it was necessary to execute an instruction for transferring the operation result data to the general-purpose register once. In this embodiment, the transfer to the general-purpose register as described above is unnecessary.

[0035] That is, the arithmetic circuit 4 (arithmetic unit) directly receives data without passing through other storage elements such as general-purpose registers when the first instruction is executed, and directly outputs the operation result to the data memory 5 without passing through other storage elements such as general-purpose registers.

[0036] Next, the operation when executing the data transfer instruction in the data memory 5 will be described with reference to Fig. 6. That is, Fig. 6 is an example of the operation when the second instruction is executed.

[0037] In FIG. 6, the data at the memory address "7FFDH" (I / O port 6) is stored in the address "0003H" of the data memory 5. That is, the transfer is completed in one instruction.

[0038] In the case of a conventional CPU having general-purpose registers, it was necessary to execute an instruction to transfer data from the I / O port 6 to the general-purpose registers once. In the present embodiment, as described above, the transfer to the general-purpose registers is not required.

[0039] That is, data is directly input to the I / O port 6 without passing through other storage elements such as general-purpose registers from the data memory 5, and is directly output to the data memory 5 without passing through other storage elements such as general-purpose registers.

[0040] According to the present embodiment, the CPU 1 includes an arithmetic circuit 4 that executes an arithmetic operation specified by an instruction code, and a data memory 5 that can store data that is an input to the arithmetic circuit 4 and data that is an arithmetic result of the arithmetic circuit 4. And it has a first instruction that calculates the specified address in the address space including the data memory 5 as an executable instruction and the specified address in the address space, and stores the result in the specified address in the address space. And the arithmetic circuit 4 directly receives data from the data memory 5 without passing through other storage elements, and directly outputs the arithmetic result to the data memory 5 without passing through other storage elements.

[0041] Since the CPU 1 is configured as described above, data can be directly read from the data memory 5 and calculated without passing through general-purpose registers or the like, and the calculation result can be directly written to the data memory. Therefore, the number of cycles required for instruction execution can be shortened and the processing speed can be increased.

[0042] It also includes an I / O port 6 for data input / output with the outside. The I / O port 6 is mapped to an address space continuous with the data memory 5. And it has a second instruction that transfers the data at the specified address in the above address space to the specified address in the address space as an executable instruction. And the I / O port 6 is configured such that data is directly input from the data memory 5 without passing through other storage elements and directly written to the data memory without passing through other storage elements. By doing so, a general-purpose register is not required even when data is input / output to / from the I / O port 6. Therefore, the number of cycles required for instruction execution can be further reduced, and the processing speed can be increased.

[0043] It also includes a control circuit 3 that reads data from a predetermined address in the address space based on the address specified in the instruction code and supplies it to the arithmetic circuit 4. By doing so, the first instruction and the second instruction can reduce the number of instruction execution cycles and contribute to increasing the processing speed.

[0044] The data memory has word lines and bit lines and is composed of a static RAM that activates the word lines and bit lines at a predetermined timing based on an address to perform reading and writing to / from memory cells. By doing so, the storage of data in the CPU 1 can be aggregated in a high-integration and large-capacity storage device. Therefore, a general-purpose register composed of a conventional D-type flip-flop is not required.

[0045] Note that the present invention is not limited to the above embodiment. That is, those skilled in the art can variously modify and implement it according to conventionally known knowledge without departing from the gist of the present invention. As long as the configuration of the central processing unit of the present invention is still provided even by such modifications, of course, it is included in the scope of the present invention.

Explanation of Reference Numerals

[0046] 1 CPU (Central Processing Unit) 2 Instruction Memory 3 Control Circuit (Control Unit) 4 Arithmetic circuit (arithmetic unit) 5 Data memory (static RAM) 6 I / O port

Claims

1. A central processing unit that executes an instruction code read from an instruction memory, comprising: An arithmetic unit that executes the operation specified by the instruction code; A data memory capable of storing data that is an input to the arithmetic unit and data that is an operation result of the arithmetic unit, Having a first instruction that calculates the specified address of the address space including the data memory as an executable instruction and the specified address of the address space, and stores the result in the specified address of the address space; When the first instruction is executed, the arithmetic unit directly receives data from the data memory without passing through other storage elements, and directly outputs the operation result to the data memory without passing through other storage elements. A central processing unit characterized by the above.

2. Comprising an I / O port for inputting and outputting data to and from the outside, The I / O port is mapped to an address consecutive to the data memory in the address space, Furthermore, having a second instruction that transfers the data at the specified address of the address space as an executable instruction to the specified address of the address space, The I / O port directly receives data from the data memory without passing through other storage elements, and directly outputs data to the data memory without passing through other storage elements. The central processing unit according to claim 1, characterized by the above.

3. The central processing unit according to claim 1 or 2, further comprising a control unit that reads data from a predetermined address in the address space based on the data specified by the instruction code and supplies the data to the arithmetic unit.

4. The data memory has word lines and bit lines, and is configured as a static RAM that activates the word lines and the bit lines at a predetermined timing based on the address to perform reading and writing to memory cells. The central processing unit according to claim 3, characterized by the above.

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