Semiconductor device

Abstract

To reduce the number of terminals used for data transfer which is performed between semiconductor chips.SOLUTION: A first semiconductor chip includes a transmission-side peripheral circuit, which outputs bit values of target data in a parallel transmission system synchronously with a system clock, and a parallel-input / series-output circuit which receives the target data supplied in the parallel transmission system and outputs bit values of the target data in a series transmission system synchronously with a multiplication clock obtained by integrally multiplying a frequency of the system clock. A second semiconductor chip includes a series-input / parallel-output circuit, which receives the target data supplied in the series transmission system and outputs bit values of the target data in a parallel transmission system synchronously with the multiplication clock, a hold circuit including a plurality of registers each holding bit values of the target data outputted from the series-input / parallel-output circuit synchronously with the multiplication clock, and a reception-side peripheral circuit which fetches bit values of the target data held by the hold circuit synchronously with the system clock.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In a semiconductor device having a plurality of semiconductor chips, the following techniques are known as techniques related to data transfer between semiconductor chips. For example, Patent Document 1 describes a device having a plurality of transmission circuits on a first die, a plurality of reception circuits on a second die, and a plurality of conductive lines that communicably couple the first die to the second die such that the plurality of transmission circuits transmit data bits in parallel to the plurality of reception circuits.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device having a multi-chip configuration including a plurality of semiconductor chips, when data transfer is performed between semiconductor chips, each semiconductor chip requires terminals for transmitting and receiving data to be transferred. In particular, when each bit value of the data to be transferred is transferred by a parallel transmission method, a terminal is required for each bit, so the number of terminals increases as the number of bits increases. When the number of terminals increases in each semiconductor chip, not only does the area of the semiconductor chip increase, but also the number of test man-hours increases, leading to an increase in cost.

[0005] The present invention has been made in view of the above points, and an object thereof is to reduce the number of terminals used for data transfer performed between semiconductor chips.

Means for Solving the Problems

[0006] The semiconductor device according to the present invention includes a first semiconductor chip that transmits target data, which is data to be transferred and consists of a plurality of bits, and a second semiconductor chip that receives the target data transmitted from the first semiconductor chip. The first semiconductor chip includes a transmission-side peripheral circuit that outputs each bit value of the target data in a parallel transmission method in synchronization with a system clock, and a parallel input and serial output circuit that receives the target data supplied in the parallel transmission method and outputs each bit value of the target data in a serial transmission method in synchronization with a multiplied clock whose frequency is an integral multiple of the frequency of the system clock. The second semiconductor chip includes a serial input and parallel output circuit that receives the target data supplied in the serial transmission method and outputs each bit value of the target data in a parallel transmission method in synchronization with the multiplied clock, a holding circuit that includes a plurality of registers that hold each bit value of the target data output from the serial input and parallel output circuit in synchronization with the multiplied clock, and a reception-side peripheral circuit that captures each bit value of the target data held in the holding circuit in synchronization with the system clock.

Effects of the Invention

[0007] According to the present invention, it is possible to reduce the number of terminals used for data transfer performed between semiconductor chips.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Best Mode for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the drawings, the same reference numerals are given to substantially the same or equivalent components or parts.

[0010] FIG. 1 is a diagram showing an example of the configuration of a semiconductor device 10 according to a first embodiment of the present invention. The semiconductor device 10 has a multi-chip configuration including a first semiconductor chip 20 and a second semiconductor chip 30. In the present embodiment, the first semiconductor chip 20 is stacked on the second semiconductor chip 30. The first semiconductor chip 20 and the second semiconductor chip 30 are connected via a plurality of bumps 50. Transmission and reception of signals and data between the first semiconductor chip 20 and the second semiconductor chip 30 are performed via the bumps 50. The semiconductor device 10 may have a package substrate 60 on which a stacked body including the first semiconductor chip 20 and the second semiconductor chip 30 is mounted. On the package substrate 60, the first semiconductor chip 20 and the second semiconductor chip 30 may be juxtaposed. In this case, transmission and reception of signals and data between the first semiconductor chip 20 and the second semiconductor chip may be performed via wires or wirings formed on the package substrate 60. Hereinafter, the case of transferring data from the first semiconductor chip 20 to the second semiconductor chip 30 will be described as an example.

[0011] FIG. 2 is a circuit block diagram showing an example of the circuit configuration of each of the first semiconductor chip 20 and the second semiconductor chip 30. The first semiconductor chip 20 transmits target data D, which is data to be transferred and consists of a plurality of bits b1, b2, ··· b m The first semiconductor chip 20 has a transmission-side peripheral circuit 21 and a data transmission circuit 23. The data transmission circuit 23 has a parallel input serial output circuit 24 and a transmission control circuit 25. Details of each of the circuits provided in the first semiconductor chip 20 will be described below.

[0012] The transmission-side peripheral circuit 21 outputs each bit value b1, b2, ··· b of the target data D in a parallel transmission method synchronized with the system clock CK0. The transmission-side peripheral circuit 21 has a plurality of registers 22 corresponding to each bit value b1, b2, ··· b of the target data D. Each of the registers 22 is constituted by a flip-flop. By each of the registers 22 holding and outputting data synchronized with the system clock CK0, in the transmission-side peripheral circuit 21, output in a parallel transmission method of the target data D synchronized with the system clock CK0 is realized. m The transmission-side peripheral circuit 21 outputs each bit value b1, b2, ··· b of the target data D in a parallel transmission method synchronized with the system clock CK0. The transmission-side peripheral circuit 21 has a plurality of registers 22 corresponding to each bit value b1, b2, ··· b of the target data D. Each of the registers 22 is constituted by a flip-flop. By each of the registers 22 holding and outputting data synchronized with the system clock CK0, in the transmission-side peripheral circuit 21, output in a parallel transmission method of the target data D synchronized with the system clock CK0 is realized. m The transmission-side peripheral circuit 21 outputs each bit value b1, b2, ··· b of the target data D in a parallel transmission method synchronized with the system clock CK0. The transmission-side peripheral circuit 21 has a plurality of registers 22 corresponding to each bit value b1, b2, ··· b of the target data D. Each of the registers 22 is constituted by a flip-flop. By each of the registers 22 holding and outputting data synchronized with the system clock CK0, in the transmission-side peripheral circuit 21, output in a parallel transmission method of the target data D synchronized with the system clock CK0 is realized.

[0013] The parallel input serial output circuit 24 receives the target data D supplied in a parallel transmission method from the transmission-side peripheral circuit 21, and outputs each bit value b1, b2, ··· b of the target data D in a serial transmission method synchronized with the multiplication clock CK1. That is, the parallel input serial output circuit 24 sequentially outputs each bit value b1, b2, ··· b of the target data D on one signal line. Each bit value b1, b2, ··· b of the target data D sequentially output on one signal line switches at intervals corresponding to one cycle of the multiplication clock CK1. The multiplication clock CK1 is a clock signal obtained by multiplying the frequency of the system clock CK0 by an integer. That is, assuming the frequency of the system clock CK0 is f0, the frequency f1 of the multiplication clock CK1 is represented by the following formula (1). In formula (1), n is an integer larger than the number of bits m of the target data D (m < n). By setting m < n, the parallel input serial output circuit 24 can output all bit values of the target data D within a period corresponding to one cycle of the system clock CK0. The parallel input serial output circuit 24 may be configured to include a multiplexer (MUX). m The parallel input serial output circuit 24 receives the target data D supplied in a parallel transmission method from the transmission-side peripheral circuit 21, and outputs each bit value b1, b2, ··· b of the target data D in a serial transmission method synchronized with the multiplication clock CK1. That is, the parallel input serial output circuit 24 sequentially outputs each bit value b1, b2, ··· b of the target data D on one signal line. Each bit value b1, b2, ··· b of the target data D sequentially output on one signal line switches at intervals corresponding to one cycle of the multiplication clock CK1. The multiplication clock CK1 is a clock signal obtained by multiplying the frequency of the system clock CK0 by an integer. That is, assuming the frequency of the system clock CK0 is f0, the frequency f1 of the multiplication clock CK1 is represented by the following formula (1). In formula (1), n is an integer larger than the number of bits m of the target data D (m < n). By setting m < n, the parallel input serial output circuit 24 can output all bit values of the target data D within a period corresponding to one cycle of the system clock CK0. The parallel input serial output circuit 24 may be configured to include a multiplexer (MUX). m The parallel input serial output circuit 24 receives the target data D supplied in a parallel transmission method from the transmission-side peripheral circuit 21, and outputs each bit value b1, b2, ··· b of the target data D in a serial transmission method synchronized with the multiplication clock CK1. That is, the parallel input serial output circuit 24 sequentially outputs each bit value b1, b2, ··· b of the target data D on one signal line. Each bit value b1, b2, ··· b of the target data D sequentially output on one signal line switches at intervals corresponding to one cycle of the multiplication clock CK1. The multiplication clock CK1 is a clock signal obtained by multiplying the frequency of the system clock CK0 by an integer. That is, assuming the frequency of the system clock CK0 is f0, the frequency f1 of the multiplication clock CK1 is represented by the following formula (1). In formula (1), n is an integer larger than the number of bits m of the target data D (m < n). By setting m < n, the parallel input serial output circuit 24 can output all bit values of the target data D within a period corresponding to one cycle of the system clock CK0. The parallel input serial output circuit 24 may be configured to include a multiplexer (MUX). m The parallel input serial output circuit 24 receives the target data D supplied in a parallel transmission method from the transmission-side peripheral circuit 21, and outputs each bit value b1, b2, ··· b of the target data D in a serial transmission method synchronized with the multiplication clock CK1. That is, the parallel input serial output circuit 24 sequentially outputs each bit value b1, b2, ··· b of the target data D on one signal line. Each bit value b1, b2, ··· b of the target data D sequentially output on one signal line switches at intervals corresponding to one cycle of the multiplication clock CK1. The multiplication clock CK1 is a clock signal obtained by multiplying the frequency of the system clock CK0 by an integer. That is, assuming the frequency of the system clock CK0 is f0, the frequency f1 of the multiplication clock CK1 is represented by the following formula (1). In formula (1), n is an integer larger than the number of bits m of the target data D (m < n). By setting m < n, the parallel input serial output circuit 24 can output all bit values of the target data D within a period corresponding to one cycle of the system clock CK0. The parallel input serial output circuit 24 may be configured to include a multiplexer (MUX). f1 = n × f0 ··· (1)

[0014] The transmission control circuit 25 controls the input and output of the target data D in the parallel input serial output circuit 24. When the transmission control circuit 25 receives a data transmission command from a higher-level system (not shown), it generates a transfer permission signal S1, a transfer start signal S2, a transfer end signal S3, and an identification value S4 for identifying each bit of the target data D synchronized with the multiplication clock CK1, and uses these signals to control the timing of the input and output of the target data D in the parallel input serial output circuit 24. The transfer permission signal S1, the transfer start signal S2, the transfer end signal S3, and the identification value S4 are transmitted to and shared by the data receiving circuit 31 of the second semiconductor chip 30. The target data D output from the parallel input serial output circuit 24 is output in a serial transmission method via the data output terminal 41 of the first semiconductor chip 20 and supplied to the second semiconductor chip 30.

[0015] The second semiconductor chip 30 receives the target data D transmitted from the first semiconductor chip 20. The second semiconductor chip 30 includes a data receiving circuit 31, a data holding circuit 34, a receiving-side peripheral circuit 36, and a multiplication clock generation circuit 38. The data receiving circuit 31 includes a serial input parallel output circuit 32 and a reception control circuit 33. Details of each of the circuits provided in the second semiconductor chip 30 will be described below.

[0016] The serial input parallel output circuit 32 receives the target data D supplied in a serial transmission method from the parallel input serial output circuit 24, and outputs the bit values b1, b2,... b of the target data D in a parallel transmission method synchronized with the multiplication clock CK1. That is, the serial input parallel output circuit 32 outputs the bit values b1, b2,... b of the target data D on a plurality of signal lines corresponding to each bit of the target data D. The serial input parallel output circuit 32 may include a demultiplexer (DEMUX). m to output in a parallel transmission method synchronized with the multiplication clock CK1. That is, the serial input parallel output circuit 32 outputs the bit values b1, b2,... b of the target data D on a plurality of signal lines corresponding to each bit of the target data D. m The serial input parallel output circuit 32 may include a demultiplexer (DEMUX).

[0017] The reception control circuit 33 controls the timing of the input and output of the target data D in the serial input parallel output circuit 32 using the transfer permission signal S1, the transfer start signal S2, the transfer end signal S3, and the identification value S4 supplied from the transmission control circuit 25.

[0018] The data holding circuit 34 has a plurality of registers 35 corresponding to each bit value b1, b2, ··· b of the target data. Each of the registers 35 holds the corresponding bit value of the target data D output in a parallel transmission format from the serial input parallel output circuit 32 in synchronization with the multiplication clock CK1. m

[0019] The receiving side peripheral circuit 36 takes in each bit value b1, b2, ··· b of the target data D held in the data holding circuit 34 in synchronization with the system clock CK0. The receiving side peripheral circuit 36 has a plurality of registers 37 corresponding to each bit value b1, b2, ··· b of the target data D. Each of the registers 37 is constituted by a flip-flop. Each of the registers 37 takes in the corresponding bit value of the target data D held in the data holding circuit 34 in synchronization with the system clock CK0. m m

[0020] The multiplication clock generation circuit 38 generates a multiplication clock CK1 based on the system clock CK0. The multiplication clock CK1 is a clock signal obtained by multiplying the frequency of the system clock CK0 by an integer (see equation (1)). The multiplication clock CK1 generated by the multiplication clock generation circuit 38 is supplied to the data reception circuit 31 and the data holding circuit 34 provided in the second semiconductor chip 30, and is also supplied to the data transmission circuit 23 provided in the first semiconductor chip 20. The parallel input serial output circuit 24, the serial input parallel output circuit 32, and the data holding circuit 34 operate in synchronization with the multiplication clock CK1 generated by the multiplication clock generation circuit 38.

[0021] The first semiconductor chip 20 has a data output terminal 41 from which target data D is output by a serial transmission method. The second semiconductor chip 30 has a data input terminal 42 to which the target data D transmitted by the serial transmission method is input. By connecting the data output terminal 41 and the data input terminal 42 via bumps 50 (see FIG. 1), a transmission path for transmitting the target data D between the first semiconductor chip 20 and the second semiconductor chip 30 by the serial transmission method is configured.

[0022] Also, the first semiconductor chip 20 has a signal output terminal 43 from which a transfer permission signal S1, a transfer start signal S2, a transfer end signal S3, and an identification value S4 are output. The second semiconductor chip 30 has a signal input terminal 44 to which the respective signals S1 - S4 are input. By connecting the signal output terminal 43 and the signal input terminal 44 via bumps 50 (see FIG. 1), a transmission path for the respective signals S1 - S4 is configured between the first semiconductor chip 20 and the second semiconductor chip 30. Note that in FIG. 2, one signal output terminal 43 and one signal input terminal 44 are shown, but these terminals may be provided for each signal.

[0023] Also, the second semiconductor chip 30 has clock output terminals 46 and 48 from which a system clock CK0 and a multiplied clock CK1 are respectively output. The first semiconductor chip 20 has clock input terminals 45 and 47 to which the system clock CK0 and the multiplied clock CK1 are respectively input. By connecting the clock output terminal 46 and the clock input terminal 45 and the clock output terminal 48 and the clock input terminal 47 via bumps 50 (see FIG. 1), a transmission path for the system clock CK0 and the multiplied clock CK1 is configured between the first semiconductor chip 20 and the second semiconductor chip 30.

[0024] FIG. 3 is a timing chart showing an example of the operation of the semiconductor device 10. Here, a case where 5-bit data "10110" is transferred as target data D from the first semiconductor chip 20 to the second semiconductor chip 30 will be described as an example. The transmission-side peripheral circuit 21 holds 5-bit target data "10110" which is the data to be transferred.

[0025] When the transmission control circuit 25 receives a data transmission command from the upper system at time t0, it transitions the signal level of the transfer permission signal S1 to a high level at time t1 when the multiplied clock CK1 rises. The transfer permission signal S1 is shared by the transmission control circuit 25 and the reception control circuit 33. Thereby, the transmission and reception of the target data D between the data transmission circuit 23 and the data reception circuit 31 become possible.

[0026] The transmission control circuit 25 transitions the signal level of the transfer start signal S2 to a high level at time t2 when the multiplied clock CK1 rises. The transfer start signal S2 is shared by the transmission control circuit 25 and the reception control circuit 33. Thereby, both the data transmission circuit 23 and the data reception circuit 31 recognize that the transfer of the target data D has started.

[0027] At time t2, the parallel input serial output circuit 24 takes in and outputs the first bit value "1" of the target data D held in the transmission-side peripheral circuit 21. Subsequently, the parallel input serial output circuit 24 sequentially takes in and outputs the second bit value "0", the third bit value "1", the fourth bit value "1", and the fifth bit value "0" of the target data D held in the transmission-side peripheral circuit 21 at the timing (times t3, t4, t5, t6) when the multiplied clock CK1 rises. Each bit value of the target data D is transmitted to the second semiconductor chip 30 by a serial transmission method and is immediately received by the parallel input parallel output circuit 32.

[0028] At time t3, the data holding circuit 34 captures and holds the first bit value "1" of the target data D. Subsequently, the data holding circuit 34 sequentially captures and holds the second bit value "0", the third bit value "1", the fourth bit value "1", and the fifth bit value "0" of the target data D at the timing (times t4, t5, t6, t7) when the multiplication clock CK1 rises. Each bit value of the target data D is held in the corresponding registers [1] to [5] of the data holding circuit 34. The data receiving circuit 31 can specify in which register of the data holding circuit 34 each bit value of the target data D should be stored based on the identification value S4.

[0029] At time t7 when the transfer of the last bit value of the target data D is completed, the transmission control circuit 25 transitions the signal level of the transfer end signal S3 to the high level. The transfer end signal S3 is shared by the transmission control circuit 25 and the reception control circuit 33. Thereby, both the data transmission circuit 23 and the data receiving circuit 31 recognize that the transfer of the target data D is completed.

[0030] At time t8 when one cycle of the system clock CK0 has elapsed since time t0, the reception-side peripheral circuit 36 captures each bit value of the target data D held in the data holding circuit 34. Each bit value of the target data D is collectively captured into a plurality of registers 37 of the reception-side peripheral circuit 36.

[0031] FIG. 4 is a diagram showing an example of the configuration of a semiconductor device 10X according to a comparative example. The semiconductor device 10X according to the comparative example has a configuration in which a transmission-side peripheral circuit 21 provided in a first semiconductor chip 20X and a reception-side peripheral circuit 36 provided in a second semiconductor chip 30X directly transmit and receive the target data D. That is, the semiconductor device 10X according to the comparative example does not have the data transmission circuit 23, the data receiving circuit 31, the data holding circuit 34, and the multiplication clock generation circuit 38 according to the embodiment of the present invention. In the semiconductor device 10X according to the comparative example, each bit value b1, b2,... b m of the target data D is transferred from the first semiconductor chip 20X to the second semiconductor chip 30X by a parallel transmission method.

[0032] According to the semiconductor device 10X according to the comparative example, in each of the first semiconductor chip 20X and the second semiconductor chip 30X, since a terminal is required for each bit of the target data D, the number of terminals increases as the number of bits increases. When the number of terminals increases in each semiconductor chip, not only does the area of the semiconductor chip increase, but also the number of test man-hours increases, resulting in a cost increase.

[0033] On the other hand, the semiconductor device 10 according to the embodiment of the present invention includes a first semiconductor chip 20 that transmits target data D, which is data to be transferred consisting of a plurality of bits, and a second semiconductor chip 30 that receives the target data D transmitted from the first semiconductor chip 20. The first semiconductor chip 20 includes a transmission-side peripheral circuit 21 that outputs each bit value of the target data D in a parallel transmission method in synchronization with the system clock CK0, and a parallel input and serial output circuit 24 that receives the target data D supplied in the parallel transmission method and outputs each bit value of the target data D in a serial transmission method in synchronization with a multiplication clock CK1 that is an integer multiple of the frequency of the system clock CK0.

[0034] The second semiconductor chip 30 includes a serial input and parallel output circuit 32 that receives the target data D supplied in the serial transmission method and outputs each bit value of the target data D in a parallel transmission method in synchronization with the multiplication clock CK1, a data holding circuit 34 that includes a plurality of registers 35 that hold each bit value of the target data D output from the serial input and parallel output circuit 32 in synchronization with the multiplication clock CK1, and a reception-side peripheral circuit 36 that captures each bit value of the target data D held in the data holding circuit 34 in synchronization with the system clock CK0.

[0035] According to the semiconductor device 10 according to the embodiment of the present invention, the target data D is converted into serial data in the first semiconductor chip 20 on the transmission side and transferred to the second semiconductor chip 30 on the reception side. Therefore, it is not necessary to prepare terminals for each bit of the target data D, so the number of terminals does not increase as the number of bits increases. Therefore, according to the semiconductor device 10 according to the present invention, it is possible to reduce the number of terminals used for data transfer performed between the first semiconductor chip 20 and the second semiconductor chip 30. As a result, it is possible to avoid an increase in the area of the semiconductor chip or an increase in the number of test man-hours as the number of terminals increases, and thus it is possible to avoid a cost increase.

[0036] Also, the frequency of the multiplied clock CK1 is n times the frequency of the system clock CK0, and when the number of bits of the target data D is m, since n>m, the parallel input serial output circuit 24 can complete the transfer of all bit values of the target data D within a period corresponding to one cycle of the system clock CK0.

[0037] FIG. 5 is a diagram showing an example of the configuration of a semiconductor device 10A according to a second embodiment of the present invention. The semiconductor device 10A is different from the semiconductor device 10 (see FIG. 2) according to the above-described first embodiment in that the multiplied clock generation circuit 38 is provided in the first semiconductor chip 20A which is the transmission side of the target data D. That is, according to the semiconductor device 10A according to the second embodiment, the multiplied clock CK1 is supplied from the first semiconductor chip 20A which is the transmission side of the target data D to the second semiconductor chip 30A which is the reception side of the target data D.

[0038] A delay is added to the transmission line of the multiplied clock CK1 due to a capacitance component or the like formed on the bonding surface between the semiconductor chips. Thus, according to the semiconductor device 10A, in the data holding circuit 34 provided in the second semiconductor chip 30A, there is a possibility that the arrival timing of the multiplied clock CK1 may be delayed with respect to the arrival timing of the target data D. In this case, there is a possibility that a bit value dropout (hold violation) of the target data D may occur in the data holding circuit 34. In order to avoid this, it is conceivable to insert a delay element into the transmission line of the target data D so that the arrival timing of the multiplied clock CK1 always precedes the arrival timing of the target data D in the data holding circuit 34. However, the amount of delay added to the transmission line of the multiplied clock CK1 varies due to variations in the semiconductor chips and does not become uniform, so it is necessary to individually set the delay amount in the delay element, and the design difficulty is high. Further, when there are a plurality of transmission lines for the target data D, it is necessary to add an optimal delay amount for each transmission line, which further increases the difficulty.

[0039] On the other hand, according to the semiconductor device 10 according to the first embodiment of the present invention, since the multiplied clock generation circuit 38 is provided in the second semiconductor chip 30 which is the reception side of the target data D, in the data holding circuit 34, it is guaranteed that the arrival timing of the multiplied clock CK1 precedes the arrival timing of the target data D. Therefore, it is possible to avoid the occurrence of a bit value dropout (hold violation) of the target data D in the data holding circuit 34 without inserting a delay element into the transmission line of the multiplied clock CK1.

[0040] Regarding the above embodiments, the following additional remarks are further disclosed. (Additional Remark 1) A semiconductor device including a first semiconductor chip that transmits target data, which is data to be transferred and consists of a plurality of bits, and a second semiconductor chip that receives the target data transmitted from the first semiconductor chip, wherein the first semiconductor chip, A transmission-side peripheral circuit that outputs each bit value of the target data in a parallel transmission method synchronized with the system clock, A parallel input and serial output circuit that receives the target data supplied in the parallel transmission method and outputs each bit value of the target data in a serial transmission method synchronized with a multiplied clock obtained by multiplying the frequency of the system clock by an integer, including the second semiconductor chip A serial input and parallel output circuit that receives the target data supplied in the serial transmission method and outputs each bit value of the target data in a parallel transmission method synchronized with the multiplied clock, A holding circuit including a plurality of registers that hold each bit value of the target data output from the serial input and parallel output circuit synchronized with the multiplied clock, A reception-side peripheral circuit that captures each bit value of the target data held in the holding circuit synchronized with the system clock, including a semiconductor device

[0041] (Appendix 2) The second semiconductor chip includes a multiplied clock generation circuit that generates the multiplied clock, The parallel input and serial output circuit, the parallel input and serial output circuit, and the holding circuit operate synchronized with the multiplied clock generated by the multiplied clock generation circuit The semiconductor device according to Appendix 1

[0042] (Appendix 3) The first semiconductor chip has a data output terminal through which the target data is output in the serial transmission method, The second semiconductor chip has a data input terminal to which the target data transmitted in the serial transmission method is input, The data output terminal and the data input terminal are connected The semiconductor device according to Appendix 1 or Appendix 2

[0043] (Appendix 4) The frequency of the multiplied clock is n times the frequency of the system clock, where when the number of bits of the target data is m, n > m The semiconductor device according to any one of Appendices 1 to 3.

[0044] (Appendix 5) The first semiconductor chip and the second semiconductor chip are stacked. The semiconductor device according to any one of Appendices 1 to 4.

Explanation of symbols

[0045] 10, 10A, 10X Semiconductor device 20, 20A, 20X First semiconductor chip 21 Transmission-side peripheral circuit 22 Register 23 Data transmission circuit 24 Parallel input serial output circuit 25 Transmission control circuit 30, 30A, 30X Second semiconductor chip 31 Data reception circuit 32 Serial input parallel output circuit 33 Reception control circuit 34 Data holding circuit 35 Register 36 Reception-side peripheral circuit 37 Register 38 Multiplied clock generation circuit 41 Data output terminal 42 Data input terminal 43 Signal output terminal 44 Signal input terminal 45 Clock input terminal 46 Clock output terminal 47 Clock input terminal 48 Clock output terminal 50 Bump 60 Package substrate CK0 System clock CK1 Multiplied clock

Claims

1. A semiconductor device including: a first semiconductor chip that transmits target data which is data to be transferred and consists of a plurality of bits; and a second semiconductor chip that receives the target data transmitted from the first semiconductor chip, wherein the first semiconductor chip includes: a transmission-side peripheral circuit that outputs each bit value of the target data in a parallel transmission manner in synchronization with a system clock; a parallel input serial output circuit that receives the target data supplied in the parallel transmission manner and outputs each bit value of the target data in a serial transmission manner in synchronization with a multiplied clock whose frequency is an integral multiple of the frequency of the system clock; and wherein the second semiconductor chip includes: a serial input parallel output circuit that receives the target data supplied in the serial transmission manner and outputs each bit value of the target data in a parallel transmission manner in synchronization with the multiplied clock; a holding circuit including a plurality of registers that hold each bit value of the target data output from the serial input parallel output circuit in synchronization with the multiplied clock; a reception-side peripheral circuit that captures each bit value of the target data held in the holding circuit in synchronization with the system clock; and the semiconductor device.

2. The second semiconductor chip includes a multiplied clock generation circuit that generates the multiplied clock, and the parallel input serial output circuit, the parallel input serial output circuit, and the holding circuit operate in synchronization with the multiplied clock generated by the multiplied clock generation circuit. The semiconductor device according to Claim 1.

3. The first semiconductor chip has a data output terminal through which the target data is output in a serial transmission manner, the second semiconductor chip has a data input terminal to which the target data transmitted in the serial transmission manner is input, and the data output terminal and the data input terminal are connected. The semiconductor device according to Claim 1.

4. The frequency of the multiplied clock is n times the frequency of the system clock, and when the number of bits of the target data is m, n > m. The semiconductor device according to Claim 1.

5. The first semiconductor chip and the second semiconductor chip are stacked. The semiconductor device according to Claim 1.

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