Method of manufacturing image sensor

Abstract

To provide an image sensor capable of efficiently detecting high-energy photons.SOLUTION: A method of manufacturing an image sensor includes: forming an epitaxial layer on a substrate; forming a gate layer on the substrate; forming one or more circuit element layers on the gate layer; thinning the substrate to create a thinned substrate in which at least a plurality of portions is exposed in the epitaxial layer; cleaning the exposed portions of the epitaxial layer to create a textured surface on the exposed portions of the epitaxial layer; forming an amorphous layer of pure boron at a first temperature on the textured surface, that is a light incident side, using a mixture including diborane and hydrogen; and further making a rise to a second temperature that is higher than the first temperature, thereby diffusing the boron inside of the textured surface of the epitaxial layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure generally relates to image sensors suitable for sensing radiation in the deep ultraviolet (DUV) and vacuum ultraviolet (VUV) wavelengths, and methods of fabricating image sensors of that kind. Such sensors are suitable for use in photomask, reticle, or wafer inspection systems and other applications.

Background Art

[0002] [Cross - Reference to Related Applications] This application claims priority based on U.S. Provisional Patent Application No. 62 / 943,173, filed on December 3, 2019, with Yung - Ho Alex Chuang, Yinying Xiaoli, Sisir Yalamanchili, John Fielden, and David Brown as inventors, the entire contents of which are incorporated herein by reference.

[0003] In the integrated circuit industry, there is a need to further improve the resolution of inspection tools to resolve and image features (outward characteristics) on integrated circuits, photomasks, reticles, solar cells, and charge - coupled devices that have become ever smaller, and to detect defects having sizes equal to or smaller than the sizes of those features.

[0004] For an inspection system operating at a short wavelength, e.g., a wavelength less than about 250 nm, such resolution can often be provided. Specifically, for the inspection of photomasks and reticles, since the inspection light phase shift caused by various patterns is equivalent or very similar to the phase shift caused during lithography, it is desirable to use a wavelength that is the same as or close to the wavelength used in lithography (e.g., 193.4 nm in current-generation lithography and 13.5 nm in future EUV lithography) to inspect the specimen. For the inspection of patterned semiconductor wafers, by widening the wavelength range, it is possible to reduce the sensitivity to small changes in layer thickness or pattern dimensions that may cause significant changes in reflectivity at individual wavelengths. Therefore, an inspection system that operates over a relatively wide wavelength range, e.g., a wavelength range including wavelengths in the near-UV, DUV, and / or VUV regions, may be advantageous.

[0005] To detect small defects or particles on photomasks, reticles, and semiconductor wafers, it is necessary to have a high signal-to-noise ratio. Since the statistical fluctuation in the number of photons detected (Poisson noise) is the fundamental limit for the signal-to-noise ratio, a high photon or particle beam density is required to ensure a high signal-to-noise ratio during high-speed inspection. In many cases, more than about 100,000 photons per pixel are required. Usually, since the inspection system is used 24 hours a day with only short pauses, even after operating for several months, the detectors are exposed to a large amount of radiation.

[0006] Photons with a vacuum wavelength of 250 nm have an energy of approximately 5 eV. The bandgap of silicon dioxide is approximately 10 eV. Photons of such wavelengths do not seem to be absorbed by silicon dioxide, but since the structure of silicon dioxide cannot be perfectly aligned with that of silicon crystals, silicon dioxide grown on the silicon surface must exhibit some dangling bonds (unbonded hands) at the interface with the silicon. Furthermore, since the silicon dioxide is amorphous, there may also be some dangling bonds within the material. In fact, there will be a non-negligible density of defects and impurities at the interface between the oxide and the underlying semiconductor, and photons with deep UV wavelengths, especially those with wavelengths less than approximately 250 nm, can be absorbed there. Furthermore, under high radiation beam density, two high-energy photons may arrive near the same location within a very short period (in nanoseconds or picoseconds), which can trigger the excitation of electrons to the conduction band of silicon dioxide by successive two absorption events or two-photon absorption.

[0007] What is further required of sensors used in inspection, metrology, and related applications is high sensitivity. As described above, a high signal-to-noise ratio is required. If a large number of incident photons are not converted into signals by the sensor, a higher-intensity light source will be required to maintain the same inspection or measurement speed compared to an inspection or metrology system with a more efficient sensor. With a high-intensity light source, the optical system within the device and the inspection or measurement target specimen may be exposed to high-intensity light, probably causing damage or degradation over time. High-intensity light sources are also more expensive, and in particular, those with DUV and VUV wavelengths are not likely to be available. Silicon reflects DUV and VUV light incident on itself at a high rate. For example, at wavelengths near 193 nm, silicon with a 2-nm oxide layer (e.g., a natural oxide layer) on its surface reflects approximately 65% of the light incident on itself. When an oxide layer of approximately 21 nm is grown on the silicon surface, the reflectivity decreases to around 40% at wavelengths near 193 nm. A detector with a reflectivity of 40% is considerably more efficient than one with a reflectivity of 65%, but a lower reflectivity, and thus higher efficiency, is desirable.

[0008] DUV and VUV wavelengths are strongly absorbed by silicon. The most absorption of such wavelengths occurs within about 10 nm or within several tens of nm from the silicon surface. The efficiency of a sensor operating at DUV or VUV wavelengths depends on how much of the electrons generated by the absorbed photons are collected before electron recombination. Silicon dioxide can form a high-quality interface with silicon with a low defect density. Most of the materials commonly used for antireflection coatings, and most other materials, when deposited directly on silicon, result in a very high density of electrical defects on the silicon surface. Even if there are a high density of electrical defects on the silicon surface, in sensors assumed to operate at visible wavelengths, since such wavelengths usually penetrate about 100 nm or more into the silicon before absorption, that is, they are hardly affected by the electrical defects on the silicon surface, it cannot become a problem. However, since DUV and VUV wavelengths are absorbed very close to the silicon surface, a significant portion of the generated electrons can recombine and be lost at or near the silicon surface due to the electrical defects on the surface and / or the trapped charges in the layer(s) on the surface, ultimately resulting in a low-efficiency sensor. That is, it is important to control the state of the silicon surface to reduce the loss of photoelectrons.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Patent Document 9

Patent Document 10

Patent Document 11

Patent Document 12

Patent Document 13

Patent Document 14

Patent Document 15

Patent Document 16

Non-Patent Document

[0010]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0011] Therefore, what is needed is an image sensor that can efficiently detect high-energy photons and overcomes some or all of the above-mentioned difficulties.

Means for Solving the Problems

[0012] According to one or more embodiments of the present disclosure, a low-reflectivity back-illuminated image sensor is disclosed. An image sensor according to an exemplary embodiment has a semiconductor membrane comprising an epitaxial layer, the epitaxial layer having a first surface and a textured second surface on the side opposite to the first surface. Also, an image sensor according to an exemplary embodiment has one or more circuit elements formed on the first surface of the epitaxial layer. Also, an image sensor according to an exemplary embodiment has a boron layer disposed on the textured second surface of the epitaxial layer. Also, in an exemplary embodiment, the textured second surface is provided with at least one type of pseudo-random distribution of upright pyramids, inverted pyramids, and nanocones. In another exemplary embodiment, the textured second surface is provided with at least one type of periodic distribution of upright pyramids, inverted pyramids, and nanocones. In another exemplary embodiment, the textured second surface is provided with at least one type of random distribution of upright pyramids, inverted pyramids, and nanocones. Also, an image sensor according to an exemplary embodiment is incorporated into an inspection system.

[0013] A method for manufacturing a low-reflectivity back-illuminated image sensor is disclosed in accordance with one or more embodiments of the present disclosure. In one exemplary embodiment, an epitaxial layer is formed on a substrate. In another exemplary embodiment, a gate layer is formed on the substrate. In yet another exemplary embodiment, one or more circuit element layers are formed on the gate layer. In still another exemplary embodiment, the substrate is thinned to produce a thinned substrate in which at least a plurality of portions of the epitaxial layer are exposed. In yet another exemplary embodiment, the exposed portions of the epitaxial layer are pre-etched. In still another exemplary embodiment, a surface texture is generated on the exposed portions of the epitaxial layer. In yet another exemplary embodiment, a boron layer is formed on the surface texture.

[0014] As can be understood, both the foregoing summary and the following detailed description are solely exemplary and explanatory and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the invention and, together with the general description given above, serve to explain the principles of the invention.

[0015] Those skilled in the art of the present disclosure (so-called persons having ordinary skill in the art) will be able to better understand the numerous advantages of the present disclosure by referring to the accompanying drawings.

Brief Description of the Drawings

[0016]

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Best Mode for Carrying Out the Invention

[0017] In this disclosure, specific illustrations and descriptions are made in connection with certain embodiments and their specific features. The embodiments described in this application should be regarded as illustrative rather than limiting. It should be immediately apparent to those skilled in the art that various modifications and changes can be made to the form and details without departing from the essence and technical scope of this disclosure. Hereinafter, reference will be made in detail to the disclosed subject matter depicted in the accompanying drawings.

[0018] The embodiments of this disclosure are directed to image sensors for semiconductor inspection and metrology. Specifically, image sensors are disclosed that are for DUV and / or VUV radiation, have high quantum efficiency, and long operating lifetimes. The image sensors are thinned from the back side and are thus highly sensitive to radiation impinging on the back side of the self-image sensors (when the image sensors are back-illuminated). The back-side silicon surface can be textured by wet chemical etching or other structure-forming methods, such as reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), ultra-high speed laser etching, electrochemical etching, electron beam lithography or photolithography-defined etching, mechanical grooving, etc., to form upright or inverted pyramids, nanocones (other tapered structures) on the surface. This textured surface can reduce the reflection of incident light and increase the absorbed light intensity over a wide band belonging to DUV and VUV.

[0019] Wet chemical etching can be a relatively inexpensive and more mature process compared to other structure formation methods and is widely used in CMOS manufacturing. Known techniques for forming pyramid-shaped structures on (100)-oriented silicon surfaces include those using an alkaline medium such as an alkali hydroxide, alkali carbonate, ammonia, or choline. Various etchants such as ethylenediamine pyrocatechol (EDP), hydrazine, sodium hydroxide (NaOH), sodium carbonate (Na2CO3), trisodium phosphate (Na3PO4), sodium silicate (Na2SiO3), potassium hydroxide (KOH), and tetramethylammonium hydroxide (TMAH) are known in this technical field. The most common recipe includes water, NaOH or KOH, and alcohol. The alcohol component can be ethylene glycol or isopropanol. These known methods for wet chemical etching for silicon structure formation are exclusively related to the generation of pyramid-shaped textures.

[0020] When texturing the surface of a silicon substrate, by selectively removing a portion of the material, upright or inverted pyramid-shaped structures are generated depending on the specific texturing procedure. As a result, the material density on that surface can be reduced to reduce the complex dielectric constant and cause a reduction in the wavelength dependence of surface reflection.

[0021] Deposited on the textured silicon is a thin layer of high-purity amorphous boron (e.g., about 2 nm to about 20 nm thick). According to certain embodiments, one or more additional material layers can be deposited on the boron. By appropriately selecting the thickness and material of each layer, the transmission of the wavelength of interest into the image sensor can be increased. According to one embodiment, an anti-reflection coating can be deposited on the boron layer. The anti-reflection coating material can be made to contain one or more of magnesium fluoride (MgF2), hafnium oxide (HfO2), strontium tetraborate (SrB4O7), silicon dioxide (SiO2), silicon nitride (Si3N4), titanium dioxide (TiO2), and aluminum oxide (Al2O3).

[0022] The boron layer can be formed on the clean silicon using a high-temperature deposition process (e.g., about 600 °C to 800 °C) or a low-temperature deposition process (e.g., about 350 °C to 450 °C) in such a way that it has a thickness in the range of 2 to 5 nm (e.g., about 2 to 4 nm) including all ranges and values in 0.1 nm increments, resulting in a continuous and substantially pure boron layer without pinholes. The boron layer seals the silicon surface against oxidation and provides reliable hermetic sealing, thereby avoiding the oxidation problem of silicon. Although a few atomic percent (e.g., less than 10% or less than 5%) of oxygen can remain at the interface between the boron layer and the silicon surface, since it is hermetically sealed, the oxygen content will not increase significantly over time (e.g., over a period of one year). Such a low oxygen-to-silicon ratio means that a continuous silicon dioxide layer does not appear at the interface.

[0023] The image sensor described in the present application can be manufactured using CCD (Charge-Coupled Device) or CMOS (Complementary Metal-Oxide-Semiconductor) technology. The image sensor can be a two-dimensional area sensor or a one-dimensional array sensor.

[0024] Methods for manufacturing high quantum efficiency image sensors for DUV and / or VUV imaging are described. Image sensors manufactured in accordance with these methods are capable of long-life operation under high beam DUV and VUV radiation beams. These methods include a process step of forming a textured surface on a semiconductor (preferably silicon) wafer and a process step of depositing a high-purity amorphous boron layer on the textured silicon surface. An optional anti-reflection coating may be formed on the boron layer.

[0025] An inspection system is also described. The inspection system includes an illumination source, an optical system, and a detector. The optical system is configured to direct and focus radiation from the illumination source onto a specimen. The detector is configured to receive reflected or scattered light from the specimen, and the optical system is further configured to collect and focus the reflected or scattered light onto the detector. The detector can be provided with one or more image sensors. At least one image sensor is provided with a semiconductor membrane having a circuit element formed on one side of the semiconductor membrane and a boron-coated textured surface on the opposite side of the semiconductor membrane. An optional anti-reflection coating may be formed on the boron layer.

[0026] FIG. 1 depicts a schematic external view of a characteristic elucidation system 100 according to one or more embodiments of the present disclosure. The characteristic elucidation system 100 (or "tool") according to one embodiment has a characteristic elucidation subsystem 101 and a controller 114. The characteristic elucidation system 100 can be configured as an inspection system or a metrology system. For example, the characteristic elucidation system 100 can be an optical inspection system (or "tool"), a review system (or "tool") or an image-based metrology system (or "tool"). In this case, the characteristic elucidation subsystem 101 can be, but is not limited to, an inspection subsystem or a metrology subsystem configured to inspect or measure a specimen 108. The characteristic elucidation subsystem १०१ of the characteristic elucidation system 100 can be communicatively coupled to the controller 114. At the controller 114, measurement data can be received from the detector assembly 104 of the characteristic elucidation subsystem, thereby elucidating (e.g., inspecting or measuring) a structure on or within the specimen 108 and / or controlling a part or parts of the characteristic elucidation system 100.

[0027] The specimen 108 can include any specimen known in the art, such as, but not limited to, a wafer, a reticle, a photomask, etc. According to one embodiment, the specimen 108 can be placed on the stage assembly 112, and the movement of the specimen 108 can be easily performed. The stage assembly 112 can include any stage assembly known in the art, such as, but not limited to, an XY stage, an Rθ stage, etc. Also, according to one embodiment, the height of the specimen 108 can be adjusted by the stage assembly 112 during inspection to continuously focus on the specimen 108. Further, according to one embodiment, the characteristic elucidation subsystem 101 can be moved up and down during inspection to continuously focus on the specimen 108.

[0028] Also, the characteristic elucidation system 100 according to one embodiment has an illumination source 102 configured to generate an illumination beam 111. The illumination source 102 may include any illumination source known in the art suitable for generating the illumination beam 111. For example, the illumination source 102 can be one that emits DUV and / or VUV radiation. For example, the illumination source 102 can be one having one or more lasers. Also for example, the illumination source 102 can be one having a broadband illumination source.

[0029] Also, the characteristic elucidation system 100 according to one embodiment has an illumination arm 107 configured to direct the illumination from the illumination source 102 towards the specimen 108. The illumination arm 107 can incorporate optical members known in the art regardless of their number and type. In one embodiment, the illumination arm 107 is assumed to have one or more optical elements 103. At that time, the illumination arm 107 can be configured to focus the illumination from the illumination source 102 onto the surface of the specimen 108. It should be noted here that the one or more optical elements 103 include, but are not limited to, one or more lenses (e.g., objective lens 105), one or more mirrors, one or more polarizers, one or more prisms, one or more beam splitters, etc., and can include any optical element known in the art.

[0030] Also, in one embodiment, a condenser arm 109 is configured to collect the illumination reflected, scattered, diffracted, and / or radiated by the specimen 108. Also, according to one embodiment, the illumination from the specimen 108 can be directed and / or focused by the condenser arm 109 onto the sensor 106 of the detector assembly 104.

[0031] Detector 104 can have one or more image sensors 106 described in the present application. For example, the one or more image sensors 106 of the present disclosure may include, but are not limited to, boron-coated back-illuminated CCD sensors with textured back and boron-coated back-illuminated CMOS sensors with textured back. Detector 104 can have a two-dimensional array sensor or a one-dimensional line sensor.

[0032] In certain embodiments, a line on specimen 108 is illuminated by inspection system 100, and scattered and / or reflected light is collected in one or more dark-field and / or bright-field light collection channels. The image sensor in this type of embodiment may be a line sensor. In certain embodiments, a plurality of spots on specimen 108 are illuminated by inspection system 100, and scattered and / or reflected light is collected in one or more dark-field and / or bright-field light collection channels. The image sensor in this type of embodiment may be a two-dimensional array sensor.

[0033] Also, in certain embodiments, detector assembly 104 is communicatively coupled to one or more processors 116 provided in controller 114. The one or more processors 116 can be communicatively coupled to memory 118. By executing a set of program instructions stored in memory 118, the one or more processors 116 are configured to acquire measurement data from one or more sensors 106 provided in detector assembly 104 and / or to control one or more parts of characterization system 100.

[0034] In one embodiment, the illumination source 102 is a continuous light source. Examples of such illumination source 102 include, but are not limited to, arc lamps, laser-excited plasma light sources, continuous wave (CW) lasers, and the like. Also, in one embodiment, the illumination source 102 is a pulsed light source. Examples of such illumination source 102 include, but are not limited to, mode-locked lasers, Q-switched lasers, plasma light sources pumped by mode-locked or Q-switched lasers, and the like. Examples of suitable light sources that can be included in the illumination source 102 are described in Patent Document 1 in the name of Kirk et al. entitled "Methods and systems for providing illumination of a specimen for a process performed on the specimen", Patent Document 2 in the name of Bezel et al. entitled "System and method for transverse pumping of laser-sustained plasma", and Patent Document 3 in the name of Chuang et al. entitled "High brightness laser-sustained plasma broadband source", and they are hereby incorporated herein by reference respectively.

[0035] The feature elucidation system is Patent Document 4 issued on February 13, 2018 to Vazhaeparambil et al. under the title of "TDI Sensor in a Darkfield System", Patent Document 5 issued on March 8, 2018 to Romanovsky et al. under the title of "Wafer Inspection", Patent Document 6 issued on June 7, 2011 to Armstrong et al. under the title of "Split Field Inspection System Using Small Catadioptric Objectives", Patent Document 7 issued on October 19, 2010 to Chuang et al. under the title of "Beam Delivery System for Laser Dark-Field Illumination in a Catadioptric Optical System", Patent Document 8 issued on December 7, 1999 to Shafer et al. under the title of "Ultra-Broadband UV Microscope Imaging System with Wide Range Zoom Capability", Patent Document 9 issued on April 28, 2009 to Leong et al. under the title of "Surface Inspection System Using Laser Line Illumination with Two Dimensional Imaging", Patent Document 10 issued on July 14, 2015 to Kandel et al. under the title of "Metrology Systems and Methods", and Patent Document 11 issued on [specific date] to Chuang et al. under the title of "Broad Band Objective Having Improved Lateral Color Performance" It should be noted that there seems to be an incomplete citation at the end of the original text where the date for the last patent document is missing. The translation is done as accurately as possible based on the provided content.Patent Document 11 issued on January 6, 2009, titled "Optical Metrology With Reduced Sensitivity To Grating Anomalies" by Zhuang et al., Patent Document 12 issued on October 18, 2016, titled "Dynamically Adjustable Semiconductor Metrology System" by Wang et al., Patent Document 13 issued on January 5, 2016, titled "Focused Beam Spectroscopic Ellipsometry Method and System" by Piwonka-Corle et al., Patent Document 14 issued on March 4, 1997, and Patent Document 15 issued on October 2, 2001, titled "Apparatus for Analyzing Multi-Layer Thin Film Stacks on Semiconductors" by Rosencwaig et al. are outlined. Accordingly, the entire contents of all of them are incorporated herein by reference.

[0036] It should be noted that the technical scope of the present disclosure is not limited to the characteristic elucidation system 100. Rather, systems in which one or more of the image sensors of the present disclosure are incorporated may include inspection systems, metrology systems, lithography systems, and any other systems known in the art, including but not limited to these.

[0037] It should be noted here that one or more members provided in the system 100 can be communicatively coupled to various other members provided in the system 100 in any manner known in the art. For example, one or more processors 116 can be communicatively coupled to each other and to other components via a wired connection (e.g., copper wire, optical fiber cable, etc.) or a wireless connection (e.g., RF coupling, IR coupling, WiMax®, Bluetooth®, 3G, 4G, 4G LTE, 5G, etc.).

[0038] One or more processors 116 can include any one or more processing elements known in the art. In that sense, one or more processors 116 can include any microprocessor-type device configured to execute algorithms and / or instruction sets. One or more processors 116 can be configured by a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, or other computer system (e.g., a network-connected computer) configured to execute a suitable program to operate the system 100 as described throughout the present disclosure. It should be recognized that the steps described throughout the present disclosure may be executed by a single computer system or, alternatively, by a plurality of computer systems. Further, it should be recognized that the steps described throughout the present disclosure may be executed by any one or more of one or more processors 116. In general, the term "processor" can be defined broadly to include all devices having one or more processing elements that execute program instructions obtained from a memory 118. Further, a processor or logic element suitable for executing at least a portion of the steps described throughout the present disclosure may be incorporated into various subsystems of the system 100 (e.g., the illumination source 102, the detector assembly 104, the controller 114, etc.). Accordingly, the foregoing description should be construed as illustrative rather than as a limitation on the present disclosure.

[0039] The memory 118 can include any storage medium known in the art suitable for storing program instruction groups executable by one or more associated processors 116, as well as data received from its metrology subsystem and / or inspection subsystem. For example, the memory 118 can include a non-transitory memory medium. For example, the memory 118 can include, but is not limited to, read-only memory (ROM), random access memory (RAM), magnetic or optical storage devices (e.g., disks), magnetic tapes, solid state drives, etc. Further noted is that the memory 118 may be housed within a common controller housing together with one or more processors 116. According to an alternative embodiment, the memory 118 can be remotely located relative to the physical locations of the processor 116, the controller 114, etc. Also, in some embodiments, the program instruction groups held by the memory 118 are for causing one or more processors 116 to execute the steps described throughout this disclosure.

[0040] FIG. 2 depicts a flowchart showing an image sensor manufacturing method 200 according to an exemplary embodiment of the present disclosure.

[0041] In step 201, front-side circuit elements are generated without metal interconnect members. One or more standard semiconductor processing steps, such as lithography, deposition, ion implantation, annealing, and / or etching, can be used to generate the circuit elements. In step 201, CCD and / or CMOS sensor elements and devices may be generated. Since those circuit elements can be generated within an epitaxial (epi) layer on the front surface of the wafer, they are also referred to as front-side circuit elements. In embodiments, the epitaxial layer is about 10 nm to 40 nm thick. In embodiments, both the epi layer and the substrate are doped with a p-type dopant (e.g., boron), and the dopant concentration in the epi layer is made significantly lower than that of the bulk wafer. The resistivity of the epitaxial layer can be 10 to 2000 Ωcm, and the resistivity of the substrate can be less than about 1 Ωcm.

[0042] In step 203, the active sensor area is thinned on the back side. For example, those active sensor areas, and even the entire wafer, can be thinned from the back side. This thinning can be achieved by using a combination of polishing and etching to expose the epi layer. In various embodiments, the wafer is polished from the back side so that the wafer is about 200 nm to 300 nm thick. Then, the front surface and the frame area around the active sensor area are protected with a material such as photoresist or other suitable materials. Next, by using a chemical etchant to etch and remove the portion of the bulk wafer on the active sensor area, the active sensor area can be exposed. Since the dopant concentration and defect density in the bulk wafer are much higher than those in the epi layer, the etching rate of the bulk semiconductor material is much higher than that of the epi layer. When the epi layer is reached, the etching process slows down, so a membrane area with a uniform thickness can be obtained. Also, in certain embodiments, the image sensor wafer is bonded to a support wafer made of, for example, quartz, silicon, sapphire or other materials. Then, a polishing process or a combination of a polishing process and a chemical etching process can be used to polish the entire wafer until only the epi layer remains.

[0043] In step 205, a protective layer is deposited on the front surface to protect the front-side circuit elements in steps 207 to 213. For example, since subsequent etching and deposition processes can affect silicon, it is better to protect the exposed silicon or polysilicon on the front surface. According to various embodiments, step 205 can be performed prior to step 203 so that the protective layer can provide additional protection for the front surface during the backside thinning process (step 203), or so that the protective layer can provide a flat surface for bonding with the support wafer. According to various embodiments, the protective layer can be made of, for example, silicon nitride deposited using plasma-assisted CVD or other dielectric layers.

[0044] In Process 207, surface texturing is performed by generating a pseudo-random or periodic pattern on the back surface of the wafer. Prior to generating the pseudo-random or periodic pattern for surface texturing in this process, the back surface may be cleaned and prepared. The pseudo-random or periodic texture pattern may be formed on the back surface of the wafer, for example, through a mask / etching process. By using a patterning process, periodic inverted pyramids, periodic upright pyramids, pseudo-random inverted pyramids, pseudo-random upright pyramids, periodic nanocones, pseudo-random nanocones, etc. can be generated. Details regarding the creation of various pattern structures will be described later according to the descriptions in FIGS. 3A to 3I.

[0045] Alternatively and / or in addition, the back surface may be cleaned and prepared as a pre-etch surface roughness for surface texturing. Natural oxides and any contaminants, such as organic substances and metals, should be removed from the back surface during this cleaning. According to a preferred embodiment, the cleaning can be performed using a diluted HF solution or an RCA cleaning process (which is a well-known set of wafer cleaning processes including the removal of organic contaminants, oxide thin layers, and ionic contaminants). During the preparation after cleaning, the wafer can be preferably dried using a Marangoni drying technique (a surface tension-based drying technology) or a similar technology to keep the surface dry and eliminate watermarks. After cleaning, by using grits of various sizes to remove several hundred nanometers to several micrometers of the wafer, an appropriate pre-etch surface roughness that enables anisotropic wet etching can be generated.

[0046] In various embodiments, the back surface is etched, thereby generating a pseudo-random, periodic, and / or random textured surface. In various embodiments, anisotropic wet etching is used to generate a pseudo-random, periodic, and / or random surface texture on a silicon wafer. According to preferred embodiments, an alkaline solution such as KOH containing IPA can be used as an etchant. The etching rate is anisotropic and varies depending on the plane orientation. For example, the etching rate along the (100) plane is about 10 times higher than that along the (111) plane. This leads to the formation of sharp pyramid-shaped structures. The process of etching a crystalline silicon wafer using an aqueous KOH solution is as follows. First, KOH is decomposed in water to generate K + and OH - ions. Second, an H-terminated silicon surface is generated by attacking the backside junction with those OH - ions. Then, those OH - ions are reacted with the H-terminated silicon to convert it to an OH-terminated surface. Finally, the surface silicon is removed as Si(OH)6 2- or K2SiO3. Also, IPA acts as a surfactant to open surface sites. The etching rate depends on the concentration of the existing OH - ions and H2O, and its accessibility to the surface sites vacated by IPA.

[0047] There can be numerous recipes for wet etching to generate pseudo-random, periodic, pyramidal surfaces and / or random textures on a silicon wafer, and these can be used in the embodiments of the present disclosure. According to one recipe, an aqueous solution of 6 (wt%) KOH with 4 (wt%) IPA added can be used to generate random upright pyramids. By using photolithography to pattern a mask on the silicon surface, it becomes possible to etch pseudo-random and / or periodic upright or inverted pyramids. The pattern generated by lithography can have a pseudo-random structure, that is, the pattern appears random at a short scale length such as a scale length of less than several micrometers, but can repeat at a scale length of several tens of micrometers or more.

[0048] The textured surface can reduce the reflection of incident light and increase the absorbed light intensity over a wide spectral bandwidth. Such a phenomenon is described in Patent Document 16 issued on September 17, 2002, and Non-Patent Document 1, and their entire contents are incorporated herein by reference. According to alternative embodiments, the texturing of the silicon surface can be achieved by one or more of wet chemical etching, reactive ion etching (RIE), ultra-fast laser etching, electrochemical etching, electron beam lithography, and mechanical grooving. Wet chemical etching may be relatively inexpensive compared to other structure-forming methods.

[0049] Known techniques for wet chemical etching for forming a pyramidal structure on a (100)-oriented silicon surface include those using an alkaline medium, such as an alkali hydroxide, an alkali carbonate, ammonia, or choline. The most common recipes include water, sodium hydroxide or potassium hydroxide, and alcohol. The alcohol component can be ethylene glycol or isopropanol. These known methods for wet chemical etching for silicon structure formation are solely related to the generation of pyramidal textures.

[0050] When texturing the surface of a silicon substrate, by selectively removing a portion of the material, an upright or inverted pyramid-shaped structure is generated depending on the specific texturing procedure. As a result, the material density on that surface can be reduced, the complex dielectric constant can be decreased, and a reduction in the wavelength dependence of surface reflection can be achieved.

[0051] According to various embodiments, upright or inverted pyramid-shaped surface textures or nanocone-shaped surface textures can also be created by other methods, such as reactive ion etching (RIE) (with or without inductive coupling), ultra-fast laser etching, electrochemical etching, electron beam lithography, mechanical grooving, etc.

[0052] In step 209, the backside textured surface can be cleaned and prepared for boron deposition. In this cleaning, native oxide and any contaminants, such as organics and metals, should be removed from the backside. According to a preferred embodiment, the cleaning can be performed using a diluted HF solution or an RCA cleaning process (which is a well-known set of wafer cleaning steps including the removal of organic contaminants, oxide thin layers, and ionic contaminants). During the cleaning and preparation, the wafer can be preferably dried using Marangoni drying technology (a surface tension-based drying technique) or a similar technique to eliminate watermarks while keeping the surface dry. According to preferred embodiments, by protecting the wafer in a controlled atmosphere in step 209 (e.g., using dry nitrogen), the regrowth of native oxide prior to step 211 can be reduced.

[0053] In process 211, a boron layer is deposited on the textured back surface. For example, by depositing an amorphous layer of pure boron on the textured silicon surface, the silicon can be hermetically sealed to prevent oxidation. According to various embodiments, this deposition can be carried out at a temperature of about 600 - 800 °C using a mixture of diborane and hydrogen gas, thereby creating a continuous and substantially pure boron layer without pinholes. In this embodiment, in process 211, the temperature can be further increased to, for example, 850 - 900 °C over a period of about 2 - 10 minutes, so that boron can be diffused into the textured silicon surface, thereby generating a p-type doped silicon layer adjacent to the boron layer. According to an alternative embodiment, a mixture of diborane, hydrogen and nitrogen can be used to deposit a continuous and substantially pure boron layer without pinholes at a temperature of about 350 °C - about 450 °C. According to various embodiments, immediately before boron deposition, a boron-doped epitaxial silicon thin layer can be grown on the silicon surface. A detailed description of the growth of the boron-doped epitaxial silicon thin layer can be found in U.S. Patent Application No. 16 / 562396, entitled "Back-illuminated Sensor and Method of Manufacturing a Sensor", which is pending and assigned to the applicant of the present application, and the entire content thereof is incorporated herein by reference. The thickness of the boron layer can depend on the intended use of the sensor. Typically, the boron layer thickness is about 2 nm - 20 nm, including all ranges and values in 0.1 nm increments. The boron layer may have a uniform thickness or may be deposited differently on the pyramids and the rest of the textured surface. The minimum thickness is generally limited by the requirement of a pinhole-free and uniform film. The maximum thickness is generally determined by the absorption of the photons of interest by the boron. The boron layer avoids the oxidation problem of silicon by hermetically sealing the silicon surface against oxidation with high reliability. Although a few atomic percent (e.g., less than 10% or less than 5%) of oxygen may remain at the interface between the boron layer and the silicon surface, since it is hermetically sealed, the oxygen content will not increase significantly over time (e.g., over a period of one year).Such a low oxygen-to-silicon ratio means that a continuous silicon dioxide layer does not appear at the interface. Further details regarding boron deposition can be found in Non-Patent Document 2, the entire content of which is incorporated herein by reference.

[0054] The term "substantially pure boron layer" should be understood to mean a layer in which the majority is boron element. Some impurities, such as silicon or carbon, may be present on its surface or within the lattice. For example, boron silicide may be present at the boron layer / substrate interface. Oxygen may be present in the bulk of the layer, but it should not be in an easily detectable amount. That is, the layer only needs to contain boron and be composed of only boron or essentially only boron. The boron content in the boron layer can be more than 75%, more than 80%, more than 85%, more than 90%, more than 95%, more than 96%, more than 97%, more than 98% or more than 99%.

[0055] The purity and pinhole-free property of this boron layer are important in terms of the sensitivity and lifespan of the image sensor disclosed in the present application. If not all natural oxide films are removed from the surface of the epitaxial layer prior to boron deposition, the natural oxide will be affected by DUV and VUV photons, leading to deterioration of sensor performance during use. Even if all natural oxides have been removed prior to boron deposition, if there are pinholes in the boron layer, oxygen may reach the silicon through these pinholes after treatment, and the surface of the silicon may be oxidized.

[0056] According to various embodiments, after or during step 211, other layers can also be deposited on the boron layer. Among those other layers, an antireflection coating composed of one or more materials such as magnesium fluoride (MgF2), hafnium oxide (HfO2), strontium tetraborate (SrB4O7), silicon dioxide (SiO2), silicon nitride (Si3N4), titanium dioxide (TiO2), aluminum oxide (Al2O3), etc. can be included. Even if the antireflection coating is affected by DUV and VUV radiation, due to the boron layer existing between the antireflection coating and the epi layer, the epi layer is shielded from the trapped charges in the antireflection coating, so it is guaranteed that the sensitivity of the image sensor is not significantly impaired.

[0057] In step 213, the protective layer is removed or patterned. For example, the protective layer can be removed, or holes or vias can be created in the protective layer and / or the support wafer to enable electrical connection to the circuit elements. According to an embodiment, the support wafer can be removed. In that process, one or more of interconnecting members, vias, and bonding pads can also be created. Those connecting members can be formed of Al, Cu, or other metals. A passivation layer for protecting the circuit elements and the connecting members can also be deposited on the front surface.

[0058] In step 215, the completed circuit elements are packaged. The package can involve flip-chip bonding or wire bonding of the chip to the substrate. The package may be provided with a window that passes the wavelength of interest, or may be equipped with a seal or flange for hermetic sealing of the interface to the vacuum.

[0059] Figures 3A - 3I relate to one or more embodiments of the present disclosure and depict various pseudo-random and periodic pattern methods implemented in the image sensors of the embodiments.

[0060] FIG. 3A depicts a surface 300 patterned through a mask and an etching process according to one or more embodiments of the present disclosure. In this embodiment, anisotropic wet etching of the wafer surface is performed through a mask 302. The mask 302 can be a photoresist, a polymer, or a hard mask, such as a SiN mask. The wet etching process can be an alkaline etching recipe, such as by KOH, TMAH, etc. In this process, the <111> plane of the Si lattice of the wafer is attacked by etching. Thereby, etching occurs under the mask, and as a result, <111> faceted pyramids due to preferential <111> plane etching appear. This etching is continued until the bottom and top of the pyramid are as small as possible. Finally, when the etching is completed, the mask is removed. The polymer or photoresist mask can be removed using a solvent, and a hard mask such as SiN can be removed using an HF solution. Any residue can be removed by subsequently cleaning the Si surface using a standard silicon surface cleaning method (e.g., HF etching is performed during the narrow interval of RCA cleaning, and the surface oxide grown during the cleaning is removed). Since photosensitive etching protection is discussed in Non-Patent Document 3, the entire content thereof is incorporated herein by reference. Since vertical nanorods are discussed in Non-Patent Document 4, the entire content thereof is incorporated herein by reference. Since wet etching of silicon is discussed in Non-Patent Document 5, the entire content thereof is incorporated herein by reference.

[0061] FIG. 3B depicts a mask 310 suitable for generating inverted pyramids on the surface 300 of a wafer in accordance with one or more embodiments of the present disclosure. The aperture size selected in this embodiment is about 100 nm, and each exposed area is arranged at 200 nm intervals. It should be noted that the technical scope of the present disclosure is not limited to this aperture size or spacing, and they are presented solely for illustrative purposes. The aperture size can vary depending on the patterning method used. The patterning may or may not utilize proximity optics that result in smaller features, but can be achieved using advanced photolithography tools. Electron beam lithography may be used to generate the pattern.

[0062] FIG. 3C depicts a mask 320 suitable for generating upright pyramids on the surface 300 of a wafer in accordance with one or more embodiments of the present disclosure. It should be noted that the pattern of mask 320 is the reverse of the pattern of mask 310 described in FIG. 3B. It should be noted that the method of creating and the dimensions of mask 310 can be extended to mask 320.

[0063] FIG. 3D depicts a mask 330 suitable for generating pseudo-random inverted pyramids on the surface 300 of a wafer in accordance with one or more embodiments of the present disclosure. It should be noted that the method of creating mask 310 can be extended to mask 330. For the purposes of the present disclosure, a pseudo-random pattern is defined as a pattern that lacks obvious short-range regularity while exhibiting long-range regularity. FIG. 3D is an illustration of one such pattern, where the average size of the inverted pyramids that can be obtained is about 200 nm, while to recognize the periodicity of the pattern, a larger area, for example, a length scale of about 1000 nm, must be considered. This long-range regularity can be made even longer, and a unit cell can be formed with a length of 1 mm or 1 cm or more. It should be noted that the technical scope of the present disclosure is not limited to an aperture size of about 200 nm or the long-range regularity scale described in FIG. 3D, and these are presented solely for illustrative purposes.

[0064] FIG. 3E depicts a mask 340 suitable for generating pseudo-random upright pyramids on the surface 300 of a wafer in accordance with one or more embodiments of the present disclosure. It should be noted that the pattern of the mask 340 is the reverse of the pattern of the mask 330 described in FIG. 3D. It should be noted that the method of creating and the dimensions of the mask 330 can be extended to the mask 340.

[0065] FIG. 3F depicts the surface 300 including periodic nanocones patterned through a mask 352 and an etching process in accordance with one or more embodiments of the present disclosure. This type of etching can be accomplished by masking the silicon surface with a photoresist mask or a hard mask having a lower etching selectivity compared to Si, such as silicon dioxide, aluminum oxide, etc. The pattern can be defined by advanced lithography or electron beam lithography involving multiple patterning. The etching can be performed through inductively coupled reactive ion etching (ICPRIE) or reactive ion etching (RIE) using etching chemicals such as SF6 / C4F8, SF6 / O2, etc. The gradient of the nanocone sidewalls can be varied by changing process conditions, such as plasma power, gas mixing ratio, or substrate temperature during etching. Since the etching recipes are described in Non-Patent Documents 6 to 8, the entire content thereof is incorporated herein by reference, respectively.

[0066] FIG. 3G depicts a mask 360 suitable for generating periodic nanocones on the surface 300 of a wafer in accordance with one or more embodiments of the present disclosure. In this embodiment, the aperture size is less than about 50 nm and each exposed area is spaced at about 200 nm intervals. It is noted that the technical scope of the present disclosure is not limited to this aperture size or spacing, and they are presented solely for illustrative purposes. The aperture size can vary depending on the patterning method used. According to various embodiments, the masking area can be defined by electron beam lithography by depositing Al2O3 in the holes of the patterned resist and then removing the resist by a resist lift-off process to yield the illustrated pattern.

[0067] FIG. 3H depicts the surface 300 including pseudo-random nanocones patterned through a mask 354 and an etching process in accordance with one or more embodiments of the present disclosure. It is noted that the pseudo-random nanocones of FIG. 3H are produced by a pseudo-random etching mask (e.g., a mask that can be defined by electron beam lithography), although they are an etching recipe similar to the periodic pattern in FIG. 3F. Due to differences in the size of the masking area, small variations can appear in the height and width of the nanocones.

[0068] FIG. 3I depicts a mask 380 suitable for generating pseudo-random nanocones on the surface 300 of a wafer in accordance with one or more embodiments of the present disclosure. It is noted that the method of creating mask 360 can be extended to mask 380. FIG. 3I is an illustration of a pseudo-random pattern, where the average size of the nanocones that can be obtained is less than about 50 nm, while to recognize the periodicity of the pattern, a larger area, for example, a length scale of about 1000 nm, must be considered. It is noted that the technical scope of the present disclosure is not limited to an aperture size of less than about 50 nm or the long-distance regularity scale described in FIG. 3I, and these are presented solely for illustrative purposes.

[0069] FIG. 4A depicts a cross-section of a portion of an image sensor 400a having a low reflectivity back-illuminated boron-coated textured back 404 in accordance with one or more embodiments of the present disclosure. Note that FIG. 4A is not drawn to true scale and some features are emphasized for clarity purposes. In various embodiments, a silicon wafer is processed by one of the methods described herein. In various embodiments, circuit elements 420 are created on a first surface of an epitaxial silicon layer 402. In various embodiments, a protective layer 422 is added to protect the circuit elements 420. The protective layer 422 is as described hereinabove and can have a support wafer bonded to the first surface of the epitaxial silicon layer. In this embodiment, a textured surface 404 having upright pyramids 410 in a pseudo-random, periodic, and / or random distribution covers a light-sensing portion of a second surface of the epitaxial silicon layer. This textured surface 404 reduces the complex dielectric constant by reducing the material density at the surface, thereby causing a reduction in the wavelength dependence of surface reflection, increasing the amount of light absorbed by this image sensor, and improving the reflectivity and thus the efficiency.

[0070] In this example, the plane formed by the first surface of the epitaxial silicon layer 402 prior to fabricating the circuit element is of the (100) plane orientation (or any one of the planes belonging to the <100> plane family) as shown in the figure. After etching, the second surface of the epitaxial silicon layer has a plurality of faceted pyramid-shaped peaks. Specifically, those upright pyramids 410 have triangular sides of the (111) plane (or any one of the planes belonging to the <111> plane family) and a base group along the (100) plane as shown in the figure. Note that even if one or more sides of the pyramid are not perfectly or precisely aligned with the <111> plane, the reflectivity can be reduced as expected. According to various embodiments, the image sensor 400a can be optimized to be highly sensitive over a wavelength range of about 190 nm to about 450 nm. The typical linear dimension 411 of the pyramid base in this embodiment is about 200 nm. Since the textured back surface 404 is provided with a group of pyramids having a pseudo-random, periodic, and / or random distribution, some pyramids may have a base larger than its typical linear dimension, and some pyramids may have a base smaller than its typical linear dimension. For example, about 80% or more of those pyramids may have a linear dimension of 150 nm to 300 nm. In a sensor optimized for another wavelength range, another typical linear dimension may be used. The typical linear dimension of the pyramid can be controlled by adjusting one or more etching conditions, such as etchant concentration, temperature, and / or etching time. The pyramid base described in FIG. 4A is aligned at an equal distance from the first surface of the epitaxial silicon layer 402. It should be noted that the technical scope of this disclosure is not limited to this arrangement, which is presented for convenience. In fact, the pyramids on the surface 404 do not have to be precisely aligned.

[0071] In various embodiments, a high-purity amorphous boron thin layer 405 (e.g., about 2 nm to about 20 nm thick) is deposited on the textured silicon 404. This boron layer 405 hermetically seals the textured silicon, preventing or limiting oxidation. The boron layer 405 can be formed as described hereinabove. For example, the boron layer 405 can be about 5 nm thick (i.e., about 20 to 25 atomic layers of boron). The boron layer 405 can be made to have a uniform thickness or can be deposited on those pyramids in a manner different from the rest of the textured surface.

[0072] According to various embodiments, an antireflection coating 406 can be added to the textured surface 404 to further reduce the reflectivity. The antireflection coating can be made to contain one or more of magnesium fluoride (MgF2), hafnium oxide (HfO2), strontium tetraborate (SrB4O7), silicon dioxide (SiO2), silicon nitride (Si3N4), titanium oxide (TiO2), and aluminum oxide (Al2O3).

[0073] It should be noted that the textured silicon surface 404 described in the present application can be created under any type of silicon surface conditions. For example, the sawn surface, etched surface, lapped surface, and polished surface can be treated to obtain the desired textured silicon surface 404.

[0074] FIG. 4B depicts a cross-section of a portion of an image sensor 400b having a low reflectivity backside illuminated boron coated textured backside 414 according to one or more additional embodiments of the present disclosure. It should be noted that unless otherwise noted, the description of FIG. 4A should be construed as applying to FIG. 4B. In embodiments, circuit elements 420 are fabricated on a first surface of epitaxial silicon layer 402. In embodiments, a protective layer 422 is deposited on the first surface, thereby protecting the circuit elements 420. The protective layer 422 is as described above and can be assumed to have a support wafer bonded to the first surface of the epitaxial silicon layer. A textured surface 414 provided with inverted pyramids 430 having a pseudo-random, periodic, and / or random distribution covers a light sensing portion of the second surface of the epitaxial silicon layer. This textured surface 414 reduces the complex dielectric constant by reducing the material density at the surface, thereby generating a reduction in the wavelength dependence of surface reflection, increasing the amount of light absorbed by this image sensor, and improving the reflectivity and thus the efficiency.

[0075] Before forming the circuit element, the plane where the first surface of the epitaxial silicon layer 402 is absent is a (100) plane orientation (or any plane belonging to the <100> plane family) as shown in the figure. After etching, the second surface of the epitaxial silicon layer will have a structure with a large number of faceted inverted pyramid shapes. Specifically, those inverted pyramids 430 will have triangular side faces that are (111) planes (or any plane belonging to the <111> plane family) as shown in the figure, and a group of bases along the (100) plane. Note that even if one or more side faces of the inverted pyramid are not perfectly or precisely aligned with the <111> plane, the reflectivity can be reduced as expected. According to various embodiments, the image sensor 400b can be optimized to be highly sensitive over a wavelength range of approximately 190 nm to approximately 450 nm. The typical linear dimension 431 of the base of the inverted pyramid in this embodiment is approximately 200 nm. Since the textured back surface 414 is provided with a group of inverted pyramids having a pseudo-random, periodic, and / or random distribution, some of the inverted pyramids will have bases larger than their typical linear dimension, and some of the inverted pyramids will have bases smaller than their typical linear dimension. For example, more than about 80% of those pyramids can have a linear dimension of 150 nm to 300 nm. In sensors optimized for another wavelength range, another typical linear dimension can be used. The typical linear dimension of the inverted pyramid can be controlled by adjusting one or more etching conditions, such as etchant concentration, temperature, and etching time. Note that although the bases of the inverted pyramids described in FIG. 4B, such as 430, are aligned at a single height, as expected, some of the inverted pyramids may have bases at different heights, and this will not have a significant impact on the low reflectivity of the textured surface 414.

[0076] Similar to FIG. 4A, a high-purity amorphous boron thin layer 405 (e.g., about 2 nm to about 20 nm thick) can be deposited on the textured silicon 414. This boron layer 405 seals the textured silicon, preventing or limiting oxidation. The boron layer 405 can be formed as described above in connection with FIG. 2. The boron layer 405 can be, for example, about 5 nm thick, i.e., about 20 - 25 atomic layers of boron. The boron layer 405 can be made to have a uniform thickness or can be deposited on those inverted pyramids in a manner different from the rest of the textured surface.

[0077] According to various embodiments, an antireflection coating 406 can be added to the textured surface 414 to further reduce the reflectivity. The antireflection coating can be made to contain one or more of magnesium fluoride (MgF2), hafnium oxide (HfO2), strontium tetraborate (SrB4O7), silicon dioxide (SiO2), silicon nitride (Si3N4), titanium dioxide (TiO2), and aluminum oxide (Al2O3).

[0078] FIG. 4C depicts a cross-section of a portion of an image sensor 400c having a low-reflectivity back-illuminated boron-coated textured back 424 according to one or more additional embodiments of the present disclosure. It should be noted that, unless otherwise noted, the description for FIGS. 4A and 4B should be construed as being extended to FIG. 4C. In various embodiments, circuit elements 420 are fabricated on the first surface of the epitaxial silicon layer 402. In various embodiments, a protective layer 422 is deposited on that first surface, thereby protecting the circuit elements 420. The textured surface 424 having nanocones (e.g., black silicon) 440 in a pseudo-random, periodic, and / or random distribution covers at least the light-sensing portion of the second surface of the epitaxial silicon layer. This textured surface 424 reduces the complex dielectric constant by lowering the material density on that surface, thereby causing a reduction in the wavelength dependence of surface reflection, increasing the amount of light absorbed by this image sensor, and improving the reflectivity and thus the efficiency.

[0079] In various embodiments, a high-purity amorphous boron thin layer 405 (e.g., about 2 nm to about 20 nm thick) is deposited on the textured silicon 424. As noted above, this boron layer 405 hermetically seals the textured silicon, preventing or limiting oxidation. The boron layer 405 can be formed as described herein. For example, the boron layer 405 can be 5 nm thick, i.e., about 20 to 25 atomic layers of boron. The boron layer 405 can be of uniform thickness or deposited on those inverted pyramids separately from the rest of the textured surface.

[0080] According to various embodiments, an antireflection coating 406 can be added to the textured surface 424 to further reduce reflectivity. The antireflection coating can include one or more of magnesium fluoride (MgF2), hafnium oxide (HfO2), strontium tetraborate (SrB4O7), silicon dioxide (SiO2), silicon nitride (Si3N4), titanium dioxide (TiO2), and aluminum oxide (Al2O3).

[0081] In various embodiments, the image sensor 400c is optimized to be highly sensitive over a wavelength range of about 190 nm to about 450 nm. In this embodiment, the typical height 441 of the nanocones is about 700 nm, and the typical radius 442 of the base of the nanocones is about 120 nm. The radius of the tip of the nanocone is significantly smaller than the typical radius of the base. For example, the radius of the tip can be about 30 nm or less. Since the nanocone group having a pseudo-random, periodic, and / or random distribution is provided on the textured back surface 424, some of the nanocones will have a height greater than or less than 700 nm, and the radius of their bases will be greater than or less than 120 nm. For example, more than about 80% of those nanocones can have a height of 350 nm to 1000 nm, and more than about 80% of the nanocones can have a base radius of 80 nm to 160 nm. For sensors optimized for another wavelength range, another typical dimension can be used. The typical dimensions of the nanocones can be controlled by adjusting one or more etching conditions, such as etchant concentration, plasma conditions, temperature, and etching time. Although the bases of the nanocones shown in FIG. 4C, for example 440, are aligned at a single height, as expected, some of the nanocones may have bases of different heights, and this will not significantly affect the low reflectivity of the textured surface 424.

[0082] Figure 5 depicts graphs 502 - 508 showing the relationship between reflectivity and wavelength for various image sensors. Graph 502 is a reference case, showing the reflectivity - versus - wavelength behavior of an image sensor with a back - illuminated boron - coated flat back. Graph 504 shows the reflectivity - versus - wavelength behavior in an image sensor with a low - reflectivity back - illuminated boron - coated back with an upright pyramid texture. Graph 506 shows the reflectivity - versus - wavelength behavior in an image sensor with a low - reflectivity back - illuminated boron - coated back with an inverted pyramid texture. Graph 508 shows the reflectivity - versus - wavelength behavior in an image sensor with a low - reflectivity back - illuminated boron - coated back with a nanocone texture. The reflectivity values were simulated using Lumerical (trademark) FDTD for periodic upright pyramids, inverted pyramids, and nanocones. The direction of the incident light is orthogonal to the plane of the silicon substrate, and it is assumed that the incident light is composed of equal - part transverse - electric and transverse - magnetic wavefronts. In each simulation, a uniform 5 - nm boron layer was provided on the silicon. In the simulations of the flat sensor surface, the sensor surface textured with upright pyramids, and the sensor surface textured with inverted pyramids, an aluminum - oxide coating was provided on the boron layer, with thicknesses of 16.5 nm, 48 nm, and 41 nm respectively. Figure 5 demonstrates how the reflectivity is improved at wavelengths from 190 nm to 450 nm. The reflectivity of the flat sensor (reference case) can be as high as 40% or more in the wavelength range of interest. The difference in reflectivity between the flat sensor and the textured - back sensor is immediately apparent from the plots in Figure 5. The nanocone case exhibits the lowest reflectivity value. The reflectivity of the upright pyramid is also extremely low, far below 10%. The reflectivity of the inverted pyramid is less than 10% for most of the wavelength range. Note that the dimensions of the structures and the layers on those structures for which reflectivity is plotted in Figure 5 are solely for illustrative purposes.

[0083] As would be recognized by those of ordinary skill in the art, the various members, operations, devices, objects, and the accompanying discussions described in this application are used as examples to contribute to conceptual clarity, and various configuration modifications are considered. Accordingly, the described specific exemplars and the accompanying discussions used in this application are intended to represent their more general classification categories. Generally, since any use of a specific exemplar is intended to represent its classification category, it should not be construed as a limitation that specific members, operations, devices, and objects are not included.

[0084] The above description has been presented so that those of ordinary skill in the art can make and use the invention as presented in the context of a particular use and its conditions. The directional indicators used in this application, such as "top", "bottom", "above", "below", "upper side", "upward", "lower side", "downward", and "downward", are intended to present relative positions for descriptive purposes and are not intended to specify an absolute reference coordinate system. It will be apparent to those of ordinary skill in the art that various modifications can be made to the described embodiments, and the general principles defined in this application can also be applied to other embodiments. Thus, the present invention is not intended to be limited to the specific embodiments shown and described, but should be linked to the broadest technical scope consistent with the principles and novel features disclosed in this application.

[0085] Regarding the use of almost all plural and / or singular terms in this application, those of ordinary skill in the art can read them as appropriate from plural to singular and / or from singular to plural in the context and / or use. For the sake of clarity, this application does not explicitly explain various singular / plural readings.

[0086] The subject matter described in the present application is sometimes depicted with various members incorporated into other members or connected / linked to other members. As can be understood, such illustrated configurations are merely exemplary, and in fact, many other configurations can be implemented to achieve the same function. Conceptually, any member arrangement that achieves the same function, regardless of the member arrangement, is effectively "cooperating" so that the desired function is achieved. That is, any two members in the present application that are combined to achieve a specific function can be regarded as "cooperating" with each other so that the desired function is achieved, regardless of the configuration or intervening members. Similarly, any two members that are so cooperating can also be seen as "connected / linked" or "coupled" to each other to achieve the desired function, and any two members that can be so cooperated can also be seen as "couplable" to each other to achieve the desired function. Specific examples of "couplable" include, but are not limited to, members being physically fittable and / or physically interacting with each other, and / or members being wirelessly interactable and / or wirelessly interacting with each other, and / or members being logically interactable and / or logically interacting with each other.

[0087] Furthermore, as will be understood, the present invention is defined by the appended claims. As those skilled in the art will appreciate, the terms used in this application, particularly in the appended claims (e.g., the body of the appended claims), are generally intended to be "open" (e.g., the term "comprising" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "including" should be interpreted as "including but not limited to," etc.). As those skilled in the art will also appreciate, if a specific number of claim-introducing features is intended, that intention will be clearly stated in the claim, and the absence of such features indicates no intention. For example, as an aid to understanding, some of the appended claims below include the introductory phrases "at least one" and "one or more." However, the use of the indefinite article "a" or "an" should not be construed as implying that the introduction of a claim feature with that indefinite article implies that all individual claims containing that claim feature are limited to inventions containing only one of that feature, nor should such construing be done when the indefinite article "a" or "an" coexists with the indefinite article in the very same claim (e.g., "a" and / or "an" should generally be interpreted as meaning "at least one" or "one or more"). The same is true for the introduction of claim features with the definite article. In addition, even when a specific number of claim features is specified, that number should generally be interpreted to mean at least that specified number, as would be recognized by a person skilled in the art (e.g., the bare phrase "two features" without any other modifier generally means at least two features or more than two features).Furthermore, in an example where a convention similar to “at least one of A, B, and C, etc.” is used, generally, the syntax is conceived according to the sense in which a so-called person skilled in the art would understand the convention (e.g., for a “system having at least one of A, B, and C,” although not limited thereto, a system having only A, only B, only C, both A and B, both A and C, both B and C, and / or all three of A, B, and C, etc. would be included). In an example where a convention similar to “at least one of A, B, or C, etc.” is used, generally, the syntax is conceived according to the sense in which a so-called person skilled in the art would understand the convention (e.g., for a “system having at least one of A, B, or C,” although not limited thereto, a system having only A, only B, only C, both A and B, both A and C, both B and C, and / or all three of A, B, and C, etc. would be included). As should be understood by a so-called person skilled in the art, almost all disjunctive conjunctions and / or disjunctive clauses presenting two or more alternative words, regardless of where they are in the specification, claims, and drawings, should be understood as assuming the possibility of including one of those words, any of those words, or both words. For example, the phrase “A or B” would be understood to include the possibilities of “A” or “B” or “A and B.”

Claims

1. A method for manufacturing an image sensor, comprising: forming an epitaxial layer on a substrate; forming a gate layer on the substrate; forming one or more circuit element layers on the gate layer; thinning the substrate to generate a thinned substrate in which at least a plurality of portions of the epitaxial layer are exposed; cleaning the exposed portions of the epitaxial layer; generating a surface texture on the exposed portions of the epitaxial layer; forming an amorphous layer of pure boron at a first temperature on the surface texture on the light incident side using a mixture containing diborane and hydrogen; further increasing the temperature to a second temperature higher than the first temperature to diffuse boron into the surface texture of the epitaxial layer Method.

2. The method according to claim 1, wherein the surface texture has a pseudo-random distribution exhibiting long-range regularity while lacking at least one type of distinct short-range regularity among upright pyramids, inverted pyramids, and nanocones.

3. The method according to claim 1, wherein the surface texture has a periodic distribution of at least one type among upright pyramids, inverted pyramids, and nanocones.

4. The method according to claim 1, wherein the surface texture has a random distribution of at least one type among upright pyramids, inverted pyramids, and nanocones.

5. The method according to claim 1, further comprising forming an antireflection coating on the amorphous layer of pure boron.

6. The method according to claim 1, further comprising forming a protective layer on the circuit element layer prior to pre-etching the exposed portions of the epitaxial layer.

7. A method for manufacturing an image sensor, comprising: forming an epitaxial layer on a substrate; forming one or more circuit elements on the epitaxial layer; mounting a support wafer on the circuit element; exposing the epitaxial layer by thinning the substrate; cleaning the exposed surface of the epitaxial layer; generating a surface texture on the exposed surface on the epitaxial layer; forming an amorphous layer of pure boron at a first temperature on the surface texture on the light incident side using a mixture containing diborane and hydrogen; further increasing the temperature to a second temperature higher than the first temperature to diffuse boron into the surface texture of the epitaxial layer Method.

8. The method according to claim 7, wherein the surface texture has a pseudo-random distribution that lacks clear short-range regularity of at least one of upright pyramids, inverted pyramids, and nanocones while exhibiting long-range regularity.

9. The method according to claim 7, wherein the surface texture has a periodic distribution of at least one of upright pyramids, inverted pyramids, and nanocones.

10. The method according to claim 7, wherein the surface texture has a random distribution of at least one of upright pyramids, inverted pyramids, and nanocones.

11. The method according to claim 7, further comprising forming an antireflection coating on the amorphous layer of pure boron.

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