Vertical trench type capacitive coupling gate control junction type field effect transistor and manufacturing method for the same

Abstract

To provide a vertical trench type capacitive coupling gate control junction type field effect transistor in which the current characteristic from a drain to a source is not affected, current does not flow to a gate, and the reliability is high, and a manufacturing method for the same.SOLUTION: A field effect transistor includes a substrate 1 functioning as a drain region of a first doping type, an epitaxial layer 2 existing on the substrate, and a plurality of repeating units. Each of the repeating units includes two source regions 4 of the first doping type provided in the epitaxial layer and apart from each other in a lateral direction, a trench formed downward from an upper surface of the epitaxial layer and existing between the source regions, a gate 6 of a second doping type formed at an inner wall and a bottom part of the trench and in a floating state, a dielectric layer 7 formed at least on an inner bottom of the gate, and a coupling capacitance upper electrode 8 formed on the dielectric layer. The gate is controlled indirectly by the coupling capacitance upper electrode through the dielectric layer.SELECTED DRAWING: Figure 3-1

Description

[Technical Field]

[0001] This application relates to the field of semiconductor technology, and more particularly to a vertical trench capacitively coupled gate-controlled junction field effect transistor and a method for fabricating the same. [Background technology]

[0002] Silicon carbide (SiC) material is a third-generation wide bandgap semiconductor with a bandgap width of 3.2 eV, which is much larger than the 1.1 eV of conventional silicon materials. Its critical breakdown field strength is an order of magnitude higher than that of silicon materials, and it has the advantages of excellent resistance to high temperatures and pressures. Furthermore, its fast saturated drift velocity makes it suitable for the manufacture of high-temperature, high-voltage power semiconductor devices that support fast response, such as VDMOS (Vertical Double-Diffused MOSFET) and JFET (Junction Field-Effect Transistor).

[0003] A junction field-effect transistor (JFET) is a tripolar semiconductor device whose operating principle is to control the reverse bias of the pn junction between the gate electrode and the channel by applying a voltage to the gate electrode, thereby turning off the drain and source electrodes. When no voltage is applied to the gate electrode, a JFET is usually a normally-on device, with a conducting channel inside the device. Due to the advantages of low noise, small size, and high frequency response, JFETs are often applied in switching devices, power amplifier devices, and digital electronic circuits to meet the requirements of different electronic devices.

[0004] CN1238904C is a JFET device, as shown in Figure 1, which comprises a single-crystal silicon (SiC) substrate 1, a p-type epitaxial layer 2, an n-type epitaxial layer 3, a p+-type semiconductor layer 4, an n+-type source region layer 5, a p+-type gate layer 7, an n+-type drain region layer 9, a source electrode 10, a gate electrode 11, and a drain electrode 12. The conduction channel of the JFET device is located within the n-type epitaxial layer 3. This location within the semiconductor material avoids the problem of low surface mobility in SiC materials. The JFET device is a normally-on device; that is, when no voltage is applied to the p+-type gate layer 7 (i.e., gate electrode), the device is in a conducting state (current flow is indicated by the dashed line in Figure 1). Therefore, to turn the device off, a negative voltage must be applied to the p+-type gate layer 7 (i.e., gate electrode), limiting its application as a power switch. Furthermore, since the p+ type gate layer 7 (i.e., the gate electrode) and the channel form a pn junction structure, it is not possible to apply a voltage exceeding 3 V to the p+ type gate layer 7 (i.e., the gate electrode). In the case of SiC materials, when a voltage of 3 V or more is applied to the gate electrode, the gate electrode and the channel or the source electrode become conductive, the on-current becomes large, affecting the current characteristics from the drain to the source, and since a high voltage cannot be applied to the gate electrode, its application as a power switch is limited.

[0005] Therefore, conventional JFET devices cannot apply high voltage to the gate electrode, and the reliability of the gate electrode is low, which limits their application as power switches.

[0006] The above information disclosed in the Background section is intended only to enhance understanding of the background of the present application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention [Problem to be solved by the invention]

[0007] The embodiments of the present application provide a vertical trench capacitively coupled gate-controlled junction field effect transistor and a manufacturing method thereof to solve the technical problems present in conventional JFET devices, namely, that a high voltage cannot be applied to the gate electrode and that the reliability of the gate electrode is low, limiting the application of the JFET device as a power switch. [Means for solving the problem]

[0008] In a first aspect according to an embodiment of the present application, there is provided a vertical trench capacitively coupled gate-controlled junction field effect transistor, the vertical trench capacitively coupled gate-controlled junction field effect transistor comprising: a substrate and an epitaxial layer of a first doping type; and a plurality of repeat units, the epitaxial layer being located on the substrate, the substrate functioning as a drain region; and the repeat units comprising: two laterally spaced apart source regions of a first doping type formed in said epitaxial layer; a trench formed downward from the upper surface of the epitaxial layer and positioned between two source regions of the first doping type; a floating second doping type gate formed on the inner wall and bottom of the trench; a dielectric layer formed on at least the inner bottom of the gate; and a coupling capacitance upper electrode formed on the dielectric layer.

[0009] In a second aspect according to an embodiment of the present application, there is provided a method for manufacturing a vertical trench capacitively coupled gate-controlled junction field effect transistor, the method comprising: forming an epitaxial layer of a first doping type on a substrate of a first doping type; forming a plurality of repeat units, wherein the step of forming the repeat units comprises: forming two laterally spaced apart source regions of a first doping type located within the epitaxial layer; forming a trench extending downward from the top surface of the epitaxial layer and positioned between two source regions of a first doping type; forming a gate of a second doping type located on the inner wall and bottom of the trench; forming a dielectric layer on at least an inner bottom of the gate; forming a coupling capacitance upper electrode on the dielectric layer; The gate is indirectly controlled by a coupling capacitance upper electrode across a dielectric layer. [Effects of the Invention]

[0010] By adopting the above technical solutions, the embodiments of the present application have the following technical effects:

[0011] In the vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the present invention, the gate 6 is indirectly controlled by the coupling capacitance upper electrode 8 via the dielectric layer 7. The coupling capacitance upper electrode voltage applied to the coupling capacitance upper electrode 8 is coupled to the gate 6 via coupling. Because the gate 6 is floating and not directly connected to the gate electrode, even if the potential of the coupling capacitance upper electrode 8 rises above 3 V, the lower portion of the epitaxial layer located between the coupling capacitance upper electrode 8, the substrate 1, and the gate 6 does not conduct. Compared to the JFET device described in CN1238904C, the present invention does not conduct even when a high voltage (greater than 3 V, e.g., 4 V or 5 V) is applied to the coupling capacitance upper electrode 8, and this does not affect the current characteristics from the drain electrode to the source electrode of the device. Because the gate 6 is indirectly controlled by the coupling capacitance upper electrode 8 via the dielectric layer 7, no current flows through the gate 6, resulting in high reliability. [Brief explanation of the drawings]

[0012] The accompanying drawings illustrated herein are used for further understanding of the present application and constitute a part of the present application, and the exemplary embodiments and descriptions thereof are used to explain the present application and do not constitute undue limitations on the present application. [Figure 1] FIG. 1 is a schematic diagram illustrating a prior art JFET device. [Figure 2] FIG. 1 is a schematic diagram illustrating a prior art trench VDMOS device. [Figure 3-1] 1 is a schematic diagram showing a first implementation of a vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application; [Figure 3-2] 1 is a schematic diagram showing a second implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application. FIG. [Figure 3-3] FIG. 10 is a schematic diagram showing a third implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application. [Figure 3-4] FIG. 10 is a schematic diagram showing a fourth implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application. [Figure 3-5] FIG. 10 is a schematic diagram showing a fifth implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application. [Figure 3-6] FIG. 10 is a schematic diagram showing a sixth implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application. [Figure 3-7] FIG. 10 is a schematic diagram showing a seventh implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application. [Figure 3-8] FIG. 10 is a schematic diagram showing an eighth implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application. [Figure 3-9] FIG. 13 is a schematic diagram showing a ninth implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application. [Figure 3-10] FIG. 16 is a schematic diagram showing a tenth implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application. [Figure 4] FIG. 10 is a schematic diagram illustrating the formation of an epitaxial layer on a substrate in a manufacturing method of a vertical trench capacitively coupled gate-controlled junction field effect transistor according to a second implementation mode of the present application. [Figure 5]FIG. 5 is a schematic diagram illustrating the formation of a second doping type ohmic contact region, a source region, and a trench based on FIG. 4. [Figure 6] FIG. 6 is a schematic diagram showing how a trench is formed based on FIG. 5. [Figure 7] FIG. 7 is a schematic diagram showing how a gate is formed based on FIG. 6. [Figure 8] FIG. 8 is a schematic diagram illustrating the formation of a dielectric layer based on FIG. 7. [Figure 9] FIG. 9 is a schematic diagram showing how the positions of the coupling capacitance upper electrode and the source electrode are secured in advance on the dielectric layer based on FIG. 8. [Figure 10] FIG. 10 is a schematic diagram showing how a coupling capacitance upper electrode and a source electrode are formed based on FIG. 9. [Figure 11] FIG. 11 is a schematic diagram showing how a drain electrode is formed based on FIG. [Figure 12] 1 is an equivalent circuit diagram of a vertical trench capacitively coupled gate-controlled junction field effect transistor according to the present invention; [Figure 13] 1 is a schematic diagram showing a current path when the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application is conductive. FIG. [Figure 14] 1 is a schematic diagram comparing the characteristics of a vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention with those of a device based on conventional VDMOS technology. [Figure 15] 1 is a schematic diagram showing a vertical trench capacitively coupled gate-controlled junction field effect transistor according to the present application; [Figure 16] 1 shows the potential distribution in the structure of the coupling capacitance upper electrode of the vertical trench type capacitively coupled gate controlled junction field effect transistor of the present invention. [Figure 17-1] 1A and 1B are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 17-2] 1A and 1B are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 17-3] 1A and 1B are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 17-4] 1A and 1B are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 17-5] 1A and 1B are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 17-6] 1A and 1B are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 18-1] FIG. 10 is a diagram showing the carrier concentration distribution in each region of the gate 6, channel 5, and second doping type ohmic contact region 3 of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application during device operation, as affected by the voltage applied to the coupling capacitance upper electrode 8. [Figure 18-2] FIG. 10 is a diagram showing the carrier concentration distribution in each region of the gate 6, channel 5, and second doping type ohmic contact region 3 of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application, as affected by the voltage applied to the coupling capacitance upper electrode 8 during device operation. DETAILED DESCRIPTION OF THE INVENTION

[0013] In order to make the technical solutions and advantages of the embodiments of the present application clearer, the exemplary embodiments of the present application will be described in more detail below with reference to the drawings. However, it is clear that the described embodiments are only some of the embodiments of the present application and are not exhaustive of all the embodiments. In addition, the embodiments and features of the embodiments of the present application may be combined with each other without contradiction.

[0014] Traditional semiconductor devices are often fabricated using silicon, a first-generation semiconductor material. However, in recent years, the third-generation wide-bandgap semiconductor material silicon carbide has emerged. Due to its advantages, such as a wide bandgap, high breakdown voltage, and high thermal conductivity, silicon carbide-based semiconductor devices have demonstrated clear performance advantages over silicon-based devices. However, due to the immaturity of current silicon carbide material, semiconductor devices based on silicon carbide materials face performance and reliability issues. For example, numerous defects near the silicon carbide material surface result in low surface mobility, severely impacting device performance. Furthermore, silicon carbide devices have high quality requirements for gate oxides, but the quality of existing gate oxides does not meet these requirements. In conventional power devices of this type, the conduction channel is located on the surface of the silicon carbide material and oxide. Due to the characteristics of silicon carbide, there are many charges and defects on the surface of the silicon carbide and oxide, which affect the mobility of carriers in the channel, making the mobility of carriers in the channel much lower than the bulk mobility of silicon carbide. The channel mobility, or surface mobility, of silicon carbide MOSFETs is about 20 to 40 cm 2 / V s, whereas the bulk mobility of silicon carbide materials is approximately 1000 cm 2 / V·s. Low channel mobility affects the current transfer characteristics and on-resistance of the device. Also, because the current flowing through the surface of the device is located under the gate oxide, unstable traps and defect centers affect the reliability of the device's gate electrode.

[0015] In conventional power devices of this type, when the device is off and the drain electrode is at a high voltage (breakdown condition), the vertical epitaxial layer - JFET region - dielectric layer is the main breakdown voltage region. The relationship between the electric displacement vector, the electric field strength and the dielectric constant, D = ε·E, gives the electric displacement vector in the semiconductor as D 半導体 =ε 半導体 E 半導体and the electric displacement vector in the dielectric layer immediately adjacent to the semiconductor is D 誘電体 =ε 誘電体 E 誘電体 At the interface between the semiconductor and the dielectric, the electric displacement vector D is continuous, i.e., D 半導体 =D 誘電体 Therefore, ε 半導体 E 半導体 =ε 誘電体 E 誘電体 When the same type of dielectric material is adjacent to a different semiconductor material, for example, when the substrate is silicon or silicon carbide, the dielectric constants ε of the two semiconductor materials are approximately the same (ε シリコン =11.8, ε 炭化ケイ素 =9.8), but the critical breakdown field strength of silicon carbide, a third-generation wide bandgap semiconductor material, is much larger than that of silicon material (E シリコン =0.23MV / cm, E 炭化ケイ素 =2.2MV / cm), ε 半導体 E 半導体 =ε 誘電体 E 誘電体 From this, it can be seen that the electric field strength in a dielectric layer corresponding to a silicon carbide material is much greater than that in a dielectric layer corresponding to a silicon material. Thus, the dielectric layer below the gate of a silicon carbide-based device in breakdown (oxide layer or high-K dielectric) has a typical value of about 2×10 6 V / cm, where the field strength is on the order of megavolts per centimeter, and the high field strength within the dielectric layer affects the reliability of the operation of the gate electrode in silicon carbide-based devices.

[0016] As described above, the conventional technology has the technical problem that a high voltage cannot be applied to the gate electrode of a conventional silicon carbide-based junction field effect transistor, resulting in low gate reliability, which limits the application of the junction field effect transistor as a power switch. In addition, there are also the technical problems of reduced device performance due to the conduction channel being close to the surface of a material with low mobility, and reduced device reliability due to a deterioration in the quality of the gate dielectric layer.

[0017] Trench Vertical Double-Diffused MOSFET (Trench VDMOS) devices are an improved structure based on planar VDMOS, in which the gate electrode is formed by etching a trench, so that it penetrates deep into the device and controls the on / off of the channel, thereby enhancing the gate electrode's control over the channel and achieving lower on-resistance Rsp and current Idsat compared to planar VDMOS devices.

[0018] CN113363308A is a P-channel trench VDMOS device structure, as shown in Figure 2. The polysilicon gate electrode (Polysilicon Gate) is a trench-type structure that penetrates deep into the device. The MOS capacitance effect of the gate oxide attracts charge near the trench in the n-type base region (n-base), controlling whether the n-type base region (n-base) is inverted and thus controlling the channel on / off. During device operation, the inversion channel in the n-type base region (n-base) is controlled by the Polysilicon Gate and is located near the gate oxide, i.e., the boundary between the device trench and the gate oxide (the closer to the Polysilicon Gate, the greater the influence of the gate). This means that part of the conduction channel is located within the P-type drift region (P-drift), and the other part is along the surface of the trench near the gate oxide. Unlike planar VDMOS, where the conduction channel is located at the surface of the device, causing low mobility issues, trench VDMOS has more serious problems due to the trench etching, such as charges, defects, and surface scattering at the interface between the trench surface and the gate oxide layer. The low carrier mobility at the semiconductor trench surface results in a low saturation current Idsat and a high on-resistance Rsp, which affects device performance and limits the device's output power and switching speed. Trench VDMOS is a vertical trench capacitively coupled gate-controlled junction field-effect transistor suitable for switching and linear applications, and is mainly used in electronic switches, adapters, drive band energy, industrial controls, etc.

[0019] Example 1 As shown in FIG. 3-1 , a vertical trench capacitively coupled gate-controlled junction field effect transistor according to a first implementation form (i.e., Example 1) of the present application includes a substrate 1 and an epitaxial layer 2 of a first doping type, and a plurality of repeat units, the epitaxial layer 2 being located on the substrate 1, the substrate serving as a drain region, and the repeat units being: two laterally spaced apart source regions 4 of a first doping type formed in said epitaxial layer 2; a trench formed downward from the upper surface of the epitaxial layer 2 and positioned between two first doping type source regions 4; a floating gate 6 of a second doping type formed on the inner wall and bottom of the trench; a dielectric layer 7 formed on at least the inner bottom of the gate 6; and a coupling capacitance upper electrode 8 formed on the dielectric layer 7.

[0020] Here, the gate 6 of the second doping type, the epitaxial layer 2 of the first doping type, and the gate 6 of the second doping type of the adjacent repeat unit form a JFET region (i.e., the gate 6 of the second doping type of the adjacent repeat unit and the region located between the gates 6 of the second doping type of the adjacent epitaxial layer form the JFET region), and the gate 6 of the JFET region is indirectly controlled by the coupling capacitance upper electrode 8 across the dielectric layer 7.

[0021] In the vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the present invention, the gate 6 in the JFET region is indirectly controlled by the coupling capacitance upper electrode 8 via the dielectric layer 7. The coupling capacitance upper electrode voltage applied to the coupling capacitance upper electrode 8 is coupled to the gate 6 via coupling. Furthermore, since the gate 6 is floating and not directly connected to the gate electrode, even if the potential of the coupling capacitance upper electrode 8 rises above 3 V, the coupling capacitance upper electrode 8, the substrate 1, and the lower portion of the epitaxial layer located between the gate 6 do not conduct. Compared to the JFET device described in CN1238904C, in the present invention, even if a high voltage (greater than 3 V, e.g., 4 V or 5 V) is applied to the coupling capacitance upper electrode 8, the coupling capacitance upper electrode 8 does not conduct and does not affect the current characteristics from the drain electrode to the source electrode of the device. Because the gate 6 is indirectly controlled by the coupling capacitance upper electrode 8 via the dielectric layer 7, no current flows through the gate 6, resulting in high reliability.

[0022] Specifically, the dielectric layer 7 prevents current injection by the coupling capacitance upper electrode from affecting the reliability of the device and improves the operating voltage.

[0023] The vertical trench type capacitively coupled gate controlled junction field effect transistor according to the embodiment of the present application is a vertical trench type capacitively coupled gate controlled junction field effect transistor with a new structure, and is neither a conventional JFET device nor a conventional Trench VDMOS device.

[0024] In the CN1238904C JFET device, the coupling capacitor upper electrode and channel form a pn junction structure, so a voltage higher than 3 V cannot be applied to the coupling capacitor upper electrode. When SiC is used as the substrate material, if a voltage of 3 V or more is applied to the coupling capacitor upper electrode, the coupling capacitor upper electrode will become conductive with the channel and source electrode, resulting in a large on-current, which will affect the current characteristics from the drain electrode to the source electrode. This makes it impossible to apply a high voltage to the coupling capacitor upper electrode, limiting its use as a power switch.

[0025] The vertical trench capacitively coupled gate-controlled junction field effect transistor according to the embodiment of the present application has the following essential differences compared to conventional JFET devices.

[0026] The vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present application indirectly controls the coupling capacitor upper electrode by utilizing the capacitive coupling principle, thereby avoiding current injection from the coupling capacitor upper electrode to the channel and enabling the channel to be controlled by applying a higher voltage to the coupling capacitor upper electrode, making it applicable to a wider range of applications.

[0027] The vertical trench capacitively coupled gate-controlled junction field effect transistor according to the embodiment of the present application has the following essential differences compared to a JFET device:

[0028] The vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present application utilizes the principle of capacitive coupling to indirectly control the on / off of the channel by controlling the potential of the floating coupling capacitance upper electrode 8 via the dielectric layer 7.

[0029] In a typical JFET device, the top gate is directly connected to the electrode, and when a high voltage is applied, the pn junction between the top gate and the channel turns on, allowing current to flow from the top gate to the channel, resulting in negative effects. In the vertical trench capacitively coupled gate-controlled junction field-effect transistor structure according to the present invention, this problem can be avoided due to the isolation provided by the insulating gate dielectric layer.

[0030] In practice, as shown in FIG. 3-1, a vertical trench capacitively coupled gate-controlled junction field effect transistor is a drain electrode 10 provided on the lower surface of the substrate 1; two source electrodes 9 formed on the two source regions 4, respectively; A substrate 1 of a first doping type, an epitaxial layer 2 of a first doping type, and two source regions 4 of a first doping type form an internal conduction path from a drain electrode to two source electrodes located within the substrate 1 and the epitaxial layer 2.

[0031] In the vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present application, the epitaxial layer of a first doping type forms the main structure of the semiconductor device (the gate 6, source region 4, etc. are all part of the semiconductor device). The source region 4 is formed on the top of the epitaxial layer, so that the source region 4 is formed from top to bottom within the epitaxial layer. This ensures that the substrate 1, epitaxial layer 2, and two source regions 4 are all of the first doping type. Therefore, the first doping type substrate, the first doping type epitaxial layer, and the two first doping type source regions 4 form an internal conduction path (shown by a dashed line in FIG. 3-1 ) from the drain electrode 10 to the source electrode 9 located within the substrate and epitaxial layer, and this internal conduction path is all away from the surface of the trench. That is, the internal conduction path is all away from the surface of the semiconductor material and the surface of the trench, and is internal conduction, which avoids the problem of low surface mobility. The internal conduction path of the vertical trench capacitively coupled gate controlled junction field effect transistor according to the embodiment of the present application is located inside the vertical trench capacitively coupled gate controlled junction field effect transistor and is away from the surface of the trench and the surface of the semiconductor material, so that the carriers always maintain a state of high mobility and fast drift velocity, and the vertical trench capacitively coupled gate controlled junction field effect transistor has a large saturation current Idsat, a small on-resistance Rsp, and good performance.

[0032] The conduction channel of the trench VDMOS in the CN116598356A patent application is partly vertically inside the device and partly along the surface of the trench. That is, part of the conduction channel is on the surface of the trench. The reason why part of the conduction channel is on the surface of the trench is because the P-type drift region (P-drift) and the N-type base region (n-base) form a PN junction, which is off when no voltage is applied. When a voltage is applied to the polysilicon gate electrode (Polysilicon gate), the PN junction is most likely to invert and form a channel at the part closest to the polysilicon gate electrode (Polysilicon gate), i.e., the surface of the trench. Therefore, the conduction channel is located on the surface of the trench, i.e., along the surface of the trench. The trench etching causes more serious problems of charges, defects, and surface scattering at the interface between the trench surface and the gate oxide, resulting in low carrier mobility at the surface of the semiconductor trench, resulting in a low saturation current Idsat and a large on-resistance Rsp of the device, which affects device performance and limits the output power and switching speed of the device.

[0033] In the vertical trench capacitively coupled gate-controlled junction field effect transistor according to the embodiment of the present application, the substrate 1, the epitaxial layer 2, and the two source regions 4 are all of the first doping type, and are themselves conductive without forming a PN junction. Therefore, an internal conductive path is formed within the substrate and the epitaxial layer from the drain electrode 10 to the source electrode 9, and this internal conductive path is away from the surface of the semiconductor material and also away from the surface of the trench. In other words, all the internal conductive paths are away from the surface of the semiconductor material and the surface of the trench, and are internally conductive, thereby avoiding the problem of low surface mobility.

[0034] In practice, as shown in FIG. 3-1, the trench is a U-shaped trench, in this case, the dielectric layer 7 covers the coupling capacitance upper electrode space surrounded by the inner surface of the gate 6, and the dielectric layer (7) covers the top of the gate; The coupling capacitance upper electrode 8 is formed in the coupling capacitance upper electrode space.

[0035] The trench gate 6 is formed in a U-shape by etching a U-shaped trench, which allows the gate 6 to extend deep into the device and control the on / off of the JFET region, enhancing the control of the gate 6 over the JFET region, thereby achieving lower on-resistance Rsp and current Idsat compared to planar VDMOS devices.

[0036] In one embodiment, the substrate is a silicon carbide substrate, a silicon substrate, a diamond substrate, or a potassium oxide substrate; the dielectric layer is a dielectric layer of a high dielectric constant material, The coupling capacitance upper electrode 8 is a polysilicon electrode or a metal electrode.

[0037] There is a problem with the dielectric layer of conventional diamond-substrate MOSFETs. The dielectric layer formed on the diamond substrate by deposition methods, such as an oxide layer, is of poor quality and therefore performs poorly. In contrast, the diamond vertical trench capacitively coupled gate-controlled junction field-effect transistor using this device structure can solve this problem by locating the conduction channel within the device. MOSFETs (metal-oxide-semiconductor field-effect transistors) are common semiconductor devices.

[0038] Potassium oxide is a fourth-generation semiconductor material that can be used to fabricate electronic devices and electronic equipment, especially new controllable semiconductor devices.

[0039] Specifically, silica or high-K dielectrics may be used as the material for the dielectric layer, and the use of high-K dielectrics helps control the coupling capacitance of the upper electrode to the P+ type top gate, thereby improving device performance.

[0040] Specifically, the gate 6 can be made of P+ and N+ highly doped polysilicon, which reduces the contact resistance with the metal of the coupling capacitor upper electrode and the parasitic resistance of the coupling capacitor upper electrode, thereby improving device performance.

[0041] High-K dielectrics refer to materials that have a high dielectric constant (high relative permittivity).

[0042] Specifically, the substrate 1 of the first doping type is heavily doped and has a high doping concentration, and functions as a drain region of a vertical trench capacitively coupled gate-controlled junction field effect transistor.

[0043] In implementation, the vertical trench capacitively coupled gate-controlled junction field effect transistor comprises: The semiconductor device further includes a metal silicide layer (not shown in FIG. 3-1) formed between the gate 6 and the dielectric layer 7.

[0044] A metal silicide layer (abbreviated as Silicide layer) may be added under the coupling capacitance upper electrode dielectric layer, i.e., the metal silicide layer may be interposed between the dielectric layer 7 and the gate 6. In this way, the metal silicide layer under the dielectric layer 7 is a metal layer, and the electric field distribution in the metal layer is uniform, thereby optimizing the electric field on the surface of the gate 6 and improving the reliability of the device.

[0045] In the embodiment, the doping concentration of the gate 6 is 1×10 16 cm -3 That's all.

[0046] The gate doping concentration is 1×10 16 cm -3 This ensures that the top gate is not depleted and a strong electric field is not generated in the gate when a gate electrode voltage is applied.

[0047] In practice, the doping concentration of the channel 5 is higher than the doping concentration of the substrate and the epitaxial layer; The doping concentration of the channel is higher than that of the substrate, which helps to reduce the on-resistance of the device and improve the device performance.

[0048] The vertical trench capacitively coupled gate-controlled junction field effect transistor according to the first embodiment may be implemented as a normally-off device, a normally-on device.

[0049] In order to implement the vertical trench capacitively coupled gate-controlled junction field effect transistor according to Example 1 as a normally-off device, By controlling the doping of the gates 6 of the second doping type of two adjacent repeat units, when the voltage of the coupling capacitance upper electrode 8 is zero, the region sandwiched between the gates 6 of the second doping type of two adjacent repeat units of the epitaxial layer is in a depleted state, and the vertical trench capacitively coupled gate-controlled junction field effect transistor is a normally-off device.

[0050] Here, by adjusting the doping position and doping concentration of the gates 6 of the second doping type of two adjacent repeat units, the vertical trench capacitively coupled gate-controlled junction field effect transistor is implemented as a normally-off device.

[0051] If the vertical trench capacitively coupled gate-controlled junction field-effect transistor is a normally-off device, If the first doping type is N-type doping and the second doping type is P-type doping, When no voltage is applied to the vertical trench type capacitively coupled gate controlled junction field effect transistor, the vertical trench type capacitively coupled gate controlled junction field effect transistor is turned off, When a positive voltage is applied to the vertical trench type capacitively coupled gate controlled junction field effect transistor, the vertical trench type capacitively coupled gate controlled junction field effect transistor becomes conductive.

[0052] Also, if the first doping type is P-type doping and the second doping type is N-type doping, When no voltage is applied to the vertical trench type capacitively coupled gate controlled junction field effect transistor, the vertical trench type capacitively coupled gate controlled junction field effect transistor is off, When a negative voltage is applied to the vertical trench type capacitively coupled gate controlled junction field effect transistor, the vertical trench type capacitively coupled gate controlled junction field effect transistor becomes conductive.

[0053] In order to implement the vertical trench capacitively coupled gate-controlled junction field effect transistor according to Example 1 as a normally-on device, By controlling the doping of the second doping type gates 6 of two adjacent repeat units, when the voltage of the coupling capacitance upper electrode 8 is zero, the region of the epitaxial layer sandwiched between the second doping type gates 6 of the two adjacent repeat units becomes conductive, and the vertical trench capacitively coupled gate-controlled junction field effect transistor is a normally-on device.

[0054] Here, by adjusting the doping positions and doping concentrations of the second doping type gates 6 of two adjacent repeat units, the vertical trench capacitively coupled gate-controlled junction field effect transistor is implemented as a normally-on device.

[0055] When the vertical trench capacitively coupled gate-controlled junction field-effect transistor is a normally-on device, If the first doping type is N-type doping and the second doping type is P-type doping, When no voltage is applied to the vertical trench type capacitively coupled gate-controlled junction field effect transistor, the vertical trench type capacitively coupled gate-controlled junction field effect transistor is conductive, When a negative voltage is applied to the vertical trench type capacitively coupled gate controlled junction field effect transistor, the vertical trench type capacitively coupled gate controlled junction field effect transistor is turned off.

[0056] Also, if the first doping type is P-type doping and the second doping type is N-type doping, When no voltage is applied to the vertical trench type capacitively coupled gate-controlled junction field effect transistor, the vertical trench type capacitively coupled gate-controlled junction field effect transistor is conductive, When a positive voltage is applied to the vertical trench type capacitively coupled gate controlled junction field effect transistor, the vertical trench type capacitively coupled gate controlled junction field effect transistor is turned off.

[0057] That is, the region sandwiched between the second doping type gates 6 of two adjacent repeat units is the portion of the epitaxial layer sandwiched between the second doping type gates 6 of two adjacent repeat units.

[0058] <Example 2> The vertical trench type capacitively coupled gate controlled junction field effect transistor according to the second implementation form (Example 2) of the present application differs from the vertical trench type capacitively coupled gate controlled junction field effect transistor according to the first implementation form (i.e., Example 1) in the following structural differences. As shown in FIG. 3-2, the vertical trench type capacitively coupled gate controlled junction field effect transistor according to the second implementation form (Example 2) of the present application has the following: It further comprises two channels 5 of the first doping type located below the two source regions 4 respectively.

[0059] In this way, the gate 6 of the second doping type, the channel 5 of the first doping type, and the gate 6 of the second doping type of the adjacent repeat unit form a JFET region, and the gate 6 of the JFET region is indirectly controlled by the coupling capacitance upper electrode 8 across the dielectric layer 7.

[0060] In this case, as shown in FIG. 3-2, a first doping type substrate 1, a first doping type epitaxial layer 2, two first doping type channels 5, and two first doping type source regions 4 form an internal conduction path from the drain electrode to the two source electrodes located within the substrate 1 and the epitaxial layer 2.

[0061] Specifically, the channel 5 may be formed by ion implantation or other methods utilizing the original substrate, so that the doping concentration of the channel 5 is higher than the doping concentration of the epitaxial layer 2.

[0062] Specifically, the doping concentration of the first doping type channel 5 is higher than the doping concentration of the epitaxial layer 2, so that the resistance of the first doping type channel 5 is small, and thus the on-resistance Rsp of the vertical trench type capacitively coupled gate controlled junction field effect transistor is small, and the performance of the vertical trench type capacitively coupled gate controlled junction field effect transistor is good.

[0063] In this case, the vertical trench capacitively coupled gate-controlled junction field effect transistor according to the second embodiment may be implemented as a normally-off device, normally-on device.

[0064] To implement the vertical trench capacitively coupled gate-controlled junction field effect transistor according to Example 2 as a normally-off device, By controlling the doping of the gates 6 of the second doping type of two adjacent repeat units, when the voltage of the coupling capacitance upper electrode 8 is zero, the channel 5 sandwiched between the gates 6 of the second doping type of two adjacent repeat units is in a depleted state, and the vertical trench capacitively coupled gate-controlled junction field effect transistor is a normally-off device.

[0065] Here, by adjusting the doping position and doping concentration of the gates 6 of the second doping type of two adjacent repeat units, the vertical trench capacitively coupled gate-controlled junction field effect transistor may be implemented as a normally-off device.

[0066] In order to implement the vertical trench type capacitively coupled gate controlled junction field effect transistor according to the second embodiment as a normally-on device, By controlling the doping of the second doping type gates 6 of two adjacent repeat units, when the voltage of the coupling capacitance upper electrode 8 is zero, the channel 5 sandwiched between the second doping type gates 6 of the two adjacent repeat units is in a conductive state, and the vertical trench type capacitively coupled gate-controlled junction field effect transistor is a normally-on device.

[0067] Here, by adjusting the doping position and doping concentration of the second doping type gates 6 of two adjacent repeat units, the vertical trench capacitively coupled gate-controlled junction field effect transistor may be implemented as a normally-on device.

[0068] That is, the region sandwiched between the gates 6 of the second doping type of two adjacent repeat units is the channel 5 .

[0069] The CN1238904C JFET device is a normally-on device, i.e., when no voltage is applied to the gate electrode, the device conducts, and a negative voltage must be applied to the gate electrode to turn the device off, limiting the application of this device as a power switch.

[0070] Example 3 The vertical trench type capacitively coupled gate controlled junction field effect transistor according to the third implementation form (Example 3) of the present application differs from the vertical trench type capacitively coupled gate controlled junction field effect transistor according to the first implementation form (i.e., Example 1) in the following structural differences. As shown in FIG. 3-3, the vertical trench type capacitively coupled gate controlled junction field effect transistor according to the third implementation form of the present application has: The semiconductor device further comprises two second doping type ohmic contact regions 3 located outside the two source regions 4, respectively.

[0071] Here, the second doping type gate 6, the region of the epitaxial layer located between the second doping type gate 6 and the second doping type ohmic contact region 3, and the second doping type ohmic contact region 3 form a JFET region, and the gate 6 of the JFET region is indirectly controlled by the coupling capacitance upper electrode 8 across the dielectric layer 7.

[0072] The second doping type ohmic contact region 3 serves to adjust the electric field, improve the breakdown voltage BV of the device, and enhance the reliability of the device.

[0073] In this case, as shown in FIG. 3-3, a substrate 1 of a first doping type, an epitaxial layer 2 of a first doping type, and two source regions 4 of a first doping type form an internal conductive path from the drain electrode to the two source electrodes located within the substrate 1 and the epitaxial layer 2.

[0074] The vertical trench capacitively coupled gate-controlled junction field effect transistor according to the third embodiment may be implemented as a normally-off, normally-on device.

[0075] To implement the vertical trench capacitively coupled gate-controlled junction field effect transistor according to Example 3 as a normally-off device, By controlling the doping of the second doping type gate 6 and the second doping type ohmic contact region 3, when the voltage of the coupling capacitance upper electrode 8 is zero, the region of the epitaxial layer sandwiched between the second doping type gate 6 and the second doping type ohmic contact region 3 is in a depleted state, and the vertical trench capacitively coupled gate-controlled junction field effect transistor is a normally-off device.

[0076] Here, by adjusting the doping positions and doping concentrations of the adjacent second doping type gate 6 and second doping type ohmic contact region 3, the vertical trench capacitively coupled gate-controlled junction field effect transistor is implemented as a normally-off device.

[0077] In order to implement the vertical trench type capacitively coupled gate controlled junction field effect transistor according to Example 3 as a normally-on device, By controlling the doping of the second doping type gate 6 and the second doping type ohmic contact region 3, when the voltage of the coupling capacitance upper electrode 8 is zero, the region of the epitaxial layer sandwiched between the second doping type gate 6 and the second doping type ohmic contact region 3 becomes conductive, and the vertical trench type capacitively coupled gate-controlled junction field effect transistor is a normally-on device.

[0078] Here, by adjusting the doping positions and doping concentrations of the adjacent second doping type gate 6 and second doping type ohmic contact region 3, the vertical trench capacitively coupled gate-controlled junction field effect transistor is implemented as a normally-on device.

[0079] That is, the region sandwiched between the second doping type gate 6 and the second doping type ohmic contact region 3 is the region of the epitaxial layer sandwiched between the second doping type gate 6 and the second doping type ohmic contact region 3.

[0080] Specifically, the second doping type ohmic contact region 3 may be formed by ion implantation or by other methods using the original substrate.

[0081] Example 4 The vertical trench type capacitively coupled gate controlled junction field effect transistor according to the fourth implementation form (Example 4) of the present application has the following structural differences compared to the vertical trench type capacitively coupled gate controlled junction field effect transistor according to the first implementation form (i.e., Example 1). As shown in Figures 3-4, the vertical trench type capacitively coupled gate controlled junction field effect transistor according to the fourth implementation form (Example 4) of the present application has the following: two channels 5 of the first doping type located respectively below the two source regions 4; two second doping type ohmic contact regions 3 located outside the two source regions 4 and the channel 5, respectively; Here, the second doping type gate 6, the first doping type channel 5, and the second doping type ohmic contact region 3 form a JFET region, and the gate 6 of the JFET region is indirectly controlled by a coupling capacitance upper electrode 8 across a dielectric layer 7; The gate 6 , channel 5 , source region 4 and ohmic contact region 3 of the second doping type are formed in the epitaxial layer 2 .

[0082] In this case, as shown in Figure 3-4, a first doping type substrate 1, a first doping type epitaxial layer 2, a first doping type channel 5, and two first doping type source regions 4 form an internal conduction path from the drain electrode to the two source electrodes located within the substrate 1 and the epitaxial layer 2.

[0083] Specifically, the first doping type substrate 1, the first doping type epitaxial layer 2, the first doping type channel 5, and the two first doping type source regions 4 are sequentially connected. Current flows from the drain electrode 10 through the first doping type substrate 1 and the first doping type epitaxial layer 2, into the first doping type channels 5 on both the left and right sides, through the source regions 4 on both the left and right sides, and finally is collected by the two source electrodes 12 on both the left and right sides.

[0084] Specifically, the channel 5 may be formed by ion implantation or other methods using the original substrate, so that the doping concentration of the channel 5 is higher than the doping concentration of the epitaxial layer 2.

[0085] Specifically, the doping concentration of the first doping type channel 5 is higher than the doping concentration of the epitaxial layer 2, so that the resistance of the first doping type channel 5 is relatively small, and thus the on-resistance Rsp of the vertical trench type capacitively coupled gate controlled junction field effect transistor is relatively small, and the performance of the vertical trench type capacitively coupled gate controlled junction field effect transistor is good.

[0086] This application proposes a vertical trench capacitively coupled gate-controlled junction field effect transistor, and in an example device, it has a threshold voltage of 3.03 V, a breakdown voltage of 1507 V, and an on-resistance of 0.12 Ω mm 2This allows the realization of a device with a capacitance-coupled gate-controlled junction field-effect transistor. In the present vertical trench capacitively coupled gate-controlled junction field-effect transistor, the entire conducting channel is located inside the device, making it less susceptible to the effects of interface charges and low interface mobility. This results in a 50% improvement in on-resistance compared to conventional silicon carbide VDMOS. Because the dielectric layer is protected by the gate, the area required to protect the junction field effect of the coupling capacitance upper electrode can be reduced, further reducing the on-resistance. Due to the capacitive coupling effect of the channel, the current in the present invention saturates under high gate voltages, improving the short-circuit resistance of the device. The coupling capacitance upper electrode of the present vertical trench capacitively coupled gate-controlled junction field-effect transistor is a capacitively coupled gate, which operates using the capacitive coupling principle to control device operation. The requirements for the capacitance electrode work function are low, allowing for flexible use of the coupling capacitance dielectric. The typical electric field strength in the dielectric layer during device breakdown is approximately 2×10 5 V / cm, approximately an order of magnitude lower than conventional silicon carbide devices, with lower quality requirements for the capacitive coupling dielectric and clearly higher reliability, robustness, and manufacturing advantages.

[0087] Hereinafter, an example will be described in which the first doping type is N-type and the second doping type is P-type.

[0088] The P+ type ohmic contact region 3, the N type channel 5, and the P+ type gate 6 form a JFET region, the P+ type ohmic contact region 3 and the N type channel 5 form a PN junction, and the N type channel 5 and the P+ type gate 6 form a PN junction. By controlling the voltage of the coupling capacitance upper electrode 8, the depletion and pinch-off of the channel 5 are realized, and the internal conduction path is controlled, and finally the conduction and off control of the vertical trench type capacitively coupled gate controlled junction field effect transistor is realized.

[0089] The vertical trench capacitively coupled gate-controlled junction field effect transistor according to the fourth embodiment may be implemented as a normally-off, normally-on device.

[0090] To implement the vertical trench capacitively coupled gate-controlled junction field effect transistor according to Example 4 as a normally-off device, By controlling the doping of the second doping type gate 6 and the second doping type ohmic contact region 3, when the voltage of the coupling capacitance upper electrode 8 is zero, the channel 5 sandwiched between the second doping type gate 6 and the second doping type ohmic contact region 3 is in a depleted state, and the vertical trench capacitively coupled gate-controlled junction field effect transistor is a normally-off device.

[0091] Here, by adjusting the doping positions and doping concentrations of the adjacent second doping type gate 6 and second doping type ohmic contact region 3, the vertical trench capacitively coupled gate-controlled junction field effect transistor is implemented as a normally-off device.

[0092] In order to implement the vertical trench type capacitively coupled gate controlled junction field effect transistor according to Example 4 as a normally-on device, By controlling the doping of the second doping type gate 6 and the second doping type ohmic contact region 3, when the voltage of the coupling capacitance upper electrode 8 is zero, the channel 5 sandwiched between the second doping type gate 6 and the second doping type ohmic contact region 3 becomes conductive, and the vertical trench type capacitively coupled gate-controlled junction field effect transistor is a normally-on device.

[0093] Here, by adjusting the doping positions and doping concentrations of the adjacent second doping type gate 6 and second doping type ohmic contact region 3, the vertical trench capacitively coupled gate-controlled junction field effect transistor is implemented as a normally-on device.

[0094] That is, the region sandwiched between the second doping type gate 6 and the second doping type ohmic contact region 3 is the channel 5 .

[0095] Hereinafter, an example will be described in which the first doping type is N-type and the second doping type is P-type.

[0096] In the JFET region of the vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present application, the depletion region formed by the coupling capacitance upper electrode 8 and the self-formed electric field of the N-type channel 5 is connected to the depletion region of the self-formed electric field formed by the PN junction, thereby realizing self-depletion and pinch-off of the N-type channel 5 and achieving a normally-off function of the device. That is, when no voltage is applied to the coupling capacitance upper electrode 8, the path between the drain electrode and the source electrode is turned off, and when a voltage is applied to the coupling capacitance upper electrode, the path between the drain electrode and the source electrode is turned on.

[0097] Hereinafter, a method for manufacturing a vertical trench capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application will be described, taking the case where the first doping type is N-type and the second doping type is P-type as an example, and the manufacturing method includes the following steps:

[0098] Referring to FIG. 4, an N-type epitaxial layer 2 is epitaxially grown on a low-resistivity SiC N+ type substrate 1, and then the N+ epitaxial layer 1 forms an ohmic contact with the metal of the backside drain electrode 10, and the N-type epitaxial layer 2 is formed into the main structure of the device by processes such as ion implantation, thermal annealing, etching, and deposition.

[0099] 5, based on the structure formed in FIG. 4, a single cell of a device is taken as an example, and a photoresist is used as a mask material using a photomask, and a P+ type ohmic contact region 3, an N+ type ohmic contact region 4, and an N type channel 5 are formed on an N- type epitaxial layer 2 by ion implantation. This device has a centrosymmetric structure and is a single cell, but an actual device is configured by arranging a plurality of similar cells.

[0100] Referring to FIG. 6, based on the structure formed in FIG. 5, a trench is formed by etching the SiC material at the middle position of the single cell, that is, at the middle portion between the two source electrodes on the left and right, by plasma etching.

[0101] Referring to FIG. 7, based on the structure formed in FIG. 6, ion implantation is performed in the trench region to implant ions into the SiC material inside the trench near the curved surface of the trench, forming a P+ gate 6. If the trench is deep, tilted ion implantation may be used to form the vertical sidewalls of the trench as P-type. The P+ gate 6 is not connected to an external metal electrode and is a physically floating region. A voltage is then applied to the coupling capacitor upper electrode 8 or via the principle of coupling capacitance through the dielectric layer 7, which then controls the on / off of the N-type channel 5 via the JEFT effect. After implantation into the P+ gate 6 is completed, implantation into the entire active region of this trench-type vertical trench capacitively coupled gate-controlled junction field-effect transistor is completed, and thermal annealing is performed to activate and diffuse the implanted ions to form each region.

[0102] Referring to Figure 8, based on the structure formed in Figure 7, a dielectric layer 7 is deposited on the trench and the surface of the wafer by chemical vapor deposition, and the surface is polished flat by chemical mechanical polishing. An oxide layer or other high-K dielectric can be used as the dielectric layer, but a high-K dielectric is more advantageous for controlling the P+ type gate 6 and N type channel 5 by the coupling capacitance upper electrode. A high-K dielectric refers to a material with a high dielectric constant (high relative permittivity).

[0103] Referring to FIG. 9, based on the structure formed in FIG. 8, the coupling capacitor upper electrode and source regions to be etched are defined by a lithographic technique using photoresist and hard masks, and then the gate dielectric is etched by plasma etching to form trench-type coupling capacitor upper electrode and source electrodes that require subsequent metal deposition.

[0104] 10, based on the structure formed in FIG. 9, metal is deposited to form a coupling capacitance upper electrode 8 in the trench region, and a source electrode 9 is formed in the boundary region between the P+ type ohmic contact region 3 and the N+ type ohmic contact region 4. The coupling capacitance upper electrode can also be formed as a polysilicon gate by depositing polysilicon, which has the advantage that the controllability of the coupling capacitance upper electrode can be adjusted by the gate.

[0105] Referring to Figure 11, based on the structure formed in Figure 10, after the surface processing of the device is completed, the entire backside of the wafer is polished and thinned, and the backside is metallized to create the drain electrode 10 on the backside of the device and complete the entire device structure.

[0106] The operating principle of the vertical trench type capacitively coupled gate controlled junction field effect transistor of the present invention will be described in detail below.

[0107] The vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present application utilizes the characteristics of SiC wide band-gap semiconductors. Because the band-gap width of SiC is 3.4 eV, the Fermi level difference energy between P-type and N-type SiC caused by doping exceeds 3 eV. Therefore, the SiC PN junction generates a built-in voltage of more than 3 volts, and significantly adjusts the current in the junction field-effect transistor channel, laying the physical foundation for the device. Physically, this device is essentially different from the channel current caused by channel doping. This is a physical property unique to wide band-gap semiconductor devices and was discovered for the first time in the present application. It will be explained in detail below using energy band diagrams.

[0108] In the prior art, there are three common approaches to modulating the channel: the first is the inversion layer used in conventional Si MOSFETs, which, combined with high-quality silicon dioxide grown by thermal oxygen growth, is more suited to silicon materials and allows for large-scale production and application.

[0109] The second approach is the heterojunction FET, commonly referred to as HFET, which is typically made up of GaAs / AlGaAs or GaN / AlGaN. It is difficult to fabricate an enhancement-type HFET with this device structure, and this has currently been resolved by using methods such as a buried gate structure and fluorine ion implantation.

[0110] The third approach is the JFET principle, but because the bandgap width of silicon is only 1.1 eV, silicon-based JFET devices can only be fabricated as normally-on devices. Existing SiC-based JFET devices are also normally open and cannot be used directly as power electronics switching devices.

[0111] The vertical trench capacitively coupled gate controlled junction field effect transistor proposed in this application combines the wide bandgap characteristics of SiC and utilizes the high built-in voltage created by the wide bandgap of SiC to achieve a normally-off function for the device, but the threshold voltage does not exceed 1 V and the gate operating voltage does not exceed 3 V, which still does not meet the requirements of power electronic switching devices. Based on this, the present application invents a capacitively coupled gate structure that enables a threshold voltage of 3 V or more and an operating voltage of 15 V or more, fully meeting the requirements of existing power electronic devices.

[0112] The vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present application has a vertical device structure. As shown in FIGS. 3-4 , a drain electrode 10 is located below a substrate 1 at the bottom of the device, and a coupling capacitance upper electrode 8 and a source electrode 9 are located at the top of the device. The coupling capacitance upper electrode employs a trench structure. A dielectric layer 7 is located outside the coupling capacitance upper electrode 8, and a gate 6 is located outside the dielectric layer 7. The coupling capacitance upper electrode 8, the dielectric layer 7, and the gate 6 collectively constitute the coupling capacitance upper electrode structure of the vertical trench capacitively coupled gate-controlled junction field-effect transistor. Immediately adjacent to the gate 6 are a source region 4 and a channel 5, which, together with the epitaxial layer 2 and the substrate 1, form the conduction path of the vertical trench device structure. On the other side of the source region 4 and the channel 5 is a second doping type ohmic contact region 3, which, together with the source region 4, is connected to the source electrode 9. The second doping type ohmic contact region 3, the channel 5, and the gate 6 form a JFET region.

[0113] As shown in FIG. 12, an equivalent circuit diagram of the coupling capacitance upper electrode of the vertical trench capacitively coupled gate-controlled junction field-effect transistor device of Example 4 of the present application (corresponding to FIG. 3-4) has a structure in which a capacitor and the coupling capacitance upper electrode of the junction field-effect transistor are connected in series, and the capacitor in this circuit diagram is coupled to the semiconductor junction capacitor of the JFET to divide the voltage and control the on / off of the junction field-effect transistor.

[0114] When the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention is operated, as shown in FIG. 3-4, a voltage is applied to the coupling capacitance upper electrode 8 and the drain electrode 10. The voltage applied to the coupling capacitance upper electrode 8 is coupled to the gate 6 through the dielectric layer 7. The potential coupled to the gate 6 forms the second doped ohmic contact region 3 connected to the source electrode and the region of the JFET device control channel, thereby controlling the on / off of the intermediate channel.

[0115] When the applied voltage turns the channel off, the JFET region is in the off state and the channel 5 is in a depleted state. In a depleted state, the number of carriers in the channel is low. If further voltage is applied to the drain electrode 10, the channel of the device is depleted and in an off state, so that no or very little current flows between the drain electrode 10 and the source electrode 9.

[0116] When the channel is turned on by the applied voltage, the JFET region becomes conductive, the channel 5 becomes conductive, and the drain electrode and source electrode are connected. At this time, if further voltage is applied to the drain electrode 10, the channel of the device becomes conductive and is in the on state, so current flows from the drain electrode 10 to the source electrode 9, and the device operates.

[0117] The threshold voltage of the present vertical trench capacitively coupled gate-controlled junction field-effect transistor can be modulated by doping. When the doping is controlled to form a self-pinch-off JFET region, the built-in electric field due to the doping itself depletes carriers in the channel 5, forming a depletion region, when no voltage is applied to the device's coupling capacitance upper electrode. The device is then a normally-off device. Only by applying a positive voltage to the JFET region can the depletion region disappear, forming an effective channel for conduction. The pn junction formed with silicon carbide material has a large built-in potential due to the wide bandgap characteristics of silicon carbide, enabling a normally-off device structure.

[0118] If the JFET region does not self-pinch off, the device has a channel and is a normally-on device. According to the JFET operating principle, a corresponding voltage must be applied to the control region of the JFET, causing the channel to form a depletion region and turning the device off.

[0119] The on-resistance Rsp of the vertical trench capacitively coupled gate-controlled junction field-effect transistor device of the present invention is determined mainly by the resistance R1 of the JFET region and the resistance R2 of the epitaxial layer 2, and the voltage applied to the drain electrode 10 of the device is divided by the two resistors connected in series, reducing the resistance of each region and optimizing the on-resistance Rsp of the entire device.

[0120] The advantages of the vertical trench type capacitively coupled gate controlled junction field effect transistor device of the present invention will be explained below.

[0121] The coupling capacitance upper electrode of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention employs a capacitance coupling method, which has the following advantages over conventional wide bandgap metal oxide semiconductor field effect transistors:

[0122] Fig. 13 is a schematic diagram showing a current path when the vertical trench type capacitively coupled gate-controlled junction field effect transistor of the present invention is conductive. Fig. 14 is a schematic diagram comparing the characteristics of the vertical trench type capacitively coupled gate-controlled junction field effect transistor of the present invention with those of a device based on conventional VDMOS technology.

[0123] As shown in Figure 13, the dashed line with an arrow indicates the current path when the field-effect transistor is conductive. As shown in Figure 13, when the vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present invention is conductive, the current path is within the device and away from the surface of the semiconductor material, so it is not affected by the low interface mobility of the material. The performance of the vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present invention is primarily affected by the thickness of the capacitive dielectric, and the work function requirement of the electrode is low. For example, if the coupling capacitance upper electrode 8 is made of polysilicon material, either N-type polysilicon or P-type polysilicon can play the role of capacitive coupling. Capacitive dielectrics such as conventional oxide materials and high-K dielectrics can also be flexibly used to play the role of capacitive coupling.

[0124] Fig. 14 is a schematic diagram comparing the characteristics of the present vertical trench capacitively coupled gate-controlled junction field-effect transistor with that of a conventional VDMOS technology device. As shown in Fig. 14, when the active region area is the same, the present vertical trench capacitively coupled gate-controlled junction field-effect transistor clearly has an advantage in on-resistance Rsp.

[0125] Because the present vertical trench capacitively coupled gate-controlled junction field-effect transistor operates using the capacitive coupling principle, the dielectric acts as an insulating layer. When a voltage is applied to the device's coupling capacitance upper electrode, the potential is coupled to gate 6. However, due to the physical floating of gate 6, current does not flow through dielectric layer 7 to gate 6, which is the main control region of the device's JFET region. As shown in Figure 13, since the device's current conduction path does not pass through gate 6, no large current flows through gate 6, resulting in relatively high reliability. Under high drain voltages (breakdown conditions) when the device is turned off, the epitaxial layer-gate-dielectric layer becomes the main breakdown voltage region. Due to the existence of the epitaxial layer-gate semiconductor pn junction structure, a fixed negative charge exists in the depletion region within the gate, and electric field lines originate from the positive charge in the epitaxial layer and terminate at the negative charge in the gate. Therefore, high electric fields are shielded at the semiconductor junction interface. The electric field strength within the dielectric layer is reduced by the shielding effect of the gate; a typical dielectric field strength is approximately 2×10 5 V / cm, which is an order of magnitude lower than the electric field strength of the dielectric layer in conventional silicon carbide VDMOS devices. The electric field strength of the low-k dielectric layer plays an important role in protecting the dielectric layer and improving its reliability.

[0126] FIG. 15 is a schematic diagram showing a vertical trench type capacitively coupled gate-controlled junction field effect transistor of the present invention.

[0127] 16 shows the potential distribution of the coupling capacitance upper electrode structure of the vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present invention. As shown in FIG. 16, the vertical axis represents the potential distribution, and the horizontal axis represents the horizontal position.

[0128] In Figure 15, the horizontal dashed lines represent the horizontal direction, and the portion of the horizontal dashed lines to the right of the vertical dashed line corresponds to the portion to the right of coordinate 0 on the horizontal axis in Figure 16, and the portion of the horizontal dashed lines to the left of coordinate 0 on the horizontal axis in Figure 16.

[0129] In the operating device of the present invention, the current saturates at a high gate voltage due to the capacitive coupling effect of the channel. The voltage division principle of the coupling capacitance upper electrode of the device of the present invention is as shown in Figure 5, where the dielectric layer capacitance C ゲート and the junction capacitance C formed by the semiconductor depletion region formed by the gate 6 and the channel 5. 半導体 The two capacitances, and , are connected in series to divide the voltage and control the channel on / off. When the external gate voltage is Vgs, the dielectric capacitance C ゲート The voltage distributed to 半導体 / (C ゲート +C 半導体 ) and the junction capacitance of the semiconductor depletion region, C 半導体 The voltage distributed to ゲート / (C ゲート +C 半導体 ) The dielectric layer capacitance C ゲート is determined as a fixed value depending on the material and thickness of the dielectric layer 7, and when Vgs increases from 0, C ゲート and the junction capacitance C of the depletion region formed by the self-generated electric field of the semiconductor 半導体 and divide the voltage, and a part of the voltage Vgs applied to the coupling capacitance upper electrode 8 is coupled to the semiconductor junction. At this time, the junction capacitance C 半導体 Percentage of voltage coupled into C ゲート / (C ゲート +C 半導体 ) is maximized. The increase in gate voltage Vgs and the junction capacitance C of the semiconductor depletion region 半導体 As the voltage coupled to the semiconductor junction capacitance C 半導体 The depletion region of the 半導体 becomes larger, and the junction capacitance C of the semiconductor depletion region 半導体 Percentage of voltage coupled to C ゲート / (Cゲート +C 半導体 ) gradually becomes smaller. When the depletion region of the semiconductor narrows to a certain extent, the area close to the semiconductor junction interface cannot narrow any further, and the junction capacitance C 半導体 rises to and remains at a relatively large value, after which there is no further rise, at which point the voltage Vgs applied to the coupling capacitance upper electrode 8, the potential coupled to the gate 6, is at a maximum and the device is saturated.

[0130] 17-1, 17-2, 17-3, 17-4, 17-5, and 17-6 are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application, where the vertical axis represents the potential distribution and the horizontal axis represents the horizontal position.

[0131] In Figure 15, the vertical dashed lines represent the vertical direction, and the horizontal dashed lines to the right of the vertical dashed lines correspond to the parts to the right of coordinate 0 on the horizontal axis in Figures 17-1, 17-2, 17-3, 17-4, 17-5, and 17-6, and the horizontal dashed lines to the left of the vertical dashed lines correspond to the parts to the left of coordinate 0 on the horizontal axis in Figures 17-1, 17-2, 17-3, 17-4, 17-5, and 17-6.

[0132] As shown in Figures 17-1, 17-2, 17-3, 17-4, 17-5, and 17-6, the energy band distributions of the gate 6, channel 5, and second-doped ohmic contact region 3 of the present vertical trench capacitively coupled gate-controlled junction field-effect transistor show the relative changes in the conduction band, valence band, and Fermi levels of electrons and holes in each region when the coupling capacitor upper electrode of the device is in operation. As shown in Figure 17-1, when the voltage Vgs applied to the coupling capacitor upper electrode 8 is 0 V, taking the self-depleted channel 5 as an example, the Fermi level of the channel 5 is located at the center of the band gap, the device is in a self-depleted state, and the concentrations of both electrons and holes in the channel 5 are very low. The Fermi levels of the gate 6 and the second-doped ohmic contact region 3 are located near the valence band, with an extremely high concentration of holes and an extremely low concentration of electrons. As the voltage Vgs applied to the coupling capacitor upper electrode 8 increases, the distance between the conduction band and the Fermi level in the gate 6 and channel 5 gradually decreases, a low concentration of electrons appears in the gate 6, the conduction band in channel 5 is close to the electron Fermi level, and the electron concentration in channel 5 is very high, participating in conduction and forming a conductive channel. In addition, the distance between the valence band and the Fermi level in channel 5 gradually decreases, and a low concentration of holes appears in channel 5.

[0133] FIG. 18-1 shows the carrier concentration distribution in each region of the gate 6, channel 5, and second doping type ohmic contact region 3 of the vertical trench type capacitively coupled gate-controlled junction field effect transistor of the present application when the hole concentration in each region is affected by the voltage applied to the coupling capacitance upper electrode 8 and the device is operating.

[0134] FIG. 18-2 shows the carrier concentration distribution in each region of the gate 6, channel 5, and second doping type ohmic contact region 3 of the vertical trench type capacitively coupled gate-controlled junction field effect transistor of the present application when the device is operating, as the electron concentration in each region is affected by the voltage applied to the coupling capacitance upper electrode 8.

[0135] 18-1 and 18-2 show the carrier concentration distributions in the gate 6, channel 5, and second-doped ohmic contact region 3 of the vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present invention when the device is operating, as affected by the voltage applied to the coupling capacitor upper electrode 8. When the voltage Vgs applied to the coupling capacitor upper electrode 8 is 0 V, the hole concentration in the gate 6 is extremely high and the electron concentration is extremely low. When the channel 5 is modulated to a self-depleted state by doping, both the electron and hole concentrations are extremely low. As the voltage Vgs applied to the coupling capacitor upper electrode 8 increases, due to the capacitive coupling principle, the voltages on both the capacitor coupled to the dielectric layer 7 and the semiconductor junction capacitor formed by the gate 6 and channel 5 increase. When the voltage on the semiconductor junction formed by the gate 6 and channel 5 increases, the depletion region in the channel 5 narrows, changing from a depleted state to a non-depleted state. As a result, the electron concentration in the channel 5 increases rapidly, forming a conductive channel. In addition, the built-in potential at the semiconductor junction formed by the gate 6 and the channel 5 decreases, some of the electrons in the channel 5 enter the gate 6, the electron concentration at the gate 6 changes from an extremely low concentration to a low electron concentration, and some of the holes in the gate 6 enter the channel 5, increasing the hole concentration at the semiconductor junction between the gate 6 and the channel 5.

[0136] The transfer characteristics of the present vertical trench capacitively coupled gate-controlled junction field-effect transistor demonstrate that when voltages are applied to both the upper coupling capacitor electrode and the drain electrode, the device's off-state current is small when the voltage on the upper coupling capacitor electrode is low. As the voltage on the upper coupling capacitor electrode increases, the drain electrode current increases. When the voltage on the upper coupling capacitor electrode increases significantly, the semiconductor junction capacitance remains stable and the device saturates. Current SiC MOSFET devices still do not exhibit current saturation even at Vgs of 20V. In addition, the current path in the present device is farther away from the dielectric surface, thereby improving the device's short-circuit resistance.

[0137] The present vertical trench capacitively coupled gate-controlled junction field effect transistor clearly has high reliability, high robustness, and manufacturing advantages.

[0138] <Example 5> 3-5 are schematic diagrams showing a fifth implementation of the vertical trench type capacitively coupled gate-controlled junction field effect transistor of the present application. In the fifth implementation of the vertical trench type capacitively coupled gate-controlled junction field effect transistor of the present application, the shapes of the trench, the dielectric layer 7, and the coupling capacitance upper electrode 8 are different from those of the first implementation (i.e., Example 1).

[0139] As shown in FIG. 3-5, the trench is a trench having a rectangular cross section, in which case the dielectric layer 7 covers only the inner bottom of the gate 6 and does not cover the sidewalls of the gate 6; The coupling capacitance upper electrode 8 is formed only on the dielectric layer 7 .

[0140] The dielectric layer 7 does not completely cover the sidewalls of the trench, but is formed only on the inner bottom of the trench, and the coupling capacitance upper electrode 8 is located above the dielectric layer. Since this structure is planar, it has the advantage of being easy to fabricate and being simple in process.

[0141] The operating principle is that the dielectric layer 7 is located at the inner bottom of the trench, and the coupling capacitance upper electrode 8 is located above the dielectric layer 7, and the coupling capacitance upper electrode 8 controls the gate 6 through the dielectric layer, and further controls the on / off of the channel 5.

[0142] 3-6 are schematic diagrams showing a sixth implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention. In the sixth implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention, the shapes of the trench, the dielectric layer 7, and the coupling capacitance upper electrode 8 are different from those in the second implementation (i.e., Example 2).

[0143] As shown in FIGS. 3-6, the trench is a trench having a rectangular cross section, in which case the dielectric layer 7 covers only the inner bottom of the gate 6 and does not cover the sidewalls of the gate 6; The coupling capacitance upper electrode 8 is formed only on the dielectric layer 7 .

[0144] 3-7 is a schematic diagram showing a seventh implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention. In the seventh implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present invention, the shapes of the trench, the dielectric layer 7, and the coupling capacitance upper electrode 8 are different from those of the third implementation.

[0145] As shown in FIG. 3-7, the trench is a trench having a rectangular cross section, in which case the dielectric layer 7 covers only the inner bottom of the gate 6 and does not cover the sidewalls of the gate 6; The coupling capacitance upper electrode 8 is formed only on the dielectric layer 7 .

[0146] 3-8 is a schematic diagram showing an eighth implementation of the vertical trench type capacitively coupled gate-controlled junction field effect transistor of the present invention. In the eighth implementation of the vertical trench type capacitively coupled gate-controlled junction field effect transistor of the present invention, the shapes of the trench, the dielectric layer 7, and the coupling capacitance upper electrode 8 are different from those of the fourth implementation (i.e., Example 4).

[0147] As shown in FIG. 3-8, the trench is a trench having a rectangular cross section, in which case the dielectric layer 7 covers only the inner bottom of the gate 6 and does not cover the sidewalls of the gate 6; The coupling capacitor upper electrode 8 is formed only on the dielectric layer 7 .

[0148] 3-9 is a schematic diagram illustrating a ninth implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application. FIG. 3-9 shows a metal silicide layer 11. As shown in FIG. 3-9, the metal silicide layer 11 is formed between the gate 6 and the dielectric layer 7.

[0149] A metal silicide layer (abbreviated as Silicide layer) may be added under the coupling capacitance upper electrode dielectric layer, i.e., the metal silicide layer may be interposed between the dielectric layer 7 and the gate 6. In this way, the metal silicide layer under the dielectric layer 7 is a metal layer, and the distribution of the electric field in the metal layer is uniform, thereby optimizing the electric field on the surface of the gate 6 and improving the reliability of the device.

[0150] 3-10 is a schematic diagram illustrating a tenth implementation of the vertical trench capacitively coupled gate-controlled junction field effect transistor of the present application. FIG. 3-10 shows a metal silicide layer 11. As shown in FIG. 3-10, the metal silicide layer 11 is formed between the gate 6 and the dielectric layer 7.

[0151] Example 6 A method for manufacturing a vertical trench capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application includes: forming an epitaxial layer 2 of a first doping type on a substrate 1 of a first doping type; forming a plurality of repeat units, wherein the step of forming the repeat units comprises: forming two laterally spaced apart source regions 4 of a first doping type located in said epitaxial layer; forming a trench extending downward from the upper surface of the epitaxial layer and positioned between two source regions 4 of a first doping type; forming a gate 6 of a second doping type located on the inner wall and bottom of the trench; forming a dielectric layer 7 on at least the inner bottom of the gate 6; and forming a coupling capacitance upper electrode 8 on the dielectric layer 7.

[0152] In one implementation, the step of forming the repeat unit comprises: The method further includes forming two channels 5 of the first doping type located below the two source regions 4, respectively.

[0153] In one implementation, the step of forming the repeat unit comprises: forming two channels 5 of a first doping type located respectively below the two source regions 4; and forming two second doping type ohmic contact regions 3 located outside the two source regions 4, respectively.

[0154] In describing the present application and its embodiments, it should be understood that the orientations or positional relationships indicated by the terms "top," "bottom," "height," etc. are based on the orientations or positional relationships shown in the drawings, are merely for the purpose of facilitating and simplifying the description of the present application, and do not indicate or imply that the referred-to devices or elements must have a particular orientation, be constructed, or operate in a particular orientation, and therefore cannot be understood as limiting the present application.

[0155] In the present application and its examples, unless otherwise clearly specified or limited, the terms "provide," "attach," "couple," "connect," "fixed," etc. should be understood in a broad sense, and may refer to, for example, a fixed connection, a detachable connection, or an integral one, a mechanical connection, an electrical connection, a communication, a direct connection, an indirect connection via an intermediate medium, an internal communication between two elements, or an interactive relationship between two elements. Those skilled in the art can understand the specific meanings of the above terms in this specification according to specific circumstances.

[0156] In this application and its examples, unless otherwise clearly specified or limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact or that the first and second features are in indirect contact via an intermediate medium. Furthermore, a first feature being "above," "above," and "on the upper surface" of a second feature may mean that the first feature is directly above or diagonally above the second feature, or simply that the horizontal height of the first feature is higher than that of the second feature. A first feature being "below," "below," and "on the lower surface" of a second feature may mean that the first feature is directly below or diagonally below the second feature, or simply that the horizontal height of the first feature is lower than that of the second feature.

[0157] The above disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, specific example components and configurations have been described above. Of course, these are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and / or characters in different examples for purposes of brevity and clarity, and as such, does not indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, while the present application describes examples of various specific processes and materials, those skilled in the art may envision the application of other processes and / or the use of other materials.

[0158] Although preferred embodiments of the present application have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once they have learned the basic creative concepts. Therefore, it is intended that the appended claims be interpreted as including all changes and modifications that fall within the scope of the preferred embodiments and the present application.

[0159] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations. [Explanation of symbols]

[0160] 1 board 2. Epitaxial layer 3 Second doping type ohmic contact region 4 Source Area 5 channels 6 Gate 7 Dielectric Layer 8 Coupling capacitance upper electrode 9 Source electrode 10 Drain electrode 11 Metal silicide layer.

Claims

1. A semiconductor device comprising a substrate (1) and an epitaxial layer (2) of a first doping type, and a plurality of repeat units, the epitaxial layer being located on the substrate, the substrate acting as a drain region, the repeat units being: two laterally spaced apart source regions (4) of a first doping type formed in said epitaxial layer; a trench formed downward from the upper surface of the epitaxial layer and positioned between two source regions (4) of the first doping type; a floating gate (6) of a second doping type formed on the inner wall and bottom of the trench; a dielectric layer (7) formed on at least the inner bottom of the gate (6); a coupling capacitance upper electrode (8) formed on the dielectric layer (7), The gate (6) is indirectly controlled by a coupling capacitance upper electrode (8) across a dielectric layer (7). A vertical trench capacitively coupled gate-controlled junction field effect transistor (FET) comprising:

2. The gates (6) of the second doping type of adjacent repeat units and the region located between the adjacent gates (6) of the second doping type of the epitaxial layer form a JFET region, and the gates (6) of the JFET region are indirectly controlled by a coupling capacitance upper electrode (8) across a dielectric layer (7).

2. The vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 1.

3. The vertical trench capacitively coupled gate-controlled junction field effect transistor comprises: two channels (5) of the first doping type located respectively below the two source regions (4); The gate (6) of the second doping type, the channel (5) of the first doping type, and the gate (6) of the second doping type of the adjacent repeat unit form a JFET region, and the gate (6) of the JFET region is indirectly controlled by a coupling capacitance upper electrode (8) across a dielectric layer (7).

2. The vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 1.

4. The vertical trench capacitively coupled gate-controlled junction field effect transistor comprises: Further comprising two second doping type ohmic contact regions (3) located outside the two source regions (4), respectively; a second doping type gate (6), a region of the epitaxial layer located between the second doping type gate (6) and the second doping type ohmic contact region (3), and the second doping type ohmic contact region (3) form a JFET region, and the gate (6) of the JFET region is indirectly controlled by a coupling capacitance upper electrode (8) across a dielectric layer (7); 2. The vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 1.

5. The vertical trench capacitively coupled gate-controlled junction field effect transistor comprises: two channels (5) of the first doping type located respectively below the two source regions (4); and two second doping type ohmic contact regions (3) located outside the two source regions (4) and the channel (5), respectively; The second doping type gate (6), the first doping type channel (5), and the second doping type ohmic contact region (3) form a JFET region, and the gate (6) of the JFET region is indirectly controlled by a coupling capacitance upper electrode (8) across a dielectric layer (7); The gate (6), the channel (5), the source region (4), and the second doping type ohmic contact region (3) are formed in the epitaxial layer (2).

2. The vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 1.

6. The vertical trench capacitively coupled gate-controlled junction field effect transistor comprises: a drain electrode (10) provided on the lower surface of the substrate; two source electrodes (9) formed on the two source regions (4), respectively; a substrate (1) of a first doping type, an epitaxial layer (2) of a first doping type, and two source regions (4) of a first doping type, which form an internal conduction path from a drain electrode to two source electrodes located within the substrate (1) and the epitaxial layer (2); 5. The vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 2 or 4.

7. The vertical trench capacitively coupled gate-controlled junction field effect transistor comprises: a drain electrode (10) provided on the lower surface of the substrate; two source electrodes (9) formed on the two source regions (4), respectively; a substrate (1) of a first doping type, an epitaxial layer (2) of a first doping type, two channels (5) of a first doping type, and two source regions (4) of a first doping type, which form an internal conduction path from a drain electrode to two source electrodes located within the substrate (1) and the epitaxial layer (2); 6. The vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 3 or 5.

8. The trench is a U-shaped trench, in which case the dielectric layer (7) covers the coupling capacitance upper electrode space surrounded by the inner surface of the gate (6), and the dielectric layer (7) covers the top of the gate; The coupling capacitance upper electrode (8) is formed in the coupling capacitance upper electrode space.

6. The vertical trench type capacitively coupled gate-controlled junction field effect transistor according to claim 1.

9. The trench is a trench having a rectangular cross section, in which case the dielectric layer (7) covers the inner bottom of the gate (6), The coupling capacitance upper electrode (8) is formed on the dielectric layer (7).

6. The vertical trench type capacitively coupled gate-controlled junction field effect transistor according to claim 1.

10. By controlling the doping of the gates (6) of the second doping type of two adjacent repeat units, when the voltage of the coupling capacitance upper electrode (8) is zero, the region sandwiched between the gates (6) of the second doping type of two adjacent repeat units is in a depletion state, and the vertical trench type capacitively coupled gate-controlled junction field effect transistor is a normally-off device; Alternatively, by controlling the doping of the second doping type gates (6) of two adjacent repeat units, when the voltage of the coupling capacitance upper electrode (8) is zero, the region sandwiched between the second doping type gates (6) of the two adjacent repeat units becomes conductive, and the vertical trench type capacitively coupled gate-controlled junction field effect transistor is a normally-on device.

2. The vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 1.

11. By controlling the doping of the second doping type gate (6) and the second doping type ohmic contact region (3), when the voltage of the coupling capacitance upper electrode (8) is zero, the region sandwiched between the second doping type gate (6) and the second doping type ohmic contact region (3) is in a depletion state, and the vertical trench type capacitively coupled gate-controlled junction field effect transistor is a normally-off device; Alternatively, by controlling the doping of the second doping type gate (6) and the second doping type ohmic contact region (3), when the voltage of the coupling capacitance upper electrode (8) is zero, the region sandwiched between the second doping type gate (6) and the second doping type ohmic contact region (3) is in a conductive state, and the vertical trench type capacitively coupled gate-controlled junction field effect transistor is a normally-on device.

2. The vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 1.

12. the substrate is a silicon carbide substrate, a silicon substrate, a diamond substrate, or a potassium oxide substrate; the dielectric layer is made of a high dielectric constant material, The coupling capacitance upper electrode (8) is a polysilicon electrode or a metal electrode.

2. The vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 1.

13. The vertical trench capacitively coupled gate-controlled junction field effect transistor comprises: Further comprising a metal silicide layer (11) formed between the gate (6) and the dielectric layer (7).

6. The vertical trench type capacitively coupled gate-controlled junction field effect transistor according to claim 1.

14. The doping concentration of the gate (6) is 1×10 １６ cm －３ That's all.

2. The vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 1.

15. the doping concentration of the channel (5) is higher than the doping concentrations of the substrate and the epitaxial layer; 6. The vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 3 or 5.

16. forming an epitaxial layer (2) of a first doping type on a substrate (1) of a first doping type; forming a plurality of repeat units, wherein the step of forming the repeat units comprises: forming two laterally spaced apart source regions (4) of a first doping type located in said epitaxial layer; forming a trench extending downward from the upper surface of the epitaxial layer and positioned between two source regions (4) of a first doping type; forming a gate (6) of a second doping type located on the inner wall and bottom of the trench; forming a dielectric layer (7) on at least the inner bottom of said gate (6); forming a coupling capacitance upper electrode (8) on the dielectric layer (7); 1. A method for manufacturing a vertical trench capacitively coupled gate-controlled junction field effect transistor, comprising:

17. The step of forming the repeat unit comprises: The method further comprises forming two channels (5) of the first doping type located respectively below the two source regions (4), 17. The method for manufacturing a vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 16.

18. The step of forming the repeat unit comprises: forming two channels (5) of a first doping type located respectively below the two source regions (4); and forming two second doping type ohmic contact regions (3) located outside the two source regions (4), respectively.

17. The method for manufacturing a vertical trench capacitively coupled gate-controlled junction field effect transistor according to claim 16.

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