Vertical capacitive coupling gate control junction type field effect transistor and manufacturing method for the same

Abstract

To provide a vertical capacitive coupling gate control junction type field effect transistor, and a manufacturing method for the same.SOLUTION: A field effect transistor includes a departure substrate 1 of a first doping type, two bottom gates 3 of a second doping type formed in the departure substrate 1 and provided apart from each other in a lateral direction, a top gate 8 of the second doping type formed in the departure substrate 1, existing over the space between the two bottom gates 3, and having a space from the bottom gates 3, a dielectric layer 9 formed on the departure substrate 1 and existing at a position on the top gate 8 of the second doping type, and a coupling capacitance upper electrode 10 formed on the dielectric layer 9. The top gate 8 of the second doping type is controlled indirectly by the coupling capacitance upper electrode 10 through the dielectric layer 9.SELECTED DRAWING: Figure 3-4

Description

[Technical Field]

[0001] This application relates to the field of semiconductor technology, and more particularly to vertical capacitively coupled gate-controlled junction field effect transistors and methods for fabricating the same. [Background technology]

[0002] Silicon carbide (SiC) is a third-generation wide-bandgap semiconductor. Its bandgap width is 3.2 eV, much larger than the 1.1 eV of conventional silicon. Its critical breakdown field strength is an order of magnitude higher than that of silicon, and it has the advantages of excellent resistance to high temperatures and pressures. Its fast saturation drift velocity makes it suitable for the fabrication of high-temperature, high-voltage power semiconductor devices, such as vertical double-diffused MOSFETs (VDMOSs) and junction field-effect transistors (JFETs), which support fast response. The junction field-effect transistor (JFET) is also a tripolar semiconductor device. Its operating principle is to turn off the drain and source electrodes by applying a voltage to the gate electrode, thereby controlling the reverse bias of the pn junction between the gate electrode and the channel. When no voltage is applied to the gate electrode, the device is normally on, with the conducting channel located within the device body. Junction field-effect transistors have the advantages of low noise, small size, high frequency response, etc., and are therefore often applied in switching devices, power amplifier devices, and digital electronic circuits to meet the requirements of different electronic devices.

[0003] A vertical conduction double-diffused MOSFET (VDMOS) device is a vertical semiconductor device that combines the advantages of bipolar transistors and conventional MOS devices. In a VDMOS, the gate and source electrodes are located on the top surface of the device, while the drain electrode is located on the bottom surface. The gate controls the on / off state of the channel, allowing current to flow from the drain electrode through an inversion channel inside the body and on the top surface of the device to the source electrode, with the conduction channel being on the top surface of the device. VDMOS is an ideal power device for both switching and linear applications, and is primarily used in electronic switches, adapters, driveband energy, and industrial controls. Summary of the Invention [Problem to be solved by the invention]

[0004] CN1238904C is a JFET device, as shown in Figure 1, which comprises a single-crystal silicon (SiC) substrate 1, a p-type epitaxial layer 2, an n-type epitaxial layer 3, a p+-type semiconductor layer 4, an n+-type source region layer 5, a p+-type gate region layer 7, an n+-type drain region layer 9, a source electrode 10, a gate electrode 11, and a drain electrode 12. The conduction channel of the JFET device is located within the n-type epitaxial layer 3. This location within the semiconductor material avoids the problem of low surface mobility in SiC materials. The JFET device is a normally-on device; that is, when no voltage is applied to the p+-type gate region layer 7 (i.e., gate electrode), the device is in a conducting state (current flow indicated by the dashed line in Figure 1). Therefore, to turn the device off, a negative voltage must be applied to the p+-type gate region layer 7 (i.e., gate electrode), limiting its application as a power switch. Furthermore, since the p+ type gate region layer 7 (i.e., the gate electrode) and the channel form a pn junction structure, a voltage exceeding 3 V cannot be applied to the p+ type gate region layer 7 (i.e., the gate electrode). In the case of SiC materials, when a voltage of 3 V or more is applied to the gate electrode, the gate electrode and the channel or the source electrode become conductive, the on-current becomes large, affecting the current characteristics from the drain to the source, and since a high voltage cannot be applied to the gate electrode, application as a power switch is limited.

[0005] Therefore, the inability to apply a high voltage to the gate of a conventional silicon carbide-based junction field-effect transistor and the low reliability of the gate electrode limit its application as a power switch, which is a technical problem that must be solved as soon as possible by those skilled in the art.

[0006] The above information disclosed in the Background section is intended only to enhance understanding of the background of the present application, and therefore may include information that does not constitute prior art known to those skilled in the art. [Means for solving the problem]

[0007] The present embodiment provides a vertical capacitively coupled gate-controlled junction field effect transistor and a manufacturing method thereof to solve the technical problem that the application of conventional silicon carbide-based junction field effect transistors as power switches is limited due to the inability to apply a relatively high voltage to the gate and low gate reliability.

[0008] According to a first aspect of an embodiment of the present application, there is provided a vertical capacitively coupled gate-controlled junction field effect transistor, a substrate of a first doping type; two laterally spaced bottom gates of a second doping type formed in the substrate; a top gate of a second doping type formed in the substrate, the top gate being located above a space between two of the bottom gates and having a space between the top gate and the bottom gate; a dielectric layer formed on the substrate and positioned above the top gate; a coupling capacitance upper electrode formed on the dielectric layer, The top gate is indirectly controlled by a capacitive coupling top electrode across a dielectric layer.

[0009] In one embodiment, the top gate is floating, and the coupling capacitance upper electrode, the dielectric layer, and the top gate together constitute a gate structure of a field effect transistor, and the top gate of the second doping type, the portion located between the top gate and the bottom gate, and the bottom gate form JFET region 1, and the two bottom gates and the portion located between the bottom gates form JFET region 2; The top gate of JFET region 1 is indirectly controlled by the coupling capacitance upper electrode across the dielectric layer, and thus JFET region 1 and JFET region 2 are indirectly controlled by the coupling capacitance upper electrode across the dielectric layer.

[0010] According to a second aspect of the present invention, there is provided a method for manufacturing a vertical capacitively coupled gate-controlled junction field effect transistor, comprising: providing a substrate of a first doping type; forming two laterally spaced bottom gates of a second doping type formed in the substrate; forming a top gate of a second doping type formed in the substrate, the top gate being located above a space between two of the bottom gates and having a space between the top gate and the bottom gate; forming a dielectric layer formed on the substrate and overlying the top gate; forming a coupling capacitance upper electrode formed on the dielectric layer; forming two source regions of a first doping type located respectively on the two bottom gates, the two source regions being connected to portions of a substrate located between the top gate and the bottom gate; forming two source electrodes connected to the source regions on the same side. [Effects of the Invention]

[0011] By adopting the above technical solutions, the embodiments of the present application have the following technical effects:

[0012] In the vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present application, the top gate 8 is indirectly controlled by the coupling capacitance upper electrode 10 via the dielectric layer 9. The gate voltage applied to the coupling capacitance upper electrode 10 is coupled to the top gate 8 through the coupling. Furthermore, the top gate 8 is floating and not directly connected to the gate electrode. Therefore, even if the potential of the coupling capacitance upper electrode 10 rises above 3 V, the top gate 8, the portion of the substrate between the top gate 8 and the bottom gate 3, and the portion of the substrate between the bottom gate 3 are not conductive. Compared to the JFET device described in CN1238904C, the embodiment of the present application does not conduct even when a high voltage (greater than 3 V, e.g., 4 V or 5 V) is applied to the top gate 8, and therefore does not affect the current characteristics from the drain electrode to the source electrode of the device. Because the top gate 8 is indirectly controlled by the coupling capacitance upper electrode 10 via the dielectric layer 9, no current flows through the top gate 8, resulting in high reliability. [Brief explanation of the drawings]

[0013] The accompanying drawings illustrated herein are used for further understanding of the present application and constitute a part of the present application, and the exemplary embodiments and descriptions thereof are used to explain the present application and are not to be construed as unduly limiting the present application. [Figure 1] FIG. 1 is a schematic diagram illustrating a prior art JFET device. [Figure 2] FIG. 1 is a schematic diagram showing a prior art SiC VDMOS device. [Figure 3-1] 1 is a schematic diagram showing a first embodiment of a vertical capacitively coupled gate-controlled junction field effect transistor of the present invention; [Figure 3-2] FIG. 2 is a schematic diagram showing a second embodiment of a vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 3-3] FIG. 10 is a schematic diagram showing a third embodiment of a vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 3-4] FIG. 10 is a schematic diagram showing a fourth embodiment of a vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 3-5] FIG. 10 is a schematic diagram showing a fifth embodiment of a vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 4] FIG. 10 is a schematic diagram illustrating the formation of an epitaxial layer on a starting substrate in a manufacturing method according to a fourth embodiment of the vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 5] FIG. 5 is a schematic diagram illustrating the formation of a top gate and a second doping type ohmic contact region based on FIG. 4. [Figure 6] FIG. 6 is a schematic diagram showing how channel 1, channel 2, and source regions are formed based on FIG. 5. [Figure 7] FIG. 7 is a schematic diagram showing how a top gate is formed based on FIG. 6. [Figure 8] FIG. 8 is a schematic diagram showing how a dielectric layer and a coupling capacitance upper electrode are formed based on FIG. 7. [Figure 9] FIG. 9 is a schematic diagram showing how a gate electrode and a source electrode are formed based on FIG. 8. [Figure 10] FIG. 10 is a schematic diagram showing how a drain electrode is formed based on FIG. 9. [Figure 11] 1 is an equivalent circuit diagram of a vertical capacitively coupled gate-controlled junction field-effect transistor according to the present invention. [Figure 12] 1 is a schematic diagram showing a current path when the vertical capacitively coupled gate-controlled junction field effect transistor of the present application is conductive. FIG. [Figure 13] 1 is a schematic diagram comparing the characteristics of a vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention with those of a device based on conventional VDMOS technology. [Figure 14-1] 1 is a schematic diagram showing a vertical capacitively coupled gate-controlled junction field effect transistor according to the present invention; [Figure 14-2] 1 is a diagram showing an internal electric field distribution at the time of breakdown of a vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 15-1] 1 is a schematic diagram showing a vertical capacitively coupled gate-controlled junction field effect transistor according to the present invention; [Figure 15-2] 1 shows the potential distribution in the gate structure of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 16-1] 1A and 1B are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 16-2] 1A and 1B are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 16-3] 1A and 1B are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 16-4] 1A and 1B are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 16-5] 1A and 1B are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. [Figure 16-6] 1 is a diagram showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 17-1] FIG. 1 shows the carrier concentration distribution in each region of the top gate 8, channel 5, and bottom gate 3 of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention during device operation, as affected by the voltage applied to the gate electrode 11. [Figure 17-2] FIG. 1 shows the carrier concentration distribution in each region of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention, as affected by the voltage applied to the gate electrode 11, as the hole concentration in the top gate 8, channel 5, and bottom gate 3 of the device during operation. [Figure 18-1] FIG. 1 is a diagram showing a transfer characteristic curve of a vertical capacitively coupled gate-controlled junction field-effect transistor according to the present invention. [Figure 18-2] FIG. 1 is a diagram showing the transfer characteristic curve of an existing SiC MOSFET device. DETAILED DESCRIPTION OF THE INVENTION

[0014] In order to make the technical solutions and advantages of the embodiments of the present application clearer, the exemplary embodiments of the present application will be described in more detail below with reference to the drawings. However, it is clear that the described embodiments are only some of the embodiments of the present application and are not exhaustive of all the embodiments. In addition, the embodiments and features of the embodiments of the present application may be combined with each other without contradiction.

[0015] Traditional semiconductor devices are often fabricated using silicon, a first-generation semiconductor material. However, in recent years, the third-generation wide-bandgap semiconductor material silicon carbide has emerged. Due to its advantages, such as a wide bandgap, high breakdown voltage, and high thermal conductivity, silicon carbide-based semiconductor devices have demonstrated clear performance advantages over silicon-based devices. However, due to the immaturity of current silicon carbide material, semiconductor devices based on silicon carbide materials face performance and reliability issues. For example, numerous defects near the silicon carbide material surface result in low surface mobility, severely impacting device performance. Furthermore, silicon carbide devices have high quality requirements for gate oxides, but the quality of existing gate oxides does not meet these requirements. In conventional power devices of this type, the conduction channel is located on the surface of the silicon carbide material and oxide. Due to the characteristics of silicon carbide, there are many charges and defects on the surface of the silicon carbide and oxide, which affect the mobility of carriers in the channel, making the mobility of carriers in the channel much lower than the bulk mobility of silicon carbide. The channel mobility, or surface mobility, of silicon carbide MOSFETs is about 20 to 40 cm 2 / V s, whereas the bulk mobility of silicon carbide materials is approximately 1000 cm 2 / V·s. Low channel mobility affects the current transfer characteristics and on-resistance of the device. Also, because the current flowing through the surface of the device is located under the gate oxide, unstable traps and defect centers affect the reliability of the device's gate electrode.

[0016] In conventional power devices of this type, when the device is off and the drain electrode is at a high voltage (breakdown condition), the vertical epitaxial layer - JFET region - dielectric layer is the main breakdown voltage region. The relationship between the electric displacement vector, the electric field strength and the dielectric constant, D = ε·E, gives the electric displacement vector in the semiconductor as D 半導体 =ε 半導体 E 半導体 and the electric displacement vector in the dielectric layer immediately adjacent to the semiconductor is D 誘電体 =ε 誘電体 E 誘電体 At the interface between the semiconductor and the dielectric, the electric displacement vector D is continuous, i.e., D 半導体 =D 誘電体 Therefore, ε 半導体 E 半導体 =ε 誘電体 E 誘電体 When the same type of dielectric material is adjacent to a different semiconductor material, for example, when the substrate is silicon or silicon carbide, the dielectric constants ε of the two semiconductor materials are approximately the same (ε シリコン =11.8, ε 炭化ケイ素 =9.8), but the critical breakdown field strength of silicon carbide, a third-generation wide bandgap semiconductor material, is much larger than that of silicon material (E シリコン =0.23MV / cm, E 炭化ケイ素 =2.2MV / cm), ε 半導体 E 半導体 =ε 誘電体 E 誘電体 From this, it can be seen that the electric field strength in a dielectric layer corresponding to a silicon carbide material is much greater than that in a dielectric layer corresponding to a silicon material. Thus, the dielectric layer below the gate of a silicon carbide-based device in breakdown (oxide layer or high-K dielectric) has a typical value of about 2×10 6V / cm, where the field strength is on the order of megavolts per centimeter, and the high field strength within the dielectric layer affects the reliability of the operation of the gate electrode in silicon carbide-based devices.

[0017] As described above, the conventional technology has the technical problem that a high voltage cannot be applied to the gate electrode of a conventional silicon carbide-based junction field effect transistor, resulting in low gate reliability, which limits the application of the junction field effect transistor as a power switch. In addition, there are also the technical problems of reduced device performance due to the conduction channel being close to the surface of a material with low mobility, and reduced device reliability due to a deterioration in the quality of the gate dielectric layer.

[0018] CN116598356A discloses a SiC VDMOS device. As shown in Figure 2, 0 denotes a gate oxide layer, 1 denotes an N-type region, 2 denotes an N+ doped region, 3 denotes a channel region, 4 denotes an N-type ohmic contact region, 5 denotes a SiC epitaxial layer, 6 denotes a SiC starting substrate, 7 denotes polysilicon, 9 denotes a source electrode, and 10 denotes a drain electrode. When no voltage is applied to the polysilicon 7, the device is off and does not conduct. When a voltage is applied to the polysilicon 7, the capacitance effect of the metal-oxide semiconductor is utilized to attract positive charges near the surface of the channel region 3, forming an inversion channel on the surface, enabling conduction from the drain electrode to the source. Current (shown by the dotted line in Figure 2) first travels vertically from the drain electrode to the interface between the SiC surface and the oxide above the SiC, then flows through the inversion channel on the SiC surface to the source electrode. That is, part of the conduction channel is vertical and located within the device, and the other part is lateral to the surface of the device. Due to the presence of charges, defects, and surface scattering at the interface between the semiconductor material and the oxide, the effective mobility of the SiC VDMOS surface is low, which results in a low saturation current Idsat and a high on-resistance Rsp of the device, affecting device performance and limiting the device output power and switching speed.

[0019] The present application provides a vertical capacitively coupled gate-controlled junction field effect transistor. The vertical capacitively coupled gate-controlled junction field effect transistor of the present application has a vertical device structure.

[0020] Example 1 As shown in FIG. 3-1, the first embodiment of the vertical capacitively coupled gate-controlled junction field effect transistor according to the present invention is as follows: a substrate of a first doping type; two laterally spaced bottom gates 3 of a second doping type formed in the substrate; a top gate 8 of a second doping type formed in the substrate, the top gate 8 being located above a space between two of the bottom gates and having a space between the top gate 8 and the bottom gate 3; a dielectric layer 9 formed on the substrate and positioned above the top gate 8; a coupling capacitance upper electrode 10 formed on the dielectric layer 9, The top gate 8 is indirectly controlled by a coupling capacitance upper electrode 10 across a dielectric layer 9 .

[0021] Here, the top gate 8 is in a floating state, and the coupling capacitance upper electrode 10, the dielectric layer 9, and the top gate 8 together form the gate structure of a field effect transistor. a top gate 8 of a second doping type, a portion of the substrate located between said top gate 8 and said bottom gate 3, and said bottom gate 3 form a JFET region 1; The two bottom gates 3 and the portion located between the bottom gates 3 form a JFET region 2; The top gate 8 of the JFET region 1 is indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9, and thus the JFET region 1 and the JFET region 2 are indirectly controlled by the coupling capacitance upper electrode 10 across the dielectric layer 9.

[0022] The portion of the substrate located between the top gate 8 and the bottom gate 3 and the portion of the substrate located between the bottom gates 3 collectively form a channel region.

[0023] In the vertical capacitively coupled gate-controlled junction field-effect transistor according to the present embodiment, the top gate 8 of the JFET region 1 is indirectly controlled by the coupling capacitance upper electrode 10 via the dielectric layer 9. The gate voltage applied to the coupling capacitance upper electrode 10 is coupled to the top gate 8 via coupling. Furthermore, since the top gate 8 is floating and not directly connected to the gate electrode, even if the potential of the coupling capacitance upper electrode 10 rises above 3 V, the portion of the substrate located between the top gate 8 and the bottom gate 3 does not conduct. At this time, both the JFET region 1 and the JFET region 2 are not conducting. Compared to the JFET device described in CN1238904C, in the present embodiment, even if a high voltage (greater than 3 V, e.g., 4 V or 5 V) is applied to the top gate 8, the top gate 8 does not conduct and does not affect the current characteristics from the drain electrode to the source electrode of the device. Because the top gate 8 is indirectly controlled by the coupling capacitance upper electrode 10 via the dielectric layer 9, no current flows through the top gate 8, improving reliability.

[0024] The portion located between the top gate 8 and the bottom gate 3 is maintained as a substrate, which is the portion of the substrate located between the top gate 8 and the bottom gate 3. The portion located between the bottom gates 3 is maintained as a substrate, which is the portion of the substrate located between the bottom gates 3.

[0025] The vertical capacitively coupled gate-controlled junction field effect transistor according to the embodiment of the present application is a vertical capacitively coupled gate-controlled junction field effect transistor of a new structure, and is neither a conventional JFET device nor a conventional SiC VDMOS device.

[0026] The vertical capacitively coupled gate-controlled junction field effect transistor according to the embodiment of the present application has the following essential differences compared to a conventional JFET device.

[0027] The vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present application indirectly controls the top gate by utilizing the capacitive coupling principle, thereby avoiding current injection from the top gate to the channel and enabling the channel to be controlled by applying a higher voltage to the coupling capacitor upper electrode, making it applicable to a wider range of applications.

[0028] The vertical capacitively coupled gate-controlled junction field effect transistor according to the embodiment of the present application has the following essential differences compared to a JFET device:

[0029] The vertical capacitively coupled gate-controlled junction field effect transistor according to the embodiment of the present application utilizes the principle of capacitive coupling to control the potential of the floating top gate 8 via the coupling capacitive upper electrode 10 across the dielectric layer 9, thereby indirectly controlling the on / off of the portion of the substrate located between the top gate 8 and the bottom gate 3, and the portion of the substrate located between the bottom gate 3.

[0030] In a typical JFET device, the top gate is directly connected to the electrode, and when a high voltage is applied, the pn junction between the top gate and the channel turns on, allowing current to flow from the top gate to the channel, resulting in negative effects. In the vertical capacitively coupled gate-controlled junction field-effect transistor structure according to the present invention, this problem can be avoided due to the isolation provided by the insulating dielectric layer.

[0031] Specifically, the upper surface of the top gate 8 and the upper surface of the substrate are flush with each other.

[0032] In implementation, the vertical capacitively coupled gate-controlled junction field effect transistor comprises: a drain electrode 13 provided on the lower surface of the substrate; two source regions 7 of a first doping type located respectively on the two bottom gates, the two source regions 7 being connected to a portion of the substrate located between the top gate 8 and the bottom gate 3; It further comprises two source electrodes 12 connected to the source region 7 on the same side.

[0033] In this way, the substrate of the first doping type, the portion of the substrate below the gate structure and located between the bottom gate 3, and the portion of the substrate below the gate structure and located between the top gate 8 and the bottom gate 3 form an internal conduction path within the substrate from the drain electrode to the two source electrodes.

[0034] The main structure of the semiconductor device (the bottom gate 3, the second doping type ohmic contact region 4, the top gate 8, the source region 7, etc. are parts of the semiconductor device) is fabricated on top of a first doping type substrate. Within the substrate, above the gap between the two bottom gates, from top to bottom, there is the top gate 8, and the portion of the substrate located between the top gate 8 and the bottom gate 3. This ensures that the portion of the substrate located between the top gate 8 and the bottom gate 3 and the portion of the substrate located between the bottom gate 3 are all located within the substrate. This ensures that the bottom of the first doping type substrate, the portion of the substrate located between the bottom gate 3, the portion of the substrate located between the top gate 8 and the bottom gate 3, and the two source regions 7 are all of the first doping type. Therefore, the lower portion of the first doping type substrate, the portion of the substrate below the gate structure located between the bottom gate 3, and the portion of the substrate below the gate structure located between the top gate 8 and the bottom gate 3 form an internal conduction path located within the substrate from the drain electrode 13 to the two sources 12, and all of the internal conduction paths are located away from the low-mobility regions on the surface of the device. The entire internal conduction path of the vertical capacitively coupled gate-controlled junction field-effect transistor according to the present embodiment is located within the field-effect transistor, and all of the internal conduction paths are located away from the low-mobility regions on the surface of the device. That is, all of the internal conduction paths are located away from the semiconductor material surface and are internally conductive, thereby avoiding the problem of low surface mobility. This maintains high carrier mobility and fast drift velocity, and the vertical capacitively coupled gate-controlled junction field-effect transistor has a large saturation current Idsat, a small on-resistance Rsp, and good performance.

[0035] The SiC VDMOS device in the CN116598356A patent application has a conduction channel, part of which is vertical and located inside the device, and the other part of which is laterally aligned on the device surface. That is, part of the conduction channel is located on the device surface. Due to charges, defects, and surface scattering at the interface between the SiC material surface and the oxide layer, the effective carrier mobility is low, resulting in a low saturation current Idsat and a large on-resistance Rsp of the device, which impacts device performance and limits the device's output power and switching speed. In other words, the vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiments of the present application can solve the technical problem of the prior art, in which the conduction channel is close to the surface of a material with low mobility, resulting in reduced device performance.

[0036] The essential differences between the vertical capacitively coupled gate-controlled junction field effect transistor according to the embodiment of the present invention and the conventional SiC VDMOS device are as follows.

[0037] The vertical capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present application has internal conduction paths, all of which are away from the semiconductor material surface and are internally conductive, thereby avoiding the problem of low surface mobility and providing better performance. At the same time, the requirements for the quality of the gate dielectric layer of the device are low, resulting in better device reliability.

[0038] In implementation, the vertical capacitively coupled gate-controlled junction field effect transistor comprises: The semiconductor device further includes two second doping type ohmic contact regions 4 provided on both sides of the two bottom gates 3, respectively, and the second doping type ohmic contact regions 4 on the same side are connected to the bottom gates 3; The source electrode is located on the boundary between the source region 7 and the second doping type ohmic contact region 4 on the same side, i.e. the source electrode connects the source region 7 and the second doping type ohmic contact region 4 on the same side.

[0039] The bottom gate 3 is connected to the second doping type ohmic contact region 4, and the second doping type ohmic contact region 4 is connected to the source electrode 12, thereby realizing extraction of the bottom gate 3.

[0040] In practice, as shown in Figures 3-5, a vertical capacitively coupled gate-controlled junction field effect transistor is The semiconductor device further includes a metal silicide layer 14 formed between the top gate 8 and the dielectric layer 9 .

[0041] A metal silicide layer (abbreviated as "Silicide layer") can be added under the dielectric layer of the gate, i.e., the metal silicide layer can be disposed between the dielectric layer 9 and the top gate 8. This allows the metal silicide layer under the dielectric layer 9 to be a metal layer, which makes the electric field distribution in the metal layer uniform and optimizes the electric field on the surface of the top gate 8, thereby improving device reliability.

[0042] As shown in FIG. 3-1, in practice, the substrate comprises: a first doping type starting substrate 1 having the drain electrode 13 provided on the underside thereof; and an epitaxial layer 2 of a first doping type, in which the bottom gate 3, the top gate 8, the source region 7 and the ohmic contact region 4 of a second doping type are formed.

[0043] Specifically, the first doping type starting substrate 1 is heavily doped, and has a very high doping concentration, and serves as the drain region of a vertical capacitively coupled gate-controlled junction field effect transistor.

[0044] In an implementation, the starting substrate is a silicon carbide substrate.

[0045] In practice, the starting substrate is a semiconductor device substrate, such as a silicon substrate, or a diamond substrate, or a potassium oxide substrate.

[0046] There is a problem with the dielectric layer of conventional diamond-substrate MOSFETs; the dielectric layer formed on the diamond substrate by deposition methods, such as an oxide layer, is of poor quality and results in poor performance. The diamond vertical capacitively coupled gate-controlled junction field-effect transistor using this device structure solves this problem by locating the conduction channel within the device. MOSFETs (metal-oxide-semiconductor field-effect transistors) are common semiconductor devices.

[0047] Potassium oxide is a fourth-generation semiconductor material that can be used to fabricate electronic devices and electronic equipment, especially new controllable semiconductor devices.

[0048] In practice, the doping concentration of the top gate (8) is 1×10 16 cm -3 That's all.

[0049] The doping concentration of the top gate is 1×10 16 cm -3 This ensures that the top gate will not be depleted and a strong electric field will not be generated within the top gate when a voltage is applied to the gate.

[0050] In practice, the doping concentration of the channel 5 is greater than the doping concentration of the substrate; The doping concentration of the channel 26 is greater than the doping concentration of the substrate.

[0051] The doping concentration of Channel 1 and Channel 2 is greater than the doping concentration of the substrate, which helps reduce the on-resistance of the device and improve device performance.

[0052] Specifically, the material of the dielectric layer 9 may be silica or a high-K dielectric, which helps control the coupling capacitance of the upper electrode to the P+ type top gate and improves the performance of the device.

[0053] Specifically, the coupling capacitance upper electrode 10 can adopt P+ type and N+ type highly doped polysilicon, which reduces the contact resistance with the gate metal and the gate parasitic resistance, thereby improving the device performance.

[0054] High-K dielectrics refer to materials that have a high dielectric constant (high relative permittivity).

[0055] <Example 2> FIG. 3-2 shows a second embodiment of the vertical capacitively coupled gate-controlled junction field effect transistor of the present invention. The vertical capacitively coupled gate-controlled junction field effect transistor according to the second embodiment has a part of the same structure as the vertical capacitively coupled gate-controlled junction field effect transistor according to the first embodiment. The main difference between the vertical capacitively coupled gate-controlled junction field effect transistor according to the second embodiment and the vertical capacitively coupled gate-controlled junction field effect transistor according to the first embodiment is that a first doped channel 5 is formed in a position on the substrate between the top gate 8 and the bottom gate 3, as shown in FIG. 3-2. In this case, The top gate 8 is located above the channel 5 .

[0056] As shown in FIG. 3-2, the JFET region 1 is specifically formed by a top gate 8 of a second doping type, a channel 5 of a first doping type, and a bottom gate 3; The JFET region 2 is still formed by the two bottom gates 3 and the part located between the bottom gates 3 .

[0057] The top gate 8 of the JFET region 1 is indirectly controlled by a coupling capacitance upper electrode 10 across a dielectric layer 9. The first doping type channel 5 and the portion of the substrate located between the bottom gate 3 collectively form the channel region.

[0058] The portion located between the top gate 8 and the bottom gate 3 forms a channel 5 of a first doping type, and the portion located between the bottom gates 3 is kept as the substrate, which is the portion of the substrate located between the bottom gates 3.

[0059] As shown in Figure 3-2, the substrate of the first doping type, the portion of the substrate below the gate structure and located between the bottom gates 3, and the channel 5 of the first doping type below the gate structure form an internal conduction path within the substrate from the drain electrode to the two source electrodes, all of which are away from the low mobility regions at the surface of the device.

[0060] The lower portion of the substrate of the first doping type, the portion of the substrate below the gate structure and located between the bottom gates 3, and the channel 5 of the first doping type below the gate structure form an internal conduction path located in the substrate from the drain electrode to the source electrode. Control of the internal conduction path realizes on / off control of the entire vertical capacitively coupled gate-controlled junction field effect transistor. Control of the internal conduction path is realized by control of the channel 5.

[0061] The vertical capacitively coupled gate-controlled junction field-effect transistor according to the present invention has an internal conduction path entirely located within the vertical capacitively coupled gate-controlled junction field-effect transistor, and all of the internal conduction paths are located away from the low-mobility region at the device surface. That is, all of the internal conduction paths are located away from the semiconductor material surface and are internally conductive, thereby avoiding the problem of low surface mobility. This allows carriers to have high mobility and fast drift velocity, resulting in a large saturation current Idsat, a small on-resistance Rsp, and good performance.

[0062] As shown in FIG. 3-2, the substrate is a first doping type starting substrate 1 having a drain electrode 13 provided on its underside; The device comprises an epitaxial layer 2 of a first doping type, in which the bottom gate 3, channel region 5, top gate 8, source region 7, and ohmic contact region 4 of a second doping type are formed.

[0063] Specifically, the starting substrate 1 of the first doping type is heavily doped and has a high doping concentration, and serves as the drain region of a vertical capacitively coupled gate-controlled junction field effect transistor.

[0064] Specifically, the channel 5 may be formed by ion implantation or other methods using the original substrate. The doping concentration of the channel 5 is higher than the doping concentration of the epitaxial layer 2.

[0065] Specifically, since the doping concentration of the first doping type channel 5 is higher than the doping concentration of the epitaxial layer 2, the resistance of the first doping type channel 5 is reduced, which in turn reduces the on-resistance Rsp of the vertical capacitively coupled gate-controlled junction field effect transistor, thereby improving the performance of the vertical capacitively coupled gate-controlled junction field effect transistor.

[0066] Example 3 As shown in FIG. 3-3, a third embodiment of the vertical capacitively coupled gate controlled junction field effect transistor of the present application is shown. The vertical capacitively coupled gate controlled junction field effect transistor according to the third embodiment has a part of the same structure as the vertical capacitively coupled gate controlled junction field effect transistor according to the first embodiment. The main difference between the vertical capacitively coupled gate controlled junction field effect transistor according to the third embodiment and the vertical capacitively coupled gate controlled junction field effect transistor according to the first embodiment is that, as shown in FIG. 3-3, a first doping type channel 26 is formed by ion implantation at a position located between two bottom gates 3 of the substrate. In this case, As shown in FIG. 3-3, the JFET region is specifically formed by a top gate 8 of a second doping type, a portion of the substrate located between the top gate 8 and the bottom gate 3, and the bottom gate 3 of the second doping type; Specifically, the JFET region 2 is formed by two bottom gates 3 and a channel 2 6. The top gate 8 of the JFET region 1 is indirectly controlled by a coupling capacitance upper electrode 10 across a dielectric layer 9. The entire portion of the substrate located between the top gate 8 and the bottom gate 3 and the first doping type channel 26 functions as a channel region.

[0067] The portion of the substrate located between the top gate 8 and the bottom gate 3 is kept as a substrate, and the portion of the substrate located between the top gate 8 and the bottom gate 3 and the bottom gate 3 forms a channel 26 of a first doping type.

[0068] As shown in FIG. 3-3 , the first doping type substrate, the first doping type channel 26 below the gate structure, and the portion of the substrate below the gate structure between the top gate 8 and the bottom gate 3 form an internal conduction path located within the substrate from the drain electrode to the two source electrodes. Furthermore, all of this internal conduction path is located away from the low-mobility region on the device surface. The entire internal conduction path of the vertical capacitively coupled gate-controlled junction field-effect transistor according to the present embodiment is located within the vertical capacitively coupled gate-controlled junction field-effect transistor, and all of this internal conduction path is located away from the low-mobility region on the device surface. That is, all of the internal conduction path is located away from the semiconductor material surface and is internally conductive, thereby avoiding the problem of low surface mobility. This maintains carriers in a state of high mobility and fast drift velocity, resulting in a large saturation current Idsat, a small on-resistance Rsp, and good performance for the vertical capacitively coupled gate-controlled junction field-effect transistor.

[0069] As shown in FIG. 3-3, the substrate is a first doping type starting substrate 1 having the drain electrode 13 provided on the underside thereof; and an epitaxial layer 2 of a first doping type, in which the bottom gate 3, channel region 6, top gate 8, source region 7, and ohmic contact region 4 of a second doping type are formed.

[0070] Specifically, the starting substrate 1 of the first doping type is heavily doped and has a high doping concentration, and serves as the drain region of a vertical capacitively coupled gate-controlled junction field effect transistor.

[0071] Specifically, the channel 26 is formed by ion implantation, and the doping concentration of the channel 26 is higher than the doping concentration of the epitaxial layer 2.

[0072] Specifically, since the doping concentration of the first doping type channel 26 is higher than the doping concentration of the epitaxial layer 2, the resistance of the first doping type channel 26 is reduced, which in turn reduces the on-resistance RSP of the vertical capacitively coupled gate-controlled junction field effect transistor, thereby improving the performance of the vertical capacitively coupled gate-controlled junction field effect transistor.

[0073] Example 4 As shown in FIG. 3-4, a fourth embodiment of the vertical capacitively coupled gate controlled junction field effect transistor of the present application is shown. The vertical capacitively coupled gate controlled junction field effect transistor according to the fourth embodiment has a part of the same structure as the vertical capacitively coupled gate controlled junction field effect transistor according to the second embodiment. The main difference between the vertical capacitively coupled gate controlled junction field effect transistor according to the fourth embodiment and the vertical capacitively coupled gate controlled junction field effect transistor according to the second embodiment is that, as shown in FIG. 3-4, a first doping type channel 26 is formed by ion implantation at a position located between the two bottom gates 3 of the substrate. In this case,

[0074] As shown in FIG. 3-4, the JFET region 1 is specifically formed by a top gate 8 of a second doping type, a channel 5 of a first doping type, and a bottom gate 3 of a second doping type.

[0075] Specifically, the JFET region 2 is formed by two bottom gates 3 and a channel 2 6 .

[0076] The top gate 8 in the JFET region is indirectly controlled by a coupling capacitance upper electrode 10 across a dielectric layer 9 .

[0077] The first doping type channel 15 and the first doping type channel 26 together function as a channel region.

[0078] The portion located between the top gate 8 and the bottom gate 3 forms a channel 15 of a first doping type, and the portion located between the bottom gates 3 forms a channel 26 of a first doping type.

[0079] As shown in Figures 3-4, the first doping type substrate, the first doping type channel 26, and the first doping type channel 15 form internal conduction paths located within the substrate from the drain electrode to the two source electrodes, all of which are away from the low mobility regions at the surface of the device.

[0080] Specifically, a first doping type substrate, a first doping type channel 2 6, and a first doping type channel 1 5 are connected in sequence. Current is transmitted from the drain electrode 13, flows through the first doping type substrate and the first doping type channel 2 6, flows into the two left and right source regions 7 in the first doping type channel 1 5, and is finally collected by the two left and right source electrodes 12.

[0081] The lower portion of the first doping type substrate, the first doping type channel 26, and the first doping type channel 15 form an internal conduction path located within the substrate from the drain electrode to the source electrode. Control of the internal conduction path realizes on / off control of the entire vertical capacitively coupled gate-controlled junction field effect transistor. Control of the internal conduction path is realized by control of channel 15.

[0082] The vertical capacitively coupled gate-controlled junction field-effect transistor according to the present invention has an internal conduction path entirely located within the vertical capacitively coupled gate-controlled junction field-effect transistor, and all of the internal conduction paths are located away from the low-mobility region at the device surface. That is, all of the internal conduction paths are located away from the semiconductor material surface and are internally conductive, thereby avoiding the problem of low surface mobility. This allows carriers to maintain high mobility and fast drift velocity, resulting in a large saturation current Idsat and a small on-resistance Rsp of the vertical capacitively coupled gate-controlled junction field-effect transistor, providing excellent performance.

[0083] As shown in FIG. 3-4, the substrate is a first doping type starting substrate 1 having the drain electrode 13 provided on the underside thereof; and an epitaxial layer 2 of a first doping type, in which the bottom gate 3, channel 2 6, channel 1 5, top gate 8, source region 7, and ohmic contact region 4 of a second doping type are formed.

[0084] Specifically, the starting substrate 1 of the first doping type is heavily doped and has a high doping concentration, and serves as the drain region of a vertical capacitively coupled gate-controlled junction field effect transistor.

[0085] Specifically, since the doping concentrations of the first doping type channel-1 5 and the first doping type channel-2 6 are higher than the doping concentration of the epitaxial layer 2, the resistance between the first doping type channel-1 5 and the first doping type channel-2 6 is reduced, which in turn reduces the on-resistance Rsp of the vertical capacitively coupled gate-controlled junction field effect transistor, thereby improving the performance of the vertical capacitively coupled gate-controlled junction field effect transistor.

[0086] It should be noted that the vertical capacitively coupled gate-controlled junction field effect transistors according to Examples 1 to 4 can all be implemented as both normally-off devices and normally-on devices.

[0087] In order to implement the vertical capacitively coupled gate-controlled junction field effect transistors according to Examples 1 to 4 as normally-off devices, By controlling the doping of the second doping type bottom gate 3, the first doping type channel 1 5, the first doping type channel 2 6, and the second doping type top gate 8, when the voltage of the coupling capacitor upper electrode 10 is zero, the region sandwiched between the bottom gate 3 and the top gate 8 is in a depletion state, and the field effect transistor is a normally-off device. Here, the doping positions and doping concentrations of the bottom gate 3 and the top gate 8 are mainly adjusted, and they play a secondary role to the doping positions and doping concentrations of the first doping type channel 1 5 and the first doping type channel 2 6.

[0088] Also, if either or both of the first doping type channel 15 and the first doping type channel 26 are absent, the vertical capacitively coupled gate-controlled junction field effect transistor can be implemented as a normally-off device by adjusting the doping positions and doping concentrations of the bottom gate 3 and the top gate 8.

[0089] If the vertical capacitively coupled gate-controlled junction field-effect transistor is a normally-off device, The first doping type is N-type doping and the second doping type is P-type doping; When no voltage is applied to the vertical capacitively coupled gate controlled junction field effect transistor, the vertical capacitively coupled gate controlled junction field effect transistor is turned off.

[0090] When a positive voltage is applied to the vertical capacitively coupled gate controlled junction field effect transistor, the vertical capacitively coupled gate controlled junction field effect transistor turns on.

[0091] The first doping type is P-type doping and the second doping type is N-type doping; When no voltage is applied to the vertical capacitively coupled gate controlled junction field effect transistor, the vertical capacitively coupled gate controlled junction field effect transistor is turned off.

[0092] When a negative voltage is applied to the vertical capacitively coupled gate controlled junction field effect transistor, the vertical capacitively coupled gate controlled junction field effect transistor turns on.

[0093] To implement a vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application as a normally-on device, By controlling the doping of the second doping type bottom gate 3, the first doping type channel 15, the first doping type channel 26, and the second doping type top gate 8, when the voltage of the coupling capacitance upper electrode 10 is zero, the channel 15 sandwiched between the bottom gate 3 and the top gate 8 is in a conducting state, and the vertical capacitively coupled gate-controlled junction field effect transistor is a normally-on device. Here, the doping positions and doping concentrations of the bottom gate 3 and the top gate 8 are mainly adjusted, and they play a secondary role to the doping positions and doping concentrations of the first doping type channel 15 and the first doping type channel 26.

[0094] In addition, if either or both of the first doping type channel 15 and the first doping type channel 26 are absent, the vertical capacitively coupled gate-controlled junction field effect transistor can also be implemented as a normally-on device by adjusting the doping positions and doping concentrations of the bottom gate 3 and the top gate 8.

[0095] If the vertical capacitively coupled gate-controlled junction field-effect transistor is a normally-on device, The first doping type is N-type doping and the second doping type is P-type doping; When no voltage is applied to the vertical capacitively coupled gate-controlled junction field effect transistor, the vertical capacitively coupled gate-controlled junction field effect transistor is turned on.

[0096] When a negative voltage is applied to the vertical capacitively coupled gate controlled junction field effect transistor, the vertical capacitively coupled gate controlled junction field effect transistor is turned off.

[0097] The first doping type is P-type doping and the second doping type is N-type doping; When no voltage is applied to the vertical capacitively coupled gate-controlled junction field effect transistor, the vertical capacitively coupled gate-controlled junction field effect transistor is turned on.

[0098] When a positive voltage is applied to the vertical capacitively coupled gate controlled junction field effect transistor, the vertical capacitively coupled gate controlled junction field effect transistor is turned off.

[0099] The vertical capacitively coupled gate-controlled junction field effect transistors according to Examples 1 to 4 of the present application had a threshold voltage of 3.03 V, a breakdown voltage of 1507 V, and an on-resistance of 0.192 Ω mm 2 is.

[0100] In the vertical capacitively coupled gate-controlled junction field effect transistors according to Examples 1 to 4, all of the conduction channels are located inside the device, and are less susceptible to the effects of interface charges and low interface mobility of the device.

[0101] Compared with conventional silicon carbide-based VDMOS, the on-resistance is improved by 20%. Due to the capacitive coupling effect of the channel, the current of the present invention saturates under high gate voltage, improving the short-circuit resistance of the device. The gate electrode of the present vertical capacitively coupled gate-controlled junction field-effect transistor is a capacitively coupled gate, which operates using the capacitive coupling principle to control the device operation. The requirement for the capacitance electrode work function is low, allowing for flexible use of the coupling capacitance dielectric. The typical electric field strength in the dielectric layer at device breakdown is approximately 2×10 5 V / cm, approximately an order of magnitude lower than conventional silicon carbide devices, with lower quality requirements for the capacitive coupling dielectric and clearly higher reliability, robustness, and manufacturing advantages.

[0102] Hereinafter, an example will be described in which the first doping type is N-type and the second doping type is P-type.

[0103] The P+ type top gate 8, the N type channel 5, and the P type bottom gate 3 form a JFET region, the P+ type top gate 8 and the N type channel 5 form a PN junction, and the P type bottom gate 3 and the N type channel 5 form a PN junction. By controlling the voltage of the coupling capacitance upper electrode 10, the channel 5 is depleted and pinched off, which in turn controls the internal conduction path, and finally controls the on / off of the vertical capacitively coupled gate-controlled junction field effect transistor.

[0104] In the CN1238904C JFET element, the gate electrode and channel have a pn junction structure, so a voltage of 3 V or more cannot be applied to the gate electrode. When SiC is used as the starting substrate material, applying a voltage of 3 V or more to the gate electrode causes conduction between the gate electrode and the channel or source electrode, and the large conduction current affects the current characteristics between the drain electrode and the source electrode, making it impossible to apply a high voltage to the gate electrode, limiting its application as a power switch.

[0105] Next, an example will be described in which the first doping type is N-type and the second doping type is P-type.

[0106] In the vertical capacitively coupled gate-controlled junction field-effect transistor (JFET) region according to the present embodiment, the depletion regions formed by the self-formed electric field between the P+ type top gate 8 and the N type channel 5 and the depletion region formed by the self-formed electric field between the P type bottom gate 3 and the N type channel 5 are connected to each other, thereby realizing self-depletion and pinch-off of the N type channel 5 and realizing a normally-off function of the device. That is, when no voltage is applied to the coupling capacitance upper electrode 10, the connection between the drain electrode and the source electrode is off, and when a voltage is applied to the coupling capacitance upper electrode 10, the channel between the drain electrode and the source electrode is opened.

[0107] The CN1238904C JFET element is a normally-on device, meaning that the device is on when no voltage is applied to the gate electrode, and the device can only be turned off by applying a negative voltage to the gate electrode, which limits its application as a power switch.

[0108] <Example 5> A method for manufacturing a vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application includes the steps of: providing a substrate of a first doping type; forming two laterally spaced bottom gates 3 of a second doping type formed in the substrate; forming a top gate 8 of a second doping type formed in the substrate, the top gate 8 being located above a space between two of the bottom gates and having a space between the top gate 8 and the bottom gate 3; forming a dielectric layer 9 formed on the substrate and positioned above the top gate 8; forming a coupling capacitance upper electrode 10 formed on the dielectric layer 9; forming two source regions 7 of a first doping type located respectively on the two bottom gates, the two source regions 7 being connected to portions of the substrate located between the top gate 8 and the bottom gate 3; forming two source electrodes 12 connected to the source regions 7 on the same side.

[0109] In practice, the manufacturing method comprises: The method further includes forming a first doping type channel 5 formed in a portion between the top gate 8 and the bottom gate 3, with the top gate 8 positioned above the channel 5.

[0110] In practice, the manufacturing method comprises: The method further includes the step of forming a channel 26 of a first doping type between the two bottom gates by ion implantation.

[0111] In practice, the dielectric layer is a dielectric layer of a high dielectric constant material, and the coupling capacitance upper electrode 10 is a polysilicon electrode or a metal electrode.

[0112] In one embodiment, a method for fabricating a vertical capacitively coupled gate-controlled junction field effect transistor includes: providing a drain electrode 13 on the underside of the substrate; forming two source regions 7 of a first doping type located respectively on the two bottom gates, the two source regions 7 being connected to portions of the substrate located between the top gate 8 and the bottom gate 3; and forming two second doping type ohmic contact regions 4 on both sides of the two bottom gates 3, respectively, where the second doping type ohmic contact region 4 on the same side is connected to the bottom gate 3; The source electrode is located on the boundary between the source region 7 and the second doping type ohmic contact region 4 on the same side, and the source electrode connects the source region 7 and the second doping type ohmic contact region 4 on the same side.

[0113] Next, a method for manufacturing a vertical capacitively coupled gate-controlled junction field effect transistor according to an embodiment of the present application will be described, taking the case where the first doping type is N-type and the second doping type is P-type as an example, including the following steps.

[0114] Referring to FIG. 4, a SiC N+ type starting substrate 1 is adopted as the starting substrate structure for the vertical capacitively coupled gate-controlled junction field effect transistor according to the embodiment of the present application. This low-resistance starting substrate structure is used as a support structure, and an N-type epitaxial layer 2 is formed thereon by epitaxial growth. The epitaxial layer 2 serves as a drift region for device breakdown voltage and as a main region for forming the device.

[0115] Referring to FIG. 5, based on the structure formed in FIG. 4, a P-type bottom gate 3 and a P+ type ohmic contact region 4 are formed by ion implantation, and two parts of the P-type bottom gate 3 are implanted with an appropriate distance between them, and then used to form an N-type channel 26 by implantation. This device has a semi-symmetrical structure and is one complete cell, while the actual device is composed of an array of multiple similar cells.

[0116] Referring to Figure 6, based on the structure formed in Figure 5, N-type channel 1 5, N-type channel 2 6, and N+ type ohmic contact region 7 are formed by ion implantation, and a conductive path from the drain electrode to the source electrode, i.e., N+ type starting substrate 1, N-type epitaxial layer 2, N-type channel 2 6, N-type channel 1 5, and N+ type ohmic contact region 7, is formed, and current flows from the drain electrode 13 and is collected by two source electrodes 12 on the left and right.

[0117] 7, based on the structure formed in FIG. 6, a P+ type top gate 8 is formed by ion implantation. The P+ type top gate, N type channel 5, and P type bottom gate 3 form the JFET region.

[0118] Referring to FIG. 8, based on the structure formed in FIG. 7, a dielectric layer 9 is formed by chemical vapor deposition, and a coupling capacitance upper electrode 10 is deposited above the dielectric layer 9.

[0119] 9, based on the structure formed in FIG. 8, a metal silicide for the device surface source electrode 12 is formed by deposition, thermal reaction, and etching, forming a deposition with good ohmic contact with the device. Then, through subsequent processes, a passivation layer is deposited, a through-hole is etched, surface metal is formed, etc., and the device coupling capacitance upper electrode and source electrode are brought to the surface, completing the surface process and structure of the device.

[0120] Referring to Figure 10, based on the structure formed in Figure 9, after the front surface processing of the device is completed, the entire back surface of the wafer is ground and thinned, and the back surface is metallized to create the back surface drain electrode 13 of the device, forming the entire vertical device structure.

[0121] The operating principle of the vertical capacitively coupled gate-controlled junction field effect transistor of the present invention will be explained in detail below.

[0122] The equivalent circuit diagram of the vertical capacitively coupled gate-controlled junction field-effect transistor of Example 4 (corresponding to Figure 3-4) has a structure in which a capacitance and a gate electrode of the junction field-effect transistor are connected in series, as shown in Figure 11, and the capacitance in this circuit diagram is coupled together with the semiconductor junction capacitance of the JFET to divide the voltage and control the on / off of the junction field-effect transistor.

[0123] When the vertical capacitively coupled gate-controlled junction field effect transistor of the present invention is operated, a voltage is applied to the coupling capacitance upper electrode 10 and the drain electrode 13, and the voltage applied to the coupling capacitance upper electrode 10 is coupled to the top gate 8 through the coupling capacitance upper electrode 10 and the dielectric layer 9. The potential coupled to the top gate 8 and the bottom gate 3 connected to the source electrode form the control channel region of the JFET device, controlling the on / off of the intermediate channel.

[0124] When the applied voltage turns the channel off, the JFET region (including JFET region 1 and JFET region 2) is in the off state, and channel 1 5 and channel 2 6 are in a depleted state, where the number of carriers in the channel is relatively low. If further voltage is applied to drain electrode 13 at this time, the channel of the device is depleted and in the off state, and no or very little current flows between drain electrode 13 and source electrode 12.

[0125] When the channel is turned on by the applied voltage, the JFET region (including JFET region 1 and JFET region 2) becomes conductive, channel 1 5 and channel 2 6 become conductive, and the drain electrode and source electrode are connected. At this time, if further voltage is applied to drain electrode 13, the channel of the device becomes conductive and is in the on state, so current flows from drain electrode 13 to source electrode 12, and the device operates.

[0126] The vertical capacitively coupled gate-controlled junction field-effect transistor of this application is a device that utilizes the characteristics of SiC wide bandgap semiconductors to modulate the FET channel current.

[0127] In the prior art, there are three common approaches to modulating the channel: the first is the inversion layer used in conventional Si MOSFETs, which, combined with high-quality silicon dioxide grown by thermal oxygen growth, is more suitable for silicon materials and allows for large-scale production and application.

[0128] The second approach is the GaAs / AlGaAs or GaN / AlGaN heterojunction FET, or HFET for short. This device structure is difficult to fabricate as an enhancement type, and currently this is solved by using methods such as a buried gate structure and fluorine ion implantation.

[0129] The third approach is the JFET principle. Because the bandgap width of silicon is only 1.1 eV, silicon-based JFET devices can only be fabricated as normally-on devices. The device in this application combines the wide bandgap characteristics of SiC material to utilize the high built-in voltage created by the wide bandgap of SiC to control the channel current, achieving a normally-off function for the device (threshold voltage not exceeding 1 V, operating voltage not exceeding 3 V). Combined with the capacitively coupled gate structure, the threshold voltage can reach 3 V or more and the operating voltage can reach 15 V or more, fully matching the performance of existing SiC MOSFETs.

[0130] The threshold voltage of the present vertical capacitively coupled gate-controlled junction field-effect transistor can be modulated by doping. When the JFET region forms a self-pinch-off state through doping control, the built-in electric field caused by the doping itself can deplete carriers in Channel 15 and Channel 26, forming a depleted region, when no voltage is applied to the device gate. In this case, the device is a normally-off device, and the depleted region can be eliminated by applying a positive voltage to the JFET region (including JFET Region 1 and JFET Region 2), forming an effective channel and enabling conduction. Due to the wide bandgap properties of silicon carbide, the built-in potential of the pn junction formed in the silicon carbide material is large, enabling a normally-off device structure.

[0131] When the JFET region (including JFET region 1 and JFET region 2) does not form a self-pinch-off, the device itself has a channel and is a normally-on device. According to the working principle of the JFET, a corresponding voltage needs to be applied to the control region of the JFET, which will cause the channel to form a depletion region and turn the device off.

[0132] The on-resistance Rsp of the vertical capacitively coupled gate-controlled junction field-effect transistor device of the present application is determined mainly by the resistance R1 of JFET region 1, the resistance R2 of JFET region 2, and the resistance R3 of epitaxial layer 2. The voltage applied to the drain electrode 13 of the device is divided by the three resistors connected in series, reducing the resistance of each region and optimizing the on-resistance Rsp of the entire device.

[0133] The advantages of the vertical capacitively coupled gate-controlled junction field effect transistor device of the present invention will be described below.

[0134] The gate of the vertical capacitively coupled gate-controlled junction field effect transistor of the present invention employs a capacitance-coupled method, and has the following advantages over conventional wide bandgap metal oxide semiconductor field effect transistors.

[0135] Fig. 12 is a schematic diagram showing a current path when the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention is conductive. Fig. 13 is a schematic diagram comparing the characteristics of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention with those of a device based on conventional VDMOS technology.

[0136] As shown in Figure 12, the solid line with arrows indicates the current path when the field-effect transistor is conductive. As shown in Figure 12, when the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention is conductive, the current path is within the device and away from the surface of the semiconductor material, so it is not affected by the low interface mobility of the material. The performance of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention is primarily affected by the thickness of the capacitive dielectric, and the work function requirement of the electrode is low. For example, if the coupling capacitance upper electrode 10 is made of polysilicon material, either N-type polysilicon or P-type polysilicon can play the role of capacitive coupling. Capacitive dielectrics such as conventional oxide materials and high-K dielectrics can also be flexibly used, and either can play the role of capacitive coupling.

[0137] Figure 13 is a schematic diagram comparing the characteristics of the present vertical capacitively coupled gate-controlled junction field-effect transistor and a conventional VDMOS technology device. As shown in Figure 13, when the active region area is the same, the on-resistance of the present vertical capacitively coupled gate-controlled junction field-effect transistor is smaller, clearly demonstrating the superiority of the on-resistance Rsp.

[0138] FIG. 14-1 is a schematic diagram showing a vertical capacitively coupled gate-controlled junction field effect transistor of the present invention.

[0139] 14-2 is a diagram showing the vertical internal electric field distribution at breakdown in the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention, where the vertical axis represents the electric field strength and the horizontal axis represents the vertical position.

[0140] Here, in Figure 14-1, the vertical dashed lines represent the vertical direction, and the portion of the vertical dashed lines below the horizontal dashed lines corresponds to the portion to the right of coordinate 0 on the horizontal axis in Figure 14-2, and the portion of the vertical dashed lines above the horizontal dashed lines corresponds to the portion to the left of coordinate 0 on the horizontal axis in Figure 14-2.

[0141] As shown in Figure 14-1, the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention operates using the capacitive coupling principle. Therefore, the dielectric acts as an insulating layer. When a voltage is applied to the gate of the device, the potential is coupled to the top gate 8. However, due to the physical floating of the top gate 8, current does not flow through the dielectric layer 9 to the top gate 8, which is the main control region of the JFET region of the device. As shown in Figure 12, since the current conduction path of the device does not pass through the top gate 8, no large current is generated in the top gate 8, resulting in relatively high reliability. As shown in Figure 14-2, under high drain voltages (breakdown conditions) when the device is turned off, the vertical epitaxial layer-JFET region (JFET region 1 and JFET region 2)-top gate-dielectric layer becomes the main breakdown voltage region. Due to the semiconductor pn junction structure of the JFET region (JFET region 1 and JFET region 2)-top gate, fixed negative charges exist in the depletion region within the top gate, and electric field lines originate from the positive charges in the epitaxial layer and terminate at the negative charges in the top gate. Therefore, the high electric field is shielded at the junction interface of the semiconductor junction. The electric field strength in the dielectric layer is reduced by the shielding effect of the top gate, and the typical electric field strength in the dielectric layer is about 2 × 10 5 V / cm (electric field strength in the dielectric layer at the position indicated by the circle in Figure 14-2), which is an order of magnitude lower than the electric field strength in the dielectric layer of a conventional silicon carbide VDMOS device. The electric field strength in the low-k dielectric layer plays an important role in protecting the dielectric layer and improving reliability.

[0142] FIG. 15-1 is a schematic diagram showing a vertical capacitively coupled gate-controlled junction field effect transistor of the present invention.

[0143] 15-2 shows the potential distribution of the gate structure of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention. As shown in FIG. 15-2, the vertical axis represents the potential distribution, and the horizontal axis represents the vertical position.

[0144] Here, in Figure 15-1, the vertical dashed lines represent the vertical direction, and in Figure 15-2, the portion of the vertical dashed lines below the horizontal dashed lines corresponds to the portion to the right of coordinate 0 on the horizontal axis of Figure 15-2, and the portion of the vertical dashed lines above the horizontal dashed lines in Figure 15-2 corresponds to the portion to the left of coordinate 0 on the horizontal axis of Figure 15-2.

[0145] In our working device, the current saturates at high gate voltages due to capacitive coupling effects in the channel.

[0146] The gate voltage division principle of the device of the present invention is as shown in FIG. 15-2, where a dielectric layer capacitance C ゲート and the junction capacitance C formed by the semiconductor depletion region formed by the top gate 8 and the channel 5. 半導体 The two capacitances, and , are connected in series to divide the voltage and control the channel on / off. When the external gate voltage is Vgs, the dielectric capacitance C ゲート The voltage distributed to 半導体 / (C ゲート +C 半導体 ) and the junction capacitance of the semiconductor depletion region, C 半導体 The voltage distributed to ゲート / (C ゲート +C 半導体 ) The dielectric layer capacitance C ゲート is determined as a fixed value depending on the material and thickness of the dielectric layer 9, and when Vgs increases from 0, C ゲート and the junction capacitance C of the depletion region formed by the self-generated electric field of the semiconductor 半導体 and divide the voltage, and a part of the voltage Vgs applied to the coupling capacitance upper electrode 10 is coupled to the semiconductor junction. At this time, the junction capacitance C 半導体 Percentage of voltage coupled into C ゲート / (Cゲート +C 半導体 ) is maximized. The increase in gate voltage Vgs and the junction capacitance C of the semiconductor depletion region 半導体 As the voltage coupled to the semiconductor junction capacitance C 半導体 The depletion region of the 半導体 becomes larger, and the junction capacitance C of the semiconductor depletion region 半導体 Percentage of voltage coupled to C ゲート / (C ゲート +C 半導体 ) gradually becomes smaller. When the depletion region of the semiconductor narrows to a certain extent, the area close to the semiconductor junction interface cannot narrow any further, and the junction capacitance C 半導体 rises to and remains at a relatively large value, after which there is no further rise, at which point the voltage Vgs applied to the coupling capacitance upper electrode 10, the potential coupled to the top gate 8, is at a maximum and the device is saturated.

[0147] 16-1, 16-2, 16-3, 16-4, 16-5, and 16-6 are diagrams showing energy band distributions when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present application, where the vertical axis represents the potential distribution and the horizontal axis represents the vertical position.

[0148] Here, in Figure 15-1, the vertical dashed lines represent the vertical direction, and the portion of the vertical dashed lines below the horizontal dashed lines in Figure 15-1 corresponds to the portion to the right of coordinate 0 on the horizontal axis in Figures 16-1, 16-2, 16-3, 16-4, 16-5, and 16-6, and the portion of the vertical dashed lines above the horizontal dashed lines in Figure 15-1 corresponds to the portion to the left of coordinate 0 on the horizontal axis in Figures 16-1, 16-2, 16-3, 16-4, 16-5, and 16-6.

[0149] As shown in Figures 16-1, 16-2, 16-3, 16-4, 16-5, and 16-6, the energy band distributions in the top gate 8, channel 5, and bottom gate 3 of the present vertical capacitively coupled gate-controlled junction field-effect transistor show the relative changes in the conduction band, valence band, and Fermi levels of electrons and holes in each region when the gates of the device are activated. As shown in Figure 16-1, when the voltage Vgs applied to the coupling capacitor upper electrode 10 is 0 V, taking the self-depleted channel 5 as an example, the Fermi level of channel 5 is located at the center of the band gap, the device is in a self-depleted state, and the concentrations of both electrons and holes in channel 5 are very low. The Fermi levels in the top gate 8 and bottom gate 3 are located near the valence band, with a very high concentration of holes and a very low concentration of electrons. As the voltage Vgs applied to the gate 11 increases, the distance between the conduction band and the Fermi level in the top gate 8 and the channel 5 gradually decreases, resulting in a low concentration of electrons in the top gate 8. The conduction band in the channel 5 is close to the Fermi level, and the electron concentration in the channel 5 is very high, participating in conduction and forming a conductive channel. Also, the distance between the valence band and the Fermi level in the channel 5 gradually decreases, resulting in a low concentration of holes in the channel 5.

[0150] FIG. 17-1 shows the carrier concentration distribution in each region of the top gate 8, channel 5, and bottom gate 3 of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention when the hole concentration is affected by the voltage applied to the gate 11 and the device is operating. The vertical axis represents the hole concentration, and the horizontal axis represents the vertical position. FIG. 17-2 shows the carrier concentration distribution in each region of the top gate 8, channel 5, and bottom gate 3 of the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention when the hole concentration is affected by the voltage applied to the gate 11 and the device is operating. The vertical axis represents the hole concentration, and the horizontal axis represents the vertical position. As shown in FIGS. 17-1 and 17-2, when the voltage Vgs applied to the gate 11 is 0 V, the hole concentration in the top gate 8 is extremely high and the electron concentration is extremely low. When the channel 5 is modulated to a self-depleted state by doping, both the electron and hole concentrations are extremely low. As the voltage Vgs applied to the gate 11 increases, due to capacitive coupling, the voltage drop across both the capacitor coupled to the dielectric layer 9 and the semiconductor junction capacitor formed by the top gate 8 and the channel 5 increases. As the voltage across the semiconductor junction formed by the top gate 8 and the channel 5 increases, the depletion region in the channel 5 narrows, and the depletion state becomes non-depleted. This causes the electron concentration in the channel 5 to increase rapidly, forming a conductive channel. Furthermore, the built-in potential at the semiconductor junction formed by the top gate 8 and the channel 5 decreases, causing some of the electrons in the channel 5 to move into the top gate 8, causing the electron concentration in the top gate 8 to change from an extremely low concentration to a low electron concentration. At the same time, some of the holes in the top gate 8 move into the channel 5, causing the hole concentration at the semiconductor junction between the top gate 8 and the channel 5 to increase.

[0151] Figure 18-1 shows the transfer characteristic curve of the present vertical capacitively coupled gate-controlled junction field-effect transistor. As shown in Figure 18-1, the transfer characteristic of the present vertical capacitively coupled gate-controlled junction field-effect transistor is calculated based on the principle of transfer characteristics when voltages are applied to both the gate and drain electrodes. Here, the horizontal axis of the coordinate system represents the gate voltage, and the vertical axis represents the drain current. When the gate voltage is low, the device's off-state current is small. As the gate voltage increases, the drain current increases. When the gate voltage increases significantly, the semiconductor junction capacitance remains stable and the device saturates. Figure 18-2 shows the transfer characteristic curve of an existing SiC MOSFET device, with the vertical axis representing the drain current and the horizontal axis representing the gate voltage. Current SiC MOSFET devices still do not exhibit current saturation even at a Vgs of 20 V. Furthermore, in the present device, the current path is farther from the dielectric surface, thereby improving the device's short-circuit resistance. In Figure 18-1, the gate voltage remains nearly stable when the gate voltage reaches 6 V. In Fig. 18-2, the gate voltage rises rapidly even after 15 V. Therefore, the vertical capacitively coupled gate-controlled junction field-effect transistor of the present invention is highly stable.

[0152] The present vertical capacitively coupled gate-controlled junction field effect transistor clearly has high reliability, high robustness, and manufacturing advantages.

[0153] In describing the present application and its embodiments, it should be understood that the orientations or positional relationships indicated by the terms "top," "bottom," "height," etc. are based on the orientations or positional relationships shown in the drawings, are merely for the purpose of facilitating and simplifying the description of the present application, and do not indicate or imply that the referred-to devices or elements must have a particular orientation, be constructed, or operate in a particular orientation, and therefore cannot be understood as limiting the present application.

[0154] In the present application and its examples, unless otherwise clearly specified or limited, the terms "provide," "attach," "couple," "connect," "fixed," etc. should be understood in a broad sense, and may refer to, for example, a fixed connection, a detachable connection, or an integral one, a mechanical connection, an electrical connection, a communication, a direct connection, an indirect connection via an intermediate medium, an internal communication between two elements, or an interactive relationship between two elements. Those skilled in the art can understand the specific meanings of the above terms in this specification according to specific circumstances.

[0155] In this application and its examples, unless otherwise clearly specified or limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact or that the first and second features are in indirect contact via an intermediate medium. Furthermore, a first feature being "above," "above," and "on the upper surface" of a second feature may mean that the first feature is directly above or diagonally above the second feature, or simply that the horizontal height of the first feature is higher than that of the second feature. A first feature being "below," "below," and "on the lower surface" of a second feature may mean that the first feature is directly below or diagonally below the second feature, or simply that the horizontal height of the first feature is lower than that of the second feature.

[0156] The above disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, specific example components and configurations have been described above. Of course, these are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and / or characters in different examples for purposes of brevity and clarity, and as such, does not indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, while the present application describes examples of various specific processes and materials, those skilled in the art may envision the application of other processes and / or the use of other materials.

[0157] Although preferred embodiments of the present application have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once they have learned the basic creative concepts. Therefore, it is intended that the appended claims be interpreted as including all changes and modifications that fall within the scope of the preferred embodiments and the present application.

[0158] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations. [Explanation of symbols]

[0159] 1. Starting substrate 2. Epitaxial layer 3 Bottom Gate 4. Second doping type ohmic contact region 5 Channels 6 Channel 2 7 Source Area 8 Top Gate 9 Dielectric Layer 10 Coupling capacitance upper electrode 12 Source electrode 13 Drain electrode 14 Metal silicide layer

Claims

1. a substrate of a first doping type; two laterally spaced bottom gates (3) of a second doping type formed in the substrate; a top gate (8) of a second doping type formed in the substrate, the top gate (8) being located above the space between the two bottom gates and having a space between the top gate (8) and the bottom gate (3); a dielectric layer (9) formed on the substrate and positioned above the top gate (8); a coupling capacitance upper electrode (10) formed on the dielectric layer (9), The top gate (8) is indirectly controlled by a coupling capacitance upper electrode (10) across a dielectric layer (9). A vertical capacitively coupled gate-controlled junction field effect transistor.

2. The top gate (8) is in a floating state, and the coupling capacitance upper electrode (10), the dielectric layer (9), and the top gate (8) together constitute a gate structure of a field effect transistor, and the second doping type top gate (8), the portion located between the top gate (8) and the bottom gate (3), and the bottom gate (3) form a JFET region 1, and the two bottom gates (3) and the portion located between the two bottom gates (3) form a JFET region 2, The top gate of the JFET region 1 is indirectly controlled by the coupling capacitance upper electrode (10) across the dielectric layer (9), so that the JFET region 1 and the JFET region 2 are indirectly controlled by the coupling capacitance upper electrode (10) across the dielectric layer (9).

2. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 1.

3. The field effect transistor is The semiconductor device further comprises a channel (5) of a first doping type formed in a portion between the top gate (8) and the bottom gate (3), the top gate (8) being located above the channel (5); Here, the JFET region 1 is specifically formed by a top gate (8) of a second doping type, a channel (5) of a first doping type, and a bottom gate (3).

3. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 2.

4. Further comprising a channel (6) of a first doping type formed between the two bottom gates, Here, the JFET region 1 is specifically formed by a second doping type top gate (8), a portion of the substrate located between the top gate (8) and the bottom gate (3), and the bottom gate (3); Specifically, JFET region 2 is formed by two bottom gates (3) and channel 2 (6).

3. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 2.

5. a first doping type channel (5) formed by ion implantation in a portion between the top gate (8) and the bottom gate (3), the top gate (8) being located above the channel (5); a channel (6) of a first doping type formed between the two bottom gates by ion implantation; Here, the JFET region 1 is specifically formed by a top gate (8), a channel 1 (5), and a bottom gate (3), Specifically, JFET region 2 is formed by two bottom gates (3) and channel 2 (6).

3. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 2.

6. a drain electrode (13) provided on the lower surface of the substrate; two source regions (7) of a first doping type located respectively on the two bottom gates, the two source regions (7) being connected to a portion of the substrate located between the top gate (8) and the bottom gate (3); two source electrodes (12) connected to the source regions (7) on the same side; wherein the substrate of the first doping type, the portion below the gate structure and located between the bottom gates (3), and the portion below the gate structure and located between the top gate (8) and the bottom gate (3) form an internal conduction path within the substrate from the drain electrode to the two source electrodes; 6. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 1.

7. The device further includes two second doping type ohmic contact regions (4) provided on both sides of the two bottom gates (3), respectively, and the second doping type ohmic contact regions (4) on the same side are connected to the bottom gates (3); The source electrode is located on the boundary between the source region (7) on the same side and the ohmic contact region (4) of the second doping type, and the source electrode connects the source region (7) on the same side and the ohmic contact region (4) of the second doping type.

7. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 6.

8. By controlling the doping of the bottom gate (3) of the second doping type and the top gate (8) of the second doping type, when the voltage of the coupling capacitance upper electrode (10) is zero, the region sandwiched between the bottom gate (3) and the top gate (8) is in a depletion state, and the field effect transistor is a normally-off device; Alternatively, by controlling the doping of the second doping type bottom gate (3) and the second doping type top gate (8), when the voltage of the coupling capacitance upper electrode (10) is zero, the region sandwiched between the bottom gate (3) and the top gate (8) becomes conductive, and the field effect transistor is a normally-on device.

2. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 1.

9. The substrate is a starting substrate (1) of a first doping type on the underside of which the drain electrode (13) is provided; an epitaxial layer (2) of a first doping type, wherein the bottom gate (3), channel 2 (6), channel 1 (5), top gate (8), source region (7), and ohmic contact region (4) of a second doping type are formed in the epitaxial layer (2); The coupling capacitance upper electrode (10) is located above the top gate (8).

6. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 5.

10. the starting substrate is a silicon carbide starting substrate, a silicon starting substrate, a diamond starting substrate, or a potassium oxide starting substrate; the dielectric layer is a dielectric layer of a high dielectric constant material, The coupling capacitance upper electrode (10) is a polysilicon electrode or a metal electrode.

10. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 9.

11. Further comprising a metal silicide layer (14) formed between the top gate (8) and the dielectric layer (9).

2. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 1.

12. The doping concentration of the top gate (8) is 1×10 １６ cm －3 That's all.

2. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 1.

13. The doping concentration of the channel 1 (5) is greater than the doping concentration of the substrate; the doping concentration of the channel 2 (6) is greater than the doping concentration of the substrate; 6. The vertical capacitively coupled gate-controlled junction field effect transistor according to claim 5.

14. providing a substrate of a first doping type; forming two laterally spaced bottom gates (3) of a second doping type formed in said substrate; forming a top gate (8) of a second doping type formed in the substrate, the top gate (8) being located above a space between two of the bottom gates and having a space between the top gate (8) and the bottom gate (3); forming a dielectric layer (9) formed on the substrate and positioned above the top gate (8); forming a coupling capacitance upper electrode (10) formed on the dielectric layer (9); forming two source regions (7) of a first doping type located respectively on the two bottom gates, the two source regions (7) being connected to a portion of the substrate located between the top gate (8) and the bottom gate (3); forming two source electrodes (12) connected to the source regions (7) on the same side, Fabrication of a vertical capacitively coupled gate-controlled junction field effect transistor.

15. The method further includes forming a channel (5) of a first doping type formed in a portion between the top gate (8) and the bottom gate (3), the top gate (8) being located above the channel (5).

15. The method for manufacturing a vertical capacitively coupled gate-controlled junction field effect transistor according to claim 14.

16. forming a channel (6) of a first doping type between the two bottom gates by ion implantation; 16. The method for manufacturing a vertical capacitively coupled gate-controlled junction field effect transistor according to claim 15.

17. the dielectric layer is a dielectric layer of a high dielectric constant material, The coupling capacitance upper electrode (10) is a polysilicon electrode or a metal electrode.

17. A method for manufacturing a vertical capacitively coupled gate-controlled junction field effect transistor according to claim 14.

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