Multi-chip structure including memory die stacked on die having programmable integrated circuit

Abstract

To provide a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC) for reducing processing cost, power consumption and a die area used amount, and a method.SOLUTION: A multi-chip structure includes a package substrate 604, a first die 606, and a second die 702. The first die 606 includes a programmable IC, and the programmable IC includes a memory controller. The first die is on the package substrate 604 and attached to the package substrate 604. The second die 702 includes a memory 608. The second die 702 is stacked on the first die 606. The memory 608 is communicatively coupled to the memory controller.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to multi-chip structures and methods of forming such structures, and in particular to multi-chip structures that include one or more memory dies stacked on a die having programmable integrated circuits, and methods of forming such structures. [Background technology]

[0002] A programmable integrated circuit (IC) refers to a type of IC that contains programmable circuitry. One example of a programmable IC is a field-programmable gate array (FPGA). FPGAs are characterized by the inclusion of programmable circuit blocks. A circuit design may be physically implemented in the programmable circuitry of a programmable IC by loading configuration data, sometimes called a configuration bitstream, into the device. The configuration data may be loaded into the device's internal configuration memory cells. The collective state of the individual configuration memory cells determines the function of the programmable IC. For example, the specific tasks performed by the various programmable circuit blocks and the connections between the programmable circuit blocks of a programmable IC are determined by the collective state of the configuration memory cells loaded with the configuration data. Summary of the Invention

[0003] Some examples described herein provide multi-chip structures that include one or more memory dies stacked on a die having a programmable integrated circuit (IC). Some examples described herein can eliminate the need for an interposer and / or a physical layer (PHY) interface, which can reduce processing costs, power consumption, and / or die area usage.

[0004] One example is a multi-chip structure. The multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable integrated circuit, which includes a memory controller. The first die is on and attached to the package substrate. The second die includes a memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

[0005] Another example is a method of forming a multi-chip structure. A first die is stacked on a second die. The first die includes a memory. The second die includes a programmable integrated circuit, which includes a memory controller. The memory controller is communicatively coupled to the memory by the first die stacked on the second die. The first die is attached to a package substrate.

[0006] A further example is a multi-chip structure. The multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a field programmable gate array (FPGA) and a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on a side of the first die opposite the package substrate. The memory is communicatively coupled to the memory controller.

[0007] These and other aspects can be understood with reference to the following detailed description.

[0008] For a detailed understanding of the above-listed features, which have been briefly summarized above, a more particular description can be provided with reference to exemplary implementations, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical exemplary implementations and therefore should not be considered limiting of the scope thereof. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram illustrating a programmable integrated circuit (IC) connected to an external memory, according to some examples. [Figure 2] 1 illustrates a field programmable gate array (FPGA) of a programmable IC according to some examples. [Figure 3] 1 is a schematic circuit diagram of a multi-chip structure according to some examples. [Figure 4] FIG. 1 is a schematic circuit diagram of another multi-chip structure, according to some examples. [Figure 5] FIG. 1 is a schematic circuit diagram of a further multi-chip structure, according to some examples. [Figure 6] 1 illustrates the configuration of a multi-chip structure on a printed circuit board (PCB) according to some examples. [Figure 7] 1 is another configuration of a multi-chip structure on a printed circuit board (PCB), according to some examples. [Figure 8] 1 is another configuration of a multi-chip structure on a printed circuit board (PCB), according to some examples. [Figure 9] 1 is a flowchart of a method for forming a multi-chip structure, according to some examples. DETAILED DESCRIPTION OF THE INVENTION

[0010] To facilitate understanding, identical elements common to the figures have been designated with the same reference numerals where possible, and it is anticipated that elements of one example may be beneficially incorporated into another example.

[0011] Some examples described herein provide multi-chip structures that include one or more memory dies stacked on a die having a programmable integrated circuit (IC). In some examples, these memory dies can implement memory for high-bandwidth memory (HBM). In some examples, the programmable IC includes a programmable logic region, such as the fabric of a field-programmable gate array (FPGA). The programmable IC enables user-configurable front-end processing of data read from or written to the memory of any of the memory dies.

[0012] Some examples described herein can eliminate the need for an interposer. By stacking the memory die on a base die containing the programmable IC, no interposer is implemented (which would otherwise require the base die and memory die stack to be individually attached to the interposer). By eliminating the need for an interposer, the costs associated with processing an interposer and including it in a multi-chip stack are also avoided. Furthermore, the absence of an interposer allows for the formation of a multi-chip stack with less processing, thereby reducing processing cycle time in addition to cost savings. Stacking the memory die on a base die without the need for an interposer can also result in a package with a smaller footprint and vertical profile.

[0013] Some examples described herein can eliminate the use of a physical layer (PHY) interface, such as an HBM interface, in a multi-chip structure. A physical layer interface can consume power and die area. By avoiding the use of a physical layer interface, such as an HBM interface, the physical layer interface can be avoided on two dies (e.g., on either side of an HBM physical layer connection), thereby reducing power and area usage on the two dies. Furthermore, reducing die area usage can reduce processing costs to form the dies.

[0014] Some examples can achieve additional benefits. For example, a composite device formed by a multi-chip structure can be more easily tested and, for example, can be more easily deployed in a multi-chip module with other packages and / or dies. Additionally, a multi-chip structure with programmable ICs described herein can enable customization of logic and functionality adjacent to one or more memory dies (e.g., adjacent to one or more HBM dies). Such a multi-chip structure can enable users to create, for example, custom deployable devices with high memory bandwidth and low power consumption in a single package. Furthermore, such a multi-chip structure can maintain programmability and programmability flexibility of the programmable logic region and boundary circuits, such as input / output circuits, transceiver circuits, and / or other circuits.

[0015] Various features will now be described with reference to the figures. Note that the figures may or may not be drawn to scale, and that elements of similar structure or function are represented by like reference numerals throughout the figures. Note that the figures are intended to facilitate the description of features only. The figures are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. Additionally, the illustrated examples need not have all aspects or advantages presented. An aspect or advantage described in connection with a particular example is not necessarily limited to that example, and may be practiced in any other example, even if not described as being practiced or explicitly described as being practiced. Furthermore, while methods described herein may be described in a particular order of operations, other methods according to other examples may be performed in various other orders, including more or fewer operations (e.g., including various sequential or parallel performances of various operations).

[0016] 1 is a block diagram illustrating a programmable integrated circuit (IC) 102 connected to external memory, according to some examples. The programmable IC 102 may be a system-on-chip (SoC) and may include or be an IC that is a programmable logic device, such as a field-programmable gate array (FPGA). The programmable IC 102 includes a processing system 104, a network-on-chip (NoC) 106, a configuration interconnect 108, one or more programmable logic regions 110a-110n (collectively, individually, or collectively, “programmable logic regions 110”), a memory controller 112, multi-gigabit transceivers (MGTs) 114, input / output blocks (IOs) 116, and other IP circuitry 118. The NoC 106 includes a routing network 120 and an NoC peripheral interconnect (NPI) 122.

[0017] Generally, the processing system 104 is connected to the programmable logic region 110 through the fabric interconnect 108. The processing system 104, the programmable logic region 110, the memory controller 112, the MGT 114, the IO 116, and the other IP circuits 118 are also connected to the NoC 106 (e.g., routing network 120) and therefore may be communicatively coupled to one another through the NoC 106 (e.g., routing network 120). The processing system 104, the memory controller 112, the MGT 114, the IO 116, and the other IP circuits 118 are also connected to respective subsets of the programmable logic region 110. For example, the processing system 104, the IO 116, and the other IP circuits 118 are each connected to the programmable logic region 110a, and the memory controller 112 and the MGT 114 are each connected to the programmable logic region 110n. Various circuits may be connected to any subset of programmable logic region 110, and circuits may be connected to a given subset of programmable logic region 110 in any combination with any other circuits. Additionally, in some examples, memory controller 112 may be connected to at least one of IOs 116.

[0018] The processing system 104 may include one or more processor cores. For example, the processing system 104 may include several ARM-based embedded processor cores.

[0019] Programmable logic region 110 may include any number of configurable logic blocks, look-up tables (LUTs), digital signal processing blocks, random access memory blocks, etc., as well as programmable interconnect elements as described below. Programmable logic region 110 may be programmed or configured using processing system 104 through configuration interconnect 108. For example, configuration interconnect 108 may enable frame-based programming of the fabric of programmable logic region 110 by, for example, a processor core of processing system 104 (e.g., a platform management controller (PMC)).

[0020] The routing network 120 of the NoC 106 provides routing of NoC packets between various systems or circuits. The routing network 120 includes NoC packet switches interconnected by line segments between NoC master units (NMUs) and NoC slave units (NSUs). Each NMU is an ingress circuit connecting a master circuit to the NoC 106. Each NSU is an egress circuit connecting the NoC 106 to a slave endpoint circuit. Each NoC packet switch performs NoC packet switching. Thus, the NMUs, NoC packet switches, and NSUs may be configured to provide channels for communication between the master endpoint circuits and the slave endpoint circuits via the NMUs, the NoC packet switches interconnected by line segments, and the NSUs. The NMUs, NoC packet switches, and NSUs also include register blocks that are written to configure the respective NMUs, NoC packet switches, and NSUs. The register blocks may be written through the NPI 122. For example, to write to register blocks to configure the NMUs, NoC packet switches, and NSUs, the PMCs of processing system 104 can send memory-mapped write requests to the NMUs, NoC packet switches, and NSUs through NPI 122. NPI 122 can include interconnect NPI switches that can distribute the memory-mapped write requests to the appropriate register blocks.

[0021] The IO 116 may be any input / output circuitry for communicatively coupling the programmable IC 102 with other circuits and / or systems. In some examples, the IO 116 may include a high-bandwidth memory (HBM) interface circuit, a high-density input / output (HDIO) circuit, a peripheral component interconnect express (PCIe) circuit, an extreme performance input / output (XPIO) circuit, and / or the like. The other IP circuitry 118 may be, for example, a digital clock manager, an analog-to-digital converter, system monitoring logic, and / or any circuitry for a given implementation. In some examples, at least some of the memory controller 112, the MGT 114, the IO 116, and / or the other IP circuitry 118 are configurable. For example, the memory controller 112, the MGT 114, the IO 116, and / or the other IP circuitry 118 may be configurable through the NPI 122 of the NoC 106.

[0022] In some examples, the programmable IC 102 includes an interface and control logic circuit 124. In other examples, the interface and control logic circuit 124 is on a separate IC from the programmable IC 102 (e.g., as shown by the dashed line). The interface and control logic circuit 124 is connected to an external memory 126. The external memory 126 may be, for example, memory in a single or multiple dies. In some examples, the external memory 126 is random access memory (RAM), such as dynamic RAM (DRAM), which may be implemented as high bandwidth memory (HBM).

[0023] In some examples, the interface and control logic circuit 124 is directly connected to the memory controller 112, while in other examples, the interface and control logic circuit 124 is communicatively coupled to the memory controller 112 through the IO 116 of the programmable IC 102 and the IO 128 of another IC (e.g., as shown by the dashed arrows in FIG. 1 ). In some examples where the programmable IC 102 includes the interface and control logic circuit 124, the memory controller 112 is directly connected to the interface and control logic circuit 124 (e.g., no intervening physical layer (PHY) interface), which in turn is connected to the external memory 126. In some examples where the interface and control logic circuit 124 is in an IC separate from the programmable IC 102, the memory controller 112 is directly connected to the interface and control logic circuit 124 (e.g., no intervening physical layer (PHY) interface), which in turn is connected to the external memory 126. In some examples where the interface and control logic circuit 124 is in an IC separate from the programmable IC 102, the memory controller 112 is directly connected to the IO 116 (e.g., an HBM interface), which is connected to the IO 128 (e.g., an HBM interface) of the separate IC connected to the interface and control logic circuit 124. The interface and control logic circuit 124 is then connected to the external memory 126. Thus, in these examples, the memory controller 112 is communicatively coupled to the external memory 126.

[0024] In some examples, as described in more detail below, the programmable IC 102, the interface and control logic circuitry 124 (if on separate ICs), and the external memory 126 may be included on stacked dies to form a multi-chip structure. Such a multi-chip structure may have a smaller package size and may be manufactured using reduced processing, which may increase yield and reduce manufacturing time for the multi-chip structure.

[0025] 2 illustrates a field programmable gate array (FPGA) of a programmable IC 200 that can be implemented as the programmable IC 102 of FIG. 1 according to some examples. The programmable IC 200 includes a number of different programmable tiles, including configurable logic blocks (CLBs) 202, random access memory blocks (BRAMs) 204, signal processing blocks (DSPs) 206, input / output blocks (IOBs) 208, configuration and clocking logic (CONFIG / CLOCKS) 210, specialized input / output blocks (I / Os) 212 (e.g., configuration ports and clock ports), and other programmable logic 214, such as a digital clock manager, system monitoring logic, etc. The programmable IC 200 may also include boundary circuits, such as MGTs 216, memory controllers (MCs) 218, interface and control logic circuits (INT / CNTLs) 220, and other IP circuits 222, such as PCIe interfaces, analog-to-digital converters (ADCs), etc. The boundary circuits may also be programmable.

[0026] In some FPGAs, as shown in the example included in FIG. 2 , each programmable tile may include at least one programmable interconnect element (INT) 230 with connections to input and output terminals 232 of programmable logic elements within the same tile. Each programmable interconnect element 230 may also include connections to interconnect segments 234 of adjacent programmable interconnect elements within the same tile or in other tiles. Each programmable interconnect element 230 may also include connections to interconnect segments 236 of general routing resources between logic blocks (not shown). The general routing resources may include routing channels between logic blocks (not shown) that comprise tracks of interconnect segments (e.g., interconnect segments 236) and switch blocks (not shown) that connect the interconnect segments. An interconnect segment (e.g., interconnect segment 236) of a general routing resource may span one or more logic blocks. Programmable interconnect elements 230, together with general routing resources, implement the programmable interconnect structure for the illustrated FPGA.

[0027] In one exemplary implementation, the CLB 202 may include configurable logic elements (CLEs) 240 that can be programmed to implement user logic, as well as a single programmable interconnect element 230. The BRAM 204 may include BRAM logic elements (BRLs) 242 in addition to one or more programmable interconnect elements 230. The number of programmable interconnect elements 230 included in a tile typically depends on the tile height. In the illustrated example, the BRAM 204 has the same height as five CLBs 202, although a different number (e.g., four) may be used. The signal processing block 206 may include a DSP logic element (DSPL) 244 in addition to any number of programmable interconnect elements 230. The IOB 208 may include, for example, two input / output logic elements (IOLs) 246 in addition to one programmable interconnect element 230. As will be apparent to those skilled in the art, for example, the actual I / O pads connected to input / output logic element 246 are typically not limited by the area of input / output logic element 246 .

[0028] In the illustrated example, a horizontal area near the center of the die is used for configuration and clocking logic (CONFIG / CLOCKS) 210, and possibly other control logic. Vertical columns 248 extending from this horizontal area or column are used to distribute clock and configuration signals across the entire width of the FPGA.

[0029] Some FPGAs utilizing the architecture shown in Figure 2 may include additional logic blocks that disrupt the regular column structure that makes up the majority of the FPGA. The additional logic blocks may be programmable blocks and / or dedicated logic.

[0030] It should be noted that Figure 2 is intended solely to illustrate an exemplary FPGA architecture. For example, the number of logic blocks in a row, the relative widths of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect / logic implementation included at the top of Figure 2 are merely examples. For example, in an actual FPGA, two or more adjacent CLB rows are typically included wherever a CLB appears to facilitate efficient implementation of user logic, although the number of adjacent CLB rows will vary depending on the overall size of the FPGA.

[0031] FIG. 3 is a schematic circuit diagram of a multi-chip structure according to some examples. The multi-chip structure of FIG. 3 includes a programmable IC 102 and a memory 302, where the memory 302 may be in multiple dies stacked on the die including the programmable IC 102. As simplified in FIG. 3, the programmable IC 102 includes a programmable logic region 110, a bus 304, a memory controller 112, and an interface and control logic circuit 124. The programmable logic region 110 (or other subsystems, such as the processing system 104 and / or NoC 106) is connected to the memory controller 112 through the bus 304, which may be, for example, an Advanced Extensible Interface (AXI) bus. The memory controller 112 is connected to the interface and control logic circuit 124.

[0032] Each of the memories 302 includes multiple memory slices 306. In some examples, each memory slice 306 may be 2 gigabytes (Gb) of memory or other size. Each of the memories 302 may implement DRAM and may further implement HBM. In some examples, each of the memories 302 may implement 32 Gb of HBM DRAM. The interface and control logic circuit 124 is connected to the memory slices 306 of the memory 302. The interface and control logic circuit 124 can decode read and write requests from the memory controller 112 and, in response, send native signals to the memory 302 to read from or write to the memory 302. There is no standard physical layer interface circuit between the memory controller 112 and the memory slices 306 of the memory 302 for packaging and unpackaging the read and write requests in a standard form. For example, if the memory 302 implements HBM, there is no HBM interface between the memory controller 112 and the memory slices 306.

[0033] Figure 4 is a schematic circuit diagram of another multi-chip structure, according to some examples. The multi-chip structure of Figure 4 is similar to the multi-chip structure of Figure 3, except that two die stacks containing memory 302 are stacked on top of the die containing programmable IC 102. To accommodate the additional die stacks containing memory 302, programmable IC 102 further includes an additional bus 304, memory controller 112, and interface and control logic circuit 124.

[0034] 3 and 4, the interface and control logic circuitry 124 is included on each die that includes the programmable IC 102. In other examples, a separate control die (separate from the die that includes the programmable IC 102) may include the interface and control logic circuitry 124 and may be located between the die that includes the programmable IC 102 and the die stack that includes the memory 302. The schematic circuit diagram for such an example would be the same as Figures 3 and 4, except for showing a separate control die.

[0035] FIG. 5 is a schematic circuit diagram of a further multi-chip structure according to some examples. The multi-chip structure of FIG. 5 implements an HBM interface (e.g., as a PHY interface) between a memory controller 112 and a memory slice 306. The multi-chip structure of FIG. 5 includes a programmable IC 102, a control IC 502, and a memory 302, where the control IC 502 is in a separate die stacked on the die including the programmable IC 102, and the memory 302 may be in multiple dies stacked on the die including the control IC 502. As simplified in FIG. 5 , the programmable IC 102 includes a programmable logic region 110, a bus 304, a memory controller 112, and an HBM interface (HBM PHY) 504. The programmable logic region 110 (or other subsystems such as the processing system 104 and / or NoC 106) is connected to the memory controller 112 via the bus 304, and the memory controller 112 is connected to the HBM interface 504. The HBM interface 504 is configured to package read and write requests from the memory controller 112, for example, into a standard HBM format, and to unpack responses from the memory 302 from the standard HBM format into a format usable by the memory controller 112.

[0036] The control IC 502 includes an HBM interface (HBM PHY) 506 and an interface and control logic circuit 124. The HBM interface 506 of the control IC 502 is connected to the HBM interface 504 of the programmable IC 102. The HBM interface 506 is configured to unpack read and write requests from the HBM interface 504, for example, from a standard HBM format into a native format usable by the interface and control logic circuit 124, and to package responses from the memory 302 into the standard HBM format for transmission to the HBM interface 504 of the programmable IC 102. The interface and control logic circuit 124 can decode the read and write requests from the HBM interface 506 and, in response, transmit native signals to the memories 302 to read from or write to the memories 302 on the various memory dies. The schematic diagram of FIG. 5, as well as the differences between FIGS. 3 and 4, can be modified to implement a single memory die stack.

[0037] 6 illustrates the configuration of a multi-chip structure on a printed circuit board (PCB) 602, according to some examples. The multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, and a memory die 608 stacked on the base die 606. The base die 606 includes a programmable IC 102, such as that of FIGS. 3 and / or 4, and the memory die 608 each includes a memory 302, such as that of FIGS. 3 and / or 4.

[0038] While this multi-chip structure includes a stack of four stacked memory dies 608, other examples may implement any number of memory dies 608 in any number of stacks. Each memory die 608 has external connectors 610, such as microbumps, attached to the active surface of the memory die 608 and attached to the backside of the lower die. Each memory die 608 may include through-substrate vias (TSVs) through the semiconductor substrate on which the memory 302 of each memory die 608 is formed. These TSVs may be implemented to electrically connect the memory 302 of the upper memory die 608 to the respective memory die 608 and / or to the lower die.

[0039] The programmable ICs 102 of the base die 606 include the interface and control logic circuitry 124 shown in FIGS. 3 and / or 4 . The bottom memory die 608 of the stack of memory dies 608 has external connectors 610 attached to the active surface of the bottom memory die 608 and to the backside of the base die 606. The base die 606 may, for example, include TSVs through the semiconductor substrate on which the programmable ICs 102 are formed. These TSVs may be implemented to electrically connect the memory 302 of the upper memory die 608 to the programmable ICs 102. The base die 606 also has external connectors 612, such as controlled collapse chip connection (C4) bumps, attached to the active surface of the base die 606 and attached to a first side of the package substrate 604. A second side of the package substrate 604, opposite the first side, has external connectors 614, such as ball grid array (BGA) balls, attached thereto, which are further attached to the PCB 602.

[0040] 7 is another configuration of a multi-chip structure on a PCB 602, according to some examples. The multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, a control die 702 on the base die 606, and a memory die 608 stacked on the control die 702. The base die 606 includes a programmable IC 102, such as that of FIGS. 3 and / or 4, without the interface and control logic circuitry 124. The control die 702 includes a control IC including the interface and control logic circuitry 124, such as that of FIGS. 3 and / or 4. The memory dies 608 each include a memory 302, such as that of FIGS. 3 and / or 4.

[0041] Like FIG. 6 , the multi-chip structure of FIG. 7 includes a stack of four stacked memory dies 608, although other examples may implement any number of memory dies 608 in any number of stacks. The bottom memory die 608 of the stack of memory dies 608 has an external connector 610 attached to the active surface of the bottom memory die 608 and to the backside of the control die 702. The control die 702 may include, for example, TSVs that run through a semiconductor substrate on which the logic structures (e.g., transistors) of the control die 702 are formed. These TSVs may be implemented to electrically connect the memory 302 of the upper memory die 608 to the control ICs (e.g., interface and control logic circuit 124) and / or programmable ICs 102 of the control die 702. The active surface of the control die 702 is attached to the backside of the base die 606. For example, the active surface of the control die 702 may be bonded to the backside of the base die 606 by, for example, oxide-oxide and / or metal-metal bonding via wafer bonding or other bonding techniques. Base die 606 has an external connector 612 attached to the active surface of base die 606 and attached to a first side of package substrate 604. A second side of package substrate 604 opposite the first side is attached to external connector 614, which is further attached to PCB 602.

[0042] 8 is another configuration of a multi-chip structure on a PCB 602, according to some examples. The multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, a control die 802 on the base die 606, and a memory die 608 stacked on the control die 802. The base die 606 includes a programmable IC 102, such as that shown in FIG. 5. More specifically, the programmable IC 102 also includes the HBM interface 504 shown in FIG. 5. The control die 802 includes a control IC 502, such as that shown in FIG. 5. More specifically, the control IC 502 of the control die 802 includes the interface and control logic circuit 124 and the HBM interface 506 shown in FIG. 5. The memory dies 608 each include a memory 302, such as that shown in FIG. 5.

[0043] Like FIG. 6 , the multi-chip structure of FIG. 8 includes a stack of four stacked memory dies 608, although other examples may implement any number of memory dies 608 in any number of stacks. The bottom memory die 608 of the stack of memory dies 608 has an external connector 610 attached to its active surface and to the backside of the control die 802. The control die 802 may include, for example, TSVs through a semiconductor substrate on which the logic structures (e.g., transistors) of the control IC 502 are formed. These TSVs may be implemented to electrically connect the memory 302 of the upper memory die 608 to the control IC 502 and / or the programmable IC 102 of the control die 802. The control die 802 has external connectors 804, such as microbumps, attached to the active surface of the control die 802 and to the backside of the base die 606. Base die 606 has an external connector 612 attached to the active surface of base die 606 and attached to a first side of package substrate 604. A second side of package substrate 604 opposite the first side is attached to external connector 614, which is further attached to PCB 602.

[0044] 6-8 have been described with various dies having predetermined orientations (e.g., a particular active surface of a die attached to the backside of another die), such orientations are provided as examples. Any die (e.g., any base die 606, memory die 608, control die 702, and / or control die 802) can be, for example, flipped relative to the description provided above or have any other orientation.

[0045] The multi-chip structure described above may be a programmably accessible high-density memory device. Programmable devices with high-density memory utilizing HBM logic and stacking technology may be implemented with the structure described above. Performance benefits associated with programmable ICs (e.g., FPGAs) may be maintained, while being faster, simpler, and less expensive to manufacture, and consuming less power.

[0046] Some examples may be implemented with various programmable integrated circuits (ICs), such as application specific standard products (ASSP) ICs with configurable input / output circuits and interfaces. Some examples may be implemented with multi-ported memories with host interfaces such as nx PCIe Genx, nx 100GE, nx 40G, nx 10GE, 112G PAM4, etc.

[0047] 9 is a flowchart of a method 900 for forming a multi-chip structure, according to some examples. In block 902, a base die is formed. This base die may be, for example, base die 606 of FIGS. 6-8 and may be formed by front and backside semiconductor processing that populates the base die with programmable ICs and TSVs.

[0048] Optionally, in block 904, a control die is formed. This control die may be, for example, control die 702 and / or 802 of FIGS. 7 and / or 8 and may similarly be formed by front-side and back-side semiconductor processing that implements the control IC and TSVs on the control die. Optionally, in block 906, the control die is attached to the base die. For example, the control die may be bonded to the base die by wafer-to-wafer bonding during processing of the control die and base die (e.g., before separating the dies). As another example, the control die may be attached to the base die using external connectors, such as microbumps, which may include reflowing the external connectors to attach the control die to the base die. In some examples, such as to form the multi-chip structure of FIG. 6, the control die is not implemented, and therefore, forming the control die in block 904 and attaching the control die to the base die in block 906 may be omitted.

[0049] At block 908, a stack of memory dies is formed. This stack of memory dies may be, for example, memory dies 608 of Figures 6-8, where each memory die may be formed with front and back semiconductor processing that implements memory and TSVs in the memory die, except that the top memory die may omit the back semiconductor processing and TSVs. The memory dies may be attached to each other in the stack, such as using external connectors such as microbumps, which may include reflowing the external connectors to attach the memory dies together.

[0050] In block 910, the stack of memory dies is attached to the base die, or to the control die if one is implemented. The stack of memory dies may be attached to the base die (e.g., as in FIG. 6 ) or to the control die (e.g., as in FIG. 7 or 8 ) using external connectors such as microbumps, which may include reflowing the external connectors to attach the stack of memory dies to the base die or control die. As noted above, the order of operations may be reversed. For example, if the control die is implemented as in FIG. 8 , the stack of memory dies may be attached to the control die before the control die is attached to the base die.

[0051] At block 912, the base die is attached to a package substrate, which may be, for example, package substrate 604 of FIGS. 6-8 and may be attached to the base die using external connectors such as C4 bumps, which may include reflowing the external connectors to attach the base die to the package substrate.

[0052] At block 914, the package substrate is attached to a PCB, which may be, for example, PCB 602 of Figures 6-8, and may be attached to the package substrate using external connectors such as BGA balls, which may include reflowing the external connectors to attach the package substrate to the PCB.

[0053] According to some examples, the multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable integrated circuit. The programmable integrated circuit includes a memory controller. The first die is on and attached to the package substrate. The second die includes a memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

[0054] In some examples of the above multi-chip structures, the first die may include a semiconductor substrate through which through-substrate vias (TSVs) may extend, and a memory controller may be communicatively coupled to the memory through the TSVs.

[0055] In some examples of the above multi-chip structures, the second die may be attached to the side of the first die opposite the package substrate by an external electrical connector.

[0056] In some examples of the above multi-chip architecture, the physical layer interface may not be communicatively electrically disposed between the memory controller and the memory.

[0057] In some examples of the above multi-chip structures, the first die may include a control logic circuit, which may be communicatively disposed between the memory controller and the memory.

[0058] In some examples, the multi-chip structure may further include a third die including a control logic circuit. The third die may be stacked on and attached to a surface of the first die opposite the package substrate. The second die may be stacked on and attached to a surface of the third die opposite the first die. The control logic circuit may be communicatively disposed between the memory controller and the memory. The third die may be bonded to the first die. The third die may be attached to a surface of the first die opposite the package substrate by an external electrical connector. The second die may be attached to a surface of the third die opposite the first die by an external electrical connector. The physical layer interface may not be communicatively electrically disposed between the memory controller and the memory. The first die may include a first physical layer interface communicatively coupled to the memory controller. The third die may include a second physical layer interface communicatively coupled to the first physical layer interface and the control logic circuit and between the first physical layer interface and the control logic circuit.

[0059] In some examples of the above multi-chip architectures, the programmable integrated circuit includes a field programmable gate array (FPGA).

[0060] According to some examples, a method of forming a multi-chip structure includes stacking a first die over a second die and attaching the first die to a package substrate. The first die includes a memory. The second die includes a programmable integrated circuit. The programmable integrated circuit includes a memory controller. The memory controller is communicatively coupled to the memory by the first die stacked over the second die.

[0061] In some examples of the above methods, stacking the first die on the second die may include attaching the first die to the second die by an external electrical connector, and the second die may include control logic circuitry, the control logic circuitry being communicatively disposed between the memory controller and the memory, and the physical layer interface may not be communicatively electrically disposed between the memory controller and the memory.

[0062] In some examples, the method may further include attaching a third die to the second die. The first die may be attached to the third die. The third die may include a control logic circuit. The control logic circuit may be communicatively disposed between the memory controller and the memory.

[0063] According to some examples, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a field programmable gate array (FPGA) and a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on a side of the first die opposite the package substrate. The memory is communicatively coupled to the memory controller.

[0064] In some examples of the above multi-chip architecture, the physical layer interface may not be communicatively electrically disposed between the memory controller and the memory.

[0065] In some examples of the above multi-chip architecture, the first die may include a control logic circuit, which may be communicatively disposed between the memory controller and the memory.

[0066] In some examples, the multi-chip structure may further include a third die comprising a control logic circuit. The third die may be stacked on and attached to a side of the first die opposite the package substrate. The second die may be stacked on and attached to a side of the third die opposite the first die. The control logic circuit may be communicatively disposed between the memory controller and the memory. The first die may include a first physical layer interface communicatively coupled to the memory controller. The third die may include a second physical layer interface communicatively coupled to the first physical layer interface and the control logic circuit, and between the first physical layer interface and the control logic circuit.

[0067] While the foregoing is directed to particular examples, other and further examples may be devised without departing from the basic scope of those examples, the scope of which is dictated by the following claims.

Claims

1. A package substrate; a first die comprising a programmable integrated circuit, the programmable integrated circuit including a memory controller, the first die being on and attached to the package substrate; a second die comprising a memory, the second die being stacked on the first die, the memory being communicatively coupled to the memory controller; and A multi-chip structure comprising:

2. 2. The multi-chip structure of claim 1, wherein the first die includes a semiconductor substrate having through-substrate vias (TSVs) extending through the semiconductor substrate, and the memory controller is communicatively coupled to the memory through the TSVs.

3. 10. The multi-chip structure of claim 1, wherein the second die is attached to a side of the first die opposite the package substrate by an external electrical connector.

4. 2. The multi-chip structure of claim 1, wherein a physical layer interface is not communicatively electrically disposed between said memory controller and said memory.

5. 2. The multi-chip structure of claim 1, wherein the first die includes a control logic circuit, the control logic circuit being communicatively disposed between the memory controller and the memory.

6. 10. The multi-chip structure of claim 1, further comprising: a third die comprising a control logic circuit, the third die stacked on and attached to a side of the first die opposite the package substrate; the second die stacked on and attached to a side of the third die opposite the first die; and the control logic circuit disposed in communication between the memory controller and the memory.

7. The multi-chip structure of claim 6 , wherein the third die is bonded to the first die.

8. 7. The multi-chip structure of claim 6, wherein the third die is attached to the side of the first die opposite the package substrate by an external electrical connector.

9. 7. The multi-chip structure of claim 6, wherein the second die is attached to the face of the third die opposite the first die by an external electrical connector.

10. 7. The multi-chip structure of claim 6, wherein a physical layer interface is not communicatively electrically disposed between the memory controller and the memory.

11. the first die includes a first physical layer interface communicatively coupled to the memory controller; the third die is communicatively coupled to the first physical layer interface and the control logic circuit, and includes a second physical layer interface between the first physical layer interface and the control logic circuit; 7. The multi-chip structure of claim 6.

12. 10. The multi-chip structure of claim 1, wherein the programmable integrated circuit comprises a field programmable gate array (FPGA).

13. 1. A method of forming a multi-chip structure, said method comprising: stacking a first die over a second die, the first die comprising a memory, the second die comprising a programmable integrated circuit, the programmable integrated circuit including a memory controller, the memory controller communicatively coupled to the memory by the first die stacked over the second die; and attaching the first die to a package substrate.

14. stacking the first die on the second die includes attaching the first die to the second die by an external electrical connector; the second die includes a control logic circuit, the control logic circuit being communicatively disposed between the memory controller and the memory; a physical layer interface is not communicatively electrically disposed between the memory controller and the memory; The method of claim 13.

15. 14. The method of claim 13, further comprising attaching a third die to the second die, the first die attached to the third die, the third die comprising control logic circuitry, the control logic circuitry disposed in communication between the memory controller and the memory.

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