Semiconductor device

Abstract

To provide a semiconductor device which allows lower consumed power and allows storage of data in a manner of simulating human brain.SOLUTION: A semiconductor device has a control unit, a storage unit, and a sensor unit. The storage unit has a storage circuit and a switching circuit. The storage circuit has a first transistor and a capacitance device. The switching circuit has a second transistor and a third transistor. Each of the first transistor and the second transistor has a semiconductor layer including a channel forming region having an oxide semiconductor and a back gate electrode. The control unit has a function to switch a signal given to the back gate electrode in response to a signal acquired by the sensor unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device. In particular, one aspect of the present invention relates to a semiconductor device that can detect information in the human brain. The present invention relates to a semiconductor device capable of simulating the storage of information.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to the general. [Background technology]

[0003] Used in the development of artificial intelligence (AI) The computer, a von Neumann type computer, surpasses humans in terms of calculation speed. are.

[0004] In contrast, the human brain makes correct judgments by comparing and complementing fragmented input information with memories. Or, by association with a wide range of memories, or By using creativity and foresight, people can solve problems that are difficult for computers to solve. It has the ability to do so.

[0005] In recent years, with the improvement of computer performance, neural networks have become increasingly popular for learning and predicting data. In the field of machine learning, large-scale computations such as By using deep learning techniques, the accuracy of computer recognition can be improved. Significant improvements have been reported (see Patent Document 1, for example). Even in fields where predictability is required, problems that were difficult for computers to solve can now be solved. It is becoming more and more common. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent Publication No. 2016 / 0110642 Summary of the Invention [Problem to be solved by the invention]

[0007] Conventional artificial intelligence devices are nowhere near as power-efficient as the human brain. In hardware such as CPUs and GPUs, Si transistors such as SRAM and DRAM are used. The memory element is made up of silicon transistors, which store data and perform arithmetic operations. As memory elements become smaller, leakage current increases and the As the performance of the computer increases, the circuit scale also increases, resulting in even greater power consumption.

[0008] Furthermore, the memory elements of conventional artificial intelligence devices have a standardized function for storing information. For example, memory elements such as SRAM and DRAM write and read information such as 0 or 1. In contrast, the human brain has information such as long-term memory and short-term memory. The way information is stored, and the location of information storage, such as memory in the neocortex and memory in the hippocampus, There is also diversity in memories of news.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure. An object of one embodiment of the present invention is to provide a semiconductor device that can operate with low power consumption. Furthermore, one aspect of the present invention is to mimic the memory of information in the human brain. It is an object of the present invention to provide a semiconductor device which can perform the above-described functions.

[0010] The description of these problems does not preclude the existence of other problems. An embodiment does not necessarily solve all of these problems. Problems other than these may be solved by the specification. It is obvious from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the sections. [Means for solving the problem]

[0011] One embodiment of the present invention is a sensor including a control unit, a storage unit, and a sensor unit. a switching circuit, and a memory circuit including a first transistor and a capacitor; The switching circuit has a second transistor and a third transistor, and the first transistor and The second transistor includes a semiconductor layer including a channel formation region having an oxide semiconductor. The control unit controls the first transistor and the second transistor in response to the signal obtained by the sensor unit. This is a semiconductor device having a function of switching the signal to be applied.

[0012] One embodiment of the present invention is a sensor including a control unit, a storage unit, and a sensor unit. a switching circuit, and a memory circuit including a first transistor and a capacitor; The switching circuit has a second transistor and a third transistor, and the first transistor and The second transistor includes a semiconductor layer including a channel formation region having an oxide semiconductor, and a back a gate electrode, and the control unit controls the back gate electrode in response to a signal obtained by the sensor unit. The semiconductor device has a function of switching a signal to be applied to the

[0013] One embodiment of the present invention is a sensor including a control unit, a storage unit, and a sensor unit. a switching circuit, and the memory circuit has a first transistor and a capacitor, One of the source and drain of the transistor is electrically connected to one electrode of the capacitor. , the switching circuit has a second transistor and a third transistor, and the second transistor One of the source and drain of the first transistor is electrically connected to the gate of the third transistor. The first transistor and the second transistor are semiconductors each having a channel formation region including an oxide semiconductor. a conductor layer and a back gate electrode, and the control unit controls the control unit to: This is a semiconductor device having a function of switching a signal to be applied to the back gate electrode.

[0014] One embodiment of the present invention is a sensor including a control unit, a storage unit, and a sensor unit. a switching circuit, and a memory circuit including a first transistor and a capacitor; The switching circuit has a second transistor and a third transistor, and the first transistor and The second transistor includes a semiconductor layer including a channel formation region having an oxide semiconductor, and a gate and a control unit that controls a signal to be applied to the gate electrode in response to a signal obtained by the sensor unit. The semiconductor device has a function of switching between the above.

[0015] One embodiment of the present invention is a sensor including a control unit, a storage unit, and a sensor unit. a switching circuit, and the memory circuit has a first transistor and a capacitor, One of the source and drain of the transistor is electrically connected to one electrode of the capacitor. , the switching circuit has a second transistor and a third transistor, and the second transistor One of the source and drain of the first transistor is electrically connected to the gate of the third transistor. The first transistor and the second transistor are semiconductors each having a channel formation region including an oxide semiconductor. The control unit controls the gate electrode in response to a signal obtained by the sensor unit. This is a semiconductor device that has the function of switching signals applied to electrodes.

[0016] In one embodiment of the present invention, the memory circuit includes a fourth transistor and a second transistor. One of the source and drain of the semiconductor device is electrically connected to the gate of the fourth transistor. is preferred. [Effects of the Invention]

[0017] One embodiment of the present invention can provide a semiconductor device with a novel structure. One embodiment can provide a semiconductor device that can operate with low power consumption. One aspect of the invention provides a semiconductor device that can mimic the memory of information in the human brain. One of the goals is to

[0018] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above is self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 2] 1 is a conceptual diagram illustrating a semiconductor device. [Figure 3] 1A-1C are circuit diagrams, graphs, and flowcharts showing examples of the configuration of a semiconductor device. [Figure 4]1A-1C are circuit diagrams, graphs, and flowcharts showing examples of the configuration of a semiconductor device. [Figure 5] 1A-1C are circuit diagrams, graphs, and flowcharts showing examples of the configuration of a semiconductor device. [Figure 6] 1A to 1D are conceptual diagrams showing examples of the configuration of a semiconductor device. [Figure 7] 1A and 1B are block diagrams showing configuration examples of a semiconductor device. [Figure 8] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 9] 1A-1D are circuit diagrams, waveform diagrams, graphs, and flowcharts showing examples of the configuration of a semiconductor device. [Figure 10] 1A-1D are circuit diagrams, waveform diagrams, graphs, and flowcharts showing examples of the configuration of a semiconductor device. [Figure 11] 1A to 1C are a circuit diagram, a waveform diagram, and a flowchart showing an example of the configuration of a semiconductor device. [Figure 12] 1 is a waveform diagram showing a configuration example of a semiconductor device. [Figure 13] 1A to 1D are conceptual diagrams showing examples of the configuration of a semiconductor device. [Figure 14] 1A and 1B are block diagrams showing configuration examples of a semiconductor device. [Figure 15] (A)-(D) Diagrams showing application examples of semiconductor devices. [Figure 16] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 17] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 18] (A)-(C) are cross-sectional views showing examples of transistor structures. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the invention in various forms without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0021] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. are shown in the drawings, and are not limited to the shapes or values shown in the drawings.

[0022] In addition, the present specification can be appropriately combined with the following embodiments. When multiple configuration examples are shown in one embodiment, the configuration examples may be combined as appropriate. It is possible.

[0023] Hereinafter, a semiconductor device according to one embodiment of the present invention will be described. This paper describes a semiconductor device that can achieve memory capabilities similar to those of the human brain.

[0024] <Configuration Example 1 of Semiconductor Device> FIG. 1 is a block diagram illustrating an example of a semiconductor device. The device includes a sensor unit 60, a control unit 50, and a storage unit 10. The storage unit 10 includes, for example, The memory circuit 20A includes memory circuits 20B, a switching circuit 30, and an input / output circuit 40.

[0025] In FIG. 1, only one sensor unit 60, one control unit 50, and one storage unit 10 are shown. However, a configuration may be adopted in which a plurality of each of the memory circuits 20A and 20B are provided. The switching circuit 30 and the input / output circuit 40 are not limited to the configuration shown in FIG. It can be configured as follows.

[0026] The memory circuit 20A has a plurality of memory circuits (memory circuits 21A to 21D are shown in FIG. 1). Each of the memory circuits 21A to 21D includes a plurality of memory elements. Although not shown, 21D to 21E have a driver circuit for driving a plurality of memory elements. The driving circuit controls the voltage applied to the back gate electrode of the transistor in response to the control of the control unit 50. The memory circuits 21A to 21D have a function of switching the lock gate voltage. The information storage capacity can be changed according to the signal Se obtained at 60. In memory circuits, information is stored as a voltage corresponding to the data. It is stored as a value or charge.

[0027] For example, the memory circuits 21A to 21D are configured by applying a backplane to a transistor to provide information storage capability. For example, the memory circuit 21A stores information for a long period of time. The memory circuit 21B is a memory element capable of storing short-term information. The control unit 50 can control the element.

[0028] The memory circuit 20B, like the memory circuit 20A, is configured with a plurality of memory circuits (memory circuits 22 in FIG. 1). Each of the memory circuits 22A to 22D includes a plurality of memory elements. Although not shown, the memory circuits 22A to 22D include a memory circuit for driving a plurality of memory elements. The driving circuit controls the buffer of the transistor in response to the control of the control unit 50. The memory circuit 22 has a function of switching the back gate voltage applied to the back gate electrode. A to 22D can change the information storage capacity according to the signal Se obtained by the sensor unit 60. It has the following functions.

[0029] For example, the memory circuits 21A to 21D are configured by applying a backplane to a transistor to provide information storage capability. For example, the memory circuit 21A stores information for a long period of time. The memory circuit 21B is a memory element capable of storing short-term information. The control unit 50 can control the element.

[0030] The memory circuits 20A and 20B can be applied to DOSRAM or NAND flash memory. OSRAM is preferred. DOSRAM (registered trademark) stands for "Dynamic Oxide Semiconductor Random Access Memory(RAM) " and refers to RAM with 1T (transistor) 1C (capacitance) type memory cells. NOSRAM (registered trademark) stands for "Nonvolatile Oxide Se It is an abbreviation for "Gain Cell Type (2T type, 3T type)" DOSRAM and NOSRAM refer to RAMs with OS transistors ( The low off-state current of a transistor having an oxide semiconductor in the channel formation region is utilized. It is memory.

[0031] DOSRAM is a DRAM formed using OS transistors. is a memory that temporarily stores information sent from the outside. A memory cell including a transistor and a Si transistor (having silicon in the channel formation region) and a read circuit section including a transistor for reading the memory cell. Since the components can be located on different layers in the stack, DOSRAM reduces the overall circuit area. In addition, DOSRAM can be divided into smaller memory cell arrays, It can be efficiently arranged.

[0032] NOSRAM is a non-volatile memory that uses OS transistors. Flash memory and ReRAM (Resistive Random Access Memory) memory), MRAM (Magnetoresistive Random Acce. Compared to other non-volatile memories such as EEPROM, the power consumption when writing data is Also, like flash memory and ReRAM, the element There is no degradation in performance and there is no limit to the number of times data can be written. In addition to 1-bit binary data, multi-value data of 2 or more bits can be stored. OSRAM stores multi-value data, which reduces the memory cell area per bit. It is possible.

[0033] NOSRAM can also store analog data in addition to digital data. Therefore, the memory circuits 20A and 20B can also be used as analog memories. NOSRAM can store analog data as it is, so it can be used in D / A conversion circuits and Since no A / D conversion circuit is required, NOSRAM can reduce the area of peripheral circuits. This can be done.

[0034] In one embodiment of the present invention, NOSRAM or DOSRAM is used as the memory circuit 20A, Although the configuration applied to each circuit included in the 0B will be described, one embodiment of the present invention is not limited to these. For example, with future technological innovations, non-volatile memories such as ReRAM and MRAM may become available. In some cases, such as when the power consumption when using the memory circuits 20A and 20B is sufficiently small, The configuration may be applied to each circuit included in 0B.

[0035] The switching circuit 30 switches the electrical connection between the memory circuits 20A and 20B in response to control by the control unit 50. For example, the memory circuits 21A to 21D and the memory circuits 22A to 22C have a function of controlling the connection. The function of this circuit is to control the amount of current flowing between the memory circuits. The switching circuit 30 has a function of switching the transmission of the signal obtained by the sensor unit 60. In response to the signal Se, the signals flowing between the memory circuits 21A to 21D and the memory circuits 22A to 22D The amount of current can be changed according to the back gate voltage applied to the transistor. The switching circuit 30 may be called a reconfigurable circuit (reconfigurable circuit).

[0036] The switching circuit 30 controls the amount of current flowing between the memory circuits. The switching circuit 30 has a semiconductor element for passing a current according to the information stored in the The control unit 50 controls the back gate voltage applied to the transistor to The memory circuits 20A and 20B have a function of changing the stored information. Although the arrows between the two are illustrated as pointing in one direction, they may be bidirectional depending on the flow of information. It can also be expressed as:

[0037] The switching circuit 30 is a programmable device in which the storage element has an OS transistor. In this specification and drawings, a programmable device having an OS transistor is The device is called OS-FPGA. This is called configuration data.

[0038] The OS-FPGA has a smaller memory area than FPGAs whose memory elements are composed of SRAM. Therefore, even if a context switching function is added, the area increase is small. In addition, OS-FPGA uses boosting to transmit data and parameters at high speed. It is possible.

[0039] The sensor unit 60 measures, for example, biological information such as brain waves, pulse, blood pressure, body temperature, etc. To acquire the information, various sensors such as brain wave sensor, pulse wave sensor, blood pressure sensor, and temperature sensor are used. FIG. 1 shows the output of a signal Se from one sensor. However, a configuration may be adopted in which signals obtained by a plurality of sensors are input to the control unit 50.

[0040] The control unit 50 includes a CPU (Central Processing Unit) and a G Arithmetic circuits such as PU (Graphics Processing Unit) and SR Memory circuits such as AM (Static Random Access Memory), The control unit 50 controls the voltage VBG_A to The control unit 50 has a function of outputting the VBG_C. For example, the control unit 50 uses an artificial neural network. It is possible to perform output according to input using arithmetic processing based on the algorithm.

[0041] The voltages VBG_A to VBG_C are the voltages of the memory circuits 20A, 20B and the switching circuit 30. The voltage applied to the back gate electrode of each transistor, or the back gate In FIG. 1, the voltage VBG_A is a signal that can switch the voltage applied to the memory circuit 20. In Figure 1, the voltage VBG_A is not limited to a single voltage value. The memory circuits 21A to 21D of the memory circuit 20A are applied with respective back gate electrodes. The memory circuit 20B and the switching circuit 30 can be configured to control the voltage. Similarly, the voltages are controlled as voltages applied to the back gate electrodes of different memory circuits. The configuration can be such that:

[0042] The control unit 50 controls the voltages VBG_A to VBG_B in response to the signal Se output from the sensor unit 60. The control of BG_C can be switched. For example, if the same signal Se is input repeatedly, When a signal Se with a large or small intensity is input, the voltage VBG_A Control of VBG_C can be switched.

[0043] The input / output circuit 40 transmits information to the memory circuit 20A, the memory circuit 20B, and the switching circuit 30. The input / output circuit 40 is a circuit for controlling the input and output of the memory unit 10. It may also be configured as follows.

[0044] Figure 2 shows the human brain ( This is a schematic diagram showing how the system mimics the functions of the human brain.

[0045] As shown in FIG. 2, in one embodiment of the present invention, a structure that mimics the function of the human brain is used. In order to achieve this, a transistor including an oxide semiconductor (also called an OS transistor) is OS FET technology is used. As for technology, for example, transistors (also called FETs), Examples include capacitive elements (also called capacitors, Cs) that are directly connected to the In addition, a memory configured using the above FET and Cs etc. By using one or more of these, an arithmetic unit, a register, a peripheral circuit, etc. can be configured. It is possible to make it function as a processor.

[0046] In this specification, the processor is referred to as a brain-type processor (Brain-morp hic processor, BM processor, or Brain proc It can be used as a DOSRAM, NO shown in Figure 2. SRAM and OS-FPGA will be described later. The memory (also called OS Mem.) is a memory having OS transistors, FPGA configuration data Remember.

[0047] In the NOSRAM shown in FIG. 2, the capacitance element is indicated by a broken line. For example, a parasitic barrier that may be formed between a wiring and a wiring formed in a layer different from the wiring may be used. The capacitance of the NOSRAM shown in Figure 2 is intentionally shaped. Since it is not the capacity achieved, it is shown by a dashed line.

[0048] In one embodiment of the present invention, a memory circuit and a switching circuit each including an OS transistor are By using this configuration, the leakage current that flows between the source and drain when the transistor is off (hereinafter referred to as "off") The information (data) is stored by utilizing the extremely low current. This can be realized by storing charge according to the data in a node having a certain amount of parasitic capacitance.

[0049] In a memory circuit using an OS transistor, information is stored by charging or discharging an electric charge. Rewritable, allowing for virtually unlimited data writing and reading Memory circuits using OS transistors are used in a wide range of applications, including magnetic memory and resistive memory. Since no structural changes at the atomic level are involved, it has excellent rewrite durability. Memory circuits using S transistors can be rewritten repeatedly like flash memory. Even if the electron trapping centers are increased, no instability due to the increase in electron trapping centers is observed.

[0050] Furthermore, memory circuits using OS transistors can be automatically integrated into circuits using Si transistors. Since the OS transistor can be freely arranged, it can be easily integrated. It can be manufactured using the same manufacturing equipment as Si transistors, so it can be manufactured at low cost. It can be made.

[0051] In addition to the gate electrode, source electrode, and drain electrode, the OS transistor also has a buffer If a back gate electrode is included, it can be a four-terminal semiconductor element. The input and output of signals flowing between the source and drain are controlled independently according to the voltage applied to the gate electrode. Therefore, it is possible to design circuits based on the same concept as LSI. In addition, OS transistors can perform the same functions as Si transistors in high-temperature environments. Specifically, it can withstand temperatures between 125°C and 150°C. Even at high temperatures, the ratio of on-current to off-current is large, ensuring good switching operation. This can be done.

[0052] By adopting the configuration of the semiconductor device disclosed in this embodiment, the formation of long-term memory in the human brain and its process, and the formation of short-term memory and its process can be realized by a semiconductor device having an OS transistor. Therefore, data can be stored with a function closer to that of the human brain than in the prior art. In addition, data retention can be realized with extremely low power. That is, it is possible to drive a brain-type processor with extremely low power consumption, similar to the human brain. The memory circuits 21A to 21D or 22A to 22D are configured with circuits having OS transistors. An example of the circuit configuration and operation will be described with reference to FIGS. 3(A) to (C) and FIGS. 4(A) to (C). FIG. 3(A) shows a circuit diagram of a memory element having the circuit configuration of a DOSRAM. In FIG. 3(A), the transistor MT1, the capacitor element C1, the word line WL, the bit line BL, and the back gate potential line BGL are shown. The transistor MT1 is an OS transistor and is a four-terminal element having a back gate electrode. The back gate electrode is connected to the back gate potential line BGL to receive the potential VBG. The off-current of the transistor MT1 is shown as Ioff. In FIG. 3(A), the node for holding charge, that is, the node of the wiring connecting the transistor MT1 and the capacitor element C1, is shown as the node FN. The bit line BL has a function of transmitting information (data, data potential) to be written into the memory element.

[0053] <Example Configuration 1 of NOSRAM and DOSRAM> The memory circuits 21A to 21D or 22A to 22D are configured with circuits having OS transistors. An example of the circuit configuration and operation will be described with reference to FIGS. 3(A) to (C) and FIGS. 4(A) to (C). FIG. 3(A) shows a circuit diagram of a memory element having the circuit configuration of a DOSRAM. In FIG. 3(A), the transistor MT1, the capacitor element C1, the word line WL, the bit line BL, and the back gate potential line BGL are shown.

[0054] FIG. 3(A) shows a circuit diagram of a memory element having the circuit configuration of a DOSRAM. In FIG. 3(A), the transistor MT1, the capacitor element C1, the word line WL, the bit line BL, and the back gate potential line BGL are shown. The transistor MT1 is an OS transistor and is a four-terminal element having a back gate electrode. The back gate electrode is connected to the back gate potential line BGL to receive the potential VBG. The off-current of the transistor MT1 is shown as Ioff. In FIG. 3(A), the node for holding charge, that is, the node of the wiring connecting the transistor MT1 and the capacitor element C1, is shown as the node FN.

[0055] The transistor MT1 is an OS transistor and is a four-terminal element having a back gate electrode. The back gate electrode is connected to the back gate potential line BGL to receive the potential VBG. The off-current of the transistor MT1 is shown as Ioff. In FIG. 3(A), the node for holding charge, that is, the node of the wiring connecting the transistor MT1 and the capacitor element C1, is shown as the node FN. The back gate electrode is connected to the back gate potential line BGL to receive the potential VBG. The off-current of the transistor MT1 is shown as Ioff. In FIG. 3(A), the node for holding charge, that is, the node of the wiring connecting the transistor MT1 and the capacitor element C1, is shown as the node FN. The off-current of the transistor MT1 is shown as Ioff. In FIG. 3(A), the node for holding charge, that is, the node of the wiring connecting the transistor MT1 and the capacitor element C1, is shown as the node FN. In FIG. 3(A), the node for holding charge, that is, the node of the wiring connecting the transistor MT1 and the capacitor element C1, is shown as the node FN. The node for holding charge, that is, the node of the wiring connecting the transistor MT1 and the capacitor element C1, is shown as the node FN.

[0056] The bit line BL has a function of transmitting information (data, data potential) to be written into the memory element. The word line WL also carries a signal that controls the on / off of the transistor MT1. The back gate potential line BGL supplies the potential VBG to the back gate of the transistor MT1. The bit line BL, word line WL, and back gate voltage The position lines BGL may be simply called wiring.

[0057] The potential VBG is set to a different potential for each memory element included in the memory circuits 21A to 21D, for example. For example, the backgammon when storing information in the memory circuit 21A is The back gate potential when storing information in the memory circuit 21B is V0 ( <V1 ), and the back gate potential when information is stored in the memory circuit 21C is V2 (>V1), The off-state current Ioff of the transistor MT1 is as shown in the graph in FIG. Depending on the magnitude of the back gate potential, the off-current Ioff_2 is large, followed by I The larger the off-current, the more the charge stored in node FN changes. The smaller the off-current, the less the charge held in node FN fluctuates. This allows the data retention period to differ for each memory circuit.

[0058] With this configuration, the memory circuits 21A to 21D or 22A to 22D can The function of storing information with different storage capacities is realized according to the signal Se obtained by the unit 60. .

[0059] FIG. 3C shows a flowchart for explaining the operation of the DOSRAM described above. show.

[0060] In step S01, the potential VBG given as the back gate potential is set to V1, and the memory circuit Stores information on the road.

[0061] In step S02, it is determined whether or not the signal Se output from the sensor unit 60 fluctuates. The presence or absence of a sensor signal is determined by setting multiple thresholds and comparing the thresholds with the sensor output. It is preferable to control the potential VBG given as the back gate potential according to the relationship between the Desirable.

[0062] If there is a change in step S02, the process proceeds to step S03, and the back gate potential is set to The potential VBG is set to V0, which is smaller than V1, and information is stored in the memory circuit. The potential VBG is switched so that the data retention time in the memory circuit is increased.

[0063] If there is no change or the change is small in step S03, proceed to step S04. The potential VBG given as the gate potential is set to V2, which is greater than V1, and information is stored in the memory circuit. That is, the potential VBG is switched so as to shorten the time for which information is held in the memory circuit. can.

[0064] By adopting this configuration, it is possible to store information with different storage capacities according to the output of the sensor unit. For example, if the sensor part is a temperature sensor, it can measure the information at high or low temperatures. The brain has the ability to retain information for a long period of time, while information stored at room temperature is forgotten after a certain period of time. It can be realized.

[0065] FIG. 4A shows a circuit diagram of a memory element having a NOSRAM circuit configuration. In FIG. 4A, a transistor MT2, a transistor MT3, a word line WL, a bit line B L, the back gate potential line BGL.

[0066] Transistor MT2 is an OS transistor and is a four-terminal element having a back gate electrode. The back gate electrode is connected to the back gate potential line BGL to apply a potential V BG. The off-current of transistor MT2 is illustrated as Ioff. In FIG. 4(A), a node for holding charges, that is, a node of a wiring to which the gates of transistor MT2 and transistor MT 3 are connected is illustrated as node FN.

[0067] In FIG. 4(A), transistor MT3 is illustrated as a p-channel type, but it may be an n-channel type. Also in FIG. 4(A), a 2T type having two transistors is illustrated However, it is possible to use a 2T1C type with a capacitor element added, or a 3 T type combined with another transistor. The capacitor element connected to node FN can be omitted by increasing parasitic capacitances such as the gate capacitance of transistor M T3. Or as shown in FIG. 2, the above parasitic capacitance may be positively used as a capacitance.

[0068] The potential VBG is, for example, different potentials for each memory element included in the memory circuits 21A to 21D and is controlled by the control unit 50. For example, when information is stored in the memory circuit 21A, the potential VBG applied as the back gate potential is V1, and when information is stored in the memory circuit 21B, the potential VBG applied as the back gate potential is V0 (<V1). When the potential VBG applied as the back gate potential when information is stored in the memory circuit 21C is V2 (>V1), the off-current Ioff of transistor M T2 becomes as shown in the graph of FIG. 4(B). That is, according to the magnitude relationship of the potential VBG, the off-current is also such that Ioff_2 is large, followed by Ioff_1 and Ioff T2のオフ電流Ioffは、図4(B)に示すグラフのようになる。つまり、電位VBG の大小関係に応じて、オフ電流もIoff_2が大きく、次いでIoff_1、Ioff の順である。 is in the order of Ioff_2 being large, followed by Ioff_1 and Ioff, as shown in the graph of FIG. 4(B). That is, according to the magnitude relationship of the potential VBG, the off-current is also in the order of Ioff_2 being large, followed by Ioff_1 and Ioff In other words, according to the magnitude relationship of the potential VBG, the off-current is also such that Ioff_2 is large, followed by Ioff_1 and Ioff The larger the off-current, the easier it is for the charge held in node FN to fluctuate, and the off-current As the value of Θ is smaller, the charge stored in the node FN is less likely to fluctuate. This allows for differences in retention periods.

[0069] With this configuration, the memory circuits 21A to 21D or 22A to 22D can The function of storing information with different storage capacities is realized according to the signal Se obtained by the unit 60. .

[0070] FIG. 4C is a flowchart illustrating the operation of the NOSRAM described above. show.

[0071] In step S11, the potential VBG given as the back gate potential is set to V1, and the memory circuit Stores information on the road.

[0072] In step S12, it is determined whether or not the signal Se output from the sensor unit 60 fluctuates. The presence or absence of a sensor signal is determined by setting multiple thresholds and comparing the thresholds with the sensor output. It is preferable to control the potential VBG given as the back gate potential according to the relationship between the Desirable.

[0073] If there is a change in step S12, the process proceeds to step S13, and the back gate potential is set to The potential VBG is set to V0, which is smaller than V1, and information is stored in the memory circuit. The potential VBG is switched so that the data retention time in the memory circuit is increased.

[0074] If there is no change or if the change is small in step S13, proceed to step S14. The potential VBG given as the gate potential is set to V2, which is greater than V1, and information is stored in the memory circuit. That is, the potential VBG is switched so as to shorten the time for which information is held in the memory circuit. can.

[0075] By adopting this configuration, it is possible to store information with different storage capacities according to the output of the sensor unit. For example, if the sensor part is a temperature sensor, it can measure the information at high or low temperatures. The brain has the ability to retain information for a long period of time, while information stored at room temperature is forgotten after a certain period of time. It can be realized.

[0076] <Switching circuit configuration example 1> The switching circuit 30 has a circuit configuration including OS transistors. An example of this will be described with reference to FIGS. 5(A) to 5(C) and 6(A) to 6(D). .

[0077] FIG. 5A shows a circuit configuration of a switching circuit 30 disposed between a pair of memory circuits. The circuit diagram of the memory element is shown in FIG. 5A. MT5, word line WL, bit line BL, back gate potential line BGL, input terminal IN, output The terminal OUT is shown.

[0078] The transistor MT4 is an OS transistor and is a four-terminal element having a back gate electrode. The back gate electrode is connected to the back gate potential line BGL, and is supplied with a potential V The off-state current of the transistor MT4 is shown as Ioff. 5(A), the nodes that hold the charge, namely, transistor MT4 and transistor MT The node of the wiring to which the gate of the transistor 5 is connected is shown as node FN.

[0079] Transistor MT5 is a Si transistor or an OS transistor. Node F The current flowing through transistor MT5 according to the potential of node N, that is, the current flowing between input terminal IN and output terminal OU is illustrated as Idata.

[0080] In FIG. 5(A), although transistor MT5 is illustrated as a p-channel type, it may also be an n-channel type. Also in FIG. 5(A), a 2T type having two transistors is illustrated However, it can be a 2T1C type with a capacitance element added, or a 3 T type combined with another transistor. The capacitance element connected to node FN can be omitted by increasing the parasitic capacitance such as the gate capacitance of transistor M T5.

[0081] Potential VBG is different for each switching circuit provided between any one of memory circuits 21A to 21D and any one of memory circuits 22A to 2 2D, and is controlled from control section 50. For example, the back gate potential of transistor MT4 included in the switching circuit provided between memory circuit 21A and memory circuit 22A is V1, and the back gate potential of transistor M4 included in the switching circuit provided between memory circuit 21B and memory circuit 22B is V0 (<V1), and the back gate potential of transistor M4 included in the switching circuit provided between memory circuit 21C and memory circuit 22C is V2 (>V1). Then, the off-current Ioff of transistor MT4 will have a difference in the magnitude of the off-current. At this time, if a high-level potential is held at node FN, a difference will occur in the potential (V ) of node FN according to the magnitude of the off-current. Therefore, a difference will occur in the current Idata flowing according to the potential of node FN. FN ) That is, as shown in FIG. 5B, depending on the magnitude relationship of the back gate potential, As time passes (t), the magnitude of the fluctuating current Idata varies. It is possible to make a difference in the amount of current flowing between the memory circuits for each path.

[0082] With this configuration, any one of the memory circuits 21A to 21D and the memory circuits 22A to The switching circuit provided between the wiring between the sensor unit 60 and any one of the sensors 22D is This realizes a function of generating a difference in the amount of current flowing between the memory circuits in accordance with the signal Se.

[0083] FIG. 5C is a flowchart illustrating the operation of the switching circuit described above. show.

[0084] In step S21, the potential VBG applied to the node FN is set to H level, that is, the current I Data is assumed to be non-flowing data.

[0085] In step S22, the potential VBG applied as the back gate potential is set to V0, and the transistor The off-state current Ioff of the transistor MT4 is set to an extremely low state.

[0086] In step S23, it is determined whether or not the signal Se output from the sensor unit 60 has changed. The presence or absence of a sensor signal is determined by setting multiple thresholds and comparing the thresholds with the sensor output. It is preferable to configure the potential VBG to be controlled in accordance with the relationship.

[0087] If there is a change in step S23, the process proceeds to step S24, and the back gate potential is set to The potential VBG given by the transistor MT4 is set to V1, which is larger than V0. The current Ioff is controlled to be large, and the current Idata flowing between the memory circuits is increased. If there is no or only a small change in step S23, , and continue with step S22.

[0088] In step S25, it is determined whether or not the signal Se output from the sensor unit 60 has changed. The presence or absence of a sensor signal is determined by setting multiple thresholds and comparing the thresholds with the sensor output. It is preferable to configure the potential VBG to be controlled in accordance with the relationship.

[0089] If there is a change in step S25, the process proceeds to step S26, and the back gate potential is set to The potential VBG given by the transistor MT4 is V2, which is larger than V1. The current Ioff is controlled to be even larger, and the current Idata flowing between the memory circuits is increased. If there is no or small fluctuation in step S25, the potential VBG is changed so that the If so, step S24 continues.

[0090] By adopting this configuration, the amount of current flowing between the memory circuits can be varied depending on the output of the sensor unit. For example, if the sensor is a temperature sensor, it can detect the temperature at high or low temperatures. This function activates signal transmission at room temperature and inactivates signal transmission at room temperature. It is possible.

[0091] 6A to 6D show a method for storing data in a semiconductor device according to one embodiment of the present invention. This is a diagram for explanation based on the brain of the brain.

[0092] In FIG. 6A, the information is held in the memory circuit 21A as an initial state (shown by a solid line). The transfer of information by the memory circuit 30 is inactive (a state in which the amount of current flowing between the memory circuits is small; dotted line) (indicated by arrows) and no information is stored in the memory circuits 22A to 22C (indicated by dotted lines). The state is illustrated.

[0093] In the semiconductor device according to one aspect of the present invention, the switching circuit 30 is This activates the transmission of information between memory circuits (a state in which a large amount of current flows between memory circuits; indicated by solid arrows). Therefore, as shown in FIG. 6B, the memory circuit 22 The information stored in the memory circuit 21A can be retained (shown by solid lines) by 22A to 22C. It is possible.

[0094] In the semiconductor device of one embodiment of the present invention, the memory circuit 22A It is possible to switch to erase the information in 22C (to shorten the retention period). Therefore, as shown in FIG. 6C, the switching circuit 31 switches between the memory circuit 28B and and 28C are switched to a state in which transmission of information to the memory circuits 22B and 22C is inactivated. In this case, it is possible to switch the information stored in memory to short-term memory (shown by the thin dotted line). It is Noh.

[0095] In the semiconductor device of one embodiment of the present invention, the memory circuit 22A In addition to eliminating (shortening the retention period) information in 22C, it also strengthens it. Therefore, as shown in Figure 6(D), In order to achieve this, the switching circuit 30 is more effectively used to transmit information to the memory circuits 22B and 22C. The activated state (a state in which the amount of current flowing between the memory circuits is larger; indicated by the thick arrows), The transmission of information to the circuits 22B and 22C is switched to an inactive state, and the memory circuit 22A The information stored in the memory is transferred to long-term memory (shown by the thick solid line), or the memory circuit 2 2B and 22C can transfer information stored in them to short-term memory. is.

[0096] <Combination of sensor unit and external circuit 1> The above-described configuration transmits and receives information to and from an external circuit 70 as shown in FIG. The above-described configuration can be configured to perform the following as shown in FIG. The external circuit 70 may be configured to receive information from the sensor unit 60. Alternatively, the signal may be output to an actuator or the like.

[0097] By using the configuration shown in Figure 7(A), it is possible to process signals (information) obtained from external sensors, etc. For example, biometric information such as brain waves, pulse, blood pressure, and body temperature can be recorded as brain waves. The information is acquired using various sensors such as pulse wave sensors, blood pressure sensors, and temperature sensors, and stored. The information obtained can instantly and comprehensively analyze complex changes in biological information. It is expected that you will be able to understand the situation.

[0098] Figure 7(B) shows the functions that can be realized by the semiconductor device shown in Figure 7(A) and the functions of the human brain. This is a schematic diagram for comparing functions.

[0099] In the sensor unit 60, the sensor element (for example, a photoelectric conversion element) corresponds to a human eye. The information output from the conversion element is input to a memory unit having an OS transistor. The present invention relates to a memory circuit formed of an OS transistor and a switching element formed of an OS transistor. It has a switching circuit.

[0100] The memory unit 10 is a memory element, and corresponds to the parts of the brain that control memory, such as the neocortex and hippocampus. The switching circuit corresponds to the part that transmits information, such as the optic nerve and axon. The memory unit 10 is configured to input and output information to and from an external circuit based on the information stored in the memory unit 10. can be done.

[0101] <Configuration Example 2 of Semiconductor Device> 8 is an example of a block diagram for explaining the configuration of a semiconductor device. The device includes a sensor unit 60, a control unit 50A, and a storage unit 10A. As an example, the memory circuit 26A, 26B, the switching circuit 31, and the input / output circuit 40 are included. do.

[0102] 8, one sensor unit 60, one control unit 50A, and one storage unit 10A are shown. However, a configuration may be adopted in which a plurality of memory circuits 26A, 26B, The switching circuit 31 and the input / output circuit 40 are not limited to the configuration shown in FIG. The configuration can be such that:

[0103] The memory circuit 26A has a plurality of memory circuits (memory circuits 27A to 27D are shown in FIG. 8). Each of the memory circuits 27A to 27D includes a plurality of memory elements. Although not shown, 27D to 27E have driver circuits for driving a plurality of memory elements. The drive circuit has a function of switching the signal waveform of the word signal in response to the control of the control unit 50A. The memory circuits 27A to 27D store information in accordance with the signal Se obtained by the sensor unit 60. It has the ability to change the information storage capacity. Note that information may be read as data. In the memory circuit, information is stored as a voltage value or an amount of charge according to the data. .

[0104] For example, the memory circuits 27A to 27D adjust their information storage capacity in accordance with the signal waveform of the word signal. For example, the memory circuit 27A has a memory element that can store information for a long period of time. The memory circuit 27B is configured to be a memory element capable of storing short-term information. It can be controlled by the control unit 50A.

[0105] The memory circuit 26B, like the memory circuit 26A, is configured with a plurality of memory circuits (memory circuits 28 in FIG. 8). Each of the memory circuits 28A to 28D includes a plurality of memory elements. Although not shown, the memory circuits 28A to 28D include a memory circuit for driving a plurality of memory elements. The drive circuit has a drive circuit for driving the word signal in response to the control of the control unit 50A. The memory circuits 28A to 28D have a function of switching the waveform. The information storage capacity can be changed according to the received signal Se.

[0106] For example, the memory circuits 28A to 28D adjust their information storage capacity in accordance with the signal waveform of the word signal. For example, the memory circuit 28A has a memory element that can store information for a long period of time. The memory circuit 28B is configured to be a memory element capable of storing short-term information. It can be controlled by the control unit 50A.

[0107] The memory circuits 26A and 26B can be applied to DOSRAM or NRAM. OSRAM is preferred.

[0108] In one embodiment of the present invention, NOSRAM or DOSRAM is used as the memory circuit 26A, 6B will be described, but one embodiment of the present invention is not limited to these. For example, with future technological innovations, non-volatile memories such as ReRAM and MRAM may become available. In some cases, such as when the power consumption when using the memory circuits 26A and 26B is sufficiently small, The configuration may be applied to each circuit of 6B.

[0109] The switching circuit 31 switches the electrical connection between the memory circuits 26A and 26B in response to control by the control unit 50A. For example, the memory circuits 27A to 27D and the memory circuit 28A 28D. That is, the memory circuit 28D has a function of controlling the amount of current flowing between the memory circuit 28D and the memory circuit 28D. The switching circuit 31 has a function of switching the transmission of the information obtained by the sensor unit 60. In response to the signal Se, the signals flow between the memory circuits 27A to 27D and the memory circuits 28A to 28D. The switching circuit 31 has a function of changing the amount of current flowing through it in accordance with the waveform of the word signal. These circuits are sometimes called reconfigurable circuits (reconfigurable circuits).

[0110] The switching circuit 31 controls the amount of current flowing between the memory circuits. The switching circuit 31 has a semiconductor element for passing a current according to the information stored in the The control unit 50A controls the signal waveform of the word signal to change the information stored in the memory element. In FIG. 8, the arrow between the memory circuits 26A and 26B is in one direction. Although the diagram shows arrows pointing to the right, depending on the flow of information, they may also be shown as two-way arrows. It is Noh.

[0111] The switching circuit 31 is a programmable device having OS transistors. In the present specification and drawings, a programmable device having an OS transistor is The information stored in the memory elements of the OS-FPGA is called S-FPGA. This is called ration data.

[0112] The OS-FPGA has a smaller memory area than FPGAs whose memory elements are composed of SRAM. Therefore, even if a context switching function is added, the area increase is small. In addition, OS-FPGA uses boosting to transmit data and parameters at high speed. It is possible.

[0113] The sensor unit 60 measures, for example, biological information such as brain waves, pulse, blood pressure, body temperature, etc. To acquire the information, various sensors such as brain wave sensor, pulse wave sensor, blood pressure sensor, and temperature sensor are used. FIG. 8 shows the output of a signal Se from one sensor. However, a configuration may be adopted in which signals obtained by a plurality of sensors are input to the control unit 50A.

[0114] The control unit 50A includes a CPU (Central Processing Unit), a GP Arithmetic circuits such as U (Graphics Processing Unit) and SRA M (Static Random Access Memory) or other storage circuits. The control unit 50A controls the signals WL_A to WL_B in response to the signal Se output from the sensor unit 60. The control unit 50A has a function of outputting WL_C. For example, the control unit 50A uses an artificial neural network (AINN) It is possible to perform output according to input by performing calculation processing based on the above.

[0115] The signals WL_A to WL_C are respectively output from the memory circuits 26A, 26B and the switching circuit 31. A signal (word signal) given to the gate electrode of a transistor included in the The D signal is a signal that can be switched. In FIG. 8, the state where the signal WL_A is output to the memory circuit 26A is illustrated. However, the signal WL_A is configured to control the memory circuits 27A to 27D or the memory elements included in the memory circuit 26A with different word signals. Similarly, the memory circuit 26B and the switching circuit 31 can also be configured to be controlled with different word signals for different memory circuits.

[0116] Note that the control unit 50A can switch the control of the signals WL_A to WL_C according to the signal Se output from the sensor unit 60. For example, when the same signal Se is repeatedly input, and when a signal Se with high or low intensity is input, the control of the signals WL_A to WL_C can be switched.

[0117] The input / output circuit 40 is a circuit for controlling the input / output of information to the memory circuit 26A, the memory circuit 26B, and the switching circuit 31. The input / output circuit 40 may be configured to be provided outside the memory unit 10A.

[0118] By adopting the configuration of the semiconductor device disclosed in this embodiment, the formation of long-term memory in the human brain and its process, and the formation of short-term memory and its process can be realized by a semiconductor device having OS transistors. Therefore, data can be stored with a function closer to that of the human brain than in the prior art. In addition, data retention can be realized with extremely low power. That is, it is possible to drive a brain-type processor with extremely low power consumption, similar to the human brain.

[0119] <Configuration Example 2 of NOSRAM and DOSRAM> The memory circuits 27A to 27D or 28A to 28D are circuits having OS transistors. An example of the circuit configuration and operation is shown in FIGS. 9(A) to 9(D) and FIG. This will be explained with reference to A) to (D).

[0120] FIG. 9A shows a circuit diagram of a memory element having a DOSRAM circuit configuration. FIG. 9A shows a transistor MT6, a capacitor C1, a word line WL, and a bit line BL. It shows.

[0121] The transistor MT6 is an OS transistor and is a three-terminal element having a gate electrode. The transistor MT6 may be a four-terminal element including a back gate electrode. The off-state current of the transistor MT6 is shown as Ioff. The node where the transistor MT6 and the capacitance element C1 are connected is called a node. This is shown as code FN.

[0122] The bit line BL has the function of transmitting information (data, data potential) to be written to the memory element. The word line WL also controls the transistor MT6 to be turned on or off in response to the control of the control unit 50A. It has the function of transmitting a signal (word signal) to control the power ratio (corresponding to the length of the ON time). The bit lines BL and word lines WL may be simply referred to as wiring.

[0123] The word signal given to the word line WL is, for example, a signal from the memory elements of the memory circuits 27A to 27D. The control unit 50A controls the potentials of the elements to be different for each element. is stored in the memory circuit 26B. The signal W is designated as WL_1, and the word signal when the information is stored in the memory circuit 27C is designated as WL_2. L_0 to WL_2 are signals with different on-times T0 to T2 as shown in FIG. 9(B). It can be expressed as:

[0124] The potential held at the node FN varies depending on the ON time T0 to T2 shown in FIG. 9(B). For example, during the on-time T0, the potential of the node FN is VFN_0, and during the on-time T In the case of 1, the potential of the node FN is the potential VFN_1, and in the case of the on-time T2, the potential of the node FN is If the potential VFN_2 is the potential VFN_3, the magnitude relationship is as shown in the graph in FIG. The potential changes over time, and the time it takes to reach a given potential (V0) varies ( (See time t0 to t2 in FIG. 9C). In other words, the shorter the ON time, the greater the amount of charge held at node FN. The potential easily fluctuates in a short period of time, and the longer the on time, the more the potential held at node FN fluctuates. As a result, it is possible to create a difference in the data retention period for each memory circuit.

[0125] With this configuration, the memory circuits 27A to 27D or 28A to 28D can The function of storing information with different storage capacities is realized according to the signal Se obtained by the unit 60. .

[0126] FIG. 9D is a flowchart illustrating the operation of the DOSRAM described above. show.

[0127] In step S31, a word signal to be applied to the word line WL is set as WL_1 and is written to the memory circuit. Store information.

[0128] In step S32, the word signal to be applied to the word line WL is set to WL_1, and the information is periodically If the off-current is low enough, The information refresh may be omitted.

[0129] In step S33, it is determined whether or not the signal Se output from the sensor unit 60 has changed. The presence or absence of a sensor signal is determined by setting multiple thresholds and comparing the thresholds with the sensor output. It is preferable to configure the word signal to be on-time controlled according to the relationship.

[0130] If there is a change in step S33, the process proceeds to step S34, and the power supply with the longer ON time is selected. The information is stored in the memory circuit as a code signal WL_2. The word signal is switched so that the information retention time is increased.

[0131] If there is no or only a small change in step S33, the process proceeds to step S35. The word signal applied to the line WL is set to WL_0 with a short on time, and information is stored in the memory circuit. In other words, the word signal is switched so as to shorten the time for which information is held in the memory circuit.

[0132] By adopting this configuration, it is possible to store information with different storage capacities according to the output of the sensor unit. For example, if the sensor part is a temperature sensor, it can measure the information at high or low temperatures. The brain has the ability to retain information for a long period of time, while information stored at room temperature is forgotten after a certain period of time. It can be realized.

[0133] FIG. 10A shows a circuit diagram of a memory element having a NOSRAM circuit configuration. In FIG. 10A, transistor MT7, transistor MT8, word line WL, bit The line BL is shown.

[0134] The transistor MT7 is an OS transistor and is a three-terminal element having a gate electrode. The transistor MT7 may be a four-terminal element including a back gate electrode. The off-state current of the transistor MT7 is shown as Ioff. The node between the gates of the transistors MT7 and MT8 is connected. The wiring node is illustrated as node FN.

[0135] In FIG. 10A, the transistor MT8 is shown as a p-channel type. In addition, in FIG. 10(A), a 2T type having two transistors is shown. As shown in the figure, it is a 2T1C type with a capacitance element added, or a combination with another transistor. The capacitance element connected to the node FN can be a 3T type. This can be omitted by increasing the parasitic capacitance such as the gate capacitance of the transistor MT3.

[0136] The word signal given to the word line WL is, for example, a signal from the memory elements of the memory circuits 27A to 27D. The control unit 50A controls the potentials of the elements to be different for each element. is stored in the memory circuit 27B. The signal W is designated as WL_1, and the word signal when the information is stored in the memory circuit 27C is designated as WL_2. L_0 to WL_2 are signals with different on-times T0 to T2 as shown in FIG. 10(B). It can be expressed as:

[0137] The potential held at the node FN in accordance with the on-times T0 to T2 shown in FIG. 10(B) For example, during the on-time T0, the potential of the node FN is VFN_0, and during the on-time T1, the potential of the node FN is VFN_1. During the on-time T1, the potential of the node FN is VFN_1, and during the on-time T2, the potential of the node FN is VFN_2. If the potential is VFN_2, the magnitude relationship is as shown in the graph in FIG. 10(C). The potential of changes over time, and the time it takes to reach a given potential (V0) varies. (See time t0 to t2 in FIG. 10C). In other words, the shorter the ON time, the more the voltage stored in the node FN. The potential held at node FN tends to fluctuate in a short period of time, and the longer the on-time, the As a result, the data retention period can be varied for each memory circuit. .

[0138] With this configuration, the memory circuits 27A to 27D or 28A to 28D can The function of storing information with different storage capacities is realized according to the signal Se obtained by the unit 60. .

[0139] FIG. 10D is a flowchart for explaining the operation of the NOSRAM described above. Shows.

[0140] In step S41, a word signal to be applied to the word line WL is set as WL_1 and is written to the memory circuit. Store information.

[0141] In step S42, the word signal to be applied to the word line WL is set to WL_1, and the information is periodically If the off-current is low enough, The information refresh may be omitted.

[0142] In step S43, it is determined whether or not the signal Se output from the sensor unit 60 has changed. The presence or absence of a sensor signal is determined by setting multiple thresholds and comparing the thresholds with the sensor output. It is preferable to configure the word signal to be on-time controlled according to the relationship.

[0143] If there is a change in step S43, the process proceeds to step S44, and the voltage applied to the word line WL is The word signal is set to WL_2, which has a longer on time, and information is stored in the memory circuit. The word signal is switched so that the information retention time in the memory circuit is increased.

[0144] If there is no or only a small change in step S43, the process proceeds to step S45. The word signal given to the word line WL is set to WL_0 with a short on time, and information is stored in the memory circuit. In other words, the word signal is switched so that the retention time of information in the memory circuit is shortened. .

[0145] By adopting this configuration, it is possible to store information with different storage capacities according to the output of the sensor unit. For example, if the sensor part is a temperature sensor, it can measure the information at high or low temperatures. The brain has the ability to retain information for a long period of time, while information stored at room temperature is forgotten after a certain period of time. It can be realized.

[0146] <Switching circuit configuration example 2> The switching circuit 31 has a circuit configuration including OS transistors. For an example of this, see FIGS. 11(A) to 11(C), 12, and 13(A) to 13(D). and explain.

[0147] FIG. 11A shows a circuit configuration of a switching circuit 31 disposed between a pair of memory circuits. 11A shows a circuit diagram of a memory element. The figure shows the master MT10, word line WL, bit line BL, input terminal IN, and output terminal OUT. There are.

[0148] The transistor MT9 is an OS transistor and is a three-terminal element having a gate electrode. The transistor MT9 may be a four-terminal element including a back gate electrode. The off-state current of the transistor MT9 is shown as Ioff. The node where the transistors MT9 and MT10 are connected is The node of the wiring is shown as node FN.

[0149] The transistor MT10 is a Si transistor or an OS transistor. The current flowing through the transistor MT10 according to the potential of FN, that is, the current flowing through the input terminal IN and the output terminal The current flowing between OUT is shown as Idata.

[0150] In FIG. 11A, the transistor MT10 is a p-channel type, but it can be an n-channel type. Also, in FIG. 11(A), a 2T type having two transistors is illustrated. However, there are 2T1C types with added capacitance elements, or 3T types combined with other transistors. The capacitor connected to the node FN can be set as follows: It can be omitted by increasing the parasitic capacitance such as the gate capacitance of 0.

[0151] The word signal given to the word line WL is, for example, one of the memory circuits 27A to 27D. Each switching circuit provided between the wiring and any one of the memory circuits 28A to 28D has a different For example, the memory circuit 27A and the memory circuit 28A are controlled by the control unit 50A as a potential. A word signal of the transistor MT9 of the switching circuit provided between , a transistor included in a switching circuit provided between the memory circuit 27B and the memory circuit 28B The word signal of the memory circuit MT9 is WL_1, and the word signal of the memory circuit MT9 is WL_2. The word signal of the transistor MT9 in the switching circuit is designated as WL_2. WL_1 to WL_2 are represented as signals with different ON times T0 to T2 as shown in FIG. 11(B). It is possible.

[0152] The potential held at the node FN according to the on-times T0 to T2 shown in FIG. 11(B) The longer the on-time, the more easily the potential held at node FN fluctuates. The shorter the time, the less likely the potential held at node FN is to fluctuate. If the potential is maintained, the potential of node FN (V FN ) difference Therefore, a difference occurs in the current Idata that flows depending on the potential of the node FN. As a result, it is possible to generate a difference in the amount of current flowing between the memory circuits for each memory circuit.

[0153] With this configuration, any one of the memory circuits 27A to 27D and the memory circuits 28A to 28D can be used. The switching circuit provided between the wiring between the sensor unit 60 and any one of the sensors 28D is This realizes a function of generating a difference in the amount of current flowing between the memory circuits in accordance with the signal Se.

[0154] FIG. 11C is a flowchart for explaining the operation of the switching circuit described above. Shows.

[0155] In step S51, the node FN is set to the L level, that is, the data where the current Idata does not flow. The bit line BL is set to H level.

[0156] In step 52, the word signal to be applied to the word line WL is set to WL_0, and the node FN is set to The fluctuation of the held potential is reduced.

[0157] In step S53, it is determined whether or not the signal Se output from the sensor unit 60 has changed. The presence or absence of a sensor signal is determined by setting multiple thresholds and comparing the thresholds with the sensor output. It is preferable to configure the word signal to be on-time controlled according to the relationship.

[0158] If there is a change in step S53, the process proceeds to step S54, and the voltage applied to the word line WL is The word signal is WL_1. In other words, the potential held at the node FN is increased. When the word signal is turned on, the current Idata flowing between the memory circuits is increased. If there is no or only a small change in step S53, step S52 is executed. Continue.

[0159] In step S55, it is determined whether or not the signal Se output from the sensor unit 60 has changed. The presence or absence of a sensor signal is determined by setting multiple thresholds and comparing the thresholds with the sensor output. It is preferable to configure the word signal to be on-time controlled according to the relationship.

[0160] If there is a change in step S55, the process proceeds to step S56, and the word signal is set to WL_2 In other words, the fluctuation of the potential held at the node FN is controlled to be larger, and the The ON time of the word signal is controlled so that the current Idata flowing between the memory circuits becomes even larger. If there is no or only a small change in step S55, continue with step S54. .

[0161] 11A to 11C show an example of a configuration for controlling the ON time of the word signal. However, other configurations are also possible. For example, as shown in FIG. In the example shown in FIG. When a is made smaller, the frequency of the signal given as the word signal is made smaller. The signal WL_0 of FIG. 12 is configured to be at H level for each period T11. When the data is increased, the frequency of the signal given as the word signal is increased. That is, the signal WL_1 in FIG. 12 is configured to be at H level every period T12. If the current Idata is to be further increased, the frequency of the signal given as the word signal should be further increased. In other words, the signal WL_2 in FIG. 12 is set to H level every period T13. Make it into a configuration.

[0162] By adopting this configuration, the amount of current flowing between the memory circuits can be varied depending on the output of the sensor unit. For example, if the sensor is a temperature sensor, it can detect the temperature at high or low temperatures. This function activates signal transmission at room temperature and inactivates signal transmission at room temperature. It is possible.

[0163] 13A to 13D show data storage in a semiconductor device of one embodiment of the present invention. This is a diagram for explanation, modeled on the human brain.

[0164] In FIG. 13A, information is held in the memory circuit 27A as an initial state (shown by a solid line). The transfer of information by the switching circuit 31 is inactive (a state in which the amount of current flowing between the memory circuits is small; point Indicated by arrows) and no information is stored in the memory circuits 28A to 28C (indicated by dotted lines). ) state is illustrated.

[0165] In the semiconductor device according to one aspect of the present invention, the switching circuit 31 is This activates the transmission of information between memory circuits (a state in which a large amount of current flows between memory circuits; indicated by solid arrows). Therefore, as shown in FIG. 13(B), the memory circuit 2 8A to 28C to retain the information stored in the memory circuit 27A (shown by solid lines). is possible.

[0166] In the semiconductor device of one embodiment of the present invention, the memory circuit 28A It is possible to switch to erase the information in 28C (to shorten the retention period). Therefore, as shown in FIG. 13C, the memory circuit 28B by the switching circuit 31 and 28C are switched to a state in which transmission of information to the memory circuits 28B and 28C is inactivated. In C, the information stored is switched to short-term memory (shown by the thin dotted line). It is possible.

[0167] In the semiconductor device of one embodiment of the present invention, the memory circuit 28A In addition to eliminating (shortening the retention period) information in 28C, it also strengthens it. Therefore, as shown in FIG. 13(D), In this way, the switching circuit 31 can transmit information to the memory circuits 28B and 28C more efficiently. Activated state (state in which the amount of current flowing between memory circuits is larger; indicated by thick arrows), memory The transmission of information to the circuits 28B and 28C is switched to an inactive state, and the memory circuit 28A The information stored in the memory is then transferred to long-term memory (shown by the thick solid line), or the memory circuit 28B and 28C allow information that has been retained to be transferred to short-term memory. It is Noh.

[0168] <Combination of sensor unit and external circuit 2> The above-described configuration is used for transmitting and receiving information to and from an external circuit 70 as shown in FIG. The above-described configuration can be configured to perform the signal transmission as shown in FIG. The external circuit 70 can be configured to receive information from the sensor unit 60 as shown in FIG. The signal may be output to a device or an actuator.

[0169] By using the configuration shown in FIG. 14(A), signals (information) obtained from external sensors etc. can be processed. For example, biometric information such as brain waves, pulse, blood pressure, and body temperature can be recorded in the brain. It acquires information from various sensors such as wave sensors, pulse wave sensors, blood pressure sensors, and temperature sensors, and records the information. The information obtained can instantly and comprehensively analyze complex changes in biological information. It is expected that this will enable us to grasp the following:

[0170] FIG. 14(B) shows the functions that can be realized by the semiconductor device shown in FIG. 14(A) and the human brain circumference. This is a schematic diagram for comparing the functions of edges.

[0171] In the sensor unit 60, the sensor element (for example, a photoelectric conversion element) corresponds to a human eye. The information output from the conversion element is input to a memory unit having an OS transistor. The present invention relates to a memory circuit formed of an OS transistor and a switching element formed of an OS transistor. It has a switching circuit.

[0172] The memory unit 10 is a memory element, and corresponds to the parts of the brain that control memory, such as the neocortex and hippocampus. The switching circuit corresponds to the part that transmits information, such as the optic nerve and axon. The memory unit 10 is configured to input and output information to and from an external circuit based on the information stored in the memory unit 10. can be done.

[0173] <Application examples of semiconductor devices> An application example of an electronic device to which the semiconductor device described in the above embodiment can be applied is shown in FIG. The following description will be given using (A) to (D). One embodiment of the present invention is a portable electronic device, for example, a smartphone. The present invention is applicable to information terminals such as smartphones and notebook personal computers.

[0174] A portable information terminal 2910 shown in FIG. 15A includes a housing 2911, a display portion 2912, a microphone, and a microphone amplifier. 2917, speaker unit 2914, camera 2913, external connection unit 2916, and operation The display portion 2912 includes a switch 2915 and a display panel using a flexible substrate. The information terminal 2910 has an access point inside the housing 2911. The information terminal 2910 is, for example, a smartphone, a mobile phone, or the like. Telephones, tablet information terminals, tablet personal computers, e-book terminals, etc. It can be used as follows.

[0175] Note that one embodiment of the present invention can be applied to a portable information terminal, but it can also be applied to an autonomous vehicle such as a car or a robot. This can also be applied to other mobile objects.

[0176] The cleaning robot 2920 shown in FIG. 15(B) includes a housing 2921, a display unit 2922, an operation button The sensor includes a tongue 2923, a plurality of cameras 2924 arranged on the side, and a brush 2925. Although not shown, the cleaning robot 2920 has tires, a suction port, etc. on its underside. The cleaning robot 2920 is also equipped with an infrared sensor, an ultrasonic sensor, It is equipped with various sensors such as a speed sensor, a piezoelectric sensor, an optical sensor, and a gyro sensor. The cleaning robot 2920 also includes wireless communication means.

[0177] In addition, the cleaning robot 2920 analyzes the images taken by the camera 2924 and detects the walls, furniture, or It can also detect obstacles such as steps and other obstacles by analyzing images. If an object that may become entangled in the brush 2925 is detected, the rotation of the brush 5103 will be stopped. can be done.

[0178] The display 5101 can display the remaining battery level and the amount of dust that has been sucked up. The route traveled by the cleaning robot 2920 may be displayed on the display unit 2922. .

[0179] The robot 2100 shown in FIG. 15(C) includes a computing device 2110, an illuminance sensor 2101, a Microphone 2102, upper camera 2103, speaker 2104, display 2105 , a lower camera 2106, an obstacle sensor 2107, and a movement mechanism 2108.

[0180] In the robot 2100, a computing device 2110, an illuminance sensor 2101, an upper camera 21 03, a display 2105, a lower camera 2106, an obstacle sensor 2107, etc. The semiconductor device can be used.

[0181] The microphone 2102 has a function of detecting the user's voice and environmental sounds. The speaker 2104 has a function of emitting sound. The phone 2102 and the speaker 2104 are used to communicate with the user. is possible.

[0182] The display 2105 has the function of displaying various information. The robot 2100 can display the information desired by the user on the display 2105. The display 2105 may be equipped with a touch panel.

[0183] The upper camera 2103 and the lower camera 2106 have the function of imaging the surroundings of the robot 2100. Also, the obstacle sensor 2107 can detect the presence or absence of obstacles in the traveling direction when the robot 21 00 moves forward. The robot 2 100 can recognize the surrounding environment and move safely by using the upper camera 2103, the lower camera 2106, and the obstacle sensor 2107.

[0184] The flying object 2120 shown in FIG. 15(D) has an arithmetic unit 2121, a propeller 2123, and a camera 2122, and has the function of flying autonomously.

[0185] In the flying object 2120, the above semiconductor device can be used for the arithmetic unit 2121 and the camera 2122.

[0186] FIG. 15(D) is an external view showing an example of an automobile. The automobile 2980 has a camera 298 1 and the like. Also, the automobile 2980 is equipped with various sensors such as an infrared radar, a millimeter-wave radar, and a laser radar. The automobile 2980 analyzes the image captured by the camera 2981, determines the surrounding traffic conditions such as the presence or absence of a guardrail 1201 or pedestrians, and can perform automatic driving.

[0187] <Configuration example of OS transistor> The semiconductor device shown in FIG. 16 includes a transistor 300, a transistor 500, and a capacitor element 18A is a cross-sectional view of the transistor 500 in the channel length direction. 18(B) is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 18( 4C) is a cross-sectional view of the transistor 300 in the channel width direction.

[0188] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). Since the off-state current of the transistor 500 is small, it is By using it in the OS transistors of In other words, it is possible to perform refresh operations less frequently or Since no clock operation is required, the power consumption of the semiconductor device can be reduced.

[0189] The semiconductor device described in this embodiment includes a transistor 300, a transistor 301, and a transistor 302 as shown in FIG. The transistor 500 has a capacitance element 600. The capacitor 600 is provided above the transistor 300 and the transistor 500. It is set up in.

[0190] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate a semiconductor region 313 formed of a part of the semiconductor region 311; The transistor 300 has a resistive region 314a and a low resistive region 314b. For example, the present invention can be applied to the transistors in the above embodiments.

[0191] As shown in FIG. 18C, the transistor 300 is formed by forming a semiconductor region 313 on the upper surface and the channel. The side surfaces in the width direction of the panel are covered with conductors 316 via insulators 315. By making the transistor 300 a fin type, the effective channel width is increased. This can improve the on-state characteristics of the transistor 300. Since the contribution can be increased, the off-state characteristics of the transistor 300 can be improved. Cut.

[0192] The transistor 300 may be either a p-channel type or an n-channel type. .

[0193] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are to be the drain region, silicon It is preferable that the material contains a semiconductor such as a silicon-based semiconductor, and it is preferable that the material contains single crystal silicon. are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium arsenide). Alternatively, the insulating layer 12 may be formed of a material containing gallium aluminum arsenide (GaAlAs), GaAlAs (gallium aluminum arsenide), or the like. It uses silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 30 may be formed by using GaAs and GaAlAs. 0 stands for HEMT (High Electron Mobility Transistor) ) can also be used.

[0194] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the material, elements that give n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. It contains an element that provides electrical conductivity.

[0195] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used.

[0196] Since the work function is determined by the material of the conductor, it is necessary to select the material of the conductor. Specifically, the conductor is made of nitride silicon, and the threshold voltage of the transistor can be adjusted. It is preferable to use materials such as tantalum or tantalum nitride. To achieve this, metal materials such as tungsten and aluminum are used as layers for the conductor. It is preferable to use tungsten, in particular, in terms of heat resistance.

[0197] The transistor 300 shown in FIG. 16 is an example, and the structure is not limited to this. An appropriate transistor may be used depending on the structure and driving method. In the case of a unipolar circuit using only transistors, the structure of transistor 300 is as shown in FIG. The structure of the transistor 500 may be similar to that of the transistor 500 including an oxide semiconductor. The transistor 500 will be described in detail below.

[0198] Over the transistor 300 are insulators 320, 322, 324, and The bodies 326 are stacked one on top of the other.

[0199] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0200] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0201] The insulator 322 serves to eliminate a step caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process using chemical mechanical polishing (CMP) or other methods. It may be possible.

[0202] The insulator 324 is also provided with a substrate 311 or a transistor 300, etc. A film having a barrier property that prevents diffusion of hydrogen and impurities is used in the area where the capacitor 500 is provided. It is preferable that

[0203] An example of a film having a barrier property against hydrogen is silicon nitride formed by CVD. Here, a semiconductor having an oxide semiconductor such as the transistor 500 can be used. The diffusion of hydrogen into semiconductor elements can cause a deterioration in the characteristics of the semiconductor elements. Therefore, a film that suppresses hydrogen diffusion is provided between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that reduces the amount of hydrogen desorption. The membrane is thin.

[0204] The amount of hydrogen desorption can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorbed from the insulator 324 can be determined by TDS analysis as follows: In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to a hit, it's 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 a toms / cm 2 The following is fine.

[0205] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulator 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. can be reduced.

[0206] The insulators 320, 322, 324, and 326 are connected to the capacitance element 6. 00, or the conductor 328 and the conductor 330 connected to the transistor 500 are embedded. The conductors 328 and 330 function as plugs or wiring. In addition, the conductors that function as plugs or wiring are grouped together to form the same structure. In addition, in this specification and the like, a wiring and a plug connected to the wiring may be In other words, when a part of the conductor functions as a wiring, In some cases, a portion of the conductor functions as a plug.

[0207] The materials for each plug and wiring (conductor 328, conductor 330, etc.) include metal materials, alloys, and the like. Conductive materials such as gold, metal nitride, or metal oxide materials are used in a single layer or multilayer. High-melting-point materials such as tungsten and molybdenum, which are both heat-resistant and conductive, are used. It is preferable to use tungsten. Alternatively, aluminum or It is preferable to form the wiring layer from a low-resistance conductive material such as copper. The wiring resistance can be reduced.

[0208] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 300. The conductor 356 is made of the same material as the conductors 328 and 330. It is possible.

[0209] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0210] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0211] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0212] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0213] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. An insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed on the insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0214] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. In particular, an insulator 370 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0215] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. An insulator 380, an insulator 382, and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed on the insulators 380, 382, and 384. The conductor 386 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0216] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulator 380 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0217] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the conductor 376 The wiring layer including the conductor 386 has been described above. The semiconductor device is not limited to this. Alternatively, the number of wiring layers may be three or less, or five or more wiring layers similar to the wiring layer including the conductor 356 may be provided. Good too.

[0218] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are formed. , are stacked in this order. It is preferable that any of the bodies 516 is made of a material that has a barrier property against oxygen and hydrogen. .

[0219] For example, the insulator 510 and the insulator 514 may include, for example, the substrate 311 or the transistor. Hydrogen and impurities diffuse from the region where the capacitor 300 is provided to the region where the transistor 500 is provided. It is preferable to use a film having a barrier property that prevents the diffusion of the insulator 324. The same materials as those mentioned above can be used.

[0220] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor, such as the transistor 500, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen. do.

[0221] In addition, as a film having a barrier property against hydrogen, for example, an insulator 510 and an insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0222] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0223] For example, the insulators 512 and 516 may be made of the same material as the insulator 320. In addition, by using materials with a relatively low dielectric constant for these insulators, , the parasitic capacitance occurring between the wirings can be reduced. A silicon oxide film, a silicon oxynitride film, or the like can be used as the film 516 .

[0224] In addition, the insulators 510, 512, 514, and 516 are provided with conductors 5 18, and conductors (for example, conductor 503) that constitute the transistor 500 are embedded. Note that the conductor 518 is connected to the capacitor 600 or the transistor 300. The conductor 518 functions as a plug or a wiring. It can be provided using the same material as 30.

[0225] In particular, the insulator 510 and the conductor 518 in the area in contact with the insulator 514 are free of oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 300 and the transistor 500 have barrier properties against oxygen, hydrogen, and water. The layer can be separated, and hydrogen diffusion from transistor 300 to transistor 500 can be suppressed.

[0226] Above the insulator 516 is the transistor 500 .

[0227] As shown in FIGS. 18A and 18B, the transistor 500 includes an insulator 514 and a A conductor 503 disposed so as to be embedded in an insulator 516, and a conductor 503 disposed so as to be embedded in an insulator 516 ... An insulator 520 disposed on the insulator 503, and an insulator 522 disposed on the insulator 520. , an insulator 524 disposed on the insulator 522, and an oxide layer disposed on the insulator 524. 530a, an oxide 530b disposed on the oxide 530a, and an oxide 530b disposed on the oxide 530b. Conductor 542a and conductor 542b are spaced apart from each other, and conductor 542a and conductor 542b, and an opening is formed between and overlapping the conductors 542a and 542b. The insulating layer 580 is formed on the bottom and side surfaces of the opening, and the oxide 530c is formed on the bottom and side surfaces of the opening. an insulator 550 disposed on the surface of the insulator 550; and a conductor 560 disposed on the surface of the insulator 550. and,

[0228] As shown in FIGS. 18(A) and 18(B), oxide 530a, oxide 530b, An insulator 544 is disposed between the conductor 542a and the insulator 580 and between the conductor 542b and the insulator 580. As shown in FIG. 18(A) and FIG. 18(B), the conductor 560 is A conductor 560a is provided inside the insulator 550, and a It is preferable to have a conductor 560b provided so as to As shown in FIG. 18B, an insulator 580, a conductor 560, and an insulator 550 are disposed on the insulator 580. Preferably, the body 574 is disposed.

[0229] In the following, the oxide 530a, the oxide 530b, and the oxide 530c will be collectively referred to as oxides 530a, 530b, and 530c. It is sometimes called oxide 530.

[0230] In the transistor 500, an oxide is formed in the region where the channel is formed and in the vicinity thereof. 5 shows a structure in which three layers of oxide 530a, oxide 530b, and oxide 530c are stacked. However, the present invention is not limited to this. For example, a single layer of oxide 530b, an oxide a two-layer structure of oxide 530b and oxide 530a; a two-layer structure of oxide 530b and oxide 530c; Alternatively, a stacked structure of four or more layers may be provided. Although the conductive body 560 is shown as a two-layer laminated structure, the present invention is not limited to this. For example, the conductor 560 may have a single layer structure or a laminated structure of three or more layers. The transistor 500 shown in FIGS. 16 and 18A is just an example, and the structure There are no limitations, and appropriate transistors may be used depending on the circuit configuration and driving method.

[0231] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and The conductor 542b functions as a source electrode and a drain electrode, respectively. The conductor 560 is sandwiched between the opening of the insulator 580 and the conductors 542a and 542b. The conductor 560, the conductor 542a, and the conductor 542b are formed so as to be embedded in the region. The placement of 42b is selected to be self-aligned with the opening of the insulator 580. In the transistor 500, the gate electrode is self-aligned between the source electrode and the drain electrode. Therefore, the conductor 560 can be positioned with a margin for alignment. Since the transistor 500 can be formed without any additional wiring, the area occupied by the transistor 500 can be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0232] Furthermore, the conductor 560 is self-aligned in the region between the conductors 542a and 542b. Since the conductor 560 is formed, the conductor 560 has an overlapping region with the conductor 542a or the conductor 542b. As a result, the gap formed between the conductor 560 and the conductors 542a and 542b is Therefore, the switching speed of the transistor 500 can be improved. This improves the sound quality and provides high frequency characteristics.

[0233] Conductor 560 may function as a first gate (also called top gate) electrode. In addition, the conductor 503 may function as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 503 is connected to the potential applied to the conductor 560. By independently varying the threshold voltage of the transistor 500, the threshold voltage of the transistor 500 can be controlled. In particular, applying a negative potential to the conductor 503 can turn on the transistor 500. It is possible to increase the threshold voltage above 0V and reduce the off-state current. When a negative potential is applied to the conductor 503, the amount of charge applied to the conductor 560 is larger than when no negative potential is applied. The drain current can be reduced when the applied potential is 0V.

[0234] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, The electric field and the electric field generated by the conductor 503 are connected, and a channel is formed in the oxide 530. In this specification and the like, the first gate electrode and the second gate electrode The structure of a transistor in which the channel formation region is electrically surrounded by the electric field of the electrodes is called su This is called a rounded channel (S-channel) structure.

[0235] The conductor 503 has the same structure as the conductor 518, and the insulators 514 and 5 Conductor 503a is formed in contact with the inner wall of opening 16, and conductor 503b is formed further inside. In the transistor 500, the conductor 503a and the conductor 503b are stacked. However, the present invention is not limited to this. The body 503 may be configured as a single layer or a laminated structure of three or more layers.

[0236] Here, the conductor 503a is a diffusion layer for impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing the impurities (i.e., the impurities are less likely to permeate). Or, the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material that has the above-mentioned function (which is difficult for oxygen to permeate). In the specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the impurities or oxygen. The function is to suppress the diffusion of any one or all of the above.

[0237] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503 This can prevent b from being oxidized and the electrical conductivity from decreasing.

[0238] When the conductor 503 also functions as a wiring, the conductor 503b is made of tungsten, copper, or the like. It is preferable to use a conductive material having high conductivity, such as aluminum or aluminum-based material. In this case, the conductor 505 is not necessarily provided. Although shown in the figure, it may have a laminated structure, for example, titanium, titanium nitride and the above conductive material. It may also be laminated.

[0239] The insulators 520, 522, 524, and 550 form a second gate insulating film. It has the function as.

[0240] Here, the insulator 524 in contact with the oxide 530 has more oxygen than the stoichiometric composition. It is preferable to use an insulator that contains a large amount of oxygen. That is, the insulator 524 has an excess oxygen region. It is preferable that the insulator containing such excess oxygen is formed in the oxide 530. By providing the oxide 530 in contact with the oxide 530, oxygen vacancies in the oxide 530 are reduced, and the signal quality of the transistor 500 is improved. Reliability can be improved.

[0241] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are called TDS (Th Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen atoms The converted amount of oxygen desorption is 1.0 x 10 18 atoms / cm 3 or more, preferably 1.0 x10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / c m 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower. The temperature range is preferably from 0°C to 400°C.

[0242] Also, if the insulator 524 has an excess oxygen region, the insulator 522 may be oxygen-rich (e.g., It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (the oxygen is less likely to permeate) It is preferable that:

[0243] The insulator 522 has a function of suppressing the diffusion of oxygen and impurities, and the oxide 530 The oxygen contained in the conductor 503 is preferably not diffused to the insulator 520 side. This can prevent the insulator 524 and the oxide 530 from reacting with oxygen.

[0244] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, aluminum and hafnium oxide. oxides containing ammonium (hafnium aluminate), tantalum oxide, zirconium oxide, titanium Lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba Insulators containing so-called high-k materials such as (Sr, Sr)TiO3 (BST) are used as single layers or laminated layers. As transistors become smaller and more highly integrated, the gate insulating layer Thinning the film can cause problems such as leakage current. Functions as a gate insulating film By using a high-k material as the insulator, the transistor behavior can be improved while maintaining the physical thickness. This makes it possible to reduce the gate potential during operation.

[0245] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to penetrate) ) Use an insulator containing oxide of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an oxide of aluminum or hafnium as an insulator. Aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use a material such as aluminum aluminate. When formed, the insulator 522 prevents oxygen from being released from the oxide 530 and prevents the transistor 500 from being damaged. The layer functions as a layer that suppresses the intrusion of impurities such as hydrogen from the surrounding area into the oxide 530.

[0246] Alternatively, for example, aluminum oxide, bismuth oxide, or germanium oxide may be added to these insulators. aluminum, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Alternatively, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the edge.

[0247] The insulator 520 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are suitable because they are thermally stable. By combining the insulating layer with silicon oxide or silicon oxynitride, thermal stability and It is possible to obtain a laminated insulator 520 with a high dielectric constant.

[0248] In the transistor 500 shown in FIGS. 18A and 18B, the second gate electrode has a three-layer laminate structure. As the gate insulating film, an insulator 520, an insulator 522, and an insulator 524 are shown. The second gate insulating film may have a single layer, two layers, or a laminated structure of four or more layers. In this case, the laminate structure is not limited to a laminate structure made of the same material, and may be a laminate structure made of different materials.

[0249] The transistor 500 includes an oxide 530 including a channel formation region, and an oxide semiconductor It is preferable to use a functional metal oxide. For example, the oxide 530 is In-M- Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryl Sodium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, la tantalum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use a metal oxide such as one or more selected from the following. The In-M-Zn oxides that can be used as 0 are CAAC-OS and CAC-OS. It is also preferable to use In-Ga oxide or In-Zn oxide as the oxide 530. Good too.

[0250] The metal oxide that functions as the channel forming region in the oxide 530 has a band gap It is preferable to use one having a value of 2 eV or more, preferably 2.5 eV or more. The use of metal oxides with wide band gaps reduces the off-state current of transistors. It is possible.

[0251] The oxide 530 has an oxide 530a under the oxide 530b, so that the oxide 530a The diffusion of impurities from structures formed below the oxide 530b can be suppressed. In addition, by having the oxide 530c on the oxide 530b, the oxide 530c can be formed. Therefore, the diffusion of impurities from the structure formed above into the oxide 530b can be suppressed. do.

[0252] The oxide 530 has a layered structure made of oxides with different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the constituent elements are preferably The atomic ratio of element M in the oxide 530b is It is preferable that the atomic ratio of the metal oxide used for the oxide 530a is larger than that of the element M. In the oxide 530b, the atomic ratio of the element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In. The oxide 530c is a metal oxide that can be used for the oxide 530a or the oxide 530b. can be used.

[0253] The energy of the conduction band minimum of the oxide 530a and the oxide 530c is It is preferable that the energy of the oxide is higher than the energy of the bottom of the conduction band of oxide b. The electron affinity of oxide 530a and oxide 530c is smaller than that of oxide 530b. It is preferable that:

[0254] Here, at the junctions of the oxide 530a, the oxide 530b, and the oxide 530c, The energy level of the lower conduction band edge changes gradually. The energy levels of the conduction band minimum at the junction of 530b and oxide 530c are continuous. In order to achieve this, the oxide 530 The interface between oxide 530a and oxide 530b, and the interface between oxide 530b and oxide 530c are It is preferable to lower the defect level density of the resulting mixed layer.

[0255] Specifically, oxide 530a and oxide 530b, and oxide 530b and oxide 530c are By having a common element other than oxygen (as the main component), a mixed layer with low defect level density is formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and oxide 530c are In-Ga-Zn oxide, Ga-Zn oxide, oxide Gallium or the like may be used.

[0256] At this time, the main path of the carriers is the oxide 530b. By configuring the oxide 530c as described above, the interface between the oxide 530a and the oxide 530b and the oxide The defect state density at the interface between the substrate 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 has a high On-current can be obtained.

[0257] On the oxide 530b, a conductor 542a is formed, which functions as a source electrode and a drain electrode. The conductors 542a and 542b are provided. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, ungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium , beryllium, indium, ruthenium, iridium, strontium, and lanthanum The metal elements mentioned above, or alloys containing the above metal elements, or combinations of the above metal elements It is preferable to use an alloy of tantalum nitride, titanium nitride, tungsten nitride, etc. titanium and aluminum nitrides, tantalum and aluminum nitrides, and titanium oxides Ruthenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel It is preferable to use oxides containing titanium. Nitrides containing tantalum and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide , ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel Oxides are conductive materials that are resistant to oxidation or that maintain conductivity even after absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride have low resistance to hydrogen or oxygen. It is preferable because it has barrier properties.

[0258] In addition, in FIGS. 18A and 18B, the conductor 542a and the conductor 542b are formed as a single layer. However, it may be a laminated structure of two or more layers. For example, a tantalum nitride film and a tantalum Alternatively, a titanium film and an aluminum film may be stacked. , a two-layer structure in which an aluminum film is laminated on a tungsten film, copper-magnesium-aluminum Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film, A two-layer structure in which a copper film is laminated on a stainless film may also be used.

[0259] Also, a titanium film or titanium nitride film and an aluminum film overlaid on the titanium film or titanium nitride film are used. A three-layer structure in which a titanium film or a copper film is laminated and a titanium film or a titanium nitride film is further formed on top of that. Molybdenum film or molybdenum nitride film and a An aluminum film or a copper film is laminated on top of it, and a molybdenum film or a molybdenum nitride film is further laminated on top of it. There are three-layer structures that form a transparent film. Transparent conductive materials may also be used.

[0260] As shown in FIG. 18(A), the oxide 530 is formed of the conductor 542a (conductor 542b ) and its vicinity, a region 543a and a region 543b are formed as low resistance regions. In this case, the region 543a may be used as either a source region or a drain region. The region 543b functions as the other of the source region and the drain region. A channel forming region is formed in the region sandwiched between region 543a and region 543b.

[0261] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, The oxygen concentration in the region 543a (region 543b) may decrease. The metal contained in the conductor 542a (conductor 542b) and the oxide 530 are In such a case, a metal compound layer containing the component may be formed in the region 543a (region The carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region. become.

[0262] The insulator 544 is provided to cover the conductor 542a and the conductor 542b. The insulator 544 prevents oxidation of the oxide 542a and the conductor 542b. 30 and may be provided so as to be in contact with the insulator 524.

[0263] Insulator 544 includes hafnium, aluminum, gallium, yttrium, and zirconium. Smoke, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum Alternatively, a metal oxide containing one or more metals selected from magnesium, etc. may be used. Alternatively, silicon nitride oxide or silicon nitride may be used as the insulator 544. You can be there.

[0264] In particular, the insulator 544 may be an oxide of aluminum or hafnium, or both. Insulators including aluminum oxide, hafnium oxide, aluminum, and hafnium It is preferable to use an oxide containing hafnium (hafnium aluminate). Hafnium aluminate has higher heat resistance than hafnium oxide film. This is preferable because it is difficult to crystallize during the treatment. If b is a material that is resistant to oxidation or does not significantly decrease in conductivity even when it absorbs oxygen, it is an insulating material. The insulator 544 is not an essential component and may be appropriately designed depending on the desired transistor characteristics. stomach.

[0265] By including the insulator 544, impurities such as water and hydrogen contained in the insulator 580 are converted into acids. The oxide 530c is prevented from diffusing into the oxide 530b through the insulator 550. In addition, the excess oxygen contained in the insulator 580 can prevent the conductor 560 from being oxidized. It is possible.

[0266] The insulator 550 functions as a first gate insulating film. It is preferable that the insulator 550 is disposed in contact with the inside (top surface and side surface) of the Similar to the insulator 524, an insulator containing excess oxygen and releasing oxygen upon heating is used. It is preferable to form it as follows.

[0267] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, Silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon, and Silicon oxide doped with nitrogen and silicon oxide having vacancies can be used. Silicon oxide and silicon oxynitride are preferred because they are stable to heat.

[0268] An insulator that releases oxygen when heated is used as the insulator 550, and is placed on the top surface of the oxide 530c. By providing the oxide 530b in contact with the insulator 550, the oxide 530c passes through the oxide 530b. In addition, oxygen can be effectively supplied to the channel formation region of the insulator 524. In addition, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0269] In addition, in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530, A metal oxide may be provided between the insulating material 550 and the conductor 560. It is preferable to suppress the diffusion of oxygen from the body 550 to the conductor 560. By providing a metal oxide, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, it is possible to suppress the decrease in the amount of excess oxygen supplied to the oxide 530. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. Any material that can be used for the insulator 544 may be used.

[0270] The insulator 550 may have a stacked structure, similar to the second gate insulating film. As the miniaturization and high integration of devices progresses, the gate insulating film becomes thinner, which reduces leakage current and other problems. Therefore, the insulator that functions as the gate insulating film is made of high-k material. By using a laminated structure of a thermally stable material, the physical film thickness can be maintained while It is possible to reduce the gate potential during transistor operation. It may be a layered structure.

[0271] The conductor 560 functioning as the first gate electrode is a two-layer structure in FIGS. 18(A) and 18(B). Although the structure is shown, it may be a single layer structure or a laminated structure of three or more layers.

[0272] The conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of the conductor 56. Oa has the function of suppressing oxygen diffusion, so the oxygen contained in the insulator 550 This can prevent the conductor 560b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing this include tantalum, tantalum nitride, and ruthenium. It is preferable to use ruthenium, ruthenium oxide, or the like as the conductor 560a. An oxide semiconductor that can be used for the oxide 530 can be used. In that case, the conductor 560 By forming the conductive layer 560b by sputtering, the electrical resistance of the conductive layer 560a is reduced, and the conductive layer 560b is This is called an OC (Oxide Conductor) electrode. can be done.

[0273] The conductor 560b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 560b also functions as a wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. A conductive material containing rubber as a main component can be used. For example, a laminated structure of titanium, titanium nitride and the above-mentioned conductive material may be used.

[0274] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. Preferably, the insulator 580 has an excess oxygen region. For example, the insulator 58 0, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the material contains silicon, silicon oxide having pores, or resin. Silicon nitride and silicon oxynitride are preferred because they are thermally stable. However, silicon oxide with vacancies can easily form excess oxygen regions in later processes. This is preferable because it allows

[0275] The insulator 580 preferably has an excess oxygen region. Oxygen is released upon heating. By providing the insulator 580 in contact with the oxide 530c, the oxygen in the insulator 580 is oxidized. The oxide 530 can be efficiently supplied through the insulator 530c. It is preferable that the concentration of impurities such as water or hydrogen in 80 is reduced.

[0276] The opening in the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is inserted through the opening in the insulator 580 and the conductor 542a and the conductor 542b. It is formed so as to be embedded in the region sandwiched between 542b.

[0277] In miniaturizing semiconductor devices, it is required to shorten the gate length. It is necessary to prevent the conductivity of the conductor 60 from decreasing. In this embodiment, the conductor 560 may have a shape with a high aspect ratio. The conductor 560 is provided so as to be embedded in the opening of the insulator 580. Even a shape with a high ratio can be formed without causing the conductor 560 to collapse during the process. Cut.

[0278] The insulator 574 is connected to the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. The insulator 574 is preferably provided in contact with the , insulator 550, and insulator 580 can be provided with excess oxygen regions. Oxygen can be supplied into the oxide 530 from the excess oxygen region.

[0279] For example, the insulator 574 may be hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium Metal oxides containing one or more metals selected from the group consisting of ammonium, cadmium, and ammonium can be used. .

[0280] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Therefore, the diffusion of hydrogen and nitrogen can be suppressed even if the sputtering method is used. The aluminum oxide film formed by this method is both an oxygen source and a barrier to impurities such as hydrogen. It can also function as a membrane.

[0281] In addition, it is preferable to provide an insulator 581 that functions as an interlayer film over the insulator 574. The insulator 581, like the insulator 524, has a low impurity concentration such as water or hydrogen. It is preferably reduced.

[0282] In addition, the openings formed in the insulators 581, 574, 580, and 544 Conductor 540a and conductor 540b are placed in the opening. The conductors 540a and 540b are provided facing each other with the conductor 560 in between. It has the same structure as the conductor 546 and the conductor 548 described later.

[0283] An insulator 582 is provided on the insulator 581. The insulator 582 is resistant to oxygen and hydrogen. Therefore, the insulator 582 is preferably made of an insulating material. The insulator 582 may be made of the same material as the insulator 514. For example, aluminum oxide may be used. It is preferable to use metal oxides such as tungsten oxide, hafnium oxide, and tantalum oxide.

[0284] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0285] An insulator 586 is provided on the insulator 582. The insulator 586 is The same materials as those of 320 can be used. In addition, these insulators have a relatively low dielectric constant. By using a material with high insulating properties, the parasitic capacitance between wiring can be reduced. The edge 586 can be a silicon oxide film, a silicon oxynitride film, or the like.

[0286] Also, the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator The edge 574, the insulator 581, the insulator 582, and the insulator 586 are provided with the conductor 546 and Conductors 548 and the like are embedded.

[0287] The conductor 546 and the conductor 548 are connected to the capacitor 600, the transistor 500, or the transistor The conductor 546 functions as a plug or wiring that connects to the transistor 300. The conductor 548 can be formed using the same material as the conductor 328 and the conductor 330. Cut.

[0288] Next, a capacitor 600 is provided above the transistor 500. 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0289] Moreover, a conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 12 functions as a plug or wiring that connects to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. The body 610 can be formed simultaneously.

[0290] The conductor 612 and the conductor 610 may be made of molybdenum, titanium, tantalum, or tungsten. a metal film containing an element selected from aluminum, copper, chromium, neodymium, and scandium; Or a metal nitride film containing the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film) Indium tin oxide, tungsten nitride film, etc. can be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide are used. It is also possible.

[0291] In FIG. 16, the conductor 612 and the conductor 610 are shown as single-layer structures, but the present invention is not limited to this configuration. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors with barrier properties and high adhesion to highly conductive conductors A thin conductor may be formed.

[0292] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. The conductor 620 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, are used. It is preferable to use tungsten, and it is particularly preferable to use tungsten. When forming the structure at the same time as other structures, low-resistance metal materials such as Cu (copper) and Al (aluminum) are used. It is best to use a

[0293] An insulator 650 is provided on the conductor 620 and the insulator 630. The insulator 650 can be formed using the same material as the insulator 320. It may also function as a planarizing film that covers the underlying unevenness.

[0294] By using this structure, a semiconductor device using a transistor having an oxide semiconductor This can suppress the fluctuation of electrical characteristics and improve reliability. In semiconductor devices using transistors having compound semiconductors, miniaturization or high integration is being attempted. It is possible.

[0295] <Additional notes regarding the present specification etc.> The above-described embodiments and the respective components in the embodiments will be described below with additional notes.

[0296] The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments to realize the present invention. In addition, in one embodiment, multiple configuration examples may be shown. In this case, the configuration examples can be combined as appropriate.

[0297] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the form, and / or one or more other implementations The contents (or a part of the contents) described in the embodiments may be applied, combined, or replaced. You can do things like drawing.

[0298] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0299] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. , another figure (or a part thereof) described in the embodiment, and / or one or more By combining the figures (or a part thereof) described in other embodiments of the present invention, This allows for even more diagrams to be constructed.

[0300] In addition, in the block diagrams in this specification, components are classified by function and are independent of each other. However, in actual circuits, the components are divided into functional blocks. It is difficult to separate the functions into separate parts, and there are cases where multiple functions are involved in one circuit, or where a circuit is involved in multiple circuits. Therefore, the blocks in the block diagram may be The present invention is not limited to the components described above, and may be rephrased appropriately depending on the situation.

[0301] In addition, in the drawings, the size, layer thickness, and area are shown at arbitrary scales for the convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the purpose of clarity, and are not limited to the shapes or values shown in the drawings. fluctuations in signal, voltage, or current due to noise, or signal due to timing deviations These may include variations in signal, voltage, or current.

[0302] In this specification and the like, when describing the connection relationship of a transistor, "one side" (or first electrode, or first terminal), "the other side of the source or drain" (or second electrode The source and drain of a transistor are called the first terminal and the second terminal. This is because it varies depending on the structure or operating conditions of the transistor. The names of the source (drain) terminal and the source (drain) electrode, etc. Can be rephrased appropriately depending on the situation.

[0303] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably with "electrodes" and "wiring." This also includes cases where the wiring is formed integrally.

[0304] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. The potential difference from the reference potential. For example, the reference potential is the ground voltage (earth If we use the term "voltage", we can translate voltage into potential. Ground potential is not necessarily 0V. It does not necessarily mean that the potential is relative, and depending on the reference potential, The potential applied to wiring etc. may be changed.

[0305] In this specification, the terms "film" and "layer" are used in some cases or in other situations. For example, the term "conductive layer" can be used interchangeably with " It may be possible to change the term to "conductive film." In some cases, the term "insulating layer" can be changed to the term "insulating layer."

[0306] In this specification, a switch refers to a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It refers to a device that has the function of controlling whether or not current flows by entering a state where it is in a non-operating state. A switch is a device that has the function of selecting and switching a path through which a current flows.

[0307] In this specification and the like, the channel length is, for example, the length of a semiconductor the body (or the part of the semiconductor through which current flows when the transistor is on) and the gate The distance between the source and drain in the region where they overlap or where the channel is formed. It means separation.

[0308] In this specification, the channel width is, for example, the width of a semiconductor (or a transistor) when it is in an on state. The area where the gate electrode overlaps with the gate electrode (the area where current flows in the semiconductor when the gate electrode is in the non-transistor state), or the channel The length of the portion where the source and drain face each other in the region where the capacitor is formed. .

[0309] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are electrically connected, A and B are also included. Connected to means that there is an object that has some electrical effect between A and B. When this occurs, it refers to something that enables the transmission and reception of electrical signals between A and B. [Explanation of symbols]

[0310] 10: Memory section, 10A: Memory section, 20A: Memory circuit, 20B: Memory circuit, 21A: Memory Circuit, 21B: Memory circuit, 21C: Memory circuit, 21D: Memory circuit, 22A: Memory circuit, 2 2B: Memory circuit, 22C: Memory circuit, 22D: Memory circuit, 26A: Memory circuit, 26B: Memory Memory circuit, 27A: Memory circuit, 27B: Memory circuit, 27C: Memory circuit, 27D: Memory circuit, 28A: Memory circuit, 28B: Memory circuit, 28C: Memory circuit, 28D: Memory circuit, 30: times Path, 31: Circuit, 40: Input / Output Circuit, 50: Control Unit, 50A: Control Unit, 60: Sensor Unit, 70: external circuit, 300: transistor, 311: substrate, 313: semiconductor region, 314a : low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator body, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor body, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulation body, 362: insulator, 364: insulator, 366: conductor, 370: insulator, 372: insulation body, 374: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulation body, 386: conductor, 500: transistor, 503: conductor, 503a: conductor, 50 3b: conductor, 505: conductor, 510: insulator, 512: insulator, 514: insulator, 5 16: Insulator, 518: Conductor, 520: Insulator, 522: Insulator, 524: Insulator, 5 30: oxide, 530a: oxide, 530b: oxide, 530c: oxide, 540a: conductor electric body, 540b: electric conductor, 542a: electric conductor, 542b: electric conductor, 543a: area, 54 3b: Region, 544: Insulator, 546: Conductor, 548: Conductor, 550: Insulator, 56 0: conductor, 560a: conductor, 560b: conductor, 574: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 600: capacitive element, 610: conductor , 612: conductor, 620: conductor, 630: insulator, 650: insulator, 1201: Drail, 2100: Robot, 2101: Illuminance sensor, 2102: Microphone, 2 103: Upper camera, 2104: Speaker, 2105: Display, 2106: Lower camera Mela, 2107: Obstacle sensor, 2108: Moving mechanism, 2110: Computing unit, 2120: Aircraft, 2121: Computing unit, 2122: Camera, 2123: Propeller, 2910: Information Terminal, 2911: housing, 2912: display unit, 2913: camera, 2914: speaker unit, 2915: Operation switch, 2916: External connection part, 2917: Microphone, 2920: Cleaning part Bot, 2921: Housing, 2922: Display, 2923: Operation buttons, 2924: Camera ,2925:Brush, 2980:Automobile, 2981:Camera, 5101:Display, 5103: Brush

Claims

[Claim 1] The device includes a control unit, a storage unit, and a sensor unit, the storage unit includes a storage circuit and a switching circuit; the memory circuit includes a first transistor and a capacitor; the switching circuit includes a second transistor and a third transistor; the first transistor and the second transistor each include a semiconductor layer including a channel formation region having an oxide semiconductor and a back gate electrode; The control unit has a function of switching a signal to be applied to the back gate electrode in accordance with a signal obtained by the sensor unit.

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