Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device having a thick gate insulating film that can be stably manufactured.SOLUTION: A semiconductor device includes, on a substrate, a first semiconductor element and a second semiconductor element. The first semiconductor element includes a first stacked body composed of a channel layer and a first gate electrode that covers the periphery of the channel layer in a cross section of the first semiconductor element in the gate width direction. The second semiconductor element has a second gate electrode formed on the substrate via a second gate insulating film, and a channel region formed in the substrate below the second gate electrode.SELECTED DRAWING: Figure 40

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] In semiconductor devices with GAA-FETs (Gate All Around Field Effect Transistors) using nanosheet structures, input / output (IO) devices are formed near logic devices using GAA-FETs. The I / O devices must operate at a higher voltage than the GAA-FETs that make up the logic devices. For this reason, when I / O devices are formed using GAA-FETs, the gate insulating film must be thicker than conventional devices.

[0003] However, when manufacturing input / output devices with a GAA-FET structure using conventional nanosheet-based GAA-FET manufacturing methods, it is difficult to form a gate insulating film thick enough to withstand high voltages. For example, if a thick gate insulating film is formed on a GAA-FET using nanosheets in the input / output section, the gaps between the stacked Si layers (Si nanosheet layers) will be filled with insulating film. In this case, it is difficult to form a gate electrode between the Si layers, significantly reducing the performance of the semiconductor device.

[0004] To address these issues, a configuration has been proposed in which, in an input / output device with a GAA-FET structure using a nanosheet structure, all Si nanosheet layers except the bottom layer are removed, and only the bottom Si nanosheet layer is used as the input / output device (see, for example, Patent Document 1). In a semiconductor device with this configuration, the Si layer and SiGe layer are removed except for the bottom Si nanosheet layer, creating a large space around the bottom Si nanosheet layer. This makes it possible to form a thick gate insulating film in the input / output device. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 10,229,971 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the semiconductor device having the configuration described in Patent Document 1, etching must be stopped reliably within the SiGe layer, which is only a few tens of nanometers thick. Such precise control of etching is extremely difficult in practice. Therefore, it is difficult to stably realize the semiconductor device having the configuration described in Patent Document 1.

[0007] In order to solve the above-mentioned problems, the present invention provides a semiconductor device having a thick gate insulating film that can be more stably produced, and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0008] The semiconductor device of the present invention includes a first semiconductor element and a second semiconductor element on a substrate. The first semiconductor element has a first stacked body including a channel layer and a first gate electrode covering the periphery of the channel layer in a cross section of the first semiconductor element in the gate width direction, and a first gate insulating film interposed between the channel layer and the first gate electrode. The second semiconductor element has a second gate electrode formed on the substrate via a second gate insulating film, and a channel region formed in the substrate below the second gate electrode.

[0009] A method for manufacturing a semiconductor device according to the present invention manufactures a semiconductor device including a first semiconductor element and a second semiconductor element on a substrate. The method includes the steps of forming a channel region by implanting impurity ions into the substrate in a region for forming the second semiconductor element. The method also includes the steps of stacking a Si layer and a SiGe layer in the region for forming the first semiconductor element and the region for forming the second semiconductor element to form a Si / SiGe stack. The method also includes the steps of removing the SiGe layer and forming a first gate insulating film in the region for forming the first semiconductor element. The method also includes the steps of removing the SiGe layer, removing the Si layer, and forming a second gate insulating film thicker than the first gate insulating film in the region for forming the second semiconductor element. The method also includes the steps of forming a metal layer and forming a first gate electrode and a second gate electrode in the region for forming the first semiconductor element and the region for forming the second semiconductor element. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a semiconductor device that can be manufactured through simple steps and that allows the formation of a thick gate insulating film, and a method for manufacturing the semiconductor device. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram (plan view) showing a schematic configuration of a semiconductor device according to a first embodiment. [Figure 2] 2 is a cross-sectional view (cross-sectional view in the gate length direction) taken along line X1 of the first semiconductor element shown in FIG. 1. [Figure 3] 2 is a cross-sectional view (cross-sectional view in the gate width direction) taken along line Y1 of the first semiconductor element shown in FIG. 1. [Figure 4] 2 is a cross-sectional view (cross-sectional view in the gate length direction) taken along line X2 of the second semiconductor element shown in FIG. 1. [Figure 5] 1. FIG. 3 is a cross-sectional view (cross-sectional view in the gate width direction) taken along line Y2 of the second semiconductor element shown in FIG. [Figure 6] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 7]2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 11] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 12] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 13] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 14] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 15] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 16] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 17] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 18] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 19] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 20] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 21] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 22] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 23] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 24] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 25] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 26] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 27] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 28] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 29] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 30] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 31] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 32] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 33] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 34] 10 is a cross-sectional view (cross-sectional view in the gate length direction) taken along line X1 of a first semiconductor element of a semiconductor device according to a second embodiment. FIG. [Figure 35] 10 is a cross-sectional view (cross-sectional view in the gate width direction) taken along line Y1 of the semiconductor device according to the second embodiment. FIG. [Figure 36] 10 is a cross-sectional view (cross-sectional view in the gate length direction) taken along line X2 of a second semiconductor element of a semiconductor device according to a second embodiment. FIG. [Figure 37] 10 is a cross-sectional view (cross-sectional view in the gate width direction) taken along line Y2 of the semiconductor device according to the second embodiment. FIG. [Figure 38] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment. [Figure 39] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment. [Figure 40] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment. [Figure 41] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment. [Figure 42] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment. [Figure 43] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment. [Figure 44] 10 is a cross-sectional view (cross-sectional view in the gate length direction) taken along line X1 of a first semiconductor element of a semiconductor device according to a third embodiment. FIG. [Figure 45] 10 is a cross-sectional view (cross-sectional view in the gate width direction) taken along line Y1 of the semiconductor device according to the third embodiment. FIG. [Figure 46] 10 is a cross-sectional view (cross-sectional view in the gate length direction) taken along line X2 of a second semiconductor element of a semiconductor device according to a third embodiment. FIG. [Figure 47] 10 is a cross-sectional view (cross-sectional view in the gate width direction) taken along line Y2 of the semiconductor device according to the third embodiment. FIG. [Figure 48] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 49] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 50] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 51] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 52] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 53] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 54] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 55] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 56] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 57] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 58] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 59] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 60] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 61] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 62] 10 is a cross-sectional view (cross-sectional view in the gate length direction) taken along line X1 of a first semiconductor element of a semiconductor device according to a fourth embodiment. FIG. [Figure 63] 10 is a cross-sectional view (cross-sectional view in the gate length direction) taken along line X2 of a second semiconductor element of a semiconductor device according to a fourth embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, examples of embodiments for carrying out the present invention will be described, but the present invention is not limited to the following examples. The explanation will be given in the following order. 1. Semiconductor device of the first embodiment 2. Manufacturing method of the semiconductor device of the first embodiment 3. Semiconductor device according to the second embodiment 4. Method for manufacturing the semiconductor device of the second embodiment 5. Semiconductor device according to the third embodiment 6. Manufacturing method of semiconductor device according to the third embodiment 7. Semiconductor device according to the fourth embodiment

[0013] 1. Semiconductor Device of First Embodiment Specific embodiments of the semiconductor device of the present invention will be described below. Figure 1-5 shows a schematic configuration diagram of a semiconductor device according to a first embodiment. [Configuration of semiconductor device] FIG. 1 is a plan view (top view) of the semiconductor device. FIG. 2 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X1. FIG. 3 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1 taken along line Y1. FIG. 4 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X2. FIG. 5 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1 taken along line Y2.

[0014] The semiconductor device 10 shown in FIG. 1 includes a first semiconductor element 100 and a second semiconductor element 200 on a substrate 11. As shown in FIGS. 2 and 3, the first semiconductor element 100 is a Gate All Around (GAA)-FET having a first stack formed by stacking Si nanosheet layers (first Si layers) 101, 102, and 103 and a gate electrode 112. As shown in FIGS. 4 and 5, the second semiconductor element 200 is a planar-type Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) having a gate electrode 212 formed on the substrate 11 via a gate insulating film 210 (second gate insulating film).

[0015] 1, the first semiconductor element 100 includes a gate electrode 112 (first gate electrode) and a source / drain region 108 (first source / drain region) formed on a substrate 11. The second semiconductor element 200 includes a gate electrode 212 (second gate electrode) and a source / drain region 208 (second source / drain region) formed on the substrate 11.

[0016] 1, the second semiconductor element 200 has a larger gate length than the first semiconductor element 100. Because the second semiconductor element 200 is an input / output device, the voltage applied to the gate electrode 212 is higher than the voltage applied to the gate electrode 112 of the first semiconductor element 100. For this reason, it is preferable that the second semiconductor element 200 have a larger gate length than the first semiconductor element 100 in order to suppress a through current between the source / drain regions 208, known as punch-through. On the other hand, it is preferable that the first semiconductor element 100 that will become a logic device is formed with a shorter gate length in order to improve the switching speed.

[0017] 2 and 4, in cross-sectional views of the first semiconductor element 100 and the second semiconductor element 200 in the gate length direction, the first semiconductor element 100 and the second semiconductor element 200 are entirely sealed by an insulating layer 41 on a substrate 11. In addition, an STI (Shallow Trench Isolation) 42 is formed on the surface of the substrate 11 as an element isolation region. The STI 42 is composed of the insulating layer 41 embedded in the substrate 11. The STI 42 is formed between the first semiconductor element 100 and the second semiconductor element 200. The STI 42 is formed in a region other than the region where the first semiconductor element 100 and the second semiconductor element 200 are formed.

[0018] (First semiconductor element) 2, the first semiconductor element 100 has a gate electrode 112 in the lowermost layer on a substrate 11. The first semiconductor element 100 has a first stacked body having a stacked structure including the gate electrode 112, that is, [gate electrode 112 / Si layer 101 / gate electrode 112 / Si layer 102 / gate electrode 112 / Si layer 103].

[0019] 2, the first semiconductor element 100 has a gate electrode 112 and a sidewall 106 above the uppermost Si layer 103. The gate electrode 112 is formed in the center of the Si layer 103, and the sidewall 106 is formed around the gate electrode 112. The gate electrode 112 includes a metal layer 104. A high-dielectric-constant material layer (first high-dielectric-constant layer) 105 is provided on the bottom and side surfaces of the gate electrode 112, i.e., on contact surfaces with the Si layer 103 and the sidewalls 106. The metal layer 104 is filled in the high-dielectric-constant material layer 105. In the first semiconductor element 100, the high-dielectric-constant material layer 105 may be, for example, a combination of the high-dielectric-constant material layer 105 and a low-dielectric-constant material layer (not shown) that is thinner than the high-dielectric-constant material layer 105 and is made of a low-dielectric-constant material having a lower dielectric constant than the high-dielectric-constant material layer 105. In the first semiconductor element 100, the stacked film of the high-dielectric-constant material layer 105 and the low-dielectric-constant material layer functions as a gate insulating film (first gate insulating film).

[0020] The first semiconductor element 100 has independent source / drain regions 108 on both side surfaces of a first stack consisting of Si layers 101, 102, and 103 and a gate electrode 112. The Si layers 101, 102, and 103 are connected to the source / drain regions 108 on both sides. In addition, an inner spacer 107 (first inner spacer) made of an insulating layer (first insulating layer) is formed between the gate electrode 112, which is disposed between the substrate 11 and the Si layers 101, 102, and 103, and the source / drain region 108.

[0021] 2, the gate electrode 112 formed between the substrate 11 and the Si layers 101, 102, and 103 is formed of the metal layer 104. The contact surfaces of the gate electrode 112 with the Si layers 101, 102, and 103 and the inner spacer 107 are covered with a high-dielectric-constant material layer 105 and a low-dielectric-constant material layer (not shown). The metal layer 104 is filled inside the high-dielectric-constant material layer 105.

[0022] 3, the first semiconductor element 100 has a high-dielectric-constant material layer 105 formed on the substrate 11 and the STI 42. The first semiconductor element 100 also has Si layers 101, 102, and 103 stacked on the high-dielectric-constant material layer 105 with a metal layer 104 constituting a gate electrode 112 interposed therebetween. The high-dielectric-constant material layer 105 and a low-dielectric-constant material layer (not shown) are formed between the metal layer 104 and the Si layers 101, 102, and 103. Therefore, in the cross-sectional view in the gate width direction, the Si layers 101, 102, and 103 are surrounded by the high-dielectric-constant material layer 105 and a low-dielectric-constant material layer (not shown), respectively.

[0023] 2. Therefore, in the cross-sectional view in the gate width direction shown in FIG. 3, the periphery of the Si layers 101, 102, and 103 is covered by the gate electrode 112. That is, in the first semiconductor element 100, the Si layers 101, 102, and 103 constituting the first stack are channel layers in which a channel is formed. In the first semiconductor element 100, the entire cross-section in the gate width direction of the Si layers 101, 102, and 103 that form the channel portion is surrounded by the gate electrode 112, as shown in FIG.

[0024] (Second semiconductor element) In the cross-sectional view in the gate length direction shown in FIG. 4, the second semiconductor element 200 has a gate electrode 212 on a substrate 11 via a gate insulating film 210 and a high-dielectric-constant material layer 205. The substrate 11 has a trench 211 in a region where the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are formed, which is deeper than the surrounding region. Therefore, the substrate 11 has a step between the region where the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are formed and the surrounding region. In the trench 211 of the substrate 11, the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are formed in a low-position region (low-position region) formed lower by the step. The trench forming this step is sufficiently shallower than the STI 42.

[0025] The second semiconductor element 200 also has Si layers (second Si layers) 201, 202, and 203 and an inner spacer 207 (second inner spacer) made of an insulating layer (second insulating layer) on the side surfaces of the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212. Therefore, the second semiconductor element 200 has a second stacked body made of a stacked structure of [inner spacer 207 / Si layer 201 / inner spacer 207 / Si layer 202 / inner spacer 207 / Si layer 203] on the side surface of the gate insulating film 210 on the substrate 11. The inner spacer 207 and the Si layers 201, 202, and 203 are arranged on the surface of the substrate 11 around a low-position region where the gate electrode 212 and the like are arranged, on a high-position region (high-position region) formed higher than the groove portion 211 by a step.

[0026] Furthermore, the Si layers 201, 202, and 203 have a smaller thickness in the gate length direction than the inner spacer 207. Therefore, the gate insulating film 210 and the Si layers 201, 202, and 203 are disposed between the stacked layers of the inner spacer 207. In the gate length direction, the gate insulating film 210 is disposed toward the center of the element, and the Si layers 201, 202, and 203 are disposed outside the gate insulating film 210.

[0027] 4, the second semiconductor element 200 has sidewalls 206 above the uppermost Si layer 203. The sidewalls 206 are formed on outer surfaces of the gate electrode 212, the high-dielectric-constant material layer 205, and the gate insulating film 210. The side surfaces of the sidewalls 206 are in contact with the gate insulating film 210, and the bottom surfaces are in contact with the Si layer 203 and the gate insulating film 210.

[0028] The second semiconductor element 200 has source / drain regions 208 on the side surfaces of a stack made up of Si layers 201, 202, and 203 and an inner spacer 207. The inner spacer 207 and the Si layers 201, 202, and 203 are in contact with the source / drain regions 208. The source / drain regions 208 are formed in contact with the surface of the substrate 11. The source / drain regions 208 are arranged around a region on the substrate 11 where the gate electrode 212, the high-dielectric-constant material layer 205, and the gate insulating film 210 are in contact with each other. Therefore, the source / drain regions 208 are arranged on a high-position region (high-position region) formed by a step on the surface of the substrate 11. Contacts 209 for connection to external wiring are connected to the source / drain regions 208. The contacts 209 are formed of a metal material embedded in through holes that penetrate from the top of the insulating layer 41 of the second semiconductor element 200 to the source / drain regions 208.

[0029] The gate electrode 212 is composed of a metal layer 204. A high-dielectric-constant material layer 205 (second high-dielectric-constant material layer) is provided on the bottom and side surfaces of the gate electrode 212, i.e., on the contact surface with the gate insulating film 210. The metal layer 204 is filled in the high-dielectric-constant material layer 205.

[0030] The substrate 11 is a region between the pair of source-drain regions 208, and has an impurity diffusion region (not shown) below the gate insulating film 210 and the gate electrode 212. The impurity diffusion region is formed to a predetermined depth on the surface side of the substrate 11. For example, if the second semiconductor element 200 is a PMOS, the substrate 11 has a diffusion region of an n-type impurity such as phosphorus. Also, if the second semiconductor element 200 is an NMOS, the substrate 11 has a diffusion region of a p-type impurity such as boron. In the second semiconductor element 200, the impurity diffusion region of the substrate 11 becomes a region (channel region) where a channel is formed when the second semiconductor element 200 is operating.

[0031] The gate insulating film 210 is formed between the gate electrode 212 and the substrate 11, between the gate electrode 212 and the Si layers 201, 202, and 203 and the inner spacer 207, and between the gate electrode 212 and the sidewall 216. The gate insulating film 210 has a thickness sufficient to withstand the high voltage applied to the second semiconductor element 200 which serves as an input / output device. For this reason, the gate insulating film 210 is formed to be sufficiently thicker than the high-dielectric-constant material layer 205.

[0032] 5, the second semiconductor element 200 has a gate insulating film 210 formed on the substrate 11 and the STI 42, and a high-dielectric-constant material layer 205. The second semiconductor element 200 has a metal layer 204 that forms a gate electrode 212 on the high-dielectric-constant material layer 205.

[0033] The second semiconductor element 200 has a gate electrode 212 formed on a substrate 11 with a gate insulating film 210 interposed therebetween. Furthermore, the second semiconductor element 200 has a pair of source / drain regions 208 at positions facing each other across the gate electrode 212 and sandwiching a channel region. Therefore, when a gate voltage is applied to the gate electrode 212, a channel is formed in the substrate 11 of the second semiconductor element 200. Furthermore, the source / drain regions 208 are formed so as to be in direct contact with the channel region of the substrate 11. In the second semiconductor element 200, the Si layers 201, 202, and 203 contact the source-drain regions 208 at their side edges, but are separated in the center of the element by a gate insulating film 210 and a gate electrode 212. Therefore, the Si layers 201, 202, and 203 are not formed continuously between the pair of source-drain regions 208. Therefore, in the second semiconductor element 200, no channel is formed in the Si layers 201, 202, and 203. That is, in the first semiconductor element 100, a channel is formed in the Si layers 101, 102, and 103 that constitute the first stack, whereas in the second semiconductor element 200, a channel is formed in the substrate 11.

[0034] Furthermore, in the second semiconductor element 200, central portions of the Si layers 201, 202, and 203 constituting the stack are removed compared to the first semiconductor element 100. In the central portion of the element, the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are continuously formed from the top of the element to the surface of the substrate 11 without any Si layer or the like inside. In this manner, the second semiconductor element 200 has a configuration in which the Si layers 201, 202, and 203 are removed in the central portion of the element, thereby providing a large space for forming the gate insulating film 210 and the gate electrode 212. As a result, the second semiconductor element 200 has an area secured for forming a gate insulating film of sufficient thickness capable of withstanding the high voltage applied to the input / output device.

[0035] (Layer structure of second semiconductor element) The Si layers 201, 202, and 203 of the second semiconductor element 200 are formed at approximately the same height as the Si layers 101, 102, and 103 of the first semiconductor element 100, with the upper surface of the substrate 11 as the reference.

[0036] In the second semiconductor element 200, the inner spacer 207 is divided into two or more parts at least in the stacking direction by the Si layers 201 and 202. Therefore, the inner spacer 207 is formed by being divided into two or more parts in the stacking direction. The Si layers 201 and 202 are interposed between the stacked parts of the inner spacer 207.

[0037] The Si layers 201, 202, and 203 are formed so that their thickness in the surface direction of the substrate 11 (gate length direction) is smaller than that of the inner spacer 207. Therefore, in the cross-sectional view in the gate width direction shown in FIG. 3 , the Si layers 201, 202, and 203 and the inner spacer 207 have steps on their wall surfaces toward the center of the second semiconductor element 200. These steps form recesses on the inner surface sides of the Si layers 201, 202, and 203. An insulating film 210 is embedded in the recesses on the side surfaces of the Si layers 201, 202, and 203. As a result, the Si layers 201, 202, and 203 and the insulating film 210 are disposed between the stacked inner spacers 207. The Si layers 201 , 202 , and 203 are in contact with the insulating film 210 , the inner spacer 207 , and the source / drain region 208 .

[0038] The Si layers 201, 202, and 203 may have the same thickness as the inner spacer 207, or may have a thickness equal to or less than the thickness of the inner spacer 207. If the Si layers 201, 202, and 203 and the inner spacer 207 have the same thickness, the recesses described above are not formed. Therefore, the gate insulating film 210 embedded in the recesses is not present. Only the Si layers 201 and 202 are disposed between the stacked inner spacers 207.

[0039] Furthermore, the source / drain region 208 is not exposed because the Si layers 201, 202, and 203 remain between the stacked layers of the inner spacer 207. Therefore, in the manufacturing process of the semiconductor device described later, damage to the source / drain region 208 can be suppressed in the steps of removing the Si layers 201, 202, and 203, removing the SiGe layer, forming the gate electrode, and the like.

[0040] According to the above-described configuration, the second semiconductor element 200 has an area for forming a gate insulating film of sufficient thickness to withstand the high voltage applied to the second semiconductor element 200, which serves as an input / output device. With this structure, the second semiconductor element 200 has a shape similar to that of a GAA-FET in a portion between the gate insulating film 210 and the source / drain region 208, and yet can be operated at a voltage higher than that of the first semiconductor element 100 that constitutes the logic device. This makes it possible to suppress a decrease in the reliability of the second semiconductor element 200.

[0041] Furthermore, in the first semiconductor element 100 and the second semiconductor element 200, the Si layers 101, 102, 103 and the Si layers 201, 202, 203 are formed to the same height. Therefore, the first semiconductor element 100 and the second semiconductor element 200 can share the same process for forming the Si layers 101, 102, 103 and the Si layers 201, 202, 203. As a result, variations in height between the Si layers 101, 102, 103 and the Si layers 201, 202, 203 can be suppressed. Furthermore, by sharing the same process for forming the Si layers 101, 102, 103 and the Si layers 201, 202, 203, it is possible to suppress the complexity of the manufacturing process and the increase in manufacturing costs.

[0042] 2. Manufacturing Method of Semiconductor Device Next, a method for manufacturing the semiconductor device 10 shown in FIGS. 1-5 will be described. 6 to 33 show manufacturing process diagrams of the semiconductor device 10. In the manufacturing process of the semiconductor device 10 shown in FIGS. 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, and 32, the left side of the drawing shows a cross-sectional view (cross-sectional view in the gate length direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 taken along line X1, and the right side of the drawing shows a cross-sectional view (cross-sectional view in the gate length direction) of the second semiconductor element 200. Also, in the manufacturing process of the semiconductor device 10 shown in FIGS. 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, and 33, the left side of the drawing shows a cross-sectional view (cross-sectional view in the gate width direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 taken along line Y1, and the right side of the drawing shows a cross-sectional view (cross-sectional view in the gate width direction) of the second semiconductor element 200.

[0043] First, as shown in FIGS. 6 and 7, impurities for forming a PTS (Punch Through Stopper) are implanted into the substrate 11 in the region where the first semiconductor element 100 will be formed. This forms a PTS layer in the substrate 11, which has a gradual concentration gradient from the surface toward the inside. When forming the PTS layer as a p-type, boron is implanted as the impurity, and when forming the PTS layer as an n-type, phosphorus is implanted as the impurity. At this time, a resist layer 12 is patterned over the entire surface of the substrate 11 except for the region where the PTS will be formed. The patterning of the resist layer 12 is performed, for example, by forming the resist layer 12 over the entire surface, and then performing exposure and development processes using a photomask on which a predetermined pattern has been formed.

[0044] Next, as shown in FIGS. 8 and 9, impurities for channel formation are implanted into the substrate 11 in the region where the second semiconductor element 200 will be formed. This forms an impurity diffusion region in the substrate 11 that will become the channel region. The channel region is formed continuously at least from the bottom of the gate electrode 212 to the bottom of the region where the source / drain region 208 will be formed. Furthermore, impurity ions are implanted into the substrate 11 in the region where the second semiconductor element 200 will be formed, respectively, for NMOS and PMOS. When the second semiconductor element 200 is formed as an NMOS, boron is implanted as the impurity, and when the second semiconductor element 200 is formed as a PMOS, phosphorus is implanted as the impurity. At this time, a resist layer 13 is patterned and formed on the entire surface of the substrate 11 except for the region where the impurities are implanted. The patterning of the resist layer 13 can be performed, for example, by forming the resist layer 13 on the entire surface, followed by exposure and development using a photomask on which a predetermined pattern is formed. Here, the amount of impurity injected for forming the PTS is different from the amount of impurity injected for forming the channel, and the amount of impurity injected for forming the PTS is larger than the amount of impurity injected for forming the channel.

[0045] Next, by the following processing, a Si / SiGe stack, a dummy gate insulating film 22, a dummy gate 20, a hard mask 21, sidewalls 106, 206, inner spacers 107, 207, and source / drain regions 108, 208 shown in FIGS. 10 and 11 are formed on the substrate 11. First, the SiGe layer 14, Si layers 17 and 101, SiGe layer 15, Si layers 18 and 102, SiGe layer 16, and Si layers 19 and 103 are stacked on the substrate 11. The SiGe layers 14, 15, and 16, and the Si layers 17, 18, 19, 101, 102, and 103 are formed by epitaxial growth of Si and SiGe. The Si layers 17 and 101, the Si layers 18 and 102, and the Si layers 19 and 103 are formed as the same layer in the same process by epitaxial growth. Then, by separating each element in a later process, the Si layers 101, 102, and 103 are formed on the first semiconductor element 100 side, and the Si layers 17, 18, and 19 are formed on the second semiconductor element 200 side. The SiGe layers 14, 15, and 16 are formed to a thickness of, for example, about 10-15 nm, and the Si layers 17, 18, 19, 101, 102, and 103 are formed to a thickness of, for example, about 5 nm.

[0046] Next, STI is formed on the substrate 11, and a dummy gate insulating film 22, a dummy gate 20, a hard mask 21, and sidewalls 106 and 206 are formed. Then, the stack of the SiGe layers 14, 15, and 16 and the Si layers 17, 18, 19, 101, 102, and 103 is etched using reactive ion etching (RIE) or the like. As a result, as shown in FIGS. 10 and 11 , independent Si / SiGe stacks (pillars) are formed in the first semiconductor element 100 and the second semiconductor element 200. Here, the stack of the SiGe layer 14, the Si layer 101, the SiGe layer 15, the Si layer 102, the SiGe layer 16, and the Si layer 103 is formed in the first semiconductor element 100. In addition, in the second semiconductor element 200, a stack of a SiGe layer 14, a Si layer 17, a SiGe layer 15, a Si layer 18, a SiGe layer 16, and a Si layer 19 is formed.

[0047] Next, in the formation region of the first semiconductor element 100 and the formation region of the second semiconductor element 200, the side surfaces of the SiGe layers 14, 15, and 16 exposed in the gate length direction of the Si / SiGe stack are selectively etched to partially remove the side surfaces of the SiGe layers 14, 15, and 16. Then, recesses are formed in the side surfaces of the SiGe layers 14, 15, and 16 relative to the side surfaces of the Si layers 17, 18, and 19 and the Si layers 101, 102, and 103. Note that in the selective etching process for the side surfaces of the SiGe layers 14, 15, and 16, the side surfaces of the SiGe layers 14, 15, and 16 in the gate width direction are covered by the dummy gates 34 and 35. Therefore, the side surfaces of the SiGe layers 14, 15, and 16 in the gate width direction are not etched. The SiGe layers 14, 15, and 16 are etched using isotropic etching, such as atomic layer etching (ALE), quasi-ALE, or selective vapor-phase etching. These techniques have selectivity for Si over SiGe and the reverse selectivity for SiGe over Si during the etching process. Therefore, these techniques can selectively etch the side surfaces of the SiGe layers 14, 15, and 16, forming recesses in the side surfaces of the Si / SiGe stack. The depth of the recesses is adjusted taking into account the thicknesses of the inner spacers 107 and 207 of the first semiconductor element 100 and the second semiconductor element 200. Next, an insulating layer is formed of SiN or the like to selectively cover the dummy gate insulating film 22, the dummy gate 20, the hard mask 21, and the sidewalls 106, 206, and anisotropic etching such as RIE is performed to remove the insulating layer exposed from the side surfaces of the Si / SiGe stack, leaving inner spacers 107, 207 made of the insulating layer in the recesses on the side surfaces of the SiGe layers 14, 15, 16. Through the above steps, inner spacers 107 and 207 are formed on the Si / SiGe laminate.

[0048] Then, an STI 42 embedded in the substrate 11 is formed between the region where the first semiconductor element 100 is to be formed and the region where the second semiconductor element 200 is to be formed. Then, an insulating layer 41 that covers the entire substrate 11 is formed, and then the insulating layer 41 is polished and planarized by CMP or the like to expose and planarize the upper surface of the hard mask 21. Furthermore, source and drain regions 108 and 208 are formed on the side surfaces of the Si / SiGe laminate. Each of these steps is performed by a conventionally known method.

[0049] Next, a resist layer 23 is formed on the entire surface of the substrate 11, and then the resist layer 23 is patterned so as to open only the region where the second semiconductor element 200 is to be formed, as shown in FIGS. 14 and 15, the hard mask 21 and dummy gate 20 of the second semiconductor element 200 are removed. The hard mask 21 is made of, for example, SiN. Therefore, the hard mask 21 is selectively etched using a chemical such as hydrogen fluoride, which can selectively wet etch SiN relative to SiO and Si. The dummy gate 20 is made of, for example, polysilicon (p-Si) or amorphous silicon (α-Si). Therefore, a method capable of selectively etching polysilicon (p-Si) or amorphous silicon (α-Si), such as plasma etching, is used.

[0050] 16 and 17, the dummy gate insulating film 22 of the second semiconductor element 200 is removed. Furthermore, the SiGe layers 14, 15, and 16 of the second semiconductor element 200 are selectively etched, thereby exposing the Si layers 17, 18, and 19 of the second semiconductor element 200. The selective etching of the SiGe layers 14, 15, and 16 is performed, for example, by dry etching using a mixed gas containing hydrogen fluoride and oxygen, or by wet etching using a mixed solution of hydrogen fluoride and hydrogen peroxide.

[0051] Next, the Si layers 17, 18, and 19 of the second semiconductor element 200 are selectively removed. In this step, an etching process is performed using a chemical dry etching (CDE) device or the like that can selectively remove the Si layers 17, 18, and 19. Alternatively, wet etching may be performed using an etching solution that can selectively remove the Si layers 17, 18, and 19. When wet etching is performed, for example, the following (1) and (2) can be applied. (1) Use APM, which is a mixture of ammonia, H2O2, and pure water (4:1:400, 4:1:20, 4:1:100, etc.) at 40C. (2) Use TMAH such as 5% NH4OH 60°C, 2.38% TMAH 60°C, or 5% TMAH 60°C. As a result of this step, as shown in FIGS. 18 and 19, parts of the Si layers 17, 18, and 19 remain between the stacked layers of the inner spacer 207 and in contact with the source / drain region 208, and become Si layers 201, 202, and 203. In this process, the Si layers 17, 18, and 19 are removed, and a groove 211 is formed by digging into the surface of the substrate 11, and a step is formed between the opening and the lower parts of the inner spacer 207 and the source / drain region 208.

[0052] In this step, the amount of the Si layers 201, 202, and 203 remaining between the stacked layers of the inner spacer 207 is adjusted by adjusting the etching conditions and time for the Si layers 17, 18, and 19. When all of the Si layers 17, 18, and 19 are removed, the source / drain regions 208 are exposed inside the device. In this case, the source / drain regions 208 are likely to be damaged in subsequent steps, leading to a deterioration in the characteristics of the semiconductor device. Furthermore, if subsequent manufacturing steps are performed with the source / drain regions 208 exposed, the source / drain regions 208 are likely to be damaged, leading to a deterioration in the characteristics of the semiconductor device. For this reason, in the selective removal step of the Si layers 17, 18, and 19, it is preferable to leave at least a portion of the Si layers 201, 202, and 203 between the stacked layers of the inner spacer 207 so that the source / drain regions 208 are not exposed. Furthermore, the etching conditions and time for the Si layers 17, 18, and 19 are adjusted to adjust the amount of etching on the surface of the substrate 11. In this embodiment, the etching is performed under conditions that reduce the amount of etching on the surface of the substrate 11. For example, when a CDE device is used, CDE processing conditions that provide higher selectivity for the Si layers 17, 18, and 19 than for the substrate 11 are applied. In addition, in the case of wet etching, an etchant is selected, etching conditions are set, and so on. This allows adjustments to be made so that the etching amounts of the Si layers 17, 18, and 19 are relatively large and the amount of etching on the surface of the substrate 11 is reduced.

[0053] Next, after removing the resist layer 23, an insulating layer 24 is formed on the entire surface of the substrate 11, as shown in FIGS. 20 and 21. The insulating layer 24 is made of, for example, SiO2 or the like. The insulating layer 24 is formed by, for example, CVD or the like. The insulating layer 24 becomes the gate insulating film 210 in the second semiconductor element 200 shown in FIGS. 4 and 5. For this reason, the insulating layer 24 is formed to a sufficient thickness so as to be able to withstand the high voltage applied to the second semiconductor element 200.

[0054] Next, after the entire surface of the substrate 11 is filled with a resist layer 25, the resist layer 25 is patterned so as to open only the region where the first semiconductor element 100 is to be formed, as shown in FIGS. Then, the insulating layer 24 of the first semiconductor element 100 is selectively removed. In this process, the dummy gate 20, the hard mask 21, and the dummy gate insulating film 22 are also removed. As a result, the top surface of the Si layer 103 of the first semiconductor element 100 and the inner walls of the sidewalls 106 are exposed. Furthermore, the SiGe layers 14, 15, and 16 of the first semiconductor element 100 are selectively etched. As a result, the interlayer spaces between the Si layers 101, 102, and 103 of the first semiconductor element 100 are exposed as shown in Fig. 24 and Fig. 25. The selective etching of the SiGe layers 14, 15, and 16 is performed by, for example, dry etching using a mixed gas containing hydrogen fluoride and oxygen, or wet etching using a mixed solution of hydrogen fluoride and hydrogen peroxide.

[0055] Next, as shown in FIGS. 26 and 27, the resist layer 25 is stripped off to expose the second semiconductor element 200. 28 and 29, a high-dielectric-constant material layer 26 is formed on the entire surface of the substrate 11. The high-dielectric-constant material layer 26 is formed of, for example, hafnium dioxide (HfO2), hafnium oxynitride (HfON), etc. The high-dielectric-constant material layer 26 is formed by, for example, ALD (Atomic Layer Deposition), etc.

[0056] Next, as shown in FIGS. 30 and 31 , a metal layer 27 is formed on the high-dielectric-constant material layer 26. The metal layer 27 is formed of, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium (Nb), tungsten (W), or the like. The metal layer 27 is formed by, for example, CVD. Through this process, in the first semiconductor element 100, gate electrodes 112 (see FIG. 2 ) made of the metal layer 104 are formed between the substrate 11 and each of the Si layers 101, 102, and 103, with the high-dielectric-constant material layer 105 interposed therebetween. In the second semiconductor element 200, the metal layer 204 is embedded on the substrate 11 with the high-dielectric-constant material layer 205 and gate insulating film 210 interposed therebetween, to form a gate electrode 212 (see FIG. 2 ).

[0057] Next, as shown in FIGS. 32 and 33 , the insulating layer 24, the high-dielectric-constant material layer 26, and the metal layer 27 above the insulating layer 41 are removed. Furthermore, the surfaces of the insulating layer 41, the insulating layer 24, the high-dielectric-constant material layer 26, and the metal layer 27 are planarized. For example, CMP is used to remove and planarize the insulating layer 24, the high-dielectric-constant material layer 26, and the metal layer 27. As a result, a gate electrode 112 made of the high-dielectric-constant material layer 105 and the metal layer 104 is formed in the first semiconductor element 100. Furthermore, a gate electrode 212 made of the high-dielectric-constant material layer 205 and the metal layer 204 is formed in the second semiconductor element 200. Furthermore, in the second semiconductor element 200, the insulating layer 24 with its surface planarized becomes the gate insulating film 210.

[0058] Furthermore, contacts 109, 209 are formed to connect external wiring to the source / drain regions 108, 208. For example, a resist layer is patterned over the entire surface of the substrate 11, with openings only in the areas where the contacts 109, 209 are to be formed. Then, the insulating layer 41 is etched through the openings in the resist layer to form through-holes that expose the upper surfaces of the source / drain regions 108, 208. Then, Cu or W is filled into the through-holes, and the resist layer is removed and the surface is planarized. As a result, the contacts 109, 209 that connect to the source / drain regions 108, 208 are formed, as shown in FIGS. 32 and 33.

[0059] Through the above steps, a semiconductor device 10 having a first semiconductor element 100 and a second semiconductor element 200 formed on a substrate 11 as shown in FIG. 2-5 can be manufactured. In the above-described method for manufacturing the semiconductor device 10, epitaxial growth of the Si layer and the SiGe layer can be performed in common for the first semiconductor element 100 and the second semiconductor element 200. This facilitates control of the process for forming the Si / SiGe stack and the process for processing the Si / SiGe stack. Furthermore, since there is no significant difference in the thickness of the SiGe layer, the insulating layer can be easily formed on the wall surface when forming the inner spacers 107, 207. Furthermore, there is no oxidation step that can cause device degradation after the formation of the source / drain regions 108, 208. This makes it possible to suppress performance degradation of the semiconductor device.

[0060] 3. Semiconductor Device of Second Embodiment Next, a semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment described below has the same configuration as the semiconductor device according to the first embodiment described above, with some exceptions. Therefore, detailed description of the same configuration as the semiconductor device according to the first embodiment will be omitted.

[0061] [Semiconductor device according to the second embodiment] 34 to 37 show the configuration of the semiconductor device of the second embodiment. Fig. 34 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in Fig. 1 taken along line X1. Fig. 35 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in Fig. 1 taken along line Y1. Fig. 36 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in Fig. 1 taken along line X2. Fig. 37 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in Fig. 1 taken along line Y2. In the semiconductor device of the second embodiment, the first semiconductor element 100 shown in Figures 34 and 35 has the same configuration as the semiconductor device of the first embodiment. Therefore, only the configuration of the second semiconductor element 200A shown in Figures 36 and 37 will be described below.

[0062] (Second semiconductor element) In the cross-sectional view in the gate length direction shown in FIG. 36, the second semiconductor element 200A has a gate electrode 212 on a substrate 11, with a gate insulating film 210 and a high-dielectric-constant material layer 215 interposed therebetween. In the second semiconductor element 200A, the substrate 11 has a groove 211A that is deeper than the surrounding area in a region where the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are formed. The groove 211A of the second semiconductor element 200A of the second embodiment is dug deeper in the lateral direction of the substrate 11 than the groove 211 of the second semiconductor element 200 of the first embodiment described above. Furthermore, the groove 211A of the second semiconductor element 200A of the second embodiment has a larger dug region than the groove 211 of the second semiconductor element 200 of the first embodiment. That is, the area where the groove 211A is adjacent to the substrate 11 is larger than the area of the opening 217 at the top of the element. In the groove 211 of the second semiconductor element 200 of the first embodiment, the lower part of the inner spacer 207 is hardly dug. In contrast, in the groove 211A of the second semiconductor element 200A of the second embodiment, the substrate 11 is dug down to the lower part of the inner spacer 207.

[0063] The gate insulating film 210 is formed so as to cover the surface of the groove 211A. Since the groove 211A is formed down to the bottom of the inner spacer 207, the gate insulating film 210 is formed down to the bottom of the inner spacer 207. Furthermore, a high-dielectric-constant material layer 215 is formed to cover the inner surface of the gate insulating film 210, and a metal layer 214 constituting the gate electrode 212 is filled inside the gate insulating film 210 and the high-dielectric-constant material layer 215. That is, in the second semiconductor element 200 of the above-described first embodiment, the metal layer 204 constituting the gate electrode 212 is formed only above the groove 211, whereas in the second semiconductor element 200A of the second embodiment, the metal layer 214 constituting the gate electrode 212 is formed continuously into the groove 211A. Furthermore, since the groove 211A is enlarged laterally more than the opening 217 in the upper part of the element, the area of the metal layer 214 adjacent to the substrate 11 is larger than that of the opening 217 in the upper part of the element. The second semiconductor element 200A also has an impurity diffusion region in the substrate 11 around the groove 211A in which the gate insulating film 210 and the gate electrode 212 are formed. Therefore, in the second semiconductor element 200A, the impurity diffusion region in the substrate 11 becomes a region (channel region) where a channel is formed when the second semiconductor element 200 is driven.

[0064] 37, the second semiconductor element 200A has a gate insulating film 210 formed on the substrate 11 and the STI 42, and a high-dielectric-constant material layer 215. The second semiconductor element 200A has a metal layer 214 that constitutes a gate electrode 212 on the high-dielectric-constant material layer 215. 37, the second semiconductor element 200A has a trench 211A in which the substrate 11 is dug to a lower position. A gate insulating film 210 is formed to cover the inside of the trench 211A. Therefore, the gate insulating film 210 is formed in contact with the surface of the substrate 11, the side surfaces of the trench 211A, and the top surface of the trench 211A. A metal layer 214 is embedded in the gate insulating film 210 and the high-dielectric-constant material layer 215 in the trench 211A.

[0065] In the semiconductor device of the second embodiment described above, the second semiconductor element 200A has the same configuration as the second semiconductor element 200 of the first embodiment described above, except for the groove 211A, gate insulating film 210, high-dielectric-constant material layer 215, and metal layer 214 formed in the substrate 11. Therefore, in the second semiconductor element 200A, a channel is formed in the substrate 11 when a gate voltage is applied to the gate electrode 212. Furthermore, in the second semiconductor element 200A, the groove 211A is expanded in the depth direction and lateral direction on the substrate 11, so the area in which the gate electrode 212 is formed is larger. Therefore, the second semiconductor element 200A of the second embodiment has a longer channel length, as indicated by the arrow in FIG. 36 , than the second semiconductor element 200 of the first embodiment. As a result, the second semiconductor element 200A has improved device stability.

[0066] 4. Manufacturing Method of Semiconductor Device of Second Embodiment Next, a method for manufacturing the semiconductor device according to the second embodiment shown in FIGS. 34-37 will be described. FIGS. 38-41 show manufacturing process diagrams for the semiconductor device according to the second embodiment. In the manufacturing process of the semiconductor device shown in FIGS. 38 and 40, the left side of the drawing shows a cross-sectional view (cross-sectional view in the gate length direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 taken along line X1, and the right side of the drawing shows a cross-sectional view (cross-sectional view in the gate length direction) of the second semiconductor element 200A taken along line X2. In addition, in the manufacturing process of the semiconductor device shown in FIGS. 39 and 41, the left side of the drawing shows a cross-sectional view (cross-sectional view in the gate width direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 taken along line Y1, and the right side of the drawing shows a cross-sectional view (cross-sectional view in the gate width direction) of the second semiconductor element 200A taken along line Y2.

[0067] First, the steps shown in FIGS. 6 to 17 in the method for manufacturing the semiconductor device according to the first embodiment are carried out. Then, the Si layers 17, 18, and 19 of the second semiconductor element 200A are selectively removed. In this step, a CDE process or wet etching using an etching solution is performed, which can selectively remove the Si layers 17, 18, and 19. As a result of this step, parts of the Si layers 17, 18, and 19 remain between the stacked layers of the inner spacer 207 and in positions that contact the source / drain regions 208, becoming Si layers 201, 202, and 203, as shown in FIGS. In this step, the surface of the substrate 11 is dug while the Si layers 17, 18, and 19 are removed, and steps are formed between the openings and the lower parts of the inner spacers 207 and source / drain regions 208, forming trenches 211A. In the second semiconductor element 200A, the amount of recession in the surface of the substrate 11 is made larger than that of the second semiconductor element 200 of the first embodiment by adjusting the CDE processing conditions, the type of etching solution used, the etching conditions and time, etc. 8 and 9, the first semiconductor element 100 is protected by patterning a resist layer, and this process is performed for each of the PMOS and NMOS.

[0068] 20 to 33 in the method for manufacturing the semiconductor device of the first embodiment described above, the semiconductor device of the second embodiment shown in Fig. 40 and Fig. 41 can be manufactured by appropriately applying the steps shown in Fig. 20 to Fig. 33 in the method for manufacturing the semiconductor device of the first embodiment described above. Also, the method for manufacturing the semiconductor device of the second embodiment can obtain the same effects as the method for manufacturing the semiconductor device of the first embodiment described above.

[0069] 5. Semiconductor Device of Third Embodiment Next, a semiconductor device according to a third embodiment will be described. The semiconductor device according to the third embodiment described below has the same configuration as the semiconductor device according to the first embodiment described above, with some exceptions. Therefore, detailed description of the same configuration as the semiconductor device according to the first embodiment will be omitted.

[0070] [Semiconductor device according to the third embodiment] 42 to 45 show the configuration of the semiconductor device of the third embodiment. Fig. 42 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in Fig. 1 taken along line X1. Fig. 43 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in Fig. 1 taken along line Y1. Fig. 44 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in Fig. 1 taken along line X2. Fig. 45 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in Fig. 1 taken along line Y2. In the semiconductor device of the third embodiment, the first semiconductor element 100 shown in Figures 42 and 43 has the same configuration as the semiconductor device of the first embodiment. Therefore, only the configuration of the second semiconductor element 200B shown in Figures 44 and 45 will be described below.

[0071] (Second semiconductor element) 44, the second semiconductor element 200B has source / drain regions 218 on the inner surface of the substrate 11. Except for the configurations of the source / drain regions 218 and the contacts 219, the second semiconductor element 200B has the same configuration as the second semiconductor element 200 of the above-described first embodiment. Therefore, similar to the second semiconductor element 200 of the first embodiment described above, the substrate 11 has a groove 211 that is deeper than the surrounding area in a region where the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are formed. Then, a metal layer 204 that constitutes the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 is formed on the inner wall side of the Si layers 201, 202, 203, and the inner spacer 207, including the groove 211.

[0072] The source / drain region 218 is formed on the surface of the substrate 11 outside the gate insulating film 210, from the bottom of the lowermost inner spacer 207 to the edge of the position where the insulating layer 41 is embedded as the STI . The source / drain regions 218 are formed by diffusing impurities into the surface of the substrate 11. The source / drain regions 218 have a higher concentration of diffused impurities than the diffused region on the surface of the substrate 11 below the gate electrode 212, which serves as the channel. Furthermore, the source / drain regions 218 have an impurity diffused therein that has a different conductivity type from that below the gate electrode 212, which serves as the channel.

[0073] Contacts 219 for connection to external wiring are connected to the source / drain regions 218. The contacts 219 are formed of a metal material embedded in through holes that penetrate from the top of the insulating layer 41 of the second semiconductor element 200B to the source / drain regions 218.

[0074] In the cross-sectional view in the gate width direction shown in FIG. 45, the second semiconductor element 200B has the same configuration as the cross-sectional view in the gate width direction of the second semiconductor device of the first embodiment shown in FIG. 5 described above.

[0075] In the semiconductor device of the third embodiment described above, the second semiconductor element 200B has source / drain regions 218 formed in the substrate 11. In this configuration, the source / drain regions 218 can be formed by ion implantation, which makes it easy to adjust the characteristics of the second semiconductor element 200B.

[0076] 6. Manufacturing Method of Semiconductor Device of Third Embodiment Next, a method for manufacturing the semiconductor device according to the third embodiment shown in FIGS. 42-45 will be described. FIGS. 46-61 show manufacturing process diagrams for the semiconductor device according to the third embodiment. In the manufacturing process of the semiconductor device shown in FIGS. 46, 48, 50, 52, 54, 56, 58, and 60, the left side of the drawings shows a cross-sectional view (cross-sectional view in the gate length direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 along line X1, and the right side of the drawings shows a cross-sectional view (cross-sectional view in the gate length direction) of the second semiconductor element 200B. Also, in the manufacturing process of the semiconductor device 10 shown in FIGS. 47, 49, 51, 53, 55, 57, 59, and 61, the left side of the drawings shows a cross-sectional view (cross-sectional view in the gate width direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 along line Y1, and the right side of the drawings shows a cross-sectional view (cross-sectional view in the gate width direction) of the second semiconductor element 200A along line Y2.

[0077] 6 to 9 in the method for manufacturing the semiconductor device of the first embodiment described above are performed. Then, a Si / SiGe stack, a dummy gate insulating film 22, a dummy gate 20, and a hard mask 21 are formed, and these stacks are separated into individual elements. Furthermore, an STI 42 is formed in the substrate 11, and sidewalls 106 and 206 are formed, thereby fabricating the structures of the first semiconductor element 100 and the second semiconductor element 200B shown in FIGS. 46 and 47.

[0078] Next, a resist layer 28 is formed on the entire surface of the substrate 11, and then, as shown in FIGS. 48 and 49, the resist layer 28 is patterned so as to open only the region where the second semiconductor element 200B is to be formed. 50 and 51, impurity ions are implanted through the openings in the resist layer 28 into the formation region of the second semiconductor element 200B, followed by annealing or the like to form source / drain regions 218 inside the substrate 11. In the implantation of the impurity ions, the sidewalls 206 serve as a mask, so that the impurities are implanted only into the region of the substrate 11 outside the Si / SiGe stack. Then, annealing or the like causes the impurities to diffuse to the bottom of the Si / SiGe stack. As a result, a continuous source / drain region 218 is formed in the surface of the substrate 11, from the end on the STI 42 side to the bottom of the Si / SiGe stack. Furthermore, impurity ions are implanted into the substrate 11 in the formation region of the second semiconductor element 200B for both the NMOS and PMOS. Specifically, in patterning the resist layer 28, only the second semiconductor element 200B that will become the NMOS is opened, and impurity ions such as phosphorus are implanted. Furthermore, the resist layer 28 is patterned to open only the second semiconductor element 200B that will become the PMOS, and impurity ions such as boron are implanted. Through this process, impurity ions of different conductivity types are implanted into the second semiconductor element 200B that will become the NMOS or PMOS.

[0079] Next, as shown in Figures 52 and 53, the resist layer 28 is peeled off. Then, inner spacers 107 and 207 are formed on the first semiconductor element 100 and the second semiconductor element 200B.

[0080] 54 and 55, the AlO (aluminum oxide) layer 29 is patterned so as to open only the region where the first semiconductor element 100 is to be formed. Then, as shown in FIGS. 56 and 57, source / drain regions 108 are formed in the first semiconductor element 100. The source / drain regions 108 are formed in the first semiconductor element 100 for both the NMOS and the PMOS. Specifically, in patterning the AlO layer 29, only the first semiconductor element 100 that will become the NMOS is opened, and n-type source / drain regions 108 are formed by epitaxial growth with the addition of impurity ions such as phosphorus. Furthermore, the AlO layer 29 is patterned to open only the first semiconductor element 100 that will become the PMOS, and p-type source / drain regions 108 are formed by epitaxial growth with the addition of impurity ions such as boron. Through this process, source / drain regions 108 of different conductivity types are formed in the first semiconductor element 100 that will become the NMOS or the PMOS.

[0081] Next, as shown in FIGS. 58 and 59, the AlO layer 29 is peeled off. 10 to 33 in the method for manufacturing the semiconductor device of the first embodiment described above, the semiconductor device of the third embodiment shown in Figures 60 and 61 can be manufactured. Also, the method for manufacturing the semiconductor device of the third embodiment can obtain the same effects as the method for manufacturing the semiconductor device of the first embodiment described above.

[0082] 7. Semiconductor Device of Fourth Embodiment Next, a semiconductor device according to a fourth embodiment will be described. The semiconductor device according to the fourth embodiment described below has a similar configuration to the semiconductor device according to the first embodiment described above. Therefore, a description of the same configuration as the semiconductor device according to the first embodiment will be omitted.

[0083] 62 and 63 show the configuration of a semiconductor device according to the second embodiment. FIG. 62 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X1. FIG. 63 corresponds to a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X2. In the description of the fourth embodiment, the configurations of the cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1 taken along line Y-1 and line Y2 (cross-sectional view in the gate width direction) are omitted. The cross-sectional view in the gate width direction also has a configuration in which the first semiconductor element 100 and the second semiconductor element 200 shown in FIG. 3 or FIG. 5 are stacked, similar to FIGS. 62 and 63.

[0084] In the semiconductor device of the fourth embodiment, a first semiconductor element 100C shown in FIG. 62 and a second semiconductor element 200C shown in FIG. 62 has a third semiconductor element 100D and a fourth semiconductor element 100E, each having a configuration similar to that of the first semiconductor element 100 shown in Fig. 2, stacked on a substrate 11. In the first semiconductor element 100C, the fourth semiconductor element 100E is formed on the third semiconductor element 100D. In addition, in the first semiconductor element 100C, the source-drain region 108a of the third semiconductor element 100D is formed as a p-type PMOS, and the source-drain region 108b of the fourth semiconductor element 100E is formed as an n-type NMOS.

[0085] 63 has a fifth semiconductor element 200D and a sixth semiconductor element 200E, each having a configuration similar to that of the second semiconductor element 200 shown in Fig. 4, stacked on a substrate 11. In the second semiconductor element 200C, the sixth semiconductor element 200E is formed on the fifth semiconductor element 200D. In the second semiconductor element 200C, the source-drain region 208a of the fifth semiconductor element 200D is formed as a p-type PMOS, and the source-drain region 208b of the sixth semiconductor element 200E is formed as an n-type NMOS.

[0086] The semiconductor device of the fourth embodiment can be manufactured, for example, by the following steps. As in the semiconductor device of the first embodiment described above, a third PMOS semiconductor element 100D and a fifth PMOS semiconductor element 200D are formed on a substrate 11. Then, another substrate 11 is bonded to the upper surface side of the substrate 11 on which the third semiconductor element 100D and the fifth semiconductor element 200D are formed. Then, as in the semiconductor device of the first embodiment described above, a fourth NMOS semiconductor element 100D and a sixth NMOS semiconductor element 200D are formed on the substrate 11. Through these steps, the semiconductor device of the fourth embodiment shown in FIGS. 62 and 63 can be manufactured.

[0087] In the semiconductor device of the fourth embodiment, the third semiconductor element 100D and the fourth semiconductor element 100E of the first semiconductor element 100C may be any combination of PMOS and NMOS, PMOS and PMOS, or NMOS and NMOS. Similarly, the fifth semiconductor element 200D and the sixth semiconductor element 200E of the second semiconductor element 200C may be any combination of PMOS and NMOS, PMOS and PMOS, or NMOS and NMOS. Furthermore, in the semiconductor device of the fourth embodiment, the second semiconductor element 200C, the fifth semiconductor element 200D, and the sixth semiconductor element 200E may be configured not only in the same manner as the second semiconductor element 200 shown in FIG. 4 described above, but also in any combination of the second semiconductor element 200A of the second embodiment shown in FIG. 36 and the second semiconductor element 200B of the third embodiment shown in FIG. 44.

[0088] The present invention is not limited to the configurations described in the above-described embodiments, and various modifications and changes are possible without departing from the scope of the present invention. [Explanation of symbols]

[0089] 10 semiconductor device, 11 substrate, 12, 13, 23, 25, 28 resist layer, 14, 15, 16 SiGe layer, 17, 18, 19 Si layer, 20 dummy gate, 21 hard mask, 22 dummy gate insulating film, 24, 41 insulating layer, 26, 105, 205, 215 high-dielectric-constant material layer, 29 AlO layer, 42 STI, 100, 100C first semiconductor element, 100D third semiconductor element, 100E fourth semiconductor element, 101, 102, 103 Si layer, 104, 204, 214, 27 metal layer, 106, 206, 216 sidewall, 107, 207 inner spacer, 108, 108a, 108b, 208, 208a, 208b, 218 Source and drain regions, 109, 209, 219 contacts, 112, 212 gate electrodes, 200, 200A, 200B, 200C second semiconductor element, 200D fifth semiconductor element, 200E sixth semiconductor element, 201, 202, 203 Si layer, 210 gate insulating film, 211, 211A groove portion, 217 opening

Claims

1. A semiconductor device comprising a first semiconductor element and a second semiconductor element on a substrate, The first semiconductor element comprises: a first stacked body including a channel layer and a first gate electrode covering the periphery of the channel layer in a cross section of the first semiconductor element in a gate width direction; a first gate insulating film interposed between the channel layer and the first gate electrode; and The second semiconductor element comprises: a second gate electrode formed on the substrate via a second gate insulating film; a channel region formed in the substrate below the second gate electrode. Semiconductor device.

2. The second semiconductor element comprises: a Si layer and a second insulating layer are provided on a side surface of the second gate electrode, and the second gate insulating film is interposed between the second gate electrode and the Si layer and the second insulating layer; The semiconductor device according to claim 1 .

3. The second semiconductor element comprises: a second source / drain region formed on a side surface of the laminated Si layer and the second insulating layer on the substrate; The semiconductor device according to claim 2 .

4. A second source / drain region is provided in the substrate. The semiconductor device according to claim 1 .

5. The first semiconductor element comprises: a first source / drain region formed on a side surface of the first stacked body in a gate length direction; a first insulating layer formed between the first gate electrode disposed between the channel layers and a side surface of the first source / drain region; Equipped with The semiconductor device according to claim 1 .

6. In the second semiconductor element, the substrate has a groove portion below the second gate electrode that is dug deeper than the periphery below the second gate electrode. The semiconductor device according to claim 1 .

7. The second gate electrode is disposed above the trench. The semiconductor device according to claim 6.

8. The second gate electrode is formed inside the groove. The semiconductor device according to claim 6.

9. A method for manufacturing a semiconductor device including a first semiconductor element and a second semiconductor element on a substrate, the method comprising: forming a channel region by implanting impurity ions into the substrate in a region where the second semiconductor element is to be formed; forming a Si / SiGe stack by stacking a Si layer and a SiGe layer in the formation region of the first semiconductor element and the formation region of the second semiconductor element; removing the SiGe layer in a region where the first semiconductor element is to be formed; forming a first gate insulating film in a region where the first semiconductor element is to be formed; removing the SiGe layer in a region where the second semiconductor element is to be formed; removing the Si layer in a region where the second semiconductor element is to be formed; forming a second gate insulating film thicker than the first gate insulating film in a region where the second semiconductor element is to be formed; forming a metal layer in the formation region of the first semiconductor element and the formation region of the second semiconductor element, and forming a first gate electrode and a second gate electrode. A method for manufacturing a semiconductor device.

10. forming second source / drain regions in the second semiconductor element formation region at positions facing each other across the channel region; The method for manufacturing a semiconductor device according to claim 9 .

11. forming the second source / drain regions on the substrate in the second semiconductor element formation region; The method for manufacturing a semiconductor device according to claim 10.

12. forming the second source / drain regions in the substrate in the second semiconductor element formation region; The method for manufacturing a semiconductor device according to claim 10.

13. forming an insulating layer on a sidewall of the SiGe layer in the first semiconductor element formation region and the second semiconductor element formation region; The method for manufacturing a semiconductor device according to claim 9 .

14. removing the Si layer so that it remains only between the insulating layers in the region where the second semiconductor element is to be formed. The method for manufacturing a semiconductor device according to claim 13.

15. In the step of removing the Si layer, a groove is formed in the substrate. The method for manufacturing a semiconductor device according to claim 14.

16. The metal layer is buried in the groove, and the second gate electrode is formed in the groove. The method for manufacturing a semiconductor device according to claim 15.

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