Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing rises in temperature in a first wiring part, a second wiring part, and a third wiring part.SOLUTION: Regarding a first semiconductor chip 31 and a second semiconductor chip 32, ON / OFF is controlled in such a manner that currents in reverse directions can flow through a first wiring part 101 and a second wiring part 102. The first wiring part 101, the second wiring part 102, and a third wiring part 103 are collectively disposed on the opposite sides to the side of a first heat sink 21 and the side of a second heat sink 22 across the first semiconductor chip 31 and the second semiconductor chip 32. The first wiring part 101 and the second wiring part 102 include portions which are disposed oppositely. A semiconductor device comprises: a third heat sink 23 which is disposed on the opposite side to the first wiring part 101, the second wiring part 102, and the third wiring part 103 across the first semiconductor chip 31 and the second semiconductor chip 32 and disposed opposed to the first wiring part 101 and the second wiring part 102; and a fourth heat sink 24 which is disposed opposed to the third wiring part 103.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device having a first semiconductor chip and a second semiconductor chip. [Background technology]

[0002] Conventionally, semiconductor devices having a first semiconductor chip and a second semiconductor chip have been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor device, the first semiconductor chip is disposed on a first heat sink, and the second semiconductor chip is disposed on a second heat sink. The semiconductor device also has a first wiring portion connected to the first semiconductor chip, a second wiring portion connected to the second semiconductor chip, and a third wiring portion connected to the first and second semiconductor chips. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-154937 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described above, heat generated in the first semiconductor chip is dissipated from the first heat sink, and heat generated in the second semiconductor chip is dissipated from the second heat sink. However, in the semiconductor device described above, the first wiring portion connected to the first semiconductor chip, the second wiring portion connected to the second semiconductor chip, and the third wiring portion connected to the first and second semiconductor chips also generate heat. Therefore, there is currently a demand for a semiconductor device described above that dissipates heat from the first wiring portion, the second wiring portion, and the third wiring portion and prevents the first wiring portion, the second wiring portion, and the third wiring portion from becoming too hot.

[0005] An object of the present disclosure is to provide a semiconductor device that can prevent the first wiring portion, the second wiring portion, and the third wiring portion from becoming too hot. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, a semiconductor device includes a first semiconductor chip (31) and a second semiconductor chip (32) on which switching elements are formed, a first heat sink (21) on which the first semiconductor chip is disposed, a second heat sink (22) on which the second semiconductor chip is disposed, a sealing member (50) that seals the first semiconductor chip and the second semiconductor chip and is made of a resin material, a first wiring portion (101) connected to the first semiconductor chip, a second wiring portion (102) connected to the second semiconductor chip, and a third wiring portion (103) that connects the first semiconductor chip and the second semiconductor chip, The on / off of the heat sink is controlled so that currents flow in opposite directions through the first wiring portion and the second wiring portion, the first wiring portion, the second wiring portion, and the third wiring portion are arranged together on the first heat sink side and the opposite side of the second heat sink side, with the first semiconductor chip and the second semiconductor chip sandwiched between them, the first wiring portion and the second wiring portion have portions arranged opposite each other, and the heat sink (23) is arranged opposite the first wiring portion and the second wiring portion and the fourth heat sink (24) is arranged opposite the third wiring portion.

[0007] According to this, the third heat sink is arranged to face the first wiring portion and also to face the second wiring portion. The fourth heat sink is arranged to face the third wiring portion. This makes it easier for heat that may be generated in the first to third wiring portions to be dissipated from the third and fourth heat sinks, and prevents the first to third wiring portions from becoming too hot.

[0008] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of the semiconductor device shown in FIG. [Figure 3] FIG. 2 is a diagram showing the circuit configurations of a first semiconductor chip and a second semiconductor chip. [Figure 4] FIG. 2 is a cross-sectional view showing a current flowing through the semiconductor device. [Figure 5] FIG. 2 is a plan view showing a current flowing in the semiconductor device; [Figure 6] FIG. 2 is a plan view showing a current flowing in the semiconductor device; [Figure 7] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 9A] FIG. 10 is a cross-sectional view of a semiconductor device according to another embodiment. [Figure 9B] FIG. 10 is a cross-sectional view of a semiconductor device according to another embodiment. [Figure 9C] FIG. 10 is a cross-sectional view of a semiconductor device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0011] (First embodiment) A first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is suitable for use, for example, in a vehicle to control various electronic components.

[0012] As shown in Figures 1 and 2, the semiconductor device includes an external connection heat sink 10, a first heat sink 21, a second heat sink 22, a third heat sink 23, a fourth heat sink 24, a first semiconductor chip 31, a second semiconductor chip 32, a sealing member 50, and first to third wiring portions 101 to 103. Figure 1 is a cross-sectional view taken along line II in Figure 2. Figure 2 is a plan view of the semiconductor device shown in Figure 1, but for ease of understanding, a protective film 60, which will be described later, is omitted.

[0013] The heat sink 10 for external connection has a main heat sink 11 made of a copper plate or the like having one surface 11a and another surface 11b, and an insulating sheet 12 arranged on the one surface 11a side of the main heat sink 11. When the semiconductor device is mounted on a mounting member such as a vehicle, the other surface 11b side of the main heat sink 11 is joined to the mounting member. The main heat sink 11 is made of, for example, a copper plate, and the insulating sheet 12 is made of, for example, an epoxy resin.

[0014] In the following description of this embodiment, one direction in the plane of the external connection heat sink 10 is referred to as the X-axis direction, a direction perpendicular to the X-axis direction in this plane is referred to as the Y-axis direction, and a direction perpendicular to the X-axis and Y-axis directions is referred to as the Z-axis direction. For example, in FIG. 1 , the left-right direction of the paper surface is referred to as the X-axis direction, the direction perpendicular to the paper surface is referred to as the Y-axis direction, and the up-down direction of the paper surface is referred to as the Z-axis direction. Note that the X-axis direction is also the arrangement direction of the first semiconductor chip 31 and the second semiconductor chip 32, as will be described later. The Z-axis direction is also the stacking direction of the first semiconductor chip 31 and the first heat sink 21, and the stacking direction of the second semiconductor chip 32 and the second heat sink 22, as will be described later.

[0015] The first to fourth heat sinks 21 to 24 are each a block made of copper or the like. In this embodiment, they are each a rectangular shape in plan view, and are made equal in length in the Y-axis direction and equal in length in the Z-axis direction (i.e., thickness). Note that "equal" here includes slight manufacturing errors.

[0016] The first to fourth heat sinks 21 to 24 are arranged side by side on the insulating sheet 12 of the external connection heat sink 10. Specifically, the first to fourth heat sinks 21 to 24 are arranged side by side in the X-axis direction in the order of the fourth heat sink 24, the first heat sink 21, the second heat sink 22, and the third heat sink 23. In FIG. 1, the fourth heat sink 24, the first heat sink 21, the second heat sink 22, and the third heat sink 23 are arranged side by side in the order of the left side of the paper in the X-axis direction to the right side of the paper.

[0017] The first semiconductor chip 31 and the second semiconductor chip 32 are configured by forming semiconductor elements such as switching elements such as MOSFET elements and IGBT elements, and freewheeling diode elements, etc. Note that MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor, and IGBT is an abbreviation for Insulated Gate Bipolar Transistor.

[0018] In this embodiment, the first semiconductor chip 31 has a first electrode 311 formed on one surface 31a and a second electrode 312 formed on the other surface 31b, and a semiconductor element formed to allow current to flow between the first electrode 311 and the second electrode 312. The first semiconductor chip 31 also has a plurality of pad portions 313 formed on the one surface 31a, including gate pads connected to gate electrodes in MOSFET elements and IGBT elements. The pad portions 313 are shown in FIG. 2.

[0019] Similarly, the second semiconductor chip 32 has a first electrode 321 formed on one surface 32a and a second electrode 322 formed on the other surface 32b, and a semiconductor element formed to allow current to flow between the first electrode 321 and the second electrode 322. The second semiconductor chip 32 also has a plurality of pad portions 323 formed on the one surface 32a, including gate pads connected to gate electrodes in MOSFET elements and IGBT elements. The pad portions 323 are shown in FIG. 2.

[0020] The first semiconductor chip 31 is disposed on the first heat sink 21 via a first bonding member 41. The second semiconductor chip 32 is disposed on the second heat sink 22 via a second bonding member 42. In other words, the first to fourth heat sinks 21 to 24 are disposed on the same side in the Z-axis direction (i.e., the lower side of the paper in FIG. 1) with respect to the first semiconductor chip 31 and the second semiconductor chip 32.

[0021] The first bonding member 41 is made of a material that electrically and thermally connects the first semiconductor chip 31 and the first heat sink 21, such as solder or sintered silver. The second bonding member 42 is made of a material that electrically and thermally connects the second semiconductor chip 32 and the second heat sink 22, such as solder or sintered silver. By placing the first semiconductor chip 31 on the first heat sink 21 in this manner, heat from the first semiconductor chip 31 is dissipated from the first heat sink 21 to the external connection heat sink 10. By placing the second semiconductor chip 32 on the second heat sink 22, heat from the second semiconductor chip 32 is dissipated from the second heat sink 22 to the external connection heat sink 10.

[0022] In this embodiment, the first semiconductor chip 31 and the second semiconductor chip 32 are connected in series to form an upper arm UA and a lower arm LA of an inverter circuit or the like. Specifically, as shown in FIG. 3 , the first semiconductor chip 31 is used to form the upper arm UA, with the second electrode 312 connected to the first wiring portion 101 and the first electrode 311 connected to the third wiring portion 103. The second semiconductor chip 32 is used to form the lower arm LA, with the second electrode 322 connected to the third wiring portion 103 and the first electrode 321 connected to the second wiring portion 102. The first wiring portion 101 serves as a so-called P wiring, the second wiring portion 102 serves as a so-called N wiring, and the third wiring portion 103 serves as a so-called O wiring. Although not shown, the third wiring portion 103 is connected to an external load or the like. In such a circuit configuration, the switching elements of the first semiconductor chip 31 and the second semiconductor chip 32 are alternately turned on, and at the moment when the on state switches, currents flow in opposite directions through the first wiring section 101 and the second wiring section 102.

[0023] 1, the sealing member 50 is disposed on the external connection heat sink 10 so as to seal the first semiconductor chip 31, the second semiconductor chip 32, the first heat sink 21, the second heat sink 22, the third heat sink 23, the fourth heat sink 24, etc. In this embodiment, the sealing member 50 is formed by laminating multiple film members made of resin such as prepreg and integrating them under heat and pressure. Note that the sealing member 50 disposed between the first heat sink 21, the second heat sink 22, the third heat sink 23, and the fourth heat sink 24 is disposed by the resin material constituting the film members flowing in when the film members are integrated under heat and pressure.

[0024] Hereinafter, in this embodiment, the portion of the sealing member 50 that is placed on the insulating sheet 12 and seals the first and second semiconductor chips 31, 32, the first to fourth heat sinks 21 to 24, etc. will be referred to as the first sealing member 51, and the portion that is placed on the first sealing member 51 will be referred to as the second sealing member 52.

[0025] The first to third wiring portions 101 to 103 are appropriately arranged on the first sealing member 51 or the second sealing member 52 so that the first semiconductor chip 31 and the second semiconductor chip 32 form an upper arm UA and a lower arm LA. That is, the first to third wiring portions 101 to 103 of this embodiment are arranged together on the same side (i.e., the upper side of the paper in FIG. 1) with respect to the first semiconductor chip 31 and the second semiconductor chip 32. The first to third wiring portions 101 to 103 are made of, for example, aluminum wiring or copper wiring.

[0026] Specifically, first chip via holes 511 are formed in the first sealing member 51 to expose the first electrodes 311 of the first semiconductor chip 31. Second chip via holes 512 are formed in the first sealing member 51 to expose the first electrodes 321 of the second semiconductor chip 32. Second heat sink via holes 513 are formed in the first sealing member 51 to expose the portion of the second heat sink 22 on the first heat sink 21 side. Note that each of the via holes 511 to 513 is formed in plurality.

[0027] The third wiring section 103 has a third wiring section wiring layer 131 disposed on the first sealing member 51 so as to face the portion of the fourth heat sink 24, the first heat sink 21, the first semiconductor chip 31, and the second heat sink 22 that is on the first heat sink 21 side. The third wiring section wiring layer 131 is connected to the first electrode 311 of the first semiconductor chip 31 through the first chip via 511a disposed in the first chip via hole 511. The third wiring section wiring layer 131 is also connected to the second heat sink 22 through the second heat sink via 513a disposed in the second heat sink via hole 513, and is connected to the second electrode 322 of the second semiconductor chip 32 through the second heat sink 22. The first chip via 511a and the second heat sink via 513a are formed of, for example, copper vias. Similarly, each via described below is also formed of, for example, copper vias.

[0028] The third wiring portion wiring layer 131 of this embodiment has a generally rectangular planar shape with the longitudinal direction in the X-axis direction, and is formed so that the length in the Y-axis direction is shorter than that of the first wiring portion wiring layer 111 in the portion where it overlaps with the first wiring portion wiring layer 111 (described later) in the Z-axis direction. Furthermore, the third wiring portion wiring layer 131 is formed so as not to overlap with the pad portion 313 of the first semiconductor chip 31 in the Z-axis direction. In other words, "in the Z-axis direction" can also be defined as when viewed from the Z-axis direction.

[0029] The second wiring portion 102 has a second wiring portion wiring layer 121 arranged on the first sealing member 51 so as to face the third heat sink 23, the second heat sink 22, and the second semiconductor chip 32. The second wiring portion wiring layer 121 is connected to the first electrode 321 of the second semiconductor chip 32 through the second chip via 512a arranged in the second chip via hole 512.

[0030] In this embodiment, the second wiring portion wiring layer 121 has a generally rectangular planar shape with the X-axis direction as the longitudinal direction. The second wiring portion wiring layer 131 is formed so that its end portion on the side opposite to the second semiconductor chip 32 in the X-axis direction protrudes from the first wiring portion wiring layer 111 described later. The second wiring portion wiring layer 121 is formed so as not to overlap with the pad portions 323 of the second semiconductor chip 32 in the Z-axis direction.

[0031] The second sealing member 52 is disposed on the first sealing member 51 so as to cover the third wiring portion wiring layer 131 and the second wiring portion wiring layer 121. The second sealing member 52 has a third wiring portion via hole 523 formed therein, which exposes a portion of the third wiring portion wiring layer 131 that faces the fourth heat sink 24. The second sealing member 52 also has a second wiring portion via hole 522 formed therein, which exposes a portion of the second wiring portion wiring layer 121 that faces the third heat sink 23.

[0032] First heat sink via holes 531 are formed in the first sealing member 51 and the second sealing member 52, exposing the portion of the first heat sink 21 on the second heat sink 22 side. Note that a plurality of each of the via holes 522, 523, and 531 are formed.

[0033] The first wiring portion 101 has a first wiring portion wiring layer 111 arranged on the second sealing member 52 so as to face the third heat sink 23, the second semiconductor chip 32, and a portion of the first heat sink 21 that faces the second heat sink 22. Specifically, the first wiring portion wiring layer 111 is arranged so as to face the second wiring portion wiring layer 121 and a portion of the first heat sink 21 that faces the second heat sink 22. In other words, the first wiring portion wiring layer 111 has a portion located on the opposite side of the second wiring portion wiring layer 121 from the third heat sink 23.

[0034] The first wiring portion wiring layer 111 has a generally rectangular planar shape with its longitudinal direction in the X-axis direction. The first wiring portion wiring layer 111 is formed such that both ends in the Y-axis direction protrude from the third wiring portion wiring layer 131 in a portion facing the first heat sink 21. In other words, the first wiring portion wiring layer 111 has a non-overlapping portion that does not face the third wiring portion wiring layer 131 in a portion facing the first heat sink 21. The protruding portion of the first wiring portion wiring layer 111 is connected to the first heat sink 21 through a first heat sink via 531a arranged in the first heat sink via hole 531, and is connected to the second electrode 312 of the first semiconductor chip 31 through the first heat sink 21.

[0035] A first terminal portion 112 constituting the first wiring portion 101, a second terminal portion 122 constituting the second wiring portion 102, and a third terminal portion 132 constituting the third wiring portion 103 are arranged on the second sealing member 52. The third terminal portion 132 is arranged to face the fourth heat sink 24 in the Z-axis direction, and is connected to the third wiring portion wiring layer 131 through a third wiring portion via 523a arranged in a third wiring portion via hole 523 formed in the second sealing member 52.

[0036] The second terminal portion 122 is arranged to face the third heat sink 23 and is connected to the second wiring portion wiring layer 121 through the second wiring portion via 522a arranged in the second wiring portion via hole 522 formed in the second sealing member 52.

[0037] The first terminal 112 is configured as a part of the first wiring portion wiring layer 111, and is configured as a portion facing the third heat sink 23. In this embodiment, the first terminal 112, the second terminal 122, and the third terminal 132 are arranged in the X-axis direction in the order of the third terminal 132, the first terminal 112, and the second terminal 122. More specifically, the first and second semiconductor chips 31, 32 and the first to third terminals 112 to 132 are arranged in the Z-axis direction along the X-axis direction in the order of the third terminal 132, the first semiconductor chip 31, the second semiconductor chip 32, the first terminal 112, and the second terminal 122.

[0038] A protective film 60 made of solder resist or the like is formed on the second sealing member 52. The protective film 60 is formed with a contact hole 61 that exposes the first terminal portion 112, a contact hole 62 that exposes the second terminal portion 122, and a contact hole 63 that exposes the third terminal portion 132.

[0039] Also, on the second sealing member 52, first signal terminals 141 connected to pads 313 of the first semiconductor chip 31 and second signal terminals 142 connected to pads 323 of the second semiconductor chip 32 are formed. Although not particularly shown, the pads 313 of the first semiconductor chip 31 and the first signal terminals 141 are electrically connected through a connection wiring layer arranged on the first sealing member 51 and connection vias formed in the first sealing member 51 and the second sealing member 52. Similarly, the pads 323 of the second semiconductor chip 32 and the second signal terminals 142 are electrically connected through a connection wiring layer arranged on the first sealing member 51 and connection vias formed in the first sealing member 51 and the second sealing member 52. The first signal terminals 141 and the second signal terminals 142 are arranged so as to be exposed from contact holes formed in the protective film 60.

[0040] The above is the configuration of the semiconductor device in this embodiment. In this semiconductor device, as described above, the switching elements of the first semiconductor chip 31 and the second semiconductor chip 32 are alternately turned on, and as shown in FIGS. 4 to 6, current flows as indicated by arrow A at the moment when the on state is switched. In this case, in this embodiment, the first to third wiring portions 101 to 103 are arranged as described above, so that impedance can be reduced. Note that in FIG. 5, arrow A indicates the current flowing from the second terminal portion 122 to the first semiconductor chip 31. In FIG. 6, arrow A indicates the current flowing from the first semiconductor chip 31 to the first terminal portion 112.

[0041] 4, the first wiring portion wiring layer 111 and the second wiring portion wiring layer 121 are arranged to face each other. Therefore, in this portion, current flows in opposite directions through the first wiring portion wiring layer 111 and the second wiring portion wiring layer 121, thereby reducing the impedance between the first wiring portion wiring layer 111 and the second wiring portion wiring layer 121.

[0042] In the portion indicated by arrow b, the first wiring portion wiring layer 111 and the second heat sink 22 are arranged to face each other. Therefore, in this portion, current flows in opposite directions through the first wiring portion wiring layer 111 and the second heat sink 22, thereby reducing the impedance between the first wiring portion wiring layer 111 and the second heat sink 22.

[0043] In the portion indicated by the arrow c, the third wiring portion wiring layer 131 and the first heat sink 21 are arranged to face each other. Therefore, in this portion, current flows in opposite directions through the third wiring portion wiring layer 131 and the first heat sink 21, thereby reducing the impedance between the third wiring portion wiring layer 131 and the first heat sink 21.

[0044] In the portion indicated by arrow d, the first wiring portion wiring layer 111 and the third wiring portion wiring layer 131 are arranged to face each other. Therefore, in this portion, current flows in opposite directions through the first wiring portion wiring layer 111 and the third wiring portion wiring layer 131, thereby reducing the impedance between the first wiring portion wiring layer 111 and the third wiring portion wiring layer 131.

[0045] Furthermore, the semiconductor device of this embodiment is provided with a third heat sink 23 and a fourth heat sink 24 in addition to the first heat sink 21 on which the first semiconductor chip 31 is disposed and the second heat sink 22 on which the second semiconductor chip 32 is disposed. Specifically, the third heat sink 23 is disposed so as to face the first wiring portion wiring layer 111 and the first terminal 112, and is disposed so as to face the second wiring portion wiring layer 121 and the second terminal 122. The fourth heat sink 24 is disposed so as to face the third wiring portion wiring layer 131 and the third terminal 132. This makes it possible to easily dissipate heat that may be generated in the first to third wiring portions 101 to 103 from the third heat sink 23 and the fourth heat sink 24, thereby preventing the first to third wiring portions 101 from becoming too hot.

[0046] According to the present embodiment described above, the third heat sink 23 is disposed to face the first wiring portion wiring layer 111 and the first terminal 112, and also faces the second wiring portion wiring layer 121 and the second terminal 122. The fourth heat sink 24 is disposed to face the third wiring portion wiring layer 131 and the third terminal 132. This makes it possible to easily dissipate heat that may be generated in the first to third wiring portions 101 to 103 from the third heat sink 23 and the fourth heat sink 24, thereby preventing the first to third wiring portion 101 from becoming too hot. Furthermore, since the first to fourth heat sinks 21 to 24 are disposed on the same side of the first and second semiconductor chips 31 and 32, and the first to third wiring portions 101 to 103 are collectively disposed on the opposite side of the first to fourth heat sinks 21 to 24 across the first and second semiconductor chips 31 and 32, it is possible to prevent the arrangement from becoming complicated.

[0047] (1) In this embodiment, the first to fourth heat sinks 21 to 24 have the same thickness. Therefore, when forming the sealing member 50, the flowability of the resin material forming the sealing member 50 is less likely to vary, and quality variations can be suppressed.

[0048] (2) In this embodiment, in the Z-axis direction, the first and second semiconductor chips 31, 32 and the first to third terminal portions 112 to 132 are arranged in the X-axis direction in the following order: third terminal portion 132, first semiconductor chip 31, second semiconductor chip 32, first terminal portion 112, second terminal portion 122. This makes it easy to route the first to third wiring portions 101.

[0049] (3) In this embodiment, the first wiring portion wiring layer 111 and the third wiring portion wiring layer 131 are configured so that, in the portions located on the first heat sink 21, the first wiring portion wiring layer 111 has a portion that does not overlap with the third wiring portion wiring layer 131. The non-overlapping portion of the first wiring portion wiring layer 111 is connected to the first heat sink 21. This makes it possible to easily connect the first wiring portion wiring layer 111 and the first heat sink 21.

[0050] (4) In this embodiment, the first wiring portion wiring layer 111 is configured to have a portion located on the opposite side of the second wiring portion wiring layer 121 from the third heat sink 23. This facilitates routing of the first wiring portion 101 and the second wiring portion 102 when the third terminal portion 132, the first semiconductor chip 31, the second semiconductor chip 32, the first terminal portion 112, and the second terminal portion 122 are arranged in this order along the X-axis direction.

[0051] (Second embodiment) A second embodiment will now be described. This embodiment differs from the first embodiment in that the number of first semiconductor chips 31 and second semiconductor chips 32 is changed. As the rest of the configuration is the same as the first embodiment, a description thereof will be omitted here.

[0052] 7, the semiconductor device of this embodiment is provided with two first semiconductor chips 31, each of which is arranged on the first heat sink 21. In this embodiment, the two first semiconductor chips 31 are arranged on the first heat sink 21 so as to be adjacent to each other in the Y-axis direction.

[0053] Similarly, two second semiconductor chips 32 are provided, each arranged on the second heat sink 22. In this embodiment, the two second semiconductor chips 32 are arranged on the second heat sink 22 so as to be adjacent to each other in the Y-axis direction.

[0054] In this embodiment, the two first semiconductor chips 31 are connected in parallel to form one upper arm UA, and the two second semiconductor chips 32 are connected in parallel to form one lower arm LA.

[0055] The length of the first heat sink 21 in the Y-axis direction is adjusted so that two first semiconductor chips 31 can be arranged side by side in the Y-axis direction. Similarly, the length of the second heat sink 22 in the Y-axis direction is adjusted so that two second semiconductor chips 32 can be arranged side by side in the Y-axis direction.

[0056] In this embodiment, the third heat sink 23 and the fourth heat sink 24 have the same length in the Y-axis direction as the first heat sink 21 and the second heat sink 22.

[0057] The third wiring portion wiring layer 131 is disposed so as to face the two first semiconductor chips 31. However, in this embodiment, the third wiring portion wiring layer 131 has a recessed portion 133 provided in the approximate center in the Y-axis direction at the end portion on the first semiconductor chip 31 side in the X-axis direction. Therefore, in the portion of the first wiring portion wiring layer 111 facing the first heat sink 21, the portion disposed within the recessed portion 133 is also a non-overlapping portion that does not overlap with the third wiring portion wiring layer 131 in the Z-axis direction.

[0058] The second wiring portion wiring layer 121 is disposed so as to face the two second semiconductor chips 32 .

[0059] The first wiring portion wiring layer 111 is disposed so as to face two second semiconductor chips 32. As in the first embodiment, the first wiring portion wiring layer 111 is connected to the first heat sink 21 through the first heat sink via 531a at a portion of the first wiring portion wiring layer 111 that faces the first heat sink 21 and that protrudes in the Y-axis direction from the third wiring portion wiring layer 131. The first wiring portion wiring layer 111 is also connected to the first heat sink 21 through the first heat sink via 531a at a portion of the third wiring portion wiring layer 131 that faces the portion where the recessed portion 133 is formed. That is, the first wiring portion wiring layer 111 of this embodiment is connected to the first heat sink 21 even at the center side in the Y-axis direction, and has more connection points with the first heat sink 21 than the first embodiment.

[0060] That is, in the present embodiment, as described above, the length of the first heat sink 21 in the Y-axis direction is made longer than in the first embodiment. Therefore, in the present embodiment, by increasing the number of connection points between the first wiring portion wiring layer 111 and the first heat sink 21, it becomes easier to stabilize the potential of the first heat sink 21.

[0061] Furthermore, in this embodiment, the length in the Y-axis direction is longer than in the first embodiment, and therefore two first terminals 112, two second terminals 122, and two third terminals 132 are provided to improve connectivity with an external circuit. When the semiconductor device is connected to an external circuit, one of the two first terminals 112, two second terminals 122, and two third terminals 132 is connected to the external circuit. However, the semiconductor device may be configured so that both of the two first terminals 112, two second terminals 122, and two third terminals 132 are connected to the external circuit.

[0062] As in the present embodiment described above, even in a semiconductor device including two first semiconductor chips 31 and two second semiconductor chips 32, the same effects as those of the first embodiment can be obtained.

[0063] (Third embodiment) A third embodiment will now be described. This embodiment is different from the second embodiment in that the number of first semiconductor chips 31 and second semiconductor chips 32 is changed. As the rest of the configuration is the same as the second embodiment, a description thereof will be omitted here.

[0064] 8, the semiconductor device of this embodiment includes four first semiconductor chips 31, each arranged on the first heat sink 21. In this embodiment, the four first semiconductor chips 31 are arranged on the first heat sink 21 so that two first semiconductor chips 31 are adjacent to each other in the X-axis direction and the Y-axis direction.

[0065] Similarly, four second semiconductor chips 32 are provided, and each is arranged on the second heat sink 22. In this embodiment, the four second semiconductor chips 32 are arranged on the second heat sink 22 so that two second semiconductor chips 32 are adjacent to each other in the X-axis direction and the Y-axis direction.

[0066] In this embodiment, the four first semiconductor chips 31 are connected in parallel to form one upper arm UA, and the four second semiconductor chips 32 are connected in parallel to form one lower arm LA.

[0067] Furthermore, compared to the second embodiment, the first heat sink 21 has two first semiconductor chips 31 arranged in the X-axis direction, and therefore the length in the X-axis direction is longer than that of the first heat sink 21 of the second embodiment. Similarly, the second heat sink 22 has two second semiconductor chips 32 arranged in the X-axis direction, and therefore the length in the X-axis direction is longer than that of the second heat sink 22 of the second embodiment.

[0068] The lengths of the first wiring portion wiring layer 111, the second wiring portion wiring layer 121, and the third wiring portion wiring layer 131 in the X-axis direction are adjusted to match the shapes of the first heat sink 21 and the second heat sink 22.

[0069] As in the present embodiment described above, even in a semiconductor device including four first semiconductor chips 31 and four second semiconductor chips 32, the same effects as those of the first embodiment can be obtained.

[0070] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0071] For example, in the first embodiment, the locations of the first to third wiring portions 101 to 103 can be changed as appropriate, as long as the fourth heat sink 24 is arranged to face the third wiring portion 103 and the third heat sink 23 is arranged to face the first wiring portion 101 and the second wiring portion 102. For example, the semiconductor device may have the configurations shown in Figures 9A to 9C.

[0072] 9A, compared to the first embodiment, the first semiconductor chip 31 and the first heat sink 21 are arranged in an opposite manner to the second semiconductor chip 32 and the second heat sink 22. In other words, in this semiconductor device, the fourth heat sink 24, the second heat sink 22, the first heat sink 21, and the third heat sink 23 are arranged in this order in the X-axis direction.

[0073] In this semiconductor device, the third wiring portion wiring layer 131 has a third wiring portion first wiring layer 131a formed on the first sealing member 51 at a position facing the fourth heat sink 24 and a portion of the second heat sink 22 facing the fourth heat sink 24. The third wiring portion wiring layer 131 also has a third wiring portion second wiring layer 131b formed on the first sealing member 51 at a position facing the portion of the second heat sink 22 facing the first heat sink 21, a position facing the second heat sink 22 side of the first heat sink 21, and a position facing the first semiconductor chip 31. The third wiring portion first wiring layer 131a and the third wiring portion second wiring layer 131b are formed separately on the first sealing member 51.

[0074] The first wiring layer 131a for the third wiring portion and the second wiring layer 131b for the third wiring portion are each connected to the second heat sink 22 through a via 513a for the second heat sink formed in the first sealing member 51. The first wiring layer 131a for the third wiring portion is connected to the third terminal portion 132 through a via 523a for the third wiring portion formed in the second sealing member 52. The second wiring layer 131b for the third wiring portion is connected to the first electrode 311 of the first semiconductor chip 31 through a via 511a for the first chip formed in the first sealing member 51.

[0075] The first wiring portion wiring layer 111 and the second wiring portion wiring layer 121 are arranged such that the first wiring portion wiring layer 111 is disposed on the first sealing member 51, and the second wiring portion wiring layer 121 is disposed on the second sealing member 52. In other words, compared to the first embodiment, the arrangement relationship between the first wiring portion wiring layer 111 and the second wiring portion wiring layer 121 is reversed. The first wiring portion wiring layer 111 is connected to the first heat sink 21 through a first heat sink via 531a formed in the first sealing member 51. The first wiring portion wiring layer 111 is also connected to the first terminal portion 112 through a first wiring portion via 521a formed in the second sealing member 52.

[0076] The wiring layer 121 for the second wiring portion is connected to the first electrode 321 of the second semiconductor chip 32 through the via 512a for the second chip formed in the first and second sealing members 51 and 52. In this semiconductor device, the second terminal 122 is formed from a part of the wiring layer 121 for the second wiring portion.

[0077] Even if the first to third wiring portions 101 to 103 are arranged in this manner, the circuit configuration shown in FIG. 3 can be realized, and the same effects as those of the first embodiment can be obtained.

[0078] In the semiconductor device shown in Figure 9B, similar to the semiconductor device shown in Figure 9A, compared to the first embodiment described above, the first semiconductor chip 31 and the first heat sink 21, and the second semiconductor chip 32 and the second heat sink 22 are arranged in reverse.

[0079] In this semiconductor device, the wiring layer 111 for the first wiring portion is disposed on the second sealing member 52 and is connected to the first heat sink 21 through the vias 531a for the first heat sink formed in the first and second sealing members 51 and 52. The first terminal portion 112 is formed from a part of the wiring layer 111 for the first wiring portion.

[0080] The wiring layer 121 for the second wiring portion has a first wiring layer 121a for the second wiring portion formed on the second sealing member 52 at a position facing the first semiconductor chip 31, a position facing a portion of the first heat sink 21 on the second heat sink 22 side, a position facing a portion of the second heat sink 22 on the first heat sink 21 side, and a position facing the second semiconductor chip 32. The wiring layer 121 for the second wiring portion has a second wiring layer 121b for the second wiring portion formed on the first sealing member 51 at a position facing the third heat sink 23 and a position facing a portion of the first heat sink 21 on the third heat sink 23 side.

[0081] The second wiring layer 121b for the second wiring portion is connected to the second terminal portion 122 through a via 522a for the second wiring portion formed in the second sealing member 52. The second wiring layer 121b for the second wiring portion is connected to the first wiring layer 121a for the second wiring portion through a via 522a for the second wiring portion formed in the second sealing member 52. The first wiring layer 121a for the second wiring portion is connected to the first electrode 321 of the second semiconductor chip 32 through a via 512a for the second chip formed in the first and second sealing members 51 and 52.

[0082] Even if the first to third wiring portions 101 to 103 are arranged in this manner, the circuit configuration shown in FIG. 3 can be realized, and the same effects as those of the first embodiment can be obtained.

[0083] 9C, the third wiring portion wiring layer 131 is disposed in the second sealing member 52. The third wiring portion wiring layer 131 is connected to the first electrode 311 of the first semiconductor chip 31 through the first chip via 511a formed in the first and second sealing members 51 and 52. The third wiring portion wiring layer 131 is also connected to the second heat sink 22 through the second heat sink via 513a formed in the first and second sealing members 51 and 52. In this semiconductor device, the third terminal portion 132 is formed by a part of the third wiring portion wiring layer 131.

[0084] The first wiring portion wiring layer 111 and the second wiring portion wiring layer 121 are arranged such that the first wiring portion wiring layer 111 is disposed on the first sealing member 51 and the second wiring portion wiring layer 121 is disposed on the second sealing member 52. The first wiring portion wiring layer 111 is connected to the first heat sink 21 through a first heat sink via 531a formed in the first sealing member 51. The first wiring portion wiring layer 111 is also connected to the first terminal portion 112 through a first wiring portion via 521a formed in the second sealing member 52.

[0085] The wiring layer 121 for the second wiring portion is connected to the first electrode 321 of the second semiconductor chip 32 through the via 512a for the second chip formed in the first and second sealing members 51 and 52. In this semiconductor device, the second terminal 122 is formed from a part of the wiring layer 121 for the second wiring portion.

[0086] Even if the first to third wiring portions 101 to 103 are arranged in this manner, the circuit configuration shown in FIG. 3 can be realized, and the same effects as those of the first embodiment can be obtained.

[0087] In addition, in each of the above embodiments, the semiconductor device does not necessarily have to include the external connection heat sink 10. The semiconductor device may be used by being arranged such that the first to fourth heat sinks 21 to 24 are thermally connected to a mount member via an insulating member arranged on the mount member side. [Explanation of symbols]

[0088] 21 First heat sink 22 Second heat sink 31 First semiconductor chip 32 Second semiconductor chip 50 Sealing member 101 1st wiring section 102 2nd wiring section 103 Third wiring section

Claims

1. A semiconductor device, a first semiconductor chip (31) and a second semiconductor chip (32) on which switching elements are formed; a first heat sink (21) on which the first semiconductor chip is placed; a second heat sink (22) on which the second semiconductor chip is placed; a sealing member (50) made of a resin material that seals the first semiconductor chip and the second semiconductor chip; a first wiring portion (101) connected to the first semiconductor chip; a second wiring portion (102) connected to the second semiconductor chip; a third wiring portion (103) that connects the first semiconductor chip and the second semiconductor chip; the first semiconductor chip and the second semiconductor chip are controlled to be turned on and off so that currents flow in opposite directions through the first wiring portion and the second wiring portion; the first wiring portion, the second wiring portion, and the third wiring portion are collectively arranged on the side opposite to the first heat sink side and the second heat sink side, with the first semiconductor chip and the second semiconductor chip interposed therebetween; the first wiring portion and the second wiring portion have portions that are arranged opposite to each other, A semiconductor device having a third heat sink (23) arranged on the opposite side of the first wiring portion, the second wiring portion, and the third wiring portion across the first semiconductor chip and the second semiconductor chip, and arranged opposite the first wiring portion and the second wiring portion, and a fourth heat sink (24) arranged opposite the third wiring portion.

2. 2. The semiconductor device according to claim 1, wherein the first to fourth heat sinks have the same thickness.

3. the first wiring portion includes a first terminal portion (111) disposed on the sealing member, the second wiring portion includes a second terminal portion (121) disposed on the sealing member, the third wiring portion includes a third terminal portion (131) disposed on the sealing member, 3. The semiconductor device according to claim 1, wherein the first semiconductor chip, the second semiconductor chip, the first terminal portion, the second terminal portion, and the third terminal portion are arranged in the stacking direction of the first semiconductor chip and the first heat sink, along the arrangement direction of the first semiconductor chip and the second semiconductor chip, in the order of the third terminal portion, the first semiconductor chip, the second semiconductor chip, the first terminal portion, and the second terminal portion.

4. the first wiring portion and the third wiring portion are disposed opposite to each other in the stacking direction at a portion located on the first heat sink, and are formed so that the first wiring portion has a portion located on the first heat sink where the first wiring portion does not overlap with the third wiring portion, The semiconductor device according to claim 3 , wherein the first wiring portion is connected to the first semiconductor chip by connecting the non-overlapping portion to the first heat sink.

5. the first wiring portion has a portion disposed on the opposite side of the second wiring portion from the third heat sink, the third wiring portion is connected to the second heat sink and to the second semiconductor chip, and is also connected to a portion of the first semiconductor chip on an opposite side to the first heat sink side; The semiconductor device according to claim 4 , wherein the second wiring portion is connected to a portion of the second semiconductor chip on an opposite side to the second heat sink side.

Images