A / d converter circuit

Abstract

To provide an A / D converter circuit that can convert an analog signal to a digital signal accurately with a simple structure.SOLUTION: An A / D converter circuit 1 is provided with: a plurality of A / D converters 10_1-10_m to which same analog signals are respectively inputted and which convert the analog signals to digital signals, in response to a plurality of trigger signals having a predetermined phase difference; a selecting part that selects one trigger signal from the plurality of trigger signals; a reference A / D converter 10_r that converts the analog signals to the digital signals, in response to the selected trigger signal; and parameter obtaining parts 474 and 476 which obtain correction parameters for correcting the digital signal converted by the A / D converter corresponding to the selected trigger signal, on the basis of the digital signal converted by the A / D converter corresponding to the selected trigger signal of the plurality of A / D converters and the digital signals converted by the reference A / D converter.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to an A / D converter circuit. [Background technology]

[0002] Conventionally, A / D converter circuits using a time interleave method (hereinafter simply referred to as the "interleave method") have been used, which converts analog signals into digital signals by driving multiple A / D converters (hereinafter also referred to as "ADCs") with a predetermined phase difference.

[0003] Interleaved A / D converter circuits use multiple ADCs, and mismatches between these ADCs can cause distortion in the waveform of the output data. Patent Document 1 and Non-Patent Document 1 disclose techniques for correcting waveform distortion caused by mismatches. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-23164 [Non-patent literature]

[0005] [Non-Patent Document 1] Junya Matsuno, Masanori Furuta, Tetsuro Itakura. Digital correction technology for achieving high speed and small area in time-interleaved ADCs. Toshiba Review. 2014, vol. 69, no. 7, pp. 28-31

[0006] [overview] However, the present inventors have come to recognize the following problem: That is, they thought that there is room for correcting the output data of the A / D converter with a simple configuration.

[0007] The present disclosure has been made in light of these circumstances, and one of its exemplary purposes is to provide an A / D converter circuit that can convert an analog signal into digital data with high accuracy using a simple configuration.

[0008] An A / D converter circuit according to one embodiment of the present disclosure includes a plurality of A / D converters that each receive the same analog signal as input and convert each analog signal into a digital signal in response to a corresponding trigger signal from a plurality of trigger signals having a predetermined phase difference; a selection unit that selects one trigger signal from the plurality of trigger signals; a reference A / D converter that converts the analog signal into a digital signal in response to the selected trigger signal; and a parameter acquisition unit that acquires a correction parameter for correcting the digital signal converted by the A / D converter corresponding to the selected trigger signal from the plurality of A / D converters, based on the digital signal converted by the A / D converter corresponding to the selected trigger signal and the digital signal converted by the reference A / D converter.

[0009] Any combination of the above components and conversion of the expressions of the present disclosure into methods, devices, systems, etc. are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an interleaved A / D converter circuit according to a reference technique. [Figure 2] FIG. 2 is a diagram for explaining the operation of the A / D converter circuit according to the reference technique. [Figure 3] FIG. 3 is a diagram showing an example of digital data in which spurious signals appear. [Figure 4] FIG. 4 is a block diagram of an A / D converter circuit according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a timing chart showing trigger signals input to m ADCs. [Figure 6]FIG. 6 is a timing chart for explaining the timing at which the reference ADC acquires an analog signal. [Figure 7] FIG. 7 is a block diagram of a correction circuit block according to one embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram showing modes that the A / D converter circuit according to the embodiment can take. [Figure 9] FIG. 9 is a flowchart of an offset measurement process performed by the A / D converter circuit according to the embodiment. [Figure 10] FIG. 10 is a flowchart of a gain measurement process performed by the A / D converter circuit according to the embodiment. [Figure 11] FIG. 11 is a timing chart showing an example of a flow in which the A / D converter circuit according to the embodiment acquires the offset parameter of channel 1 and corrects the offset of the digital signal of channel 1. [Figure 12] FIG. 12 is a timing chart showing an example of a flow in which the A / D converter circuit according to the embodiment acquires the gain parameter of channel 1 and corrects the gain of the digital signal of channel 1. [Figure 13] FIG. 13 is a timing chart showing the flow of measuring offsets for m channels and correcting the offsets for each channel.

[0011] [Detailed explanation] (overview) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0012] An A / D converter circuit according to one embodiment includes a plurality of A / D converters that receive the same analog signal as input and convert each analog signal into a digital signal in response to a corresponding trigger signal from a plurality of trigger signals having a predetermined phase difference; a selection unit that selects one trigger signal from the plurality of trigger signals; a reference A / D converter that converts the analog signal into a digital signal in response to the selected trigger signal; and a parameter acquisition unit that acquires a correction parameter for correcting the digital signal converted by the A / D converter corresponding to the selected trigger signal from the plurality of A / D converters, based on the digital signal converted by the A / D converter corresponding to the selected trigger signal and the digital signal converted by the reference A / D converter.

[0013] According to this configuration, analog signals can be converted into digital data with high accuracy using a simple configuration.

[0014] In one embodiment, the A / D converter circuit may further include a correction section that corrects the digital signal converted by the A / D converter based on a correction parameter.

[0015] In one embodiment, the correction unit may correct the offset or gain of the digital signal converted by the A / D converter based on the correction parameter.

[0016] In one embodiment, the parameter acquisition unit may acquire a correction parameter for each of the digital signals converted by the multiple A / D converters, and the correction unit may correct each of the digital signals converted by the multiple A / D converters based on the correction parameter.

[0017] In one embodiment, the A / D converter circuit may further include an integration unit that integrates the digital signals converted by the multiple A / D converters, each corrected by the correction unit, and generates digital data that converts the analog signals into a digital waveform.

[0018] (background) As communication speeds increase, electronic devices are required to operate at higher speeds. In particular, A / D converter circuits, which are the interface between the analog and digital sections, need to be faster and more accurate. Interleaving is one method of achieving this.

[0019] 1 is a diagram showing an interleaved A / D converter circuit 9 according to the reference technology. The A / D converter circuit 9 according to the reference technology has two channels. As shown in FIG. 1, the A / D converter circuit 9 includes a divider circuit 90, two delay circuits 92a and 92b, two ADCs 94a and 94b, and an integrating circuit 96.

[0020] The divider circuit 90 receives the clock signal CLOCK and inputs a clock signal CKdiv9 to each of delay circuits 92a and 92b. The delay circuits 92a and 92b correct the phase of the input clock signal CKdiv9 and input the corrected clock signals CK91 and CK92 to ADCs 94a and 94b. The clock signals CK91 and CK92 have a predetermined phase difference.

[0021] An analog signal AIN is input to the ADCs 94a and 94b. The ADCs 94a and 94b perform A / D conversion of the analog signal AIN in response to clock signals CK91 and CK92, and output digital signals DOUT91 and DOUT92 to the integrating circuit 96. The integrating circuit 96 integrates the digital signals DOUT91 and DOUT92, and outputs digital data ADOUT9.

[0022] Fig. 2 is a diagram for explaining the operation of the A / D converter circuit 9 according to the reference technology. Fig. 2 shows an analog signal AIN, a clock signal CK91 input to an ADC 94a of channel 1, and a clock signal CK92 input to an ADC 94b of channel 2. The phase difference between the clock signals CK91 and CK92 is half a cycle.

[0023] The analog signal AIN is sampled on each channel at the rising edge of the clock signals CK91 and CK92, and the sampled analog signal is A / D converted. In Figure 2, the analog signal AIN is labeled "1" for the signal sampled by the ADC 94a on channel 1, and "2" for the signal sampled by the ADC 94b on channel 2. By using the ADCs 94a and 94b on two channels, the analog signal AIN can be sampled at twice the sampling rate compared to using a single ADC. For example, if the sampling rate of each of the ADCs 94b and 94b is 100 MSPS (Mega sample(s) per second), a sampling rate of 200 MSPS can be achieved.

[0024] However, spurious signals appear in the output digital data, causing waveform distortion. The following four mismatches can be cited as the causes of spurious signals: Offset mismatch (offset mismatch between each ADC) Timing mismatch (clock skew and mismatch in the delay groups of each ADC) Gain mismatch (gain mismatch between each ADC) Bandwidth mismatch (mismatch due to the mutual relationship between the two parameters (gain component and phase / frequency component) of each ADC) When correcting the timing of an ADC (phase equalization), the conventional circuit configuration requires a complicated correction algorithm and adjustment circuit, and the adjustment itself is difficult.

[0025] FIG. 3 is a diagram showing an example of digital data in which spurious components appear. FIG. 3 shows digital data output by a four-channel interleaved A / D converter circuit. In FIG. 3, the horizontal axis is the time axis, and the analog signal 900 input to the A / D converter circuit is shown by a solid line. In FIG. 3, the digital signals obtained by A / D conversion using each of the four ADCs are shown by circles corresponding to the channel numbers of the corresponding ADC. When spurious components appear, the waveform of the digital signal obtained by the ADC becomes distorted and misaligned with the analog signal 900.

[0026] To eliminate distortion in the waveform of digital signals, it is necessary to eliminate mismatches between each ADC. One way to eliminate mismatches is to use a calibration technique (circuit) that measures each ADC value and performs calculations and corrections using a special circuit or CPU (Central Processing Unit). High-precision calibration requires high-precision measurements, high-precision correction, and the comparison results of each ADC to match (eliminating mismatches).

[0027] To perform accurate measurements, the timing for acquiring data from each ADC to be compared must first be synchronized (with high accuracy). With conventional interleaved A / D converter circuit mechanisms, the phases of each ADC are different to begin with, so a method and mechanism for synchronizing data acquisition or determining this using an algorithm is required, which makes the mechanism and layout complex. Specifically, conventional technology requires filters, specialized circuits for the CPU / ALU (Arithmetic and Logic Unit), and the mechanism (circuit) for detecting and adjusting the timing itself is complex, requiring a large circuit area and power consumption.

[0028] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0029] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0030] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0031] 4 is a block diagram of an A / D converter circuit 1 according to an embodiment of the present disclosure. The A / D converter circuit 1 converts an analog signal AIN into digital data ADOUT. The A / D converter circuit 1 includes m (m is an integer equal to or greater than 2) ADCs 10_1 to 10_m, a reference ADC 10_r, a trigger signal generation circuit 20, delay circuits 22_1 to 22_m, a selector 24 (selection unit), a controller 30, a correction circuit block 40, and an integration circuit 50. The ADCs 10_1 to 10_m and the reference ADC 10_r are each a self-oscillating ADC.

[0032] The trigger signal generation circuit 20 generates m trigger signals CK1_1 to CKm_1 having a predetermined phase difference based on the clock signal CLOCK. The generated trigger signals CK1_1 to CKm_1 are input to corresponding delay circuits among the delay circuits 22_1 to 22_m, respectively.

[0033] The delay circuits 22_1 to 22_m delay the input trigger signals CK1_1 to CKm_1, respectively, to generate trigger signals CK1_2 to CKm_2. The trigger signals CK1_2 to CKm_2 are input to the corresponding ADCs 10_1 to 10_m, respectively. The trigger signals CK1_2 to CKm_2 are also input to a selector 24.

[0034] 5 is a timing chart showing trigger signals CK1_2 to CKm_2 input to m ADCs 10_1 to 10_m. Each of the trigger signals CK1_2 to CKm_2 is a rectangular pulse wave, and the pulse width is one cycle of the clock signal CLOCK. The cycle of the trigger signals CK1_2 to CKm_2 is m cycles of the clock signal CLOCK. Furthermore, the phases of the trigger signals CK1_2 to CKm_2 differ from each other by one cycle of the clock signal CLOCK.

[0035] 4, the configuration of the A / D converter circuit 1 will be described. The m ADCs 10_1 to 10_m each receive the same analog signal AIN and convert the analog signal AIN into digital signals DOUT1 to DOUTm in response to a corresponding one of a plurality of trigger signals CK1_2 to CKm_2 having a predetermined phase difference. The digital signals DOUT1 to DOUTm are input to a correction circuit block 40.

[0036] The controller 30 controls the operations of the selector 24 and the correction circuit block 40. Specifically, the controller 30 inputs to the selector 24 and the correction circuit block 40 a selection signal SEL that specifies which of the trigger signals CK1_1 to CKm_1 the selector 24 should select.

[0037] The selector 24 selects one trigger signal from the plurality of trigger signals CK1_2 to CKm_2 in response to a selection signal SEL, and inputs the selected trigger signal CKref to the reference ADC 10_r.

[0038] The reference ADC 10_r converts the analog signal AIN into a digital signal DOUTref in response to the trigger signal (trigger signal CKref) selected by the selector 24. The digital signal DOUTref is input to the correction circuit block 40.

[0039] 6 is a timing chart illustrating the timing at which the reference ADC 10_r acquires (samples) the analog signal AIN. In FIG. 6, the timing at which the trigger signals CK1_2, CK2_2, CKm_2, and CKref rise is indicated by an upward arrow. When the selector 24 selects the trigger signal CK1_2 (Case 1), the trigger signal CKref rises at the same timing as the trigger signal CK1_2. Therefore, in Case 1, the ADC 10_1 and the reference ADC 10_r acquire the analog signal AIN at the same timing. When the trigger signal CK2_2 is selected (Case 2) or when the trigger signal CKm_2 is selected (Case 3), the reference ADC 10_r acquires the analog signal AIN at the same timing as the ADC 10_2 or ADC 10_m. In this way, the reference ADC 10_r acquires the analog signal AIN at the same timing as the ADCs 10_1 to 10_m corresponding to the selected trigger signals CK1_2 to CKm_2, and A / D converts the acquired analog signal AIN.

[0040] Returning to Fig. 4, the configuration of the A / D converter circuit 1 will be described. The correction circuit block 40 corrects the digital signals DOUT1 to DOUTm generated by the ADCs 10_1 to 10_m corresponding to the trigger signal CKref selected by the selector 24, based on the digital signal DOUTref generated by the reference ADC 10_r. The correction circuit block 40 outputs the digital signals CADO1 to CADOm to the integrated circuit 50. The digital signals CADO1 to CADOm may be corrected digital signals or uncorrected digital signals.

[0041] The integration circuit 50 integrates the digital signals CADO1 to CADOm output from the correction circuit block 40 to generate digital data ADOUT. The digital data ADOUT is data having a waveform obtained by A / D converting the analog signal AIN. The integration circuit 50 may integrate the digital signals CADO1 to CADOm corrected by the correction circuit block 40 to generate the digital data ADOUT. This makes it possible to obtain more accurate digital data ADOUT by using the digital signals CADO1 to CADOm corrected for all channels.

[0042] 7 is a block diagram of a correction circuit block 40 according to an embodiment of the present disclosure. The correction circuit block 40 includes a signal hold circuit 42, an encoder 44, m arithmetic units 46_1 to 46_m, m correction circuits 48_1 to 48_m (correction units), and an error output circuit 49.

[0043] The signal hold circuit 42 holds the output signal DOUTref from the reference ADC 10_r and outputs an output signal CHKref in response to the trigger signal CKref. The signal hold circuit 42 has a D flip-flop circuit 420. The D flip-flop circuit 420 is provided so that the trigger signal CKref is input to a clock input terminal and the digital signal DOUTref of the reference ADC 10_r is input to a data input terminal. The output signal CHKref of the D flip-flop circuit 420 is input to each of the arithmetic units 46_1 to 46_m.

[0044] The encoder 44 receives the selection signal SEL and outputs the enable signals EN1 to ENm to the arithmetic units 46_1 to 46_m. Specifically, the encoder 44 sets the enable signals EN1 to ENm input to the arithmetic units 46_1 to 46_m of the channel corresponding to the selection signal SEL to high, and sets the remaining enable signals EN1 to ENm to low.

[0045] The arithmetic units 46_1 to 46_m acquire correction parameters for correcting the digital signals DOUT1 to DOUTm based on the corresponding digital signals DOUT1 to DOUTm and the output signal CHKref. The correction parameters include an offset parameter for correcting the offset of the digital signals DOUT1 to DOUTm and a gain parameter for correcting the gain of the digital signals DOUT1 to DOUTm.

[0046] Since the arithmetic units 46_1 to 46_m according to this embodiment have substantially the same configuration, the configuration of the arithmetic unit 46_1 will be mainly described here. The arithmetic unit 46_1 includes a NAND circuit 460, a D flip-flop circuit 462, and an arithmetic circuit 470.

[0047] The NAND circuit 460 is provided so that the enable signal EN1 from the encoder 44 is input to a first input terminal thereof, and the trigger signal CKref of the reference ADC 10_r is input to a second input terminal thereof. The output signal gck1 of the NAND circuit 460 is input to a clock input terminal of a D flip-flop circuit 462.

[0048] The D flip-flop circuit 462 is provided so that the digital signal DOUT1 from the ADC 10_1 is input to the data input terminal thereof. The output signal CHKD1 of the D flip-flop circuit 462 is input to the arithmetic circuit 470.

[0049] The arithmetic circuit 470 calculates a correction parameter for correcting the digital signal DOUT1 based on the output signal CHKD1 from the D flip-flop circuit 462 and the output signal CHKref from the D flip-flop circuit 420. The arithmetic circuit 470 has a calculator 472, a gain parameter acquisition unit 474, an offset parameter acquisition unit 476, and an error acquisition unit 478.

[0050] The calculator 472 performs various calculations based on the output signal CHKD1 and the output signal CHKref. Specifically, the calculator 472 may calculate an offset error and a gain error of the output signal CHKD1 relative to the output signal CHKref. For example, the calculator 472 may calculate, as the offset error, the difference between the output signal CHKD1 and the output signal CHKref obtained when the analog signal AIN is zero. Furthermore, the calculator 472 may calculate, as the gain error, a value obtained by subtracting the offset error from the difference between the output signal CHKD1 and the output signal CHKref obtained when the analog signal AIN is full (maximum value of full scale).

[0051] The gain parameter acquisition unit 474 and the offset parameter acquisition unit 476 acquire correction parameters for correcting the digital signals DOUT1 to DOUTm converted by the ADCs 10_1 to 10_m corresponding to the trigger signal CKref, based on the digital signals DOUT1 to DOUTm converted by the ADCs 10_1 to 10_m corresponding to the trigger signal CKref selected by the selector 24 and the digital signal DOUTref converted by the reference ADC 10_r. For example, when the trigger signal CK1_2 of channel 1 is selected, correction parameters for correcting the digital signal DOUT1 converted by the ADC 10_1 are acquired. Note that correction parameters may be acquired for all channels.

[0052] The gain parameter acquisition unit 474 acquires the gain parameter based on the calculation result of the calculator 472. Specifically, the gain parameter is acquired based on the gain error of the output signal CHKD1 and the output signal CHKref calculated by the calculator 472. For example, the gain parameter may be a parameter that cancels out the gain error of the digital signal DOUT1 and the output signal CHKref. The signal Sga including the gain parameter is transmitted to the correction circuit 48_1.

[0053] The offset parameter acquisition unit 476 acquires the offset parameter based on the calculation result of the calculator 472. The offset parameter acquisition unit 476 may acquire the offset parameter based on the offset error of the output signal CHKD1 and the output signal CHKref calculated by the calculator 472. For example, the offset parameter may be a parameter that cancels out the offset error of the digital signal DOUT1 and the output signal CHKref. The signal Sof including the offset parameter is transmitted to the correction circuit 48_1.

[0054] The error acquiring unit 478 acquires error information about the digital signal DOUT1 based on the calculation result of the calculator 472. For example, if the difference between the output signal CHKD1 and the output signal CHKref is greater than a predetermined threshold, the error acquiring unit 478 may acquire error information indicating that the digital signal DOUT1 is in error. The signal Serr including the error information is transmitted to the error output circuit 49.

[0055] The correction circuits 48_1 to 48_m correct the digital signals DOUT1 to DOUTm converted by the ADCs 10_1 to 10_m based on the correction parameters. The correction circuits 48_1 to 48_m may correct each of the digital signals DOUT1 to DOUTm or may correct a part of the digital signals DOUT1 to DOUTm.

[0056] In this embodiment, the correction circuits 48_1 to 48_m correct the offset or gain of the digital signals DOUT1 to DOUTm based on the correction parameters. Note that the method for correcting the digital signals DOUT1 to DOUTm is not limited to this.

[0057] The correction circuit 48_1 corrects the digital signal DOUT1 converted by the ADC 10_1 based on the correction parameter and outputs the corrected digital signal CADO1. For example, the correction circuit 48_1 may correct the offset of the digital signal DOUT1 based on the offset parameter. Also, the correction circuit 48_1 may correct the gain of the digital signal DOUT1 based on the gain parameter. Furthermore, the correction circuit 48_1 may correct the offset and gain of the digital signal DOUT1 based on the offset parameter and the gain parameter.

[0058] The error output circuit 49 outputs a signal ERR_CNT indicating information about an error in the digital signals DOUT1 to DOUTm based on the signal Serr from the arithmetic units 46_1 to 46_m. The signal ERR_CNT may include, for example, information identifying the digital signals DOUT1 to DOUTm in which an error has occurred and information indicating the number of times the error has occurred.

[0059] FIG. 8 is a diagram showing modes that can be taken by the A / D converter circuit 1 according to this embodiment. As shown in FIG. 8, the A / D converter circuit 1 according to this embodiment takes modes Normal 1 to Normal 3, OFFSET, or GAIN. In FIG. 8, the "CALLON" column indicates whether a measurement to acquire a correction parameter for correcting the digital signals DOUT1 to DOUTm is performed (1) or not performed (0). The "GAIN" column indicates whether the digital signals DOUT1 to DOUTm are corrected (1) or not corrected (0) using a gain parameter. Note that when the mode is OFFSET or GAIN, the digital signals DOUT1 to DOUTm cannot be corrected using the gain parameter. The "OFF / FULL" column indicates whether the digital signals DOUT1 to DOUTm are corrected (1) or not corrected (0) using an offset parameter.

[0060] In Normal 0 mode, no correction is performed on the digital signals DOUT1 to DOUTm. In Normal 1 mode, the offset of the digital signals DOUT1 to DOUTm is corrected. In Normal 2 mode, the gain of the digital signals DOUT1 to DOUTm is corrected. In Normal 3 mode, the offset and gain of the digital signals DOUT1 to DOUTm are corrected. In OFFSET mode, an offset measurement process is performed. In GAIN mode, a gain measurement process is performed.

[0061] 9 is a flowchart of the offset measurement process performed by the A / D converter circuit 1 according to this embodiment. The offset measurement process acquires offset parameters for each channel. The flow of the offset measurement process will be described below with reference to FIG.

[0062] First, the analog signal AIN is set to zero (S101). The magnitude of the analog signal AIN may be controlled by a circuit (not shown). While the offset measurement process is being performed, the analog signal AIN is maintained at zero.

[0063] Next, the controller 30 selects a channel (S103). In the first selection, the controller 30 may select channel 1. In addition, in the second or subsequent selections, the controller 30 may select an unselected channel, for example, the channel next to the previously selected channel.

[0064] Next, the analog signal AIN is A / D converted by the ADCs 10_1 to ADC_m of the channel selected in S103 and the reference ADC_r (S105). For example, when channel 1 is selected, the ADC 10_1 A / D converts the analog signal AIN to generate a digital signal DOUT1. In this case, the selector 24 selects the trigger signal CK1_2, and the reference ADC_r A / D converts the analog signal AIN in accordance with the trigger signal CKref based on the selection to generate a digital signal DOUTref.

[0065] Next, the calculator 472 calculates an offset error based on the digital signals DOUT1 to DOUT_m generated by the ADCs 10_1 to 10_m of the channel selected in S103 and the digital signal DOUTref generated by the reference ADC 10_r (S107). When channel 1 is selected, the calculator 472 calculates the difference between the output signal CHKD1 corresponding to the digital signal DOUT1 and the output signal CHKref corresponding to the digital signal DOUTref as the offset error of the digital signal DOUT1.

[0066] Next, the offset parameter acquisition unit 476 acquires an offset parameter for correcting the offset of the digital signal DOUT1 based on the offset error calculated in S107 (S109).

[0067] Next, the controller 30 determines whether to end the offset measurement process (S111). For example, the controller 30 may determine to end the offset measurement process if offset parameters have been acquired for all channels. Alternatively, the controller 30 may determine not to end the offset measurement process if there are any channels for which offset parameters have not been acquired.

[0068] If it is determined in S111 that the offset measurement process should not be ended, the processes of S103 to S111 are repeated. On the other hand, if it is determined in S111 that the offset measurement process should be ended, the offset measurement process ends.

[0069] 10 is a flowchart of the gain measurement process performed by the A / D converter circuit 1 according to this embodiment. The gain measurement process acquires gain parameters for each channel. The flow of the gain measurement process will be described below with reference to FIG.

[0070] First, the analog signal AIN is set to full (S201). The magnitude of this analog signal AIN may be controlled by a circuit (not shown). While the gain measurement process is being performed, the analog signal AIN is maintained at full.

[0071] Next, the processes of S203 and S205 are carried out, but since these processes are substantially the same as the processes of S103 and S105, a description thereof will be omitted here.

[0072] When the process of S205 is completed, the calculator 472 calculates the gain error between the digital signals DOUT1 to DOUT_m generated by the ADCs 10_1 to 10_m of the selected channel and the digital signal DOUTref generated by the reference ADC_r (S207). When channel 1 is selected, the calculator 472 calculates the gain error of the digital signal DOUT1 based on the output signal CHKD1 corresponding to the digital signal DOUT1 and the output signal CHKref corresponding to the digital signal DOUTref. Note that the calculator 472 may use the calculated offset error when calculating the gain error.

[0073] Next, the gain parameter acquisition unit 474 acquires a gain parameter for correcting the gain of the digital signal DOUT1 based on the gain error calculated in S207 (S209).

[0074] Next, the controller 30 determines whether to end the gain measurement process (S211). For example, if gain parameters have been acquired for all channels, the controller 30 may determine to end the gain measurement process. Alternatively, if there are any channels for which gain parameters have not been acquired, the controller 30 may determine not to end the gain measurement process.

[0075] If it is determined in S211 that the gain measurement process should not be ended, the processes of S203 to S211 are repeated. On the other hand, if it is determined in S211 that the gain measurement process should be ended, the gain measurement process ends.

[0076] FIG. 11 is a timing chart showing an example of a flow in which the A / D converter circuit 1 according to this embodiment acquires the offset parameter of channel 1 and corrects the offset of the digital signal DOUT1 of channel 1.

[0077] At timing t11, the mode switches from Normal 0 to OFFSET. This starts the offset measurement process in the A / D converter circuit 1. However, here, the offset parameters are acquired only for channel 1. At this time, the analog signal AIN is zero.

[0078] At timing t12, the selection signal SEL becomes channel 1. At this time, the enable signal EN1 input to the arithmetic unit 46_1 of channel 1 becomes high. This starts a process of acquiring an offset parameter for correcting the offset of the digital signal DOUT1 of channel 1. At this time, the selector 24 selects the trigger signal CK1_2 of channel 1 and outputs the trigger signal CKref.

[0079] At timing t13, the trigger signal CK1_2 of channel 1 rises, and in response, the ADC 10_1 A / D converts the analog signal AIN to generate a digital signal DOUT1 of Dat(0). Also, at timing t13, the trigger signal CKref rises, and in response, the reference ADC 10_r A / D converts the analog signal AIN to generate a digital signal Dref of Dref(0).

[0080] At timing t14, the trigger signal CK1_2 falls, and in response, the output signal CHKD1 becomes datck(0) corresponding to DAT(0). At the same timing, the output signal gck1 rises, and in response, the output signal CHKref becomes drefck(0) corresponding to the digital signal Dref(0).

[0081] The calculator 472 calculates the offset error of the digital signal DOUT1 based on datck(0) and drefck(0), and obtains the value of Cal(0) by using the calculation result as ALU1. The offset parameter acquisition unit 476 obtains the value of OF(0) corresponding to Cal(0) as the offset parameter OF1.

[0082] At timing t15, the mode switches from OFFSET to Normal 1 or Normal 3. As a result, the digital signal DOUT1 is corrected using the obtained offset parameter.

[0083] At timing t16, the ADC 10_1 and the reference ADC_r each perform A / D conversion of the analog signal AIN. This generates a digital signal DOUT1 of Dat(1) and a digital signal DOUTref of Dref(1). This digital signal DOUT1 is corrected using an offset parameter OF1, resulting in a digital signal CADO1 of CALDat(1).

[0084] FIG. 12 is a timing chart showing an example of a flow in which the A / D converter circuit 1 according to this embodiment acquires the gain parameter of channel 1 and corrects the gain of the digital signal DOUT1 of channel 1.

[0085] At timing t21, the mode switches from Normal 0 to GAIN, which starts the gain measurement process in the A / D converter circuit 1. At this time, the analog signal AIN is full.

[0086] At timing t22, the selection signal SEL becomes channel 1. At this time, the enable signal EN1 input to the arithmetic unit 46_1 of channel 1 becomes high. This starts a process of acquiring a gain parameter for correcting the gain of the digital signal DOUT1 of channel 1. At this time, the selector 24 selects the trigger signal CK1_2 of channel 1 and outputs the trigger signal CKref.

[0087] At timing t23, the trigger signal CK1_2 of channel 1 rises, and in response, the ADC 10_1 A / D converts the analog signal AIN to generate a digital signal DOUT1 of Dat(0). Also, at timing t23, the trigger signal CKref rises, and in response, the reference ADC 10_r A / D converts the analog signal AIN to generate a digital signal Dref of Dref(0).

[0088] At timing t24, the trigger signal CK1_2 falls, and in response, the output signal CHKD1 becomes datck(0) corresponding to DAT(0). At the same timing, the output signal gck1 rises, and in response, the output signal CHKref becomes drefck(0) corresponding to the digital signal Dref(0).

[0089] The calculator 472 calculates the gain error of the digital signal DOUT1 based on datck(0) and drefck(0), and obtains the value of Cal(0) by using the calculation result as ALU1. The gain parameter acquisition unit 474 obtains the value of GAIN(0) corresponding to Cal(0) as the gain parameter GA1.

[0090] At timing t25, the mode switches from GAIN to Normal 2 or Normal 3. As a result, the gain of the digital signal DOUT1 is corrected using the obtained gain parameter. Note that the offset of the digital signal DOUT1 may be corrected using the already obtained offset parameter OF1.

[0091] At timing t26, the ADC 10_1 and the reference ADC_r each perform A / D conversion of the analog signal AIN. This generates a digital signal DOUT1 of Dat(1) and a digital signal DOUTref of Dref(1). This digital signal DOUT1 is corrected using a gain parameter GAIN1, resulting in a digital signal CADO1 of CALDat(1).

[0092] 13 is a timing chart showing the flow of offset measurement for m channels and offset correction for each channel, where the analog signal AIN is zero.

[0093] At timing t31, the mode is switched from Normal 0 to OFFSET, and channel 1 is selected. This starts the offset measurement process, and the process for acquiring the offset parameters of channel 1 begins.

[0094] A / D conversion is performed on channel m (timing t32). Note that A / D conversion is not limited to channel m, and may be performed on channel n (n is any value from 1 to m). Next, A / D conversion is performed on channel 1 (timing t33). As a result, a digital signal DOUT1 of Dat1(2) is generated, and a digital signal DOUTref is generated by the reference ADC_r (timing t34). An offset parameter OF1 for correcting the digital signal DOUT1 is obtained based on the digital signal DOUT1 and the digital signal DOUTref (timing t35).

[0095] At timing t36, the selected channel switches from channel 1 to channel 2. A / D conversion is performed on channel m,1 (timings t37 and t38), and then A / D conversion is performed on channel 2 (timing t39), resulting in a digital signal DOUT2 and a digital signal DOUTref (timing t40). An offset parameter OF2 for correcting digital signal DOUT2 is obtained based on digital signal DOUT2 and digital signal DOUTref.

[0096] Thereafter, offset parameters OF3 to OFm for correcting the offsets of the digital signals DOUT3 to DOUTm are obtained for channels 3 to m in this order.

[0097] When offset parameters OF1 to OFm are obtained for channels 1 to m, respectively, the mode switches from OFFSET to Normal 1 or Normal 3 at timing t41. This ends the offset measurement process, and the digital signals DOUT1 to DOUTm are corrected using the offset parameters OF1 to OFm obtained in this process. For example, when A / D conversion is performed in ADC 10_1 of channel 1 at timing t43, the resulting digital signal DOUT1 is corrected with the offset parameter OF1, and finally a corrected digital signal CADO1 of CalDat(m+1) is output.

[0098] Although an example has been described here in which the digital signals DOUT1 to DOUTm are corrected using the offset measurement process for m channels and the offset parameters obtained in that process, it is also possible to replace the offset with a gain. That is, similar to the process shown in Fig. 13, it is also possible to correct the digital signals DOUT1 to DOUTm using the gain measurement process for m channels and the gain parameters obtained in that process.

[0099] The configuration and operation of the A / D converter circuit 1 according to this embodiment have been described above. According to the A / D converter circuit 1 according to this embodiment, correction parameters for correcting the digital signals DOUT1 to DOUTm converted by the ADCs 10_1 to 10_m corresponding to the trigger signal CKref are acquired based on the digital signals DOUT1 to DOUTm converted by the ADCs 10_1 to 10_m corresponding to the trigger signal CKref and the digital signal DOUTref converted by the reference ADC 10_r. This makes it possible to correct the digital signals DOUT1 to DOUTm using the correction parameters.

[0100] According to this configuration, corrected digital data ADOUT can be generated by simply adding a circuit that compares the digital signals DOUT1 to DOUTm converted by the ADCs 10_1 to 10_m with the digital signal DOUTref converted by the reference ADC 10_r. Therefore, the A / D converter circuit 1 according to this embodiment can accurately convert the analog signal AIN into digital data ADOUT with a simple configuration.

[0101] Furthermore, the A / D converter circuit 1 according to this embodiment can generate corrected digital data ADOUT through a simple process of comparing digital signals DOUT1 to DOUTm with digital signal DOUTref. This eliminates the need for complex algorithms and special arithmetic circuits, and also enables the circuit to be miniaturized and consume less power. Furthermore, the number of channels can be easily increased or decreased, shortening the time required for developing the A / D converter circuit (design, verification, layout, etc.).

[0102] (supplement) Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. Furthermore, not only the embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention.

[0103] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0104] (Item 1) a plurality of A / D converters each receiving the same analog signal and converting the analog signal into a digital signal in response to a corresponding one of a plurality of trigger signals having a predetermined phase difference; a selector for selecting one trigger signal from the plurality of trigger signals; a reference A / D converter that converts the analog signal into a digital signal in response to the selected trigger signal; a parameter acquisition unit that acquires, based on the digital signal converted by the A / D converter corresponding to the selected trigger signal among the plurality of A / D converters and the digital signal converted by the reference A / D converter, a correction parameter for correcting the digital signal converted by the A / D converter corresponding to the selected trigger signal. A / D converter circuit.

[0105] (Item 2) further comprising a correction unit that corrects the digital signal converted by the A / D converter based on the correction parameter. Item 1. The A / D converter circuit according to item 1.

[0106] (Item 3) the correction unit corrects an offset or a gain of the digital signal converted by the A / D converter based on the correction parameter. Item 2. The A / D converter circuit according to item 2.

[0107] (Item 4) the parameter acquisition unit acquires the correction parameter for each of the digital signals converted by the plurality of A / D converters; the correction unit corrects each of the digital signals converted by the plurality of A / D converters based on the correction parameter. Item 2 or 3. The A / D converter circuit according to item 2 or 3.

[0108] (Item 5) further comprising an integration unit that integrates the digital signals converted by the plurality of A / D converters and that have been respectively corrected by the correction unit, and generates digital data by converting the analog signals into digital waveforms. Item 4. The A / D converter circuit according to item 4. [Explanation of symbols]

[0109] 1 A / D converter circuit, 10_1 to 10_m ADC, 10_r reference ADC, 20 trigger signal generation circuit, 22_1 to 22_m delay circuit, 24 selector, 30 controller, 40 correction circuit block, 42 signal holding circuit, 44 encoder, 46_1 to 46_m arithmetic unit, 48_1 to 48_m correction circuit, 49 error output circuit, 50 integration circuit, 460 NAND circuit, 462 D flip-flop circuit, 470 arithmetic circuit, 472 arithmetic unit, 474 gain parameter acquisition unit, 476 offset parameter acquisition unit, 478 error acquisition unit.

Claims

1. a plurality of A / D converters each receiving the same analog signal and converting the analog signal into a digital signal in response to a corresponding one of a plurality of trigger signals having a predetermined phase difference; a selector for selecting one trigger signal from the plurality of trigger signals; a reference A / D converter that converts the analog signal into a digital signal in response to the selected trigger signal; a parameter acquisition unit that acquires, based on the digital signal converted by the A / D converter corresponding to the selected trigger signal among the plurality of A / D converters and the digital signal converted by the reference A / D converter, a correction parameter for correcting the digital signal converted by the A / D converter corresponding to the selected trigger signal. A / D converter circuit.

2. a correction unit that corrects the digital signal converted by the A / D converter based on the correction parameter; 2. The A / D converter circuit according to claim 1.

3. the correction unit corrects an offset or a gain of the digital signal converted by the A / D converter based on the correction parameter.

3. The A / D converter circuit according to claim 2.

4. the parameter acquisition unit acquires the correction parameter for each of the digital signals converted by the plurality of A / D converters; the correction unit corrects each of the digital signals converted by the plurality of A / D converters based on the correction parameter.

4. The A / D converter circuit according to claim 2 or 3.

5. further comprising an integration unit that integrates the digital signals converted by the plurality of A / D converters and that have been respectively corrected by the correction unit, and generates digital data by converting the analog signals into digital waveforms.

5. The A / D converter circuit according to claim 4.

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