Method for manufacturing semiconductor device

Abstract

To solve the problem in a method for manufacturing a semiconductor device having a self-aligned contact structure, in which there is a need for a technique capable of suppressing precipitation of unreacted carbon on a surface of a metal silicide film.SOLUTION: A method for manufacturing a semiconductor device includes: a silicon film forming step of forming a silicon film 46 on a first main surface 10a of a semiconductor layer 10 having a side surface and a bottom surface of a trench TR; a thermal oxide film forming step of forming a thermal oxide film 31 by thermally oxidizing the silicon film, in which a part of the silicon film formed on the first main surface outside the trench remains without being thermally oxidized; a metal film forming step of forming a metal film 48 on the silicon film; a first annealing step of reacting the silicon film with the metal film to form a precursor film 49; and a second annealing step of reacting the first main surface outside the trench with the precursor film to form a metal silicide film 23.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device manufactured using a silicon carbide semiconductor layer. In this semiconductor device, a trench gate and an interlayer insulating film are embedded in a trench formed in the main surface of the semiconductor layer. A structure in which a trench gate and an interlayer insulating film are embedded in a trench is called a self-aligned contact structure. In a semiconductor device with a self-aligned contact structure, a nickel film is formed on the main surface of the semiconductor layer, a nickel silicide film is formed on the main surface of the semiconductor layer by annealing, and then the unreacted nickel film is removed, thereby forming a metal silicide film in ohmic contact with the main surface of the semiconductor layer. In a semiconductor device with a self-aligned contact structure, an interlayer insulating film is not provided on the main surface of the semiconductor layer, so there is no need to form a contact hole in the interlayer insulating film, and the metal silicide film can be formed in a self-aligned manner.

[0003] When silicon contained in a semiconductor layer reacts with a nickel film to form a metal silicide film, unreacted carbon contained in the semiconductor layer may precipitate on the surface of the metal silicide film. Such carbon precipitation inhibits bonding between the metal silicide film and other metal layers. For this reason, Patent Document 2 proposes a technique in which a silicon film is formed in contact with a nickel film, the nickel film and the silicon film are reacted by low-temperature annealing to form a nickel silicide precursor film, and then the semiconductor layer and the precursor film are reacted by high-temperature annealing to silicidate the precursor film. According to this technique, the precursor film contains sufficient silicon, which suppresses the reaction of silicon contained in the semiconductor layer during silicidation, thereby suppressing the precipitation of unreacted carbon. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2023-055162 [Patent Document 2] Japanese Patent Publication No. 2022-146600 Summary of the Invention [Problem to be solved by the invention]

[0005] In a method for manufacturing a semiconductor device having a self-aligned contact structure, a technique is needed that can prevent unreacted carbon from precipitating on the surface of a metal silicide film. [Means for solving the problem]

[0006] The present specification discloses a method for manufacturing a semiconductor device, comprising: a trench forming step of forming a trench (TR) in a first main surface of a semiconductor layer (10) having a first main surface (10a) and a second main surface (10b); a silicon film forming step of forming a silicon film (46) on the first main surface of the semiconductor layer including the side and bottom surfaces of the trench; a thermal oxide film forming step of thermally oxidizing the silicon film to form a thermal oxide film (31); a gate electrode forming step of forming a gate electrode (34) in the trench, wherein an upper surface of the gate electrode is located below an opening edge (44) of the trench; and an interlayer insulating film forming step of forming an interlayer insulating film (42) on the first main surface of the semiconductor layer, wherein a portion of the interlayer insulating film is embedded in the trench. the first annealing step of performing annealing at a first temperature to react the silicon film with the metal film to form a precursor film (49); and the second annealing step of performing annealing at a second temperature higher than the first temperature to react the precursor film with the first main surface outside the trench to form a metal silicide film (23).

[0007] In the manufacturing method, a silicon film is formed on the first main surface of the semiconductor layer, and then the silicon film is thermally oxidized to form a thermal oxide film. In the thermal oxide film forming step, thermal oxidation is performed so that a portion of the silicon film formed on the first main surface outside the trench remains without being thermally oxidized. The thermal oxide film formed on the side surface of the trench can function as a part of the gate insulating film. In this way, the manufacturing method allows the silicon film to remain on the first main surface outside the trench without performing a patterning step. The silicon film remaining on the first main surface outside the trench reacts with a metal film in a first annealing step to form a precursor film. Furthermore, in a second annealing step, the precursor film reacts with the first main surface outside the trench to form a metal silicide film. In the manufacturing method, since the precursor film is formed in advance, reaction of silicon contained in the semiconductor layer during silicidation is suppressed, and precipitation of unreacted carbon is also suppressed. In this way, the manufacturing method can manufacture a semiconductor device having a self-aligned contact structure in which precipitation of unreacted carbon on the surface of the metal silicide film is suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a cross-sectional view of a main part of a semiconductor device, and is a diagram that schematically shows a cross-sectional view of a main part corresponding to a unit cell of the semiconductor device. [Figure 2] 2 is a diagram showing a manufacturing flow for manufacturing the semiconductor device of FIG. 1. [Figure 3] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 4] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 5] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 6] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 7]2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 8] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 9] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 10] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 11] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 12] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 13] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 14] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 15] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. [Figure 16] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in one step of manufacturing the semiconductor device of FIG. 1. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, a semiconductor device disclosed in this specification will be described with reference to the drawings. Note that for the purpose of clarity in the drawings, only some of the repeatedly arranged components are denoted by reference numerals.

[0010] As shown in Fig. 1, the semiconductor device 1 is a type of semiconductor device called an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor layer 10 having a first main surface 10a and a second main surface 10b, a drain electrode 22 covering the second main surface 10b of the semiconductor layer 10, a source electrode 26 covering the first main surface 10a of the semiconductor layer 10, and a plurality of trench gates 30 provided in the upper layer portion of the semiconductor layer 10. Here, the first main surface 10a and the second main surface 10b are a pair of surfaces extending in parallel on the surface of the semiconductor layer 10, and are surfaces perpendicular to the thickness direction of the semiconductor layer 10 (in this example, the vertical direction on the paper). The semiconductor layer 10 is an n + a drain region 12 of n-type, a drift region 14 of n-type, a body region 16 of p-type, and + and a source region 18. The material of the semiconductor layer 10 is silicon carbide (SiC).

[0011] The drain region 12 is provided in a lower layer portion of the semiconductor layer 10, and is disposed at a position exposed to the second main surface 10b of the semiconductor layer 10. The drain region 12 contains a high concentration of n-type impurities and is in ohmic contact with the drain electrode 22. As will be described later, the drain region 12 is a silicon carbide substrate for epitaxially growing the drift region 14.

[0012] The drift region 14 is provided in contact with the upper surface of the drain region 12 and is disposed between the drain region 12 and the body region 16. The drift region 14 is in contact with the lower side surface of the trench gate 30. The drift region 14 is formed by epitaxial growth from the upper surface of the drain region 12.

[0013] The body region 16 is provided in contact with the upper surface of the drift region 14 and is disposed between the drift region 14 and the source region 18. The body region 16 is in contact with the side surface of the trench gate 30. The body region 16 is electrically connected to the source electrode 26 via a p-type body contact region (appearing in a cross section not shown) adjacent to the source region 18. The body region 16 is a region formed by ion-implanting p-type impurities (e.g., aluminum) from the first main surface 10a of the semiconductor layer 10.

[0014] The source region 18 is provided in contact with the upper surface of the body region 16, is provided in an upper portion of the semiconductor layer 10, and is located at a position exposed to the first major surface 10a of the semiconductor layer 10. The source region 18 is in contact with the upper portion of the side surface of the trench gate 30. The source region 18 contains a high concentration of n-type impurities and is in ohmic contact with the source electrode 26. The source region 18 is a region formed by ion-implanting n-type impurities (e.g., nitrogen) from the first major surface 10a of the semiconductor layer 10.

[0015] The source electrode 26 is provided on the first major surface 10a of the semiconductor layer 10, and includes a metal silicide film 23, a barrier metal film 24, and a metal electrode film 25.

[0016] The metal silicide film 23 is selectively provided on the first main surface 10a of the upper portion of the semiconductor layer 10 outside the trenches TR (i.e., the portion of the semiconductor layer 10 between the trenches TR, hereinafter also referred to as the "mesa portion"), and is in ohmic contact with the source region 18. The metal silicide film 23 is nickel silicide (NiSi) obtained by silicidation of nickel (Ni). Alternatively, the metal silicide film 23 is not particularly limited, and may be formed by silicidation of, for example, titanium (Ti), tantalum (Ta), tungsten (W), or molybdenum (Mo).

[0017] The barrier metal film 24 is provided in contact with the metal silicide film 23 and the interlayer insulating film 42 so as to cover the first main surface 10a of the semiconductor layer 10. The barrier metal film 24 can prevent metal elements contained in the metal electrode film 25 from diffusing beyond the barrier metal film 24 into the metal silicide film 23 and the interlayer insulating film 42, and can also prevent metal elements contained in the metal silicide film 23 from diffusing beyond the barrier metal film 24 into the metal electrode film 25. The barrier metal film 24 is not particularly limited, and may be formed by laminating titanium (Ti) and titanium nitride (TiN), for example.

[0018] The metal electrode film 25 is provided in contact with the barrier metal film 24 so as to cover the first main surface 10a of the semiconductor layer 10, and functions as a metal pad. The metal electrode film 25 is not particularly limited, but may be made of aluminum silicon (AlSi), for example.

[0019] The trench gate 30 is embedded in a trench TR that extends from the first main surface 10a of the semiconductor layer 10, passing through the source region 18 and the body region 16, and reaching the drift region 14. The trench gate 30 includes a gate insulating film 32 and a gate electrode 34. The gate insulating film 32 has a two-layer structure including a thermal oxide film 31 and a deposition film 33. Alternatively, the gate insulating film 32 may be formed of a single layer of the thermal oxide film 31. Both the thermal oxide film 31 and the deposition film 33 are made of silicon oxide. The thermal oxide film 31 is disposed outside the deposition film 33 in the trench TR and is in contact with the side and bottom surfaces of the trench TR. The deposition film 33 is disposed inside the thermal oxide film 31 in the trench TR and is in contact with the inner surface of the thermal oxide film 31. The side and bottom surfaces of the gate electrode 34 are covered with the gate insulating film 32. The gate electrode 34 is not particularly limited, but may be made of, for example, polysilicon doped with a high concentration of n-type impurities.

[0020] The gate electrode 34 is provided below an opening edge 44 of the trench TR (i.e., a boundary that defines the trench TR on the first main surface 10a of the semiconductor layer 10, and a corner defined by the first main surface 10a of the mesa portion of the semiconductor layer 10 and the side surface of the trench TR). That is, the gate electrode 34 is buried in a part of the trench TR. The gate electrode 34 is insulated from the source electrode 26 by an interlayer insulating film 42. The interlayer insulating film 42 is buried in the upper part of the trench TR above the gate electrode 34. The upper surface of the interlayer insulating film 42 is configured to be flush with the opening edge 44 of the trench TR. Alternatively, the upper surface of the interlayer insulating film 42 may be located below the opening edge 44 of the trench TR.

[0021] A silicon film 46 is formed so as to contact the bottom surface of the trench gate 30. This silicon film 46 is a remaining silicon film 46 that was formed during the manufacturing process of the semiconductor device 1, and will be understood from the description of the manufacturing method that will be described later.

[0022] Next, the operation of the semiconductor device 1 will be described. When a positive voltage higher than that of the source electrode 26 is applied to the drain electrode 22 and a positive voltage higher than the threshold voltage is applied to the gate electrode 34, the semiconductor device 1 turns on. At this time, an inversion layer channel is formed in the body region 16 that contacts the side surface of the trench gate 30. Electrons injected from the source region 18 are injected into the drift region 14 through the inversion layer in the body region 16 and then move from the drift region 14 to the drain region 12, turning the semiconductor device 1 on. When the positive voltage applied to the gate electrode 34 falls below the threshold voltage, the inversion layer in the body region 16 disappears, turning the semiconductor device 1 off. In this way, the semiconductor device 1 can perform a switching operation by controlling the current flowing through the inversion layer in response to the voltage applied to the gate electrode 34.

[0023] Next, a method for manufacturing the semiconductor device 1 will be described with reference to the manufacturing flow of FIG. 2 and the cross-sectional views of essential parts of FIGS.

[0024] 3, a semiconductor layer 10 is prepared in which a drain region 12, a drift region 14, a body region 16, and a source region 18 are stacked. This semiconductor layer 10 is prepared by growing an epitaxial layer with a low concentration of n-type impurities from the upper surface of the drain region 12, which is a silicon carbide substrate, using epitaxial growth technology, and then introducing p-type impurities and n-type impurities into the upper layer of the epitaxial layer using ion implantation technology to form the body region 16 and the source region 18. Note that a p-type body contact region (appearing in a cross section, not shown) adjacent to the source region 18 is also formed by introducing p-type impurities into the upper layer of the epitaxial layer using ion implantation technology.

[0025] Next, as shown in FIG. 4, trenches TR are formed by, for example, dry etching, from the first main surface 10a of the semiconductor layer 10, penetrating the source region 18 and the body region 16 to reach the drift region 14 (step S1 in FIG. 2). The depth of the trenches TR is not particularly limited, but may be, for example, 1 μm or more. The width of the mesa portion between adjacent trenches TR is not particularly limited, but may be, for example, 0.8 μm or less. The distance between the center lines of adjacent trenches TR (i.e., trench pitch) is not particularly limited, but may be, for example, 2 μm or less.

[0026] Next, as shown in FIG. 5, a silicon film 46 is formed on the first main surface 10a of the semiconductor layer 10, including the side and bottom surfaces of the trenches TR, using, for example, a chemical vapor deposition (CVD) method (step S2 in FIG. 2). The silicon film 46 is not particularly limited, but may be, for example, amorphous silicon or polysilicon. This silicon film formation process is performed under conditions such that the film formation rate in the direction perpendicular to the first main surface 10a of the semiconductor layer 10 is greater than the film formation rate in the direction perpendicular to the side surfaces of the trenches TR. Therefore, the thickness T1 of the silicon film 46 formed on the first main surface 10a of the mesa portion is greater than the thickness T2 of the silicon film 46 formed on the side surfaces of the trenches TR.

[0027] Next, as shown in Fig. 6, the silicon film 46 is thermally oxidized using a thermal oxidation technique to form a thermal oxide film 31 (step S3 in Fig. 2). In this thermal oxide film formation step, the oxidation rate is adjusted so that the silicon film 46 formed on the side surface of the trench TR is completely thermally oxidized, and a portion of the silicon film 46 formed on the first main surface 10a of the mesa portion remains without being thermally oxidized. Note that, because the silicon film 46 formed on the bottom surface of the trench TR has a large thickness, a portion of the silicon film 46 formed on the bottom surface of the trench TR also remains.

[0028] 7, a deposition film 33 is formed on the upper surface of the thermal oxide film 31 by, for example, CVD (step S4 in FIG. 2). The thermal oxide film 31 and the deposition film 33 form a two-layer gate insulating film 32. Note that if the single layer of the thermal oxide film 31 can ensure the required film thickness for the gate insulating film 32, the deposition film formation step for forming the deposition film 33 may be omitted.

[0029] 8, a gate electrode 34 is buried in a portion of the trench TR by, for example, CVD (step S5 in FIG. 2). Specifically, after forming a film of polysilicon doped with n-type impurities on the first main surface 10a of the semiconductor layer 10 including the inside of the trench TR, unnecessary polysilicon is removed by etch-back, thereby burying the gate electrode 34 in a portion of the trench TR. In this way, a trench gate 30 is formed in the trench TR.

[0030] 9, an interlayer insulating film 42 is formed on the first main surface 10a of the semiconductor layer 10 by, for example, a CVD method (step S6 in FIG. 2). The interlayer insulating film 42 is formed so that a portion of it is buried in the trench TR to cover the gate electrode 34, and also to cover the thermal oxide film 31 and the deposition film 33 on the mesa portion.

[0031] 10, the interlayer insulating film 42, the deposition film 33, and the thermal oxide film 31 are etched back by, for example, dry etching until the silicon film 46 remaining on the first main surface 10a of the mesa portion is exposed (step S7 in FIG. 2). In this etch-back process, the upper surface of the interlayer insulating film 42 and the upper end surfaces of the deposition film 33 and the thermal oxide film 31 are flush with the opening edge 44 of the trench TR. Note that the upper surface of the interlayer insulating film 42 and the upper end surfaces of the deposition film 33 and the thermal oxide film 31 may be located below the opening edge 44 of the trench TR so that the silicon film 46 is reliably exposed.

[0032] 11, a metal film 48 is formed on the first main surface 10a of the semiconductor layer 10 by, for example, sputtering (step S8 in FIG. 2). In this example, the metal film 48 is a nickel film, but it may also be a titanium film, a tantalum film, a tungsten film, or a molybdenum film.

[0033] Next, as shown in FIG. 12, annealing is performed at a temperature of approximately 200° C. to react the silicon film 46 with the metal film 48 to form a precursor film 49 (step S9 in FIG. 2). The precursor film 49 is nickel silicide, which is an alloy of the silicon of the silicon film 46 and the nickel of the metal film 48. The temperature in this first annealing step is such that the silicon of the silicon film 46 reacts with the nickel of the metal film 48, but the silicon contained in the silicon carbide of the semiconductor layer 10 does not substantially react with the nickel of the metal film 48. Therefore, in the first annealing step, the silicon carbide that is the material of the semiconductor layer 10 is stable, and the silicon contained in the first main surface 10a of the mesa portion is prevented from being used in the reaction.

[0034] 13, the metal film 48 that has not reacted in the first annealing step is removed by, for example, wet etching (step S10 in FIG. 2), whereby the precursor film 49 is formed in a self-aligned manner on the first main surface 10a of the mesa portion.

[0035] 14, annealing is performed at a temperature of approximately 1000°C to react the silicon contained in the silicon carbide of the mesa portion with the precursor film 49 to form the metal silicide film 23 (step S11 in FIG. 2). In this second annealing step, only a small amount of silicon contained in the silicon carbide of the mesa portion diffuses into the precursor film 49 and is used for silicidation, so the amount of carbon contained in the silicon carbide of the mesa portion that diffuses into the precursor film 49 is also small. This also prevents unreacted carbon contained in the silicon carbide from precipitating on the surface of the metal silicide film 23. Because this second annealing step is performed at a relatively high temperature, the metal silicide film 23 can make good ohmic contact with the source region 18 of the mesa portion.

[0036] Next, as shown in FIG. 15, a barrier metal film 24 is formed by using, for example, sputtering technology (Step S12 in FIG. 2).

[0037] 16, a metal electrode film 25 is formed on the first main surface 10a of the semiconductor layer 10 by using a sputtering technique (step S13 in FIG. 2). As a result, a source electrode 26 is formed in which a metal silicide film 23, a barrier metal film 24, and a metal electrode film 25 are stacked. Since the deposition of unreacted carbon on the surface of the metal silicide film 23 is suppressed, the barrier metal film 24 and the metal electrode film 25 are well bonded to the surface of the metal silicide film 23.

[0038] Finally, a drain electrode 22 is formed on the second major surface 10b of the semiconductor layer 10, thereby completing the semiconductor device 1.

[0039] In the above manufacturing method, by utilizing the difference in thickness of the silicon film 46 formed on the first main surface 10a of the semiconductor layer 10, when the silicon film 46 is thermally oxidized to form the thermal oxide film 31, the silicon film 46 formed on the side surface of the trench TR is completely thermally oxidized, while a portion of the silicon film formed on the first main surface 10a of the mesa portion remains without being thermally oxidized. A portion of the silicon film 46 can be selectively left on the first main surface 10a of the mesa portion without performing a patterning process. As a result, in the above manufacturing method, nickel silicide is formed in a self-aligned manner on the first main surface 10a of the mesa portion in the first annealing process. Because the above manufacturing method can form nickel silicide in a self-aligned manner, it is useful for manufacturing semiconductor devices with narrow mesa widths (e.g., 0.8 μm or less), such as the semiconductor device 1. Furthermore, because the silicon film 46 does not remain on the side surface of the trench TR, nickel silicide is prevented from forming on the side surface of the trench TR in the first annealing process. This reduces drain-source leakage.

[0040] In the above-described manufacturing method, a silicon film 46 is formed on the first main surface 10a of the semiconductor layer 10 (i.e., a silicon film forming step, see FIG. 5), the silicon film 46 is thermally oxidized to form a thermal oxide film 31 (i.e., a thermal oxide film forming step, see FIG. 6), and then a deposited film 33 is formed on the upper surface of the thermal oxide film 31 (i.e., a deposited film forming step, see FIG. 7), thereby forming a two-layer gate insulating film 32 consisting of the thermal oxide film 31 and the deposited film 33. Alternatively, a deposited film forming step may be performed between the silicon film forming step and the thermal oxide film forming step. In this case, in the thermal oxide film forming step, the silicon film 46 may be thermally oxidized in an atmosphere of a nitrogen oxide gas (e.g., nitric oxide (NO), dinitrogen monoxide (NO)). By the thermal oxidation using the nitrogen oxide gas, the side surfaces of the trench TR are nitrided, thereby improving channel mobility. Moreover, the oxygen contained in the nitrogen oxide gas is consumed by the oxidation of the silicon film 46, thereby suppressing oxidation of the side surface of the trench TR. As a result, the interface state on the side surface of the trench TR is kept low, and high channel mobility is achieved.

[0041] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The claimed technology includes various modifications and variations of the specific examples described above. While the above embodiments illustrate MOSFETs, the technology disclosed in this specification is also applicable to other types of semiconductor devices with trench gates, such as insulated gate bipolar transistors (IGBTs). While the above embodiments illustrate n-channel semiconductor devices, the technology disclosed in this specification is also applicable to p-channel semiconductor devices. Furthermore, the technical elements described in this specification or drawings exhibit technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology illustrated in this specification or drawings can simultaneously achieve multiple objectives, and achieving any one of these objectives is technically useful in itself. [Explanation of symbols]

[0042] 1: semiconductor device, 10: semiconductor layer, 12: drain region, 14: drift region, 16: body region, 18: source region, 22: drain electrode, 23: metal silicide film, 24: barrier metal film, 25: metal electrode film, 26: source electrode, 30: trench gate, 31: thermal oxide film, 32: gate insulating film, 33: deposited film, 34: gate electrode, 42: interlayer insulating film, 46: silicon film, 48: metal film, 49: precursor film

Claims

1. A trench forming step of forming a trench (TR) in a first main surface of a silicon carbide semiconductor layer (10) having a first main surface (10a) and a second main surface (10b); a silicon film forming step of forming a silicon film (46) on the first main surface of the semiconductor layer including the side and bottom surfaces of the trench; a thermal oxidation film forming step of thermally oxidizing the silicon film to form a thermal oxidation film (31), in which a portion of the silicon film formed on the first main surface outside the trench remains without being thermally oxidized; a gate electrode forming step of forming a gate electrode (34) in the trench, the upper surface of the gate electrode being located below an opening edge (44) of the trench; an interlayer insulating film forming step of forming an interlayer insulating film (42) on the first main surface of the semiconductor layer, a part of the interlayer insulating film being embedded in the trench and covering the gate electrode; an etch-back process of etching back the interlayer insulating film and the thermal oxide film until the silicon film remaining on the first main surface outside the trench is exposed; a metal film forming step of forming a metal film (48) on the silicon film; a first annealing step of annealing at a first temperature, in which the silicon film and the metal film are reacted to form a precursor film (49); a second annealing step of performing annealing at a second temperature higher than the first temperature, in which the precursor film reacts with the first main surface outside the trench to form a metal silicide film (23).

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the silicon film formation process, a thickness (T1) of the silicon film formed on the first main surface outside the trench is greater than a thickness (T2) of the silicon film formed on the side surface of the trench.

3. 3. The method for manufacturing a semiconductor device according to claim 2, wherein in the thermal oxidation step, the silicon film formed on the side surface of the trench is completely thermally oxidized, while a portion of the silicon film formed on the first main surface outside the trench remains without being thermally oxidized.

4. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising a metal film removing step between said first annealing step and said second annealing step, for removing said metal film that has not reacted in said first annealing step.

5. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the material of said metal film is nickel.

6. 6. The method for manufacturing a semiconductor device according to claim 1, further comprising a deposition film forming step of forming a deposition film (33) on the thermal oxide film between the thermal oxide film forming step and the gate electrode forming step.

7. The method further includes a deposition film forming step of forming a deposition film (33) on the silicon film between the silicon film forming step and the thermal oxide film forming step, 6. The method for manufacturing a semiconductor device according to claim 1, wherein in said thermal oxide film forming step, said silicon film is thermally oxidized in an atmosphere of nitrogen oxide gas.

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