Semiconductor integrated circuit device

Abstract

To provide a semiconductor integrated circuit device in which a test of an oscillation margin indicating stability of a crystal oscillation circuit is performed without an external component other than an external crystal resonator, and enable a more accurate operation during a normal operation.SOLUTION: A semiconductor integrated circuit device 100 includes: a first connection terminal 105, a second connection terminal 110, and a third connection terminal 115 for selectively connecting an external crystal resonator 200; an oscillation circuit 125 which includes an inverter circuit 140 and a feedback resistor 145 connected in parallel to each other, and in which a node 150 on one side of the inverter circuit 140 and the feedback resistor 145 connected in parallel is connected to the first connection terminal 105 and a node 155 on the other side is connected to the second connection terminal 110; and a test resistor 130 connected between one of the node 150 on the one side and the node 155 on the other side of the inverter circuit 140 and the feedback resistor 145 connected in parallel and the third connection terminal 115.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a connection terminal for connecting an external crystal oscillator. [Background technology]

[0002] Semiconductor integrated circuit devices equipped with connection terminals for externally connecting crystal units have built-in crystal oscillation circuits that include inverter circuits and feedback resistors, and it is necessary to test the oscillation margin of the crystal unit before shipping. To test the oscillation margin, a negative resistor for checking the oscillation margin must be inserted in series with the crystal unit, the oscillation circuit must be operated, and it must be confirmed whether a clock signal is output, and then the negative resistor must be removed, which is a time-consuming and labor-intensive process.

[0003] The following Patent Document 1 discloses a crystal oscillator in which a check resistor capable of varying the oscillation margin, connected in series with a crystal resonator, and a switch circuit capable of switching the connection of the check resistor with an external control signal are integrated into the oscillator circuit of a bare IC chip. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-116563 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the invention described in Patent Document 1, the check resistor is bypassed by a switch circuit during normal operation, but in that case the oscillator circuit is affected by the on-resistance of the switch circuit. It is possible to reduce the resistance value of the on-resistance of the switch circuit by increasing the size of the transistor that makes up the switch circuit, but considering that this would increase the size of the circuit, it is preferable to avoid resistor elements as much as possible.

[0006] In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit device that can perform an oscillation margin test that indicates the stability of a crystal oscillator circuit without using external components, and that enables more accurate operation during normal operation. [Means for solving the problem]

[0007] In order to solve the above problem, the semiconductor integrated circuit device of the present invention includes a first connection terminal, a second connection terminal, and a third connection terminal for selectively connecting an external crystal resonator, an oscillation circuit including an inverter circuit and a feedback resistor connected in parallel to each other, with one node of the parallel-connected inverter circuit and the feedback resistor connected to the first connection terminal and the other node of the parallel-connected inverter circuit and the feedback resistor connected to the second connection terminal, and a test resistor connected between either one of the nodes on one side and the other side of the parallel-connected inverter circuit and the feedback resistor and the third connection terminal. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram of a semiconductor integrated circuit device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing a connection state during a test of the oscillation margin of the semiconductor integrated circuit device of the first embodiment. [Figure 3] FIG. 3 is a diagram showing a connection state during normal operation of the semiconductor integrated circuit device of the first embodiment. [Figure 4] FIG. 4 is a schematic diagram of a semiconductor integrated circuit device according to the second embodiment. [Figure 5] FIG. 5 is a diagram showing a connection state during a test of the oscillation margin of the semiconductor integrated circuit device of the second embodiment. [Figure 6] FIG. 6 is a diagram showing a connection state during normal operation of the semiconductor integrated circuit device of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0010] [Embodiment 1] 1 is a schematic diagram of a semiconductor integrated circuit device 100 according to a first embodiment. As shown in FIG. 1, the semiconductor integrated circuit device 100, which is a crystal oscillation circuit, includes a first connection terminal 105, a second connection terminal 110, a third connection terminal 115, and a fourth connection terminal 120. An external crystal unit 200 is selectively connected between the first connection terminal 105 and the second connection terminal 110, or between the first connection terminal 105 and the third connection terminal 115. An external circuit (not shown) is connected to the fourth connection terminal 120 during normal operation.

[0011] The semiconductor integrated circuit device 100 further includes an oscillator circuit 125 , a test resistor 130 , and a Schmitt trigger circuit 135 .

[0012] The oscillator circuit 125 includes an inverter circuit 140 and a feedback resistor 145 connected in parallel to each other. A first node 150, which is a node on one side of the parallel-connected inverter circuit 140 and feedback resistor 145, is connected to the first connection terminal 105, and a second node 155, which is a node on the other side, is connected to the second connection terminal 110.

[0013] The test resistor 130 is connected between the second node 155 and the third connection terminal 115. The test resistor 130 is an indicator of the ability of the oscillation circuit to cancel the equivalent series resistance of the crystal unit 200 and cause it to oscillate. The resistance value of the test resistor 130 is selected to be between 5 and 10 times the equivalent series resistance of the crystal unit 200 to be externally connected. For example, if the equivalent series resistance of the crystal unit 200 to be externally connected is 300 Ω and the required oscillation margin of the crystal unit 200 is 10 times, a resistive element with a resistance value of 3000 Ω is used for the test resistor 130.

[0014] Furthermore, the second node 155 is connected to the fourth connection terminal 120 via the Schmitt trigger circuit 135, and the fourth connection terminal 120 serves as the output terminal of the crystal oscillation circuit.

[0015] Next, the operation of the semiconductor integrated circuit device 100 of the first embodiment will be described. When testing the oscillation margin of the crystal oscillator circuit, as shown in FIG. 2, the crystal oscillator 200 is connected between the first connection terminal 105 and the third connection terminal 115, and the crystal oscillator circuit is operated. Then, it is determined whether a signal with a frequency set for the crystal oscillator 200 is output from the fourth connection terminal 120. If an output signal with the predetermined frequency is output, the semiconductor integrated circuit device 100 is determined to be operating normally. If not, it is determined to not meet the criteria. Note that external load capacitances are connected between the first connection terminal 105 and ground and between the third connection terminal 115 and ground to adjust and stabilize the oscillation frequency, but detailed description thereof will be omitted in this disclosure. Note that the external load capacitances may be built into the semiconductor integrated circuit device 100.

[0016] 3, when the semiconductor integrated circuit device 100 is operated normally, a crystal unit 200 is connected between the first connection terminal 105 and the second connection terminal 110, and an external circuit requiring an input of a predetermined frequency is connected to the fourth connection terminal 120. As in the case of testing the oscillation margin, external load capacitances for adjusting and stabilizing the oscillation frequency are connected between the first connection terminal 105 and ground and between the second connection terminal 110 and ground, respectively, but detailed description thereof will be omitted in this disclosure. The external load capacitances may be configured to be built into the semiconductor integrated circuit device 100.

[0017] According to the semiconductor integrated circuit device 100 of the first embodiment, it is not necessary to externally connect a negative resistance, which has conventionally been externally connected, when testing the oscillation margin of the crystal resonator 200. Furthermore, during normal operation, the oscillation circuit can be configured without the intervention of a switch circuit or the like, and therefore there is no on-resistance included in the switch circuit, allowing the oscillation circuit to operate more accurately.

[0018] In the first embodiment, the test resistor 130 is connected between the second node 155 and the third connection terminal 115. However, the test resistor 130 may be connected between the first node 150 and the third connection terminal 115. In this case, when testing the oscillation margin of the crystal oscillation circuit, the crystal resonator 200 is connected between the second connection terminal 110 and the third connection terminal 115, and during normal operation, the crystal resonator 200 is connected between the first connection terminal 105 and the second connection terminal 110.

[0019] [Embodiment 2] 4 is a schematic diagram of a semiconductor integrated circuit device 300 according to the second embodiment. As shown in FIG. 4, the semiconductor integrated circuit device 300, which is a crystal oscillation circuit, includes a first connection terminal 305, a second connection terminal 310, a third connection terminal 315, and a fourth connection terminal 320. An external crystal unit 400 is selectively connected between the first connection terminal 305 and the second connection terminal 310, or between the first connection terminal 305 and the third connection terminal 315. During normal operation, an external circuit (not shown) is connected to the third connection terminal 315 and the fourth connection terminal 320.

[0020] The semiconductor integrated circuit device 300 further includes an oscillator circuit 325 , a test resistor 330 , and a Schmitt trigger circuit 335 .

[0021] The oscillator circuit 325 includes an inverter circuit 340 and a feedback resistor 345 connected in parallel to each other. A first node 350, which is a node on one side of the parallel-connected inverter circuit 340 and feedback resistor 345, is connected to the first connection terminal 305, and a second node 355, which is a node on the other side, is connected to the second connection terminal 310.

[0022] Test resistor 330 is connected between second node 355 and third connection terminal 315, and a switch circuit 360 is further provided between second node 355 and test resistor 330. Switch circuit 360 is electrically turned on / off by internal circuit 365. Furthermore, third connection terminal 315 is connected to general-purpose input / output port 370, which is further connected to another internal circuit (not shown).

[0023] The second node 355 is connected to the fourth connection terminal 320 via the Schmitt trigger circuit 335, and the fourth connection terminal 320 serves as the output terminal of the crystal oscillation circuit.

[0024] Next, the operation of the semiconductor integrated circuit device 300 of the second embodiment will be described. When testing the oscillation margin of the crystal oscillator circuit, as shown in FIG. 5 , the crystal unit 400 is connected between the first connection terminal 305 and the third connection terminal 315. The internal circuit 365 turns the switch circuit 360 on (closed), and the general-purpose input / output port 370 is set to a high-impedance (Hi-Z) state. The fourth connection terminal 320 then determines whether a signal with a frequency set for the crystal unit 400 is being output. If an output signal with the predetermined frequency is being output, the semiconductor integrated circuit device 300 is determined to be operating normally. If not, the semiconductor integrated circuit device 300 is determined to not meet the criteria. External load capacitances are connected between the first connection terminal 305 and ground and between the third connection terminal 315 and ground to adjust and stabilize the oscillation frequency, but detailed description thereof will be omitted in this disclosure. The external load capacitances may be built into the semiconductor integrated circuit device 300.

[0025] 6, when semiconductor integrated circuit device 300 is operated normally, crystal unit 400 is connected between first connection terminal 305 and second connection terminal 310. Furthermore, an external circuit that uses input / output of general-purpose input / output port 370 is connected to third connection terminal 315, and switch circuit 360 is turned off (open circuit state) by internal circuit 365, enabling general-purpose input / output port 370. Furthermore, an external circuit that requires input of a predetermined frequency is connected to fourth connection terminal 320, and fourth connection terminal 320 is operated as an input / output terminal of an internal circuit (not shown).

[0026] As in the case of testing the oscillation margin, external load capacitances are connected between the first connection terminal 305 and the ground and between the second connection terminal 310 and the ground to adjust or stabilize the oscillation frequency, but detailed explanations thereof will be omitted in this disclosure. The external load capacitances may be configured to be built into the semiconductor integrated circuit device 300.

[0027] That is, according to the above-mentioned second embodiment, the third connection terminal 315 is used as a connection terminal for connecting the crystal unit 400 when testing the oscillation margin of the crystal unit 400, and is used as a connection terminal for the general-purpose input / output port 370 during normal use.

[0028] Therefore, according to the second embodiment, the fourth connection terminal 320, which is used as a connection terminal for connecting the crystal unit 400 during the oscillation margin test, can be effectively used as an internal input / output terminal (not shown) via the general-purpose input / output port 370 during normal operation.

[0029] In the second embodiment, the switch circuit 360 and the test resistor 330 are connected between the second node 155 and the third connection terminal 115. However, the test resistor 330 may be connected between the first node 350 and the third connection terminal 315. In this case, when testing the oscillation margin of the crystal oscillation circuit, the crystal resonator 400 is connected between the second connection terminal 310 and the third connection terminal 315, and during normal operation, the crystal resonator 400 is connected between the first connection terminal 305 and the second connection terminal 310. [Explanation of symbols]

[0030] 100 Semiconductor integrated circuit device 105 First connection terminal 110 Second connection terminal 115 Third connection terminal 120 4th connection terminal 125 Test Resistor 125 Oscillator Circuit 130 Test Resistor 135 Schmitt trigger circuit 140 Inverter circuit 145 Feedback resistor 150 1st Node 155 Second Node 200 crystal oscillator 300 Semiconductor integrated circuit device 305 First connection terminal 310 Second connection terminal 315 Third connection terminal 320 4th connection terminal 325 Oscillator Circuit 330 Test Resistor 335 Schmitt Trigger Circuit 340 Inverter Circuit 345 Feedback Resistor 350 1st Node 355 Second Node 360 Switch Circuit 365 Internal circuit 370 general-purpose input / output ports 400 crystal oscillator

Claims

1. a first connection terminal, a second connection terminal, and a third connection terminal for selectively connecting an external crystal unit; an oscillation circuit including an inverter circuit and a feedback resistor connected in parallel to each other, with one node of the inverter circuit and the feedback resistor connected in parallel being connected to the first connection terminal and the other node being connected to the second connection terminal; a test resistor connected between the third connection terminal and one of the nodes on one side and the other side of the inverter circuit and the feedback resistor connected in parallel.

2. 2. The semiconductor integrated circuit device according to claim 1, wherein a general-purpose input / output port is further connected to said third connection terminal, and said third connection terminal is used as a connection terminal for connecting said crystal resonator when testing the oscillation margin of said crystal resonator, and is used as a connection terminal for the general-purpose input / output port during normal use.

3. 3. The semiconductor integrated circuit device according to claim 2, further comprising a switch circuit connected between said test resistor and one of a node on one side and a node on the other side of said inverter circuit and said feedback resistor connected in parallel.

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