Semiconductor device

Abstract

To provide a semiconductor device with advantageously reduced temporal characteristic variation.SOLUTION: There is provided a semiconductor device that comprises an inter-layer dielectric film provided between an upper surface of a semiconductor substrate and an upper surface electrode and having a first contact hole connecting the semiconductor substrate and the upper surface electrode to each other; a protection film provided on an upper surface of the upper surface electrode; and a plating layer provided on a region, which is not covered with the protection film, of the upper surface of the upper surface electrode. Therein: the semiconductor substrate has a first end side in top view; a first contact hole includes a first outer hole end portion closest to the first end side; and the plating layer is formed on a portion overlapping with the first outer hole end portion, of the upper surface electrode.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, semiconductor devices have been known in which a protective film made of polyimide or the like is provided to cover an emitter electrode (see, for example, Patent Document 1). Patent Document 1: JP 2022-059487 A Summary of the Invention [Problem to be solved by the invention]

[0003] It is preferable that the semiconductor device exhibits small fluctuations in characteristics over time. [Means for solving the problem]

[0004] To solve the above problems, a first aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface. Any of the semiconductor devices may include a top electrode containing aluminum. Any of the semiconductor devices may include an interlayer insulating film provided between the top surface of the semiconductor substrate and the top electrode, the interlayer insulating film having a first contact hole connecting the semiconductor substrate and the top electrode. Any of the semiconductor devices may include a protective film provided on the top surface of the top electrode. Any of the semiconductor devices may include a plating layer provided on an area of the top surface of the top electrode that is not covered by the protective film. In any of the semiconductor devices, the semiconductor substrate may have a first edge in a top view. In any of the semiconductor devices, the first contact hole may have a first outer hole end closest to the first edge. In any of the semiconductor devices, the plating layer may be formed on a portion of the top electrode that overlaps the end of the first outer hole.

[0005] In any of the above semiconductor devices, the protective film may have an outer protective portion provided between an end of the first outer hole and the first edge in a top view.

[0006] In any of the above semiconductor devices, an inner protection end of the outer protection portion closest to the first contact hole may be provided between the first outer hole end and the first edge.

[0007] In any of the above semiconductor devices, the protective film may further include an inner protective portion that is disposed farther from the first end side than the outer protective portion in a top view and that overlaps with the first contact hole.

[0008] In any of the above semiconductor devices, the semiconductor substrate may have an active portion in which a semiconductor element is formed. In any of the above semiconductor devices, the first contact hole may have an active hole end closest to the first edge among portions connecting the active portion and the upper surface electrode. In any of the above semiconductor devices, the plating layer may be formed on a portion of the upper surface electrode that overlaps with the active hole end.

[0009] In any of the above semiconductor devices, the semiconductor substrate may have a first conductivity type drift region provided in the active portion. In any of the above semiconductor devices, the semiconductor substrate may have a second conductivity type well region provided to surround the active portion in a top view. In any of the above semiconductor devices, the first contact hole may have a well hole end closest to the first edge among portions connecting the well region and the top electrode. In any of the above semiconductor devices, the plating layer may be formed on a portion of the top electrode overlapping with the well hole end.

[0010] In any of the above semiconductor devices, the semiconductor substrate may have a trench portion extending from the upper surface to the interior of the semiconductor substrate and having a longitudinal length in a first direction on the upper surface. In any of the above semiconductor devices, the end of the first outer hole may be an end of the first contact hole in the first direction.

[0011] In any of the above semiconductor devices, the semiconductor substrate may have a trench portion extending from the top surface to the interior of the semiconductor substrate and having a longitudinal length in a first direction on the top surface. In any of the above semiconductor devices, the outer protection portion may be provided between an end of the first outer hole and the first end side in the first direction.

[0012] In any of the above semiconductor devices, the semiconductor substrate may have a trench portion extending from the upper surface to the interior of the semiconductor substrate and having a longitudinal length in a first direction on the upper surface. In any of the above semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type provided in the active portion. In any of the above semiconductor devices, the semiconductor substrate may have a base region of a second conductivity type provided between the drift region and the upper surface and in contact with the trench portion. In any of the above semiconductor devices, the semiconductor substrate may have an accumulation region of the first conductivity type provided between the drift region and the base region and having a higher concentration than the drift region. In any of the above semiconductor devices, the inner protective edge may be provided between the accumulation region and the first end edge in the first direction.

[0013] In any of the above semiconductor devices, the semiconductor substrate may have a plurality of trenches aligned in a second direction on the upper surface. In any of the above semiconductor devices, each of the plurality of trenches may be provided from the upper surface to the interior of the semiconductor substrate and may have a longitudinal length in a first direction on the upper surface. In any of the above semiconductor devices, the first outer hole end may be an end of the first contact hole in the second direction.

[0014] In any of the above semiconductor devices, the semiconductor substrate may have a plurality of trench portions aligned in a second direction on the top surface. In any of the above semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type provided in the active portion. In any of the above semiconductor devices, the semiconductor substrate may have a base region of a second conductivity type provided between the drift region and the top surface and in contact with the trench portion. In any of the above semiconductor devices, the semiconductor substrate may have an accumulation region of the first conductivity type provided between the drift region and the base region and having a higher concentration than the drift region. In any of the above semiconductor devices, each of the plurality of trench portions may be provided from the top surface to the interior of the semiconductor substrate and may have a longitudinal length in a first direction on the top surface. In any of the above semiconductor devices, the inner protective edge may be provided between the accumulation region and the first end edge in the second direction.

[0015] In any of the above semiconductor devices, the semiconductor substrate may have a plurality of trench portions aligned in a second direction on the top surface. In any of the above semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type provided in the active portion. In any of the above semiconductor devices, the semiconductor substrate may have a base region of a second conductivity type provided between the drift region and the top surface and in contact with the trench portion. In any of the above semiconductor devices, the semiconductor substrate may have a contact region of the second conductivity type provided between the top surface and the base region, connected to the top surface electrode, and having a higher concentration than the base region. In any of the above semiconductor devices, each of the plurality of trench portions may be provided from the top surface to the interior of the semiconductor substrate and have a longitudinal length in a first direction on the top surface. In any of the above semiconductor devices, the inner protective edge may be provided between the contact region and the first end edge in the second direction.

[0016] In any of the above semiconductor devices, the semiconductor substrate may further have a second edge and a third edge when viewed from above. In any of the above semiconductor devices, the first contact hole may have a second outer hole end closest to the second edge and a third outer hole end closest to the third edge. In any of the above semiconductor devices, the plating layer may be formed on a portion of the top surface electrode overlapping the second outer hole end and a portion of the top surface electrode overlapping the third outer hole end.

[0017] In any of the above semiconductor devices, the plating layer may contain at least one of nickel and copper.

[0018] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged view of an area A in FIG. [Figure 3] FIG. 3 is a diagram showing an example of the X1-X1′ cross section in FIG. 2. [Figure 4] FIG. 3 is a diagram showing an example of a cross section taken along the line Y1-Y1′ in FIG. 2. [Figure 5] FIG. 2 is a diagram showing an example of a Y2-Y2′ cross section. [Figure 6] FIG. 10 is a diagram showing another example of the Y2-Y2′ cross section. [Figure 7] FIG. 10 is a diagram illustrating a path of a hole current from an outer hole end 281 in a comparative example. [Figure 8] FIG. 10 is a diagram illustrating a path of a hole current from an outer hole end 281 in an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0020] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0021] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0022] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0023] In this specification, orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0024] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0025] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0026] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0027] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Also, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0028] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows the semiconductor substrate 10, top electrode 52, active portion 160, protective film 251, protective film 252, protective film 253, and protective film 254 of the semiconductor device 100, and omits other components. Protective film 251, protective film 252, protective film 253, and protective film 254 may be insulating films formed of a polymer compound such as polyimide.

[0029] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but it may also be a compound semiconductor substrate such as silicon carbide, gallium nitride, or gallium arsenide.

[0030] In this specification, the term "top view" refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has multiple edges 231 when viewed from the top. In FIG. 1, the X-axis and Y-axis are parallel to any of the edges 231. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0031] The semiconductor substrate 10 of this example may have two sets of edges facing each other (in FIG. 1 , a set of edges 231-1 and 231-3, and a set of edges 231-2 and 231-4). In this specification, each edge 231 may be referred to as a first edge, a second edge, a third edge, or a fourth edge. Any edge 231 may function as a first edge. Any edge 231 may function as a second edge, a third edge, or a fourth edge.

[0032] Some figures in this specification illustrate a cross-sectional structure in the vicinity of one of the end edges 231. The vicinity of the other end edge 231 opposite the end edge 231 may have a similar structure to that of the end edge 231. For example, the vicinity of end edge 231-1 and the vicinity of end edge 231-3 may have a similar structure. The vicinity of end edge 231-2 and the vicinity of end edge 231-4 may have a similar structure. However, the pad 57 and the protective film 252 are not provided near end edge 231-4.

[0033] An upper surface electrode 52 is provided above the upper surface of the semiconductor substrate 10. In FIG. 1, the region where the upper surface electrode 52 is provided is surrounded by a dotted line. The upper surface electrode 52 is an electrode through which the main current of the semiconductor element provided on the semiconductor substrate 10 flows. If the semiconductor element is an IGBT (Insulated Gate Bipolar Transistor), the upper surface electrode 52 may be an emitter electrode. If the semiconductor element is a MOSFET, the upper surface electrode 52 may be a source electrode. If the semiconductor element is a diode, the upper surface electrode 52 may be an anode electrode.

[0034] The top electrode 52 is made of metal. At least a portion of the top electrode 52 may be made of aluminum or an aluminum-silicon alloy. The top electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. Furthermore, the top electrode 52 may have a plug formed by embedding tungsten or the like in the contact hole so as to contact the barrier metal and aluminum or the like.

[0035] The semiconductor substrate 10 is provided with an active portion 160 in which a semiconductor element is formed. As described above, the semiconductor element may include at least one of an IGBT, a MOSFET, or a diode. In this specification, an example in which an IGBT is provided on the semiconductor substrate 10 is described. The semiconductor substrate 10 may have a reverse conducting IGBT (RC-IGBT) or a reverse blocking IGBT (RB-IGBT). Furthermore, when a MOSFET is provided on the semiconductor substrate 10, the "emitter" described in this specification may be replaced with the "source," and the "collector" may be replaced with the "drain."

[0036] The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device is in operation. In this example, the active portion 160 refers to a region surrounded by a well region 11, which will be described later, in a top view. An upper surface electrode 52 is provided above the active portion 160. In FIG. 1, the active portion 160 and the upper surface electrode 52 share a common range, but the range of the active portion 160 and the range of the upper surface electrode 52 may be different.

[0037] The semiconductor device 100 may have one or more pads 57 above the semiconductor substrate 10. The one or more pads 57 may include a pad insulated from the top electrode 52 or a pad connected to the top electrode 52. The one or more pads 57 may include, for example, a gate pad connected to the gate electrode of an IGBT or MOSFET. The one or more pads 57 may include a pad for temperature detection, a pad for current detection, a pad for detecting the potential of the top electrode 52, or the like. In this example, each pad 57 is disposed near the edge 231-2. The vicinity of the edge 231-2 refers to the region between the edge 231-2 and the top electrode 52 or the active portion 160 in a top view. When the semiconductor device 100 is mounted, the top electrode 52 and the pads 57 may be connected to an external circuit via wiring such as wires.

[0038] At least a portion of each of protective films 251, 252, 253, and 254 is disposed above upper electrode 52 or pad 57. In FIG. 1, the area where each protective film is formed is hatched with diagonal lines. Each protective film exposes at least a portion of upper surface 53 of upper electrode 52. Wiring such as a wire may be connected to the exposed upper surface 53. Furthermore, each protective film exposes at least a portion of the upper surface of the respective pad 57. Wiring such as a wire may also be connected to the upper surface of each pad 57.

[0039] The protective film 251 is provided in contact with the edge 231 in top view. In this example, the protective film 251 is provided in a ring shape along the edge 231 of the semiconductor substrate 10. The protective film 251 may be provided extending from each edge 231 to a position overlapping with the top electrode 52 or to a position overlapping with the pad 57. In this example, the protective film 251 extends from each of the edge 231-1, 231-3, and 231-4 to a position overlapping with the top electrode 52. In addition, the protective film 251 extends from the edge 231-2 to a position overlapping with the pad 57.

[0040] The protective film 252 extends from the pad 57 to the upper electrode 52 in top view. The protective film 252 is connected to the protective film 251. The protective film 251 may be provided between two pads 57. In top view, the protective film 251 and the protective film 252 surround a partial area of the upper surface 53 of the upper electrode 52. In addition, in top view, the protective film 251 and the protective film 252 surround a partial area of the upper surface of each pad.

[0041] The protective film 253 is provided so as to extend from an end of the protective film 251 toward the inside of the active section 160. The inside of the active section 160 refers to the direction approaching the center of the active section 160 in a top view. The protective film 253 may overlap with gate wiring arranged in the active section 160. The gate wiring is wiring that transmits a gate voltage. The gate wiring may include metal wiring made of a metal such as aluminum, or may include semiconductor wiring made of a semiconductor such as polysilicon to which impurities have been added, or metal wiring and semiconductor wiring may be stacked.

[0042] The gate wiring may have a ring-shaped portion disposed outside the upper electrode 52 in a top view, and an inner portion extending from the ring-shaped portion toward the inside of the active section 160. The ring-shaped portion of the gate wiring is connected to a gate pad (e.g., pad 57-3). The ring-shaped portion of the gate wiring may be disposed below the protective film 251 or the protective film 252. The ring-shaped portion and the inner portion of the gate wiring are connected to the gate electrode of the semiconductor element provided in the active section 160. With this structure, a gate voltage can be applied to the gate electrode at each position on the semiconductor substrate 10.

[0043] The protective film 254 is provided so as to extend from an end of the protective film 251 or the protective film 252 toward the inside of the active unit 160. The protective film 254 may overlap a temperature detection diode disposed above the active unit 160 and a wiring connected to the diode. The temperature detection diode is, for example, a PN junction diode made of polysilicon.

[0044] A well region 11, which will be described later, may be formed in the semiconductor substrate 10 below each protective film. The well region 11 is a P+ type region exposed on the upper surface of the semiconductor substrate 10. The well region 11 may have a higher doping concentration than a base region 14, which will be described later. The well region 11 may be formed deeper than the base region 14.

[0045] The semiconductor substrate 10 may include an edge termination structure between the well region 11 and the edge 231. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active portion 160.

[0046] 2 is an enlarged view of region A in FIG. 1. Region A is a region including upper surface electrode 52, active portion 160, well region 11, protective film 251, and protective film 252. In this example, upper surface electrode 52 is provided over a wider area than active portion 160. An interlayer insulating film is provided between semiconductor substrate 10 and upper surface electrode 52, but is omitted in FIG. 2. A first contact hole 54 that electrically connects semiconductor substrate 10 and upper surface electrode 52 is provided in the interlayer insulating film.

[0047] 2, solid lines indicate regions such as well region 11 that are provided inside semiconductor substrate 10 and exposed on the upper surface of semiconductor substrate 10. Solid lines also indicate first contact holes 54. Broken lines and arrows indicate the range in which accumulation region 16, which is provided inside semiconductor substrate 10 and not exposed on the upper surface of semiconductor substrate 10, is provided. Broken lines and arrows also indicate the ranges in which upper surface electrode 52, active portion 160, protective film 251, and protective film 252 are provided.

[0048] The well region 11 is provided to surround the active portion 160 and the top electrode 52. A portion of the well region 11 may overlap with the top electrode 52. The above-mentioned gate wiring is provided above the well region 11, but is omitted in FIG. 2 . The gate wiring is disposed outside the top electrode 52 in a top view. "Outside" refers to the side closer to the edge 231 of the semiconductor substrate 10. The gate wiring may be provided within a range that overlaps with the well region 11 in a top view. The well region 11 may be provided over a wider range than the gate wiring. An N-type drift region 18 may be exposed on the top surface of the semiconductor substrate 10 outside the well region 11.

[0049] The protective films 251 and 252 are disposed outside the active portion 160 in top view. A portion of the protective film 251 overlaps with the top electrode 52 in top view. In the example of FIG. 2, the inner end of the protective film 251 in the X-axis direction is disposed above the top electrode 52. The inner side refers to the side farther from the edge 231 of the semiconductor substrate 10 (i.e., the side closer to the center of the active portion 160). A portion of the protective film 252 overlaps with the top electrode 52 in top view. In the example of FIG. 2, the inner end of the protective film 252 in the Y-axis direction is disposed above the top electrode 52.

[0050] In this example, an IGBT is formed as a semiconductor element in the active portion 160. The active portion 160 in FIG. 2 includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a contact region 15, and an accumulation region 16.

[0051] The gate trench 40 and the dummy trench 30 are each an example of a trench. Each trench has a groove provided in the upper surface of the semiconductor substrate 10, a conductive portion provided inside the groove, and an insulating film that insulates the semiconductor substrate 10 from the conductive portion. A gate voltage is applied to the conductive portion of the gate trench 40, and a voltage different from the gate voltage is applied to the conductive portion of the dummy trench 30. In this example, the conductive portion of the dummy trench 30 is connected to the upper electrode 52 via a contact hole or the like provided in the interlayer insulating film.

[0052] Each trench portion is provided from the upper surface of the semiconductor substrate 10 to the interior of the semiconductor substrate 10. As shown in Fig. 2, each trench portion has a longitudinal direction extending in the Y-axis direction (first direction) on the upper surface 21 of the semiconductor substrate 10, and is arranged side by side in a second direction (X-axis direction) different from the Y-axis direction. In this example, the first direction and the second direction are perpendicular to each other, but the first direction and the second direction do not have to be perpendicular to each other.

[0053] In the X-axis direction, one or more dummy trench portions 30 are provided between two gate trench portions 40. In the example of FIG. 2, one gate trench portion 40 and two dummy trench portions 30 are repeatedly provided in the X-axis direction. In other examples, a larger number of gate trench portions 40 may be continuously arranged in the X-axis direction, or a larger number of dummy trench portions 30 may be continuously arranged in the X-axis direction. Furthermore, the active portion 160 may not be provided with a dummy trench portion 30, and only gate trench portions 40 may be arranged.

[0054] 2, the ends of two gate trenches 40 in the Y-axis direction may be connected by a curved gate trench 40. Similarly, the ends of two dummy trenches 30 in the Y-axis direction may be connected by a curved dummy trench 30. This shape can reduce electric field concentration at the ends of the trenches in the Y-axis direction. In this specification, the straight line portion extending in the Y-axis direction in each trench may be treated as a single trench.

[0055] The gate trench portion 40 is electrically connected to the gate wiring described above. The gate trench portion 40 extends into the well region 11 in the Y-axis direction. The dummy trench portion 30 may also extend into the well region 11. The end of the gate trench portion 40 is electrically connected to the gate wiring provided above the well region 11. The tip portion of the gate trench portion 40 may be connected to the gate wiring via a contact hole or the like provided in the interlayer insulating film.

[0056] The well region 11 may be formed deeper than each trench portion. With this configuration, the tip of each trench portion in the Y-axis direction is surrounded by the P+ type well region 11. This reduces electric field concentration at the tip of each trench portion, improving the breakdown voltage.

[0057] A mesa portion is provided between each trench portion in the X-axis direction. A mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between two trench portions adjacent to each other in the X-axis direction. One mesa portion is disposed between each two trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the Y-axis direction along the trench. Each mesa portion may be connected to an upper surface electrode 52 by a first contact hole 54.

[0058] Each mesa portion has a P-type base region, which is omitted in FIG. 2 . The base region has a portion that is in contact with the gate trench portion 40. When a predetermined gate voltage is applied to the gate trench portion 40, a channel is formed in the base region, and the IGBT is turned on. The base region may be provided over the entire mesa portion inside the semiconductor substrate 10. The base region may or may not be exposed on the top surface of the mesa portion.

[0059] Each mesa portion has an emitter region 12 in contact with (i.e., exposed at) the upper surface of the semiconductor substrate 10. The emitter region 12 is provided between the base region and the upper surface of the semiconductor substrate 10. At least a portion of the emitter region 12 is provided in contact with the gate trench portion 40.

[0060] Each mesa portion may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10. The contact region 15 is a P+ type region with a higher concentration than the base region. The contact region 15 is provided between the base region and the upper surface of the semiconductor substrate 10. By providing the contact region 15, the contact resistance with the upper surface electrode 52 can be reduced. The emitter region 12 and the contact region 15 are connected to the upper surface electrode 52 through a first contact hole 54.

[0061] In this example, the contact regions 15 and the emitter regions 12 in the mesa portion are provided from one trench portion to the other trench portion adjacent to each other in the X-axis direction. The contact regions 15 and the emitter regions 12 are alternately arranged along the Y-axis direction.

[0062] Of the multiple contact regions 15 discretely arranged in the Y-axis direction, the one provided at the end is referred to as contact region 15-e. Contact region 15-e may be connected to well region 11. Instead of contact region 15-e, the base region may be exposed on the upper surface of semiconductor substrate 10.

[0063] In another example, the contact region 15 and the emitter region 12 of the mesa portion may be provided in a stripe pattern along the Y-axis direction. For example, the emitter region 12 may be provided in a region in contact with each trench portion, and the contact region 15 may be provided in a region sandwiched between the emitter regions 12.

[0064] 2 shows the structure near one end of the trench portion in the Y-axis direction. A similar structure may be provided near the other end of the trench portion. For example, the other end of the gate trench portion 40 in the Y-axis direction may also extend into the well region 11 and be connected to the gate wiring.

[0065] FIG. 3 is a diagram showing an example of the X1-X1' cross section in FIG. 2. The X1-X1' cross section is an XZ plane passing through the emitter region 12 and the well region 11 near the edge 231-1. In this example, the edge 231-1 may be the first edge. In another example, the edge 231-1 may be an edge 231 other than the first edge. The well region 11 in FIG. 3 is disposed opposite the edge 231-1 and extends in the Y-axis direction. The X1-X1' cross section in FIG. 3 includes the outside of the well region 11. An edge termination structure such as a P-type guard ring may be provided outside the well region 11, but is omitted in FIG. 3.

[0066] In each cross-sectional view of this specification, an arrow may be used to indicate the direction in which one of the edges 231 of the semiconductor substrate 10 is disposed. In Figure 3, the arrow indicates the direction of edge 231-1. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, a first gate wiring 50, a second gate wiring 51, an upper electrode 52, a plating layer 210, a protective film 251, and a collector electrode 24.

[0067] The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The interlayer insulating film 38 is provided between the upper surface of the semiconductor substrate 10 and the upper surface electrode 52. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. A first contact hole 54 and a second contact hole 55 are provided in the interlayer insulating film 38 in this cross section.

[0068] The upper electrode 52 is provided above the interlayer insulating film 38. The upper electrode 52 passes through a first contact hole 54 in the interlayer insulating film 38 and is connected to the upper surface 21 of the semiconductor substrate 10.

[0069] The first gate wiring 50 is provided above the interlayer insulating film 38, and the second gate wiring 51 is provided between the first gate wiring 50 and the semiconductor substrate 10. The interlayer insulating film 38 or another insulating film is provided between the second gate wiring 51 and the semiconductor substrate 10. The interlayer insulating film 38 is provided between the first gate wiring 50 and the second gate wiring 51. The first gate wiring 50 and the second gate wiring 51 are electrically connected by a second contact hole 55. The first gate wiring 50 is a metal wiring made of, for example, aluminum. The second gate wiring 51 is a wiring made of, for example, polysilicon. The first gate wiring 50, the second gate wiring 51, and the second contact hole 55 may be provided to surround the active portion 160 in a top view. The second gate wiring 51 is connected to a gate conductive portion 44 (described later) near the end of the gate trench portion 40.

[0070] Collector electrode 24 is provided on lower surface 23 of semiconductor substrate 10. Top electrode 52 and collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting top electrode 52 and collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0071] The semiconductor substrate 10 has an N- type drift region 18. The drift region 18 may be provided over the entire semiconductor substrate 10 in a top view. The well region 11 surrounds the top electrode 52 in a top view. The well region 11 is a P+ type region exposed on the top surface 21 of the semiconductor substrate 10. The well region 11 may be formed deeper than the gate trench portion 40 and the dummy trench portion 30.

[0072] An end of the upper electrode 52 may overlap the well region 11 in a top view. The first gate wiring 50 and the second gate wiring 51 overlap the well region 11 in a top view. The entire first gate wiring 50 and the entire second gate wiring 51 may overlap the well region 11 in a top view.

[0073] The protective film 251 is provided on the interlayer insulating film 38. At least a portion of the protective film 251 is provided so as to cover the upper surface 53 of the upper electrode 52. In this example, the protective film 251 also covers the entire first gate wiring 50. The protective film 251 may be provided continuously from the upper electrode 52 to the edge of the semiconductor substrate 10 (edge 231-1 in this example). A portion of the protective film 251 may be in contact with the interlayer insulating film 38.

[0074] The plating layer 210 is provided on the upper surface 53 of the upper electrode 52. The plating layer 210 is provided on an area of the upper surface 53 of the upper electrode 52 that is not covered with the protective film 251. The plating layer 210 may contain at least one of nickel and copper. The plating layer 210 may be nickel plated or copper plated. The plating layer 210 may be in contact with the protective film 251 or may be separated from it.

[0075] Wiring such as a linear wire or a plate-like lead frame that connects an external circuit to the semiconductor device 100 may be connected to the plating layer 210. The wiring may be soldered to the plating layer 210 or may be crimped.

[0076] A plurality of trench portions are provided in the upper surface 21 of the semiconductor substrate 10. Details of each trench portion will be described later. Each trench portion is formed to a predetermined depth from the upper surface 21 of the semiconductor substrate 10. In the cross section of FIG. 3, a plurality of trench portions are arranged at predetermined intervals in the X-axis direction. At least some of the trench portions are provided below the upper surface electrode 52. Some of the trench portions may be located outside the upper surface electrode 52. Some of the trench portions may be located inside the well region 11.

[0077] A P-type base region 14 is provided in each mesa portion sandwiched between two trench portions in the X-axis direction. The base region 14 may contact the trench portions on both sides of the mesa portion. In this specification, the region sandwiched between two trench portions that is not disposed in the well region 11 is referred to as a mesa portion. A drift region 18 is provided below the base region 14.

[0078] At least some of the mesa portions are provided with N+ type emitter regions 12. Some of the mesa portions may be provided with P+ type contact regions 15 instead of the emitter regions 12. In the examples of FIGS. 2 and 3, one or more mesa portions closest to the well region 11 are not provided with emitter regions 12 but with contact regions 15-e. By arranging the contact regions 15-e in the mesa portions, holes can be more easily extracted to the top electrode 52 via the mesa portions.

[0079] The emitter region 12 and the contact region 15 are exposed at the top surface 21 of the semiconductor substrate 10. The emitter region 12 has a higher doping concentration than the drift region 18. The contact region 15 has a higher doping concentration than the base region 14.

[0080] The emitter region 12 and the contact region 15 are disposed between the base region 14 and the upper surface 21 of the semiconductor substrate 10. At least a portion of the emitter region 12 is provided in contact with the gate trench portion 40.

[0081] When a predetermined on-voltage is applied to the gate conductive portion 44 of the gate trench portion 40, the surface layer of the base region 14 in contact with the gate trench portion 40 is inverted to N-type, forming a channel layer. This brings the emitter region 12 and the drift region 18 into conduction, turning the transistor on.

[0082] An N-type accumulation region 16 may be provided in at least some of the mesa portions. The accumulation region 16 is disposed between the base region 14 and the drift region 18. The accumulation region 16 is an N-type region having a higher doping concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced, thereby reducing the on-voltage. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion.

[0083] An N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower end of the base region 14 from reaching the P+ type collector region 22. If a MOSFET is provided in the semiconductor substrate 10, the buffer region 20 may not be provided.

[0084] In the semiconductor substrate 10, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 is connected to a collector electrode 24. The collector electrode 24 is formed of a metal material such as aluminum. If a MOSFET is provided in the semiconductor substrate 10, an N+ type drain region is provided instead of the collector region 22. If a diode is provided in the semiconductor substrate 10, a P-type anode region is provided instead of the emitter region 12, and an N+ type cathode region is provided instead of the collector region 22.

[0085] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the top surface 21 of the semiconductor substrate 10. In each drawing, the gate trenches 40 may be labeled G, and the dummy trenches 30 may be labeled E. Each trench extends from the top surface 21 of the semiconductor substrate 10, penetrating the base region 14, and below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed after the doped regions are formed. The trenches penetrating the doped regions also include trenches formed after the trenches are formed.

[0086] The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of a trench that extends from the upper surface 21 of the semiconductor substrate 10 to the inside of the semiconductor substrate 10. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor substrate 10 that is exposed to the inner wall of the trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0087] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to a second gate wiring 51. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0088] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy insulating film 32 and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the top electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the trench. The dummy conductive portion 34 is provided inside the trench and is provided more inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0089] In this example, the first contact hole 54 refers to a contact hole provided in the interlayer insulating film 38 that connects the top electrode 52 to the well region 11 or the active portion 160. As shown in FIG. 3 and other figures, a plurality of first contact holes 54 may be provided in the interlayer insulating film 38. The first contact hole 54 may refer to a contact hole that connects the top electrode 52 to the top surface 21 of the semiconductor substrate 10, located inside the first gate wiring 50 or the second gate wiring 51. The first contact hole 54 may refer to a contact hole that connects the top electrode 52 to the top surface 21 of the semiconductor substrate 10, located inside the center 111 of the well region 11 in a direction from the end of the active portion 160 toward the closest edge 231 (the X-axis direction in FIG. 3). Of the contact holes provided in the interlayer insulating film 38, those that are outside the well region 11 and contact the top surface 21 of the semiconductor substrate 10 may be excluded from the first contact hole 54.

[0090] 3, the first contact hole 54 has at least one of a well hole end 201 and an active hole end 211. The well hole end 201 electrically connects the top surface electrode 52 and the well region 11. The well hole end 201 is the portion of the first contact hole 54 arranged to overlap the well region 11 that is closest to the end side 231-1 in the X-axis direction.

[0091] The active hole end 211 electrically connects the upper surface electrode 52 and the active portion 160. The active hole end 211 is the portion of the first contact hole 54 arranged to overlap the active portion 160 that is closest to the end side 231-1 in the X-axis direction.

[0092] The well hole end 201 and the active hole end 211 may be portions of the first contact hole 54 that contact the upper surface 21 of the semiconductor substrate 10. In the example of Fig. 3, the well hole end 201 is a portion where the side surface of the interlayer insulating film 38 contacts the well region 11, and in the example of Fig. 3, the active hole end 211 is a boundary portion between the well region 11 and the active portion 160 that is exposed by the first contact hole 54.

[0093] The first contact hole 54 has a first outer hole end closest to the first edge of the semiconductor substrate 10. When the edge 231-1 is the first edge, the portion of the first contact hole 54 closest to the edge 231-1 in the X-axis direction is defined as the first outer hole end. When the edge 231-1 is the first edge, the well hole end 201 shown in FIG. 3 is an example of a first outer hole end. When the well hole end 201 is not provided, the active hole end 211 functions as the first outer hole end. A first outer hole end is provided for each of the two edge sides 231-1 and 231-3 of the semiconductor substrate 10. When the edge 231-1 is the second edge, the portion of the first contact hole 54 closest to the edge 231-1 in the X-axis direction is defined as the second outer hole end. Similarly, when the edge 231-1 is the third edge, the portion of the first contact hole 54 closest to the edge 231-1 in the X-axis direction is defined as the third outer hole end.

[0094] A plating layer 210 is formed on the upper surface 53 of the upper electrode 52 that overlaps the end of the first outer hole in top view. A plating layer 210 may also be formed on the upper surface 53 of the upper electrode 52 that overlaps the end of the second outer hole and the upper surface 53 of the upper electrode 52 that overlaps the end of the third outer hole. Furthermore, at each edge 231 of the semiconductor substrate 10, the portion of the first contact hole 54 closest to the edge 231 is defined as the outer hole end. At all outer hole ends, a plating layer 210 may be formed on the upper surface 53 of the upper electrode 52 that overlaps the outer hole end. In this example, a plating layer 210 is formed on the upper surface 53 of the upper electrode 52 that overlaps the outer hole end for each of the edges 231-1, 231-2, 231-3, and 231-4.

[0095] In this example, a plating layer 210 is formed on the upper surface 53 of the upper electrode 52 that overlaps the well hole end 201. A plating layer 210 may also be formed on the upper surface 53 of the upper electrode 52 that overlaps the active hole end 211. The plating layer 210 may be formed continuously from above the well hole end 201 to above the active hole end 211.

[0096] By forming the plating layer 210 on the top electrode 52 that overlaps the end of the first outer hole, stress generation in the top electrode 52 can be suppressed. During actual use, the top electrode 52 may be subjected to repeated temperature changes, generating stress. In this case, stress migration may occur in the top electrode 52. Stress migration is particularly likely to occur when the top electrode 52 contains aluminum. When stress migration occurs, the movement of holes in the XY plane of the top electrode 52 is suppressed. Note that when the semiconductor substrate 10 is a silicon carbide substrate, it is often used in an environment with large temperature fluctuations, which increases the stress generated in the top electrode 52. Furthermore, when the semiconductor device 100 is mounted in a semiconductor module equipped with a water-cooling device, it is often used in an environment with large temperature fluctuations.

[0097] In contrast, by providing the plating layer 210 above the end of the first outer hole, deformation of the top electrode 52 near the end of the first outer hole can be suppressed, and stress generation can be suppressed, compared to when the protective film 251 is provided so as to overlap the end of the first outer hole. The plating layer 210 may be provided continuously from the end of the first outer hole to the center of the semiconductor substrate 10 in a top view. The top surface 53 of the top electrode 52 may not be provided with a protective film on the inside of the end of the first outer hole. In another example, the top surface 53 of the top electrode 52 may be provided with a protective film on the inside of the end of the first outer hole.

[0098] In this example, holes that reach the end of the first outer hole from the semiconductor substrate 10 can move in the Z-axis direction from the top electrode 52 to the plating layer 210. Holes that reach the top electrode 52 from the end of the first outer hole hardly move in the X-axis direction within the top electrode 52. For this reason, even if stress migration or the like occurs in the top electrode 52, the movement of holes from the top electrode 52 to the plating layer 210 is hardly suppressed.

[0099] The entire protective film 251 in this example is provided between the first outer hole end and the first edge (edge 231-1 in the example of FIG. 3) in top view. The protective film 251 is an example of an outer protective portion. The protective film 251 has an inner protective edge 261. The inner protective edge 261 is the portion of the protective film 251 that is closest to the first contact hole 54. The inner protective edge 261 may be the portion of the side surface of the protective film 251 that contacts the top surface 53 of the top electrode 52. The inner protective edge 261 is provided between the well hole end 201 and edge 231-1 in top view.

[0100] The position of the well hole end 201 in the X-axis direction is Px1, and the position of the inner protection end 261 in the X-axis direction is Px2. If the well hole end 201 is not provided, the position of the active hole end 211 in the X-axis direction is Px1. The position of the part of the accumulation region 16 closest to the edge 231-1 in the X-axis direction is Px3. The position of the part of the well region 11 closest to the edge 231-1 in the X-axis direction is Px4. The position of the part of the emitter region 12 closest to the edge 231-1 in the X-axis direction is Px5.

[0101] Position Px1 is located more inward than position Px2 (i.e., closer to the center of the active portion 160). Position Px1 and position Px2 may both be located more inward than the center 111 of the well region 11. Position Px1 and position Px2 may both be located so as to overlap with the well region 11. That is, position Px1 and position Px2 may be located between the center 111 and position Px4. In another example, position Px2 may overlap with the well region 11, and position Px1 may be located more inward than position Px4. Furthermore, position Px1 and position Px2 may both be located more inward than position Px4.

[0102] In another example, position Px2 may be located outside the center 111 of the well region 11, and position Px1 may be located inside the center 111. In this case, position Px2 may also overlap with the well region 11. Position Px1 may be located outside or inside position Px4.

[0103] Positions Px1 and Px2 may both be located outside position Px3. That is, in the X-axis direction, the outer hole end and inner protection end 261 may be provided between the accumulation region 16 and the end side 231-1. Furthermore, positions Px1 and Px2 may both be located outside position Px5.

[0104] The distance in the X-axis direction between positions Px1 and Px2 may be smaller than the width of well region 11 in the X-axis direction. By reducing the distance between positions Px1 and Px2, a wider range can be protected by protective film 251. The distance between positions Px1 and Px2 may be equal to or smaller than half the width of well region 11, may be equal to or smaller than 10 μm, or may be equal to or smaller than 5 μm. The distance may be 0 μm or may be greater than 0 μm.

[0105] Position Px2 may be located outside the trench portion closest to end side 231-1 among the multiple trench portions. As shown in Fig. 3, position Px2 may overlap with the trench portion closest to end side 231-1. Position Px2 may be located inside the trench portion closest to end side 231-1.

[0106] The first contact hole 54 has an active hole end 211 that is closest to the first edge (edge 231-1 in this example) among the portions that connect the active portion 160 and the upper surface electrode 52. In this example, the position of the active hole end 211 in the X-axis direction coincides with a position Px4 of the edge of the well region 11. In another example, the active hole end 211 may be located inside the position Px4.

[0107] In the X-axis direction, the inner protective edge 261 may be provided between the contact region 15 and the end side 231-1. In the example of Fig. 3, the position Px4 is the outer end of the contact region 15. The inner protective edge 261 may be disposed between the position Px4 and the end side 231-1.

[0108] In top view, a plating layer 210 is provided on the upper surface 53 of the upper electrode 52 that overlaps with the active hole end 211. Since a relatively large number of holes exist in the active portion 160, a relatively large number of holes reach the active hole end 211. By providing the plating layer 210 above the active hole end 211, stress in the portion of the upper electrode 52 through which a relatively large number of holes flow can be suppressed.

[0109] 3, the active hole end 211 may be located more inward than the well hole end 201. In another example, the first contact hole 54 may not be provided at the position overlapping with the well region 11, and the well hole end 201 may not be provided.

[0110] The plating layer 210 may be provided continuously in the X-axis direction from the active hole end 211 to a position inside of position Px3. The plating layer 210 may be provided continuously in the X-axis direction from the active hole end 211 to a position inside of position Px5. The plating layer 210 may be provided continuously in the X-axis direction from the active hole end 211 to the center of the active portion 160.

[0111] FIG. 4 is a diagram showing an example of the Y1-Y1' cross section in FIG. 2. The Y1-Y1' cross section is a YZ plane passing through the first contact hole 54 and the well region 11 in the vicinity of the edge 231-2. In this example, the edge 231-2 may be the first edge. In this case, the edge 231-1 is the second edge or the third edge. When the edge 231-1 is the second edge or the third edge, a plating layer 210 may be provided above the well hole edge 201 shown in FIG. 3, or a protective film 251 may be provided. Furthermore, a plating layer 210 may be provided above the active hole edge 211, or a protective film 251 may be provided.

[0112] Well region 11 in Fig. 4 is disposed opposite edge 231-2 and extends in the X-axis direction. The Y1-Y1' cross section in Fig. 4 includes the outside of well region 11. An edge termination structure such as a guard ring may be provided outside well region 11, but is omitted in Fig. 4.

[0113] 4, the direction of edge 231-2 is indicated by an arrow. In the cross section, semiconductor device 100 of this example has semiconductor substrate 10, interlayer insulating film 38, first gate wiring 50, second gate wiring 51, upper surface electrode 52, pad electrode 280, pad 57-5, plating layer 210, protective film 251, protective film 252, and collector electrode 24. Of the components shown in FIG. 4, components with the same reference numerals as those in FIG. 3 have the same structure and function as those in FIG. 3.

[0114] In this example, the end of the top surface electrode 52 in the Y-axis direction may overlap the well region 11 in a top view. In this example, a pad 57-5 is provided outside the first gate wiring 50 and the second gate wiring 51. The pad 57-5 may be connected to a temperature detection diode or the like. The pad 57-5 is provided above the interlayer insulating film 38. In this example, the pad 57-5 has a pad electrode 280 and a plating layer 210. The pad electrode 280 may be formed of the same material as the top surface electrode 52. The pad electrode 280 is provided separately from the top surface electrode 52. The plating layer 210 is formed on the top surface of the pad electrode 280. Wiring such as a wire may be connected to the top surface of the plating layer 210.

[0115] The protective film 251 and the protective film 252 are provided on the interlayer insulating film 38. The protective film 251 is provided so as to cover a part of the upper surface of the pad electrode 280. The protective film 251 may be provided continuously from the pad electrode 280 to the edge of the semiconductor substrate 10 (edge 231-2 in this example). A part of the protective film 251 may be in contact with the interlayer insulating film 38.

[0116] The protective film 252 is provided so as to cover a portion of the upper surface of the pad electrode 280. The plating layer 210 is provided in a region of the upper surface of the pad electrode 280 that is not covered by the protective film 251 and the protective film 252. In another example, the plating layer 210 may not be provided on the pad 57-5. The protective film 252 is provided so as to cover a portion of the upper surface of the upper electrode 52. The protective film 252 also covers the entire first gate wiring 50. The protective film 252 may be in contact with the interlayer insulating film 38 between the pad electrode 280 and the first gate wiring 50, and between the first gate wiring 50 and the upper electrode 52.

[0117] The first contact holes 54 provided in the active portion 160 are provided so as to extend in the Y-axis direction. The emitter regions 12 and the contact regions 15 are alternately arranged along the Y-axis direction. The first contact holes 54 in this example expose the emitter regions 12 and the contact regions 15.

[0118] The first contact hole 54 may also be provided at a position overlapping the well region 11. An interlayer insulating film 38 may be provided between the first contact hole 54 in the active portion 160 and the first contact hole 54 in the well region 11.

[0119] 4, the first contact hole 54 has at least one of a well hole end 202 and an active hole end 222. The well hole end 202 electrically connects the upper surface electrode 52 and the well region 11. The well hole end 202 is the portion of the first contact hole 54 arranged to overlap the well region 11 that is closest to the end side 231-2 in the Y-axis direction.

[0120] The active hole end 222 electrically connects the upper surface electrode 52 and the active portion 160. The active hole end 222 is the portion of the first contact hole 54 arranged to overlap the active portion 160 that is closest to the end side 231-2 in the Y-axis direction.

[0121] The well hole end 202 and the active hole end 222 may be portions of the first contact hole 54 that contact the upper surface 21 of the semiconductor substrate 10. In the example of Fig. 4, the well hole end 202 is a portion where the side surface of the interlayer insulating film 38 contacts the well region 11, and in the example of Fig. 4, the active hole end 222 is a portion where the side surface of the interlayer insulating film 38 contacts the contact region 15 or the emitter region 12.

[0122] The first contact hole 54 has a first outer hole end closest to the first edge of the semiconductor substrate 10. When the edge 231-2 is the first edge, the portion of the first contact hole 54 closest to the edge 231-2 in the Y-axis direction is defined as the first outer hole end. When the edge 231-2 is the first edge, the well hole end 202 shown in FIG. 4 is an example of a first outer hole end. When the well hole end 202 is not provided, the active hole end 222 functions as the first outer hole end. When the edge 231-2 is the second edge, the portion of the first contact hole 54 closest to the edge 231-2 in the Y-axis direction is defined as the second outer hole end. Similarly, when the edge 231-2 is the third edge, the portion of the first contact hole 54 closest to the edge 231-2 in the Y-axis direction is defined as the third outer hole end.

[0123] In this example, a plating layer 210 is formed on the upper surface 53 of the upper electrode 52 that overlaps the well hole end 202. A plating layer 210 may also be formed on the upper surface 53 of the upper electrode 52 that overlaps the active hole end 222. The plating layer 210 may be formed continuously from above the well hole end 202 to above the active hole end 222.

[0124] In this example, deformation of the top electrode 52 near the end of the first outer hole can be suppressed, thereby suppressing stress generation. Even if stress migration or the like occurs in the top electrode 52, the movement of holes in the top electrode 52 is hardly suppressed.

[0125] In this example, the protective films 251 and 252 are entirely provided between the first outer hole end and the first edge (edge 231-2 in the example of FIG. 4) in top view. The protective films 251 and 252 are an example of an outer protective portion. The protective film 252 has an inner protective edge 262. The inner protective edge 262 is the portion of the protective film 252 that is closest to the first contact hole 54. The inner protective edge 262 may be the portion where the side surface of the protective film 252 contacts the top surface 53 of the top electrode 52. The inner protective edge 262 is provided between the well hole end 202 and edge 231-2 in top view.

[0126] The position of the well hole end 202 in the Y-axis direction is Py1, and the position of the inner protection end 262 in the Y-axis direction is Py2. If the well hole end 202 is not provided, the position of the active hole end 222 in the Y-axis direction is Py1. The position of the accumulation region 16 closest to the edge 231-2 in the Y-axis direction is Py3. The position of the well region 11 closest to the edge 231-2 in the Y-axis direction is Py4. The position of the emitter region 12 closest to the edge 231-2 in the Y-axis direction is Py5.

[0127] Position Py1 is located more inward than position Py2 (i.e., closer to the center of the active portion 160). Position Py1 and position Py2 may both be located more inward than the center 111 of the well region 11. Position Py1 and position Py2 may both be located so as to overlap with the well region 11. That is, position Py1 and position Py2 may be located between the center 111 and position Py4. In another example, position Py2 may overlap with the well region 11, and position Py1 may be located more inward than position Py4. Furthermore, position Py1 and position Py2 may both be located more inward than position Py4.

[0128] In another example, position Py2 may be located outside the center 111 of the well region 11, and position Py1 may be located inside the center 111. In this case, position Py2 may also overlap with the well region 11. Position Py1 may be located outside or inside position Py4.

[0129] Both positions Py1 and Py2 may be located outside position Py3. That is, in the Y-axis direction, the inner protective edge 262 may be provided between the accumulation region 16 and the end edge 231-2. Furthermore, both positions Py1 and Py2 may be located outside position Py5.

[0130] The distance in the X-axis direction between positions Py1 and Py2 may be smaller than the width of well region 11 in the X-axis direction. By reducing the distance between positions Py1 and Py2, a wider range can be protected by protective film 252. The distance between positions Py1 and Py2 may be equal to or smaller than half the width of well region 11, may be equal to or smaller than 10 μm, or may be equal to or smaller than 5 μm. The distance may be 0 μm or may be greater than 0 μm.

[0131] In this example, the position of the active hole end 222 in the Y-axis direction is located inside the position Py4 of the end of the well region 11. In another example, the active hole end 222 may coincide with the position Py4.

[0132] In top view, a plating layer 210 is provided on the upper surface 53 of the upper electrode 52 that overlaps with the active hole end 222. Since a relatively large number of holes exist in the active portion 160, a relatively large number of holes reach the active hole end 222. By providing the plating layer 210 above the active hole end 222, stress in the portion of the upper electrode 52 through which a relatively large number of holes flow can be suppressed.

[0133] The plating layer 210 may be provided continuously in the Y-axis direction from the active hole end 222 to a position inside of position Py3. The plating layer 210 may be provided continuously in the Y-axis direction from the active hole end 222 to a position inside of position Py5. The plating layer 210 may be provided continuously in the Y-axis direction from the active hole end 222 to the center of the active portion 160.

[0134] FIG. 5 is a diagram showing an example of the Y2-Y2' cross section. As shown in FIG. 1, the Y2-Y2' cross section is a YZ plane passing through the pad 57-1 in the vicinity of the edge 231-2. Except for structures that will be particularly described, the structure in the Y2-Y2' cross section may be the same as the structure in the Y1-Y1' cross section. In the Y2-Y2' cross section of this example, the first gate wiring 50 and the second gate wiring 51 are not provided. The first gate wiring 50 and the second gate wiring 51 may be provided closer to the edge 231-2 than the pad 57-1.

[0135] The pad 57-1 is a pad at the same potential as the upper electrode 52. The pad 57-1 is also called a Kelvin emitter pad. By detecting the potential at the pad 57-1, the potential of the upper electrode 52 can be detected. A wiring such as a wire may be connected to the pad 57-1.

[0136] A well region 11 is provided below the pad 57-1. The width of the well region 11 in the Y-axis direction may be larger than or the same as that of the well region 11 shown in the Y1-Y1' cross section.

[0137] In this example, the top electrode 52 extends to the area of the pad 57-1. The pad 57-1 in this example has the top electrode 52 and a plating layer 210. The plating layer 210 in the active portion 160 and the plating layer 210 of the pad 57-1 may be separated by a protective film 252. In another example, the protective film 252 may not be provided, and the plating layer 210 in the active portion 160 and the plating layer 210 of the pad 57-1 may be provided continuously.

[0138] In this example, the top electrode 52 extends in the Y-axis direction to the outside of the well region 11 in top view. In another example, the top electrode 52 may terminate above the well region 11 in the Y-axis direction. As shown in FIG. 3 , the top electrode 52 may have an outer connection portion 204 that contacts the semiconductor substrate 10 outside the well region 11. As described above, the portion that contacts the semiconductor substrate 10 outside the well region 11 is excluded from the first contact hole 54.

[0139] The protective film 251 is provided so as to cover a portion of the upper surface 53 of the upper electrode 52. The protective film 251 may be provided continuously from the upper electrode 52 to an edge (edge 231-2 in this example) of the semiconductor substrate 10. Outside the upper electrode 52, an insulating film 270 such as an oxide film may be provided between the protective film 251 and the semiconductor substrate 10, and an interlayer insulating film 38 may also be provided.

[0140] The protective film 252 is provided on the upper surface 53 of the upper electrode 52. The protective film 252 may be in contact with the upper surface 53 of the upper electrode 52 over the entire length in the Y-axis direction. By providing the protective film 252, the plating layer 210 in the active portion 160 can be separated from the plating layer 210 in the pad 57-1. Using the protective film 252 as a reference position makes it easier to control the connection position of wiring such as a wire to the pad 57-1. At least a portion of the protective film 252 may be disposed above the well region 11. At least a portion of the protective film 252 may be provided on the active portion 160.

[0141] The first contact hole 54 in this example is not provided in a position overlapping with the well region 11. The first contact hole 54 in this example has an active hole end 222, but does not have a well hole end 202. However, even in this example, the first contact hole 54 may have the well hole end 202.

[0142] In this example, the active hole end 222 functions as the first outer hole end. In this example as well, a plating layer 210 is formed on the upper surface 53 of the upper surface electrode 52 that overlaps with the active hole end 222. The plating layer 210 may be provided continuously in the Y-axis direction from the active hole end 222 to a position inside of position Py5. The plating layer 210 may be provided continuously in the Y-axis direction from the active hole end 222 to the center of the active portion 160.

[0143] Position Py1 of the active hole end 222 is located more inward than position Py2 of the inner protection end 262. Position Py1 may be located more outward than or more inward than position Py3 of the outer end of the accumulation region 16. In the example of FIG. 5, position Py1 is located between positions Py3 and Py5. In other examples, position Py1 may be located more inward than position Py5.

[0144] Position Py2 is located outside position Py1. Position Py2 may be located inside position Py4. Position Py2 may be located between positions Py3 and Py4. In another example, position Py2 may be located outside position Py4. Position Py2 may be located inside center 111 of well region 11.

[0145] In this example, deformation of the top electrode 52 near the end of the first outer hole can be suppressed, thereby suppressing stress generation. Even if stress migration or the like occurs in the top electrode 52, the movement of holes in the top electrode 52 is hardly suppressed.

[0146] 6 is a diagram showing another example of the Y2-Y2' cross section. The semiconductor device 100 of this example further includes a protective film 255 in addition to the configurations described herein. The protective film 255 is disposed farther from the edge 231-2 than the outer protective portions (protective films 251 and 252 in this example) in top view, and is disposed so as to overlap the first contact hole 54. The protective film 255 is an example of an inner protective portion.

[0147] A plating layer 210 is provided between protective film 255 and protective film 252. Protective film 255 may be disposed between protective film 253 and protective film 255 shown in FIG. 1. Protective film 255 may extend in the X-axis direction and be connected to protective film 251, or may be separated from protective film 251 in the X-axis direction. The width of protective film 255 in the Y-axis direction may be smaller than the width of protective film 252 in the Y-axis direction, and may be smaller than the width of protective film 251 in the Y-axis direction.

[0148] Wires or other wiring may be soldered to the plating layer 210 of the active portion 160 on the inner side of the protective film 255. Providing the protective film 255 can prevent the solder from flowing beyond the protective film 255. This can prevent the solder in the active portion 160 from scattering to other pads 57. The protective film 255 may also be provided on the Y1-Y1' cross section shown in FIG. 4. The protective film 255 may be provided between the protective film 252 and the protective film 253 shown in FIG. 1, extending in the X-axis direction so as to connect the protective film 251 and the protective film 254.

[0149] 7 is a diagram illustrating a path of a hole current from the outer hole end 281 in the comparative example. As described above, the outer hole end 281 is either the well hole end 202 or the active hole end 222. In the comparative example, a protective film 251 is provided on the upper surface 53 of the upper electrode 52 at the position Py1 of the outer hole end 281. The protective film 251 extends in the Y-axis direction to a position inside the outer hole end 281.

[0150] In this example, the hole current from the outer hole end 281 flows along the Y-axis direction inside the top electrode 52 and reaches the plating layer 210. If a crack or the like occurs in the top electrode 52, the resistance value to the hole current flowing in the Y-axis direction increases, making it difficult for the hole current from the outer hole end 281 to flow.

[0151] 8 is a diagram illustrating the path of a hole current from the outer hole end 281 in the example. In the example, as described with reference to FIGS. 1 to 6, a plating layer 210 is provided on the upper surface 53 of the upper electrode 52 at the position Py1 of the outer hole end 281. The protective film 251 is provided outside the outer hole end 281.

[0152] In this example, the plating layer 210 is also provided above the outer hole end 281, and the area covered by the plating layer 210 is larger than in the example of FIG. 7. This suppresses stress generation in the top electrode 52, and makes it possible to suppress the occurrence of cracks and the like in the top electrode 52. Furthermore, in this example, the hole current from the outer hole end 281 flows to the plating layer 210 directly above it. Therefore, even if a crack or the like occurs in the top electrode 52, the hole current from the outer hole end 281 can flow to the plating layer 210 without being obstructed.

[0153] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0154] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0155] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 30 dummy trench portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 42 gate insulating film, 44 gate conductive portion, 50 first gate wiring, 51 second gate 1. A semiconductor device including: a contact wiring, 52; an upper surface electrode, 53; an upper surface, 54; a first contact hole, 55; a second contact hole, 57; a pad, 100; a semiconductor device, 111; a center, 160; an active portion, 201, 202; an edge of a well hole, 204; an outer connection portion, 210; a plating layer, 211, 222; an edge of an active hole, 231; an edge, 251, 252, 253, 254, 255; a protective film, 261, 262; an inner protective edge, 270; an insulating film, 280; a pad electrode, 281; an outer hole edge

Claims

1. a semiconductor substrate having an upper surface and a lower surface; a top electrode comprising aluminum; an interlayer insulating film provided between the upper surface of the semiconductor substrate and the upper surface electrode, the interlayer insulating film having a first contact hole connecting the semiconductor substrate and the upper surface electrode; a protective film provided on the upper surface of the upper electrode; a plating layer provided on an area of the upper surface of the upper electrode that is not covered with the protective film; Equipped with the semiconductor substrate has a first edge in a top view; the first contact hole has a first outer hole end closest to the first edge; The plating layer is formed on a portion of the upper electrode that overlaps with an end of the first outer hole. Semiconductor device.

2. The protective film has an outer protective portion provided between the first outer hole end and the first edge in a top view. The semiconductor device according to claim 1 .

3. An inner protection end of the outer protection portion closest to the first contact hole is provided between the first outer hole end and the first edge. The semiconductor device according to claim 2 .

4. The protective film further includes an inner protective portion that is disposed farther from the first edge than the outer protective portion in a top view and that is disposed so as to overlap the first contact hole. The semiconductor device according to claim 3 .

5. the semiconductor substrate has an active portion in which a semiconductor element is formed, the first contact hole has an end portion of the first contact hole that connects the active portion and the upper surface electrode and is closest to the first edge; The plating layer is formed on a portion of the upper electrode that overlaps an end of the active hole. The semiconductor device according to claim 1 .

6. The semiconductor substrate is a drift region of a first conductivity type provided in the active portion; a second conductivity type well region provided to surround the active portion when viewed from above; and the first contact hole has a well hole end portion that is closest to the first edge of a portion that connects the well region and the upper surface electrode; The plating layer is formed on a portion of the upper electrode that overlaps an end of the well hole. The semiconductor device according to claim 5 .

7. the semiconductor substrate has a trench portion provided from the upper surface to an interior of the semiconductor substrate and having a longitudinal direction in a first direction on the upper surface; The first outer hole end is an end of the first contact hole in the first direction. The semiconductor device according to claim 1 .

8. the semiconductor substrate has a trench portion provided from the upper surface to an interior of the semiconductor substrate and having a longitudinal direction in a first direction on the upper surface; The outer protective portion is provided between the first outer hole end and the first end side in the first direction. The semiconductor device according to claim 2 .

9. The semiconductor substrate is an active portion in which a semiconductor element is formed; a trench portion provided from the upper surface to the interior of the semiconductor substrate and having a longitudinal direction in a first direction on the upper surface; a drift region of a first conductivity type provided in the active portion; a second conductivity type base region provided between the drift region and the upper surface and in contact with the trench portion; an accumulation region of a first conductivity type provided between the drift region and the base region and having a higher concentration than the drift region; and In the first direction, the inner protective edge is provided between the accumulation area and the first end side. The semiconductor device according to claim 3 .

10. the semiconductor substrate has a plurality of trench portions aligned in a second direction on the upper surface; Each of the plurality of trench portions is provided from the upper surface to the interior of the semiconductor substrate, and has a longitudinal direction in a first direction on the upper surface, The first outer hole end is an end of the first contact hole in the second direction. The semiconductor device according to claim 1 .

11. The semiconductor substrate is an active portion in which a semiconductor element is formed; a plurality of trench portions arranged in a second direction on the upper surface; a drift region of a first conductivity type provided in the active portion; a base region of a second conductivity type provided between the drift region and the upper surface; an accumulation region of a first conductivity type provided between the drift region and the base region and having a higher concentration than the drift region; and Each of the plurality of trench portions is provided from the upper surface to the interior of the semiconductor substrate, and has a longitudinal direction in a first direction on the upper surface, In the second direction, the inner protective edge is provided between the accumulation area and the first end side. The semiconductor device according to claim 3 .

12. The semiconductor substrate is an active portion in which a semiconductor element is formed; a plurality of trench portions arranged in a second direction on the upper surface; a drift region of a first conductivity type provided in the active portion; a second conductivity type base region provided between the drift region and the upper surface and in contact with the trench portion; a contact region of a second conductivity type that is provided between the upper surface and the base region, is connected to the upper surface electrode, and has a higher concentration than the base region; and Each of the plurality of trench portions is provided from the upper surface to the interior of the semiconductor substrate, and has a longitudinal direction in a first direction on the upper surface, In the second direction, the inner protective edge is provided between the contact region and the first end side. The semiconductor device according to claim 3 .

13. the semiconductor substrate further has a second end side and a third end side in a top view, the first contact hole has a second outer hole end closest to the second edge and a third outer hole end closest to the third edge; The plating layer is formed on a portion of the upper surface electrode overlapping the end of the second outer hole and a portion of the upper surface electrode overlapping the end of the third outer hole. The semiconductor device according to claim 1 .

14. The plating layer contains at least one of nickel and copper. The semiconductor device according to claim 1 .

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