Semiconductor light emitting element epitaxial wafer

Abstract

To provide a semiconductor light emitting element epitaxial wafer capable of preventing a crystal from being damaged.SOLUTION: A semiconductor light emitting element epitaxial wafer 1 includes a sapphire substrate 10 and a semiconductor crystal layer 30 laminated on the sapphire substrate 10. A void Vo is formed in the semiconductor crystal layer 30; and the sectional shape of the void Vo in the lamination direction L has a first side S1 extending in the outer direction upward from one end of a bottom Bo and a second side S2 extending in the inner direction upward from the upper end of the first side S1.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an epitaxial wafer for a semiconductor light emitting device. [Background technology]

[0002] Non-Patent Document 1 discloses a method of fabricating a structure in which a nitride semiconductor crystal is peeled off from a sapphire substrate using a laser (laser lift-off (LLO) technology), electrodes are provided on the front and back surfaces of the peeled nitride semiconductor crystal, and a current is passed through the crystal in the thickness direction (i.e., vertical direction). [Prior art documents] [Patent documents]

[0003] [Non-Patent Document 1] Michael K. Kelly Michael K. Kelly et al"Large Free-Standing GaN Substrates by Hydride Vapor Phase Epitaxy and Laser-Induced Liftoff", Japanese Journal of Applied Physics 1999 Jpn.J.Appl.Phys. 38 L217 Summary of the Invention [Problem to be solved by the invention]

[0004] However, with laser lift-off (LLO) technology, there is concern that the crystal may be damaged due to the impact of laser irradiation, so there is a need to establish a method for lifting off crystals that is less likely to cause impact on the crystal.

[0005] The present invention has been made in view of the above-mentioned conventional circumstances, and an object to be achieved is to provide an epi-wafer for a semiconductor light emitting device in which damage to the crystal is unlikely to occur. [Means for solving the problem]

[0006] The epitaxial wafer for semiconductor light emitting device of the present invention is A substrate; a semiconductor crystal layer laminated on the substrate; Equipped with voids are formed in the semiconductor crystal layer, The cross-sectional shape of the void in the stacking direction is at least a first side extending upward and outward from one end of the base; a second side extending upward and inward from an upper end of the first side; It has the following characteristics.

[0007] According to this configuration, internal stress tends to concentrate at the portion where the first side and the second side are connected, so that the semiconductor crystal layer can be peeled off from the substrate starting from the portion where the first side and the second side are connected. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram showing the structure of a nitride semiconductor light-emitting device according to Example 1. FIG. [Figure 2] FIG. 2 is a schematic plan view of a second AlN layer on which pillars are formed. [Figure 3] FIG. 2 is a schematic diagram showing the crystal growth process of a u-AlGaN layer. [Figure 4] FIG. 2 is a schematic diagram showing the process of crystal growth of a u-AlGaN layer, showing the state in which voids are formed. [Figure 5] 1 is a scanning electron microscope longitudinal cross-sectional image showing pillars and voids at a magnification. [Figure 6] 1 is a schematic diagram showing a state in which a semiconductor crystal layer is peeled off from a sapphire substrate using a notch portion as a base point. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] A preferred embodiment of the present invention will now be described.

[0010] In the epitaxial wafer for semiconductor light emitting device of the present invention, in the cross section of the void in the stacking direction, a first side extends upward and outward from each end of the bottom side, and a second side extends upward and inward from the top end of each first side. With this configuration, the semiconductor crystal layer can be more effectively peeled off from the substrate at the portion where the first side and the second side join.

[0011] In the epi-wafer for semiconductor light emitting device of the present invention, the semiconductor crystal layer has a plurality of pillars extending in a columnar shape in the stacking direction, which are arranged side by side in the horizontal direction, and the voids can be arranged between each pillar. This configuration makes it easy to peel the semiconductor crystal layer from the substrate.

[0012] Next, a first embodiment of the epitaxial wafer for semiconductor light emitting device of the present invention will be described with reference to the drawings.

[0013] Example 1 As shown in FIG. 1 , the epitaxial wafer 1 for a semiconductor light-emitting device of Example 1 (hereinafter simply referred to as the epitaxial wafer 1) includes a sapphire substrate 10 serving as a substrate, and a semiconductor crystal layer 30 stacked on the sapphire substrate 10. The semiconductor crystal layer 30 includes a first AlN layer 11, a second AlN layer 12, a u-AlGaN layer 13, an n-AlGaN layer 14, and a light-emitting layer 15. The light-emitting layer 15 includes a first guide layer 15A, a double quantum well active layer 15B, and a second guide layer 15C. The epitaxial wafer 1 is a test structure for verifying the manufacturing method for a nitride semiconductor light-emitting device of the present invention, and is obtained by performing crystal growth up to the second guide layer 15C located on the surface of the double quantum well active layer 15B, which functions as the light-emitting layer 13. The vertical direction in which each layer is stacked is the stacking direction L. The epitaxial wafer 1 of Example 1 is stacked and crystal grown mainly using MOVPE (metal-organic vapor phase epitaxy). Hereinafter, the layers from the second AlN layer 12 to the second guide layer 15C will also be referred to as epilayers.

[0014] The C-plane ((0001) plane) of the sapphire substrate 10 is the surface (the front is the upper side in FIG. 1, the same applies below.) The thickness of the sapphire substrate 10 is 450 μm.

[0015] The first AlN layer 11 is deposited on the surface of the sapphire substrate 10 using a sputtering method. The thickness of the first AlN layer 11 is 450 nm. After the first AlN layer 11 is deposited, annealing is performed in an N2 (nitrogen) atmosphere at 1700°C for 3 hours. In this way, an AlN template substrate Te having the sapphire substrate 10 and the first AlN layer 11 is fabricated using a sputtering method. Thereafter, a layer structure is formed using an MOVPE method.

[0016] An AlN template substrate Te is placed in a reactor capable of carrying out the MOVPE method (hereinafter simply referred to as a reactor), and while NH3 (ammonia), which is an N (nitrogen) raw material, is flowed onto the surface of the AlN template substrate Te (the surface of the first AlN layer 11) (hereinafter, the supply is not stopped), the temperature of the AlN template substrate Te is raised to 1200°C in an H2 (hydrogen) atmosphere, and then held for 10 minutes.

[0017] Next, a second AlN layer 12 is deposited on the surface of the first AlN layer 11 by crystal growth. The thickness of the second AlN layer 12 is 1550 nm. The second AlN layer 12 is formed by supplying TMAl (trimethylaluminum), an Al (aluminum) source, and NH3, an N source, into a reactor while the temperature of the AlN template substrate Te is set to 1200°C.

[0018] [Pillar formation process] Next, a pillar formation process is performed in which the surface side of the second AlN layer 12 is etched to form multiple pillars 12A. Specifically, a 420 nm SiO2 layer is deposited on the surface of the second AlN layer 12 using a sputtering device. Then, a resist is applied to the surface of the SiO2 layer to form a resist film, and a fine pattern with a pitch of 1000 nm and a diameter of approximately 500 nm is formed on the resist film using a nanoimprinting device. The surface of the SiO2 layer is exposed outside this fine pattern. Then, using an ICP device, the exposed SiO2 layer is dry-etched with CF4 gas. Next, buffered hydrofluoric acid is used to remove the SiO2 layer residue. Then, Cl2 gas is used to etch the surface side of the second AlN layer 12 to a depth of 1000 nm, and the SiO2 layer and resist film used as a mask are removed using buffered hydrofluoric acid.

[0019] Next, wet etching is performed. Specifically, etching is performed for 5 minutes at 85°C to 90°C using a 25% TMAH aqueous solution. By performing wet etching in this manner, the diameter of the pillars 12A is reduced, the spacing between adjacent pillars 12A is increased, and the height of the pillars is also increased. This completes the pillar formation process.

[0020] The pillars 12A extend in the stacking direction L in the shape of a hexagonal column. The height of the pillars 12A is approximately 1200 nm. The pillars 12A are arranged so as to correspond to the positions of the vertices of a regular hexagon and the position of the center of gravity (see FIG. 2). The diameter of the pillars 12A is approximately 140 nm to 250 nm. The distance (pitch) between the centers of adjacent pillars 12A is approximately 1000 nm (see FIG. 2). The length dimension of the pillars 12A in the stacking direction L (vertical direction) is greater than the diameter dimension. The pillars 12A are arranged side by side in the horizontal direction (left and right direction) (see FIG. 1).

[0021] [Void formation process] Next, a void formation process is performed to form multiple voids Vo, which are spaces. Specifically, a u-AlGaN layer 13 is stacked on the surface of the second AlN layer 12 on which the pillars 12A have been formed, and crystal growth is performed. The AlN template substrate Te on which the pillars 12A have been formed is placed back into the reactor. The temperature of the AlN template substrate Te is then raised to 1200°C, and H2, TMGa (trimethylgallium), TMAl (trimethylaluminum), and NH3 are supplied into the reactor so that the AlN mole fraction becomes 0.68. The u-AlGaN layer 13 has a thickness of 5 μm. By making the u-AlGaN layer 13 5 μm thick, the surface 12C of the second AlN layer 12, to which the base ends of the pillars 12A are connected, is buried and planarized. The u-AlGaN layer 13 is not doped with impurities such as Si or Mg. However, the u-AlGaN layer 13 may be replaced with an n-AlGaN layer doped with Si or the like. Here, the thickness of the u-AlGaN layer 13 is the dimension from the base end of the pillar 12A to the surface of the u-AlGaN layer 13.

[0022] Here, the mechanism by which voids Vo are formed will be explained. As shown in Fig. 3, when the crystal growth of the u-AlGaN layer 13 starts, the u-AlGaN layer 13 grows to cover the outer peripheral surface and upper end surface of each pillar 12A and the surface 12C of the second AlN layer 12 to which the base ends of each pillar 12A are connected. At this time, the rate at which the crystal growth of the u-AlGaN layer 13 progresses is greater at the tip ends of each pillar 12A than at the base ends of each pillar 12A.

[0023] As the crystal growth of the u-AlGaN layer 13 progresses, the thickness of the u-AlGaN layer 13 increases on the outer peripheral surface and upper end surface of each pillar 12A and on the surface 12C, as shown in Fig. 4. At the same time, on the outer peripheral surface of the base end of each pillar 12A, crystal growth progresses such that the u-AlGaN layer 13 becomes thicker so as to reinforce the outer peripheral surface of the base end of each pillar 12A.

[0024] As the crystal growth of the u-AlGaN layer 13 progresses further, the u-AlGaN layers 13 that have grown on the tip ends of the pillars 12A bond together. This prevents the source gas for the u-AlGaN layer 13 from reaching the base ends of the pillars 12A, and voids Vo are formed. The voids Vo are located between adjacent pillars 12A. In this way, the voids Vo are formed in the semiconductor crystal layer 30.

[0025] As the crystal growth of the u-AlGaN layer 13 progresses further, the surface of the u-AlGaN layer 13 becomes flat (see FIG. 1). This completes the void formation process. In the void formation process, the supply amounts of each raw material into the reactor, as well as the temperature and pressure within the reactor, are constant from the start to the end of the growth of the u-AlGaN layer 13.

[0026] 1, the cross-sectional shape of each void Vo thus formed in the stacking direction L is a shape surrounded by a bottom side Bo, a pair of first sides S1 extending upward and outward from both ends of the bottom side Bo, a pair of second sides S2 extending upward and inward from the upper ends of each first side S1, and an upper side To connecting the upper ends of each second side S2. A notch N is formed at the location where the first side S1 and the second side S2 are connected, recessed toward the outer peripheral surface of the pillar 12A.

[0027] Next, an n-AlGaN layer 14 is deposited on the planarized surface of the u-AlGaN layer 13 for crystal growth. Specifically, while H2, TMGa, TMAl, and NH3 are continuously supplied to the reactor, SiH4 is supplied to the reactor. The Si concentration in the n-AlGaN layer 14 is 6×10 18 cm -3 The supply flow rates of the raw materials are adjusted so that the thickness of the n-AlGaN layer 14 is 4 μm. The mole fraction of AlN in the n-AlGaN layer 14 is 0.62.

[0028] Next, the light emitting layer 15 is deposited on the surface of the n-AlGaN layer 14 and crystal growth is performed. First, the first guide layer 15A is deposited and crystal growth is performed. The thickness of the first guide layer 15A is 150 nm. The supply of TMGa, TMAl, and SiH4 into the reactor is stopped, and the temperature of the AlN template substrate Te is lowered to 1050°C. Once the predetermined temperature is reached, TEGa (triethylgallium) and TMAl are supplied into the reactor in place of TMGa so that the mole fraction of AlN becomes 0.45.

[0029] Next, the double quantum well active layer 15B is deposited on the surface of the first guide layer 15A and crystal grown. The double quantum well active layer 15B has an AlGaN well layer with an AlN molar fraction of 0.35 and an AlGaN barrier layer with an AlN molar fraction of 0.45 (not shown). The AlGaN well layer is 4 nm thick. The AlGaN barrier layer is 8 nm thick. The double quantum well active layer 15B is deposited and crystal grown with the temperature of the AlN template substrate Te set to 1050°C, and then an AlGaN barrier layer is deposited and crystal grown under the same growth conditions as the first guide layer 15A. This process is repeated twice to form the AlGaN / AlGaN double quantum well active layer 15B.

[0030] Next, TEGa and TMAl are supplied into the reactor so that the molar fraction of AlN becomes 0.45, and the second guide layer 15C is deposited by crystal growth, thus forming the light emitting layer 15. The second guide layer 15C has a thickness of 150 nm.

[0031] Then, the supply of TEGa and TMAl into the reactor is stopped to terminate crystal growth, and the temperature of the AlN template substrate Te is lowered to room temperature while H and NH are flowed into the reactor. After the temperature of the AlN template substrate Te has reached room temperature, the reactor is thoroughly purged, and the AlN template substrate Te is removed from the reactor. In this way, a semiconductor light-emitting device epitaxial wafer 1 having the layer structure shown in FIG. 1 is completed.

[0032] Figure 5 shows an SEM image of a cross section of the epitaxial wafer 1. Figure 5 shows a cross section of the epitaxial wafer 1 cut so as to overlap the central axes of adjacent pillars 12A. Voids Vo are formed between adjacent pillars 12A. The voids Vo surround the periphery of the pillars 12A like a corridor and are formed so as to be connected over the entire surface 12C of the second AlN layer 12. A u-AlGaN layer 13 is formed on the outer peripheral surface of the pillars 12A facing the voids Vo so as to cover this outer peripheral surface.

[0033] [Peeling process] Next, a peeling step is performed. This step is performed by bonding the epitaxial wafer 1 to a support 19. First, the epitaxial wafer 1 is divided into squares of 10 mm x 10 mm. Then, as shown in FIG. 6, an Al2O3 layer 16 is formed on the surface of the epitaxial wafer 1 (the surface of the second guide layer 15C). 、 A titanium-platinum layer 17 and a gold-tin layer 18 are stacked, and the sapphire substrate 10 is ground and polished to a thickness of 350 μm or less. The titanium-platinum layer 17 on the epitaxial wafer 1 side and a support 19 on which Ti / Pt / Au is vapor-deposited are then brought into close contact with each other and heated to 310°C while applying pressure to eutectic bond the epitaxial wafer 1 and the support 19 via the gold-tin layer 18. The Ti / Pt / Au vapor-deposited on the support 19 is not shown. The outer periphery of the rectangularly divided epitaxial wafer 1 is then pressed with tweezers from the stacking direction L (vertical direction). A crack is then generated in the epitaxial wafer 1 at the notch N of the void Vo in the portion pressed with the tweezers toward the pillar 12A. This crack propagates to the pillar 12A, dividing the pillar 12A into upper and lower portions.

[0034] The epitaxial wafer 1 is left as it is. Then, as the crack propagates, cracks also occur in the notch portions N located around the portion pressed with the tweezers (the notch portion N where the crack occurred), splitting the pillars 12A into upper and lower portions. Then, as cracks occur in most of the notch portions N, most of the pillars 12A are split into upper and lower portions. Then, as shown in FIG. 6 , a portion of the pillars 12A in the semiconductor crystal layer 30, a portion of the u-AlGaN layer 13, the n-AlGaN layer 14, and the light-emitting layer 15 are peeled off from the AlN template substrate Te. It is believed that the notch portions N have a property where stress inherent in the epitaxial wafer 1 is likely to concentrate, which is why the peeling proceeds naturally. This completes the peeling process.

[0035] Next, the effects of the above embodiment will be described. The epitaxial wafer 1 for a semiconductor light-emitting element comprises a sapphire substrate 10 and a semiconductor crystal layer 30 stacked on the sapphire substrate 10, and a void Vo is formed in the semiconductor crystal layer 30. The cross-sectional shape of the void Vo in the stacking direction L has a first side S1 extending upward and outward from one end of the bottom side Bo, and a second side S2 extending upward and inward from the upper end of the first side S1.

[0036] By wet etching the pillars 12A, the outer diameter of the pillars 12A becomes smaller and the height also increases, weakening the mechanical strength of the pillars 12A. Furthermore, grinding and polishing the sapphire substrate 10 to reduce the thickness increases the warpage of the epitaxial wafer 1 so that it becomes convex with the epitaxial layer surface facing upward. The epitaxial wafer 1 with increased convex warpage and the support 19 are stacked and pressurized (250 N / cm 2) and heating (310°C) to form a eutectic bond with the gold-tin layer 18 exerts compressive stress on the epitaxial layer, pulling it toward the support 19, due to the influence of the eutectic layer, and also the influence of the sapphire substrate 10, which pulls the epitaxial layer toward the sapphire substrate 10 in an attempt to restore the warpage of the epitaxial wafer 1 from the bonded state. It is believed that these stresses concentrate in the notch N of the pillar 12A, which has weak mechanical strength, causing the notch N to fracture. This configuration makes it easy for internal stress to concentrate in the portion where the first side S1 and the second side S2 are joined, making it possible to peel the semiconductor crystal layer 30 from the sapphire substrate 10, starting from the notch N where the first side S1 and the second side S2 are joined.

[0037] In the cross-sectional shape of the semiconductor light-emitting device epitaxial wafer 1, a first side S1 extends upward and outward from each end of the base side Bo, and a second side S2 extends upward and inward from the upper end of each first side S1. With this configuration, the sapphire substrate 10 can be more effectively separated from the semiconductor crystal layer 30 at the notch N where the first side S1 and the second side S2 join.

[0038] In the semiconductor light emitting device epi-wafer 1, the semiconductor crystal layer 30 has a plurality of pillars 12A extending in a columnar shape in the stacking direction L, which are arranged side by side in the horizontal direction (left and right direction), and voids Vo are arranged between each pillar 12A. This configuration makes it easy to peel the semiconductor crystal layer 30 from the sapphire substrate 10.

[0039] The present invention is not limited to the first embodiment described above with reference to the drawings, and the following embodiments are also included within the technical scope of the present invention. (1) Unlike Example 1, the first side may extend upward and outward from one end of the bottom side, and the second side may extend upward and inward from the top end of the first side. That is, the first side and the second side may be formed on only one side of the bottom side. Also, there may be a void in which the bottom side and the top side are connected by only the first side (only the second side). (2) Unlike the first embodiment, a semiconductor crystal layer made of other materials may be used. (3) The first AlN layer may be deposited using the MOVPE method. (4) An AlGaN layer may be used instead of the first AlN layer and the second AlN layer. That is, the base layer may be made of AlGaN and the pillars may be made of AlGaN. (5) The pillars are not limited to a hexagonal shape, but may be circular or polygonal. [Explanation of symbols]

[0040] 1...Epi-wafer for semiconductor light emitting device 10...Sapphire substrate (substrate) 12A...pillar 30...Semiconductor crystal layer Bo...bottom L…Lamination direction S1...First side S2: Second side Vo…Void

Claims

1. A substrate; a semiconductor crystal layer laminated on the substrate; Equipped with voids are formed in the semiconductor crystal layer, The cross-sectional shape of the void in the stacking direction is at least a first side extending upward and outward from one end of the base; a second side extending upward and inward from an upper end of the first side; An epitaxial wafer for a semiconductor light emitting device, comprising:

2. 2. The epi-wafer for a semiconductor light-emitting element according to claim 1, wherein in the cross-sectional shape, the first sides extend upward and outward from both ends of the bottom side, and the second sides extend upward and inward from the upper ends of each of the first sides.

3. the semiconductor crystal layer has a plurality of pillars extending in a columnar shape in the stacking direction, the pillars being arranged in a horizontal direction, The epi-wafer for a semiconductor light emitting device according to claim 2 , wherein the voids are disposed between the pillars.

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