Semiconductor device and manufacturing method thereof

Abstract

To provide a technology to improve the trade-off between on-resistance and breakdown voltage.SOLUTION: A semiconductor device 10 includes a plurality of p-type deep layers 36, a plurality of n-type deep layers 37, an n-type drift layer 38, and an n-type heavily doped layer 39. The n-type heavily doped layer is in contact with at least a portion of the lower surface of a corresponding one of the plurality of p-type deep layers, and has a higher concentration of n-type impurities than the drift layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application is a related application of Japanese Patent Application No. 2022-066834, filed on April 14, 2022, and claims priority based on this Japanese patent application, the entire contents of which are incorporated herein by reference.

[0002] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

[0003] Japanese Patent Application Laid-Open No. 2003-309261 and Japanese Patent Application Laid-Open No. 2017-152488 disclose a semiconductor device in which p-type layers and n-type layers are alternately arranged in the surface direction of a semiconductor substrate. When this semiconductor device is turned off, the p-type layers and n-type layers are depleted, and the voltage between the source and drain is maintained. Summary of the Invention

[0004] In such a semiconductor device having multiple p-type layers and multiple n-type layers, there is a trade-off between on-resistance and breakdown voltage. This specification proposes a technology to improve the trade-off between on-resistance and breakdown voltage.

[0005] The semiconductor device disclosed in this specification can include a semiconductor substrate having a trench on an upper surface thereof, a gate insulating film covering the inner surface of the trench, and a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate includes an n-type source layer in contact with the gate insulating film on a side surface of the trench, a p-type body layer in contact with the gate insulating film on the side surface of the trench located below the source layer, and a plurality of p-type deep layers each extending from the body layer to a position below a bottom surface of the trench, and extending along a first direction when the semiconductor substrate is viewed from above and arranged at intervals from each other in a second direction perpendicular to the first direction, and a plurality of n-type deep layers each extending from an adjacent front end to a front end of the body layer to a position below a bottom surface of the trench, and The semiconductor device may have a plurality of n-type deep layers arranged at corresponding intervals among a plurality of intervals defined between the p-type deep layers and in contact with the gate insulating film on the side of the trench located below the body layer, an n-type drift layer arranged below the plurality of p-type deep layers and the plurality of n-type deep layers and in contact with the plurality of n-type deep layers, and an n-type high concentration layer in contact with at least a portion of the underside of a corresponding p-type deep layer among the plurality of p-type deep layers and having a higher concentration of n-type impurities than the drift layer.

[0006] In the above semiconductor device, the n-type high-concentration layer is provided so as to contact at least a portion of the lower surface of the p-type deep layer, thereby suppressing the expansion of the depletion layer from the p-type deep layer toward the drift layer when the device is turned on. Therefore, the semiconductor device has a wide current path, resulting in low on-resistance. Furthermore, the n-type high-concentration layer is provided partially so as to contact the lower surface of the p-type deep layer. Therefore, the semiconductor device also suppresses a decrease in breakdown voltage. The semiconductor device can achieve both low on-resistance and high breakdown voltage.

[0007] The present disclosure provides a method for manufacturing a semiconductor device, which may include a deep layer formation step of forming a plurality of p-type deep layers and a plurality of n-type deep layers in an n-type epitaxial layer, wherein the p-type deep layers extend along a first direction when viewed from above the epitaxial layer and are spaced apart from one another in a second direction perpendicular to the first direction, and the n-type deep layers are arranged at corresponding intervals among a plurality of intervals defined between adjacent p-type deep layers; and an n-type high concentration layer formation step of forming an n-type high concentration layer in contact with at least a portion of a lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers, the n-type high concentration layer having a higher concentration of n-type impurities than the epitaxial layer. Note that the chronological order of the deep layer formation step and the n-type high concentration layer formation step is not particularly limited.

[0008] According to this method for manufacturing a semiconductor device, it is possible to manufacture a semiconductor device that achieves both low on-resistance and high breakdown voltage. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional perspective view of a semiconductor device 10 (a view showing an xz cross section not including a p-type deep layer 36). [Figure 2] 1 is a perspective cross-sectional view of the semiconductor device 10 with the source electrode 22 and the interlayer insulating film 20 omitted (a view showing an xz cross section not including the p-type deep layer 36). [Figure 3] An enlarged xy cross-section of a semiconductor device 10 including a p-type trench lower layer 35, a p-type deep layer 36, and an n-type deep layer 37, showing the arrangement of the p-type trench lower layer 35, the p-type deep layer 36, and the n-type deep layer 37 when the semiconductor substrate 12 is viewed from above. [Figure 4] An enlarged xy cross-sectional view of a semiconductor device 10 including trenches 14, p-type deep layers 36, and n-type deep layers 37, showing the arrangement of trenches 14, p-type deep layers 36, and n-type deep layers 37 when the semiconductor substrate 12 is viewed from above. [Figure 5]1 is a cross-sectional perspective view of a semiconductor device 10 (a view showing an xz cross section including a p-type deep layer 36). [Figure 6] 10 is an enlarged yz cross-sectional view of a modified example of the semiconductor device 10 including a p-type deep layer 36, an n-type deep layer 37, and an n-type heavily doped layer. [Figure 7] 10 is an enlarged yz cross-sectional view of a modified example of the semiconductor device 10 including a p-type deep layer 36, an n-type deep layer 37, and an n-type heavily doped layer. [Figure 8] 10 is an enlarged yz cross-sectional view of a modified example of the semiconductor device 10 including a p-type deep layer 36, an n-type deep layer 37, and an n-type heavily doped layer. [Figure 9] 3A to 3C are explanatory diagrams of a method for manufacturing the semiconductor device 10. [Figure 10] 3A to 3C are explanatory diagrams of a method for manufacturing the semiconductor device 10. [Figure 11] 3A to 3C are explanatory diagrams of a method for manufacturing the semiconductor device 10. [Figure 12] 3A to 3C are explanatory diagrams of a method for manufacturing the semiconductor device 10. [Figure 13] 3A to 3C are explanatory diagrams of a method for manufacturing the semiconductor device 10. [Figure 14] 3A to 3C are explanatory diagrams of a method for manufacturing the semiconductor device 10. [Figure 15] 3A to 3C are explanatory diagrams of a method for manufacturing the semiconductor device 10. [Figure 16] 3A to 3C are explanatory diagrams of a method for manufacturing the semiconductor device 10. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, each embodiment will be described with reference to the drawings. For the purpose of clarity of illustration, only some of the components that are repeatedly arranged will be labeled with reference numerals.

[0011] The semiconductor device 10 shown in FIGS. 1 to 5 is a power device of a type known as a MOSFET (metal-oxide-semiconductor field effect transistor) and includes a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z-direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 (a direction perpendicular to the z-direction) is referred to as the x-direction, and a direction perpendicular to the x-direction and z-direction is referred to as the y-direction. The semiconductor substrate 12 is made of silicon carbide (SiC). The semiconductor substrate 12 may also be made of other semiconductor materials such as silicon or gallium nitride. A plurality of trenches 14 are provided in the upper surface 12a of the semiconductor substrate 12. As shown in FIG. 2, the plurality of trenches 14 extend elongatedly along the y-direction on the upper surface 12a. The plurality of trenches 14 are arranged at intervals in the x-direction.

[0012] As shown in FIGS. 1, 2, and 5, the inner surface (i.e., the side and bottom surfaces) of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. As shown in FIGS. 1 and 5, the upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. A source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 at a position where the interlayer insulating film 20 is not present. A drain electrode 24 is provided on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12.

[0013] As shown in Figures 1, 2, and 5, the semiconductor substrate 12 has a plurality of source layers 30, a plurality of contact layers 32, a body layer 34, a plurality of p-type trench lower layers 35, a plurality of p-type deep layers 36, a plurality of n-type deep layers 37, a drift layer 38, a plurality of n-type high concentration layers 39, and a drain layer 40.

[0014] Each source layer 30 is an n-type layer with a high concentration of n-type impurities. Each source layer 30 is disposed in an area that partially includes the upper surface 12a of the semiconductor substrate 12. Each source layer 30 is in ohmic contact with the source electrode 22. Each source layer 30 is in contact with the gate insulating film 16 at the top of the side surface of the trench 14. Each source layer 30 faces the gate electrode 18 with the gate insulating film 16 interposed therebetween. Each source layer 30 extends longitudinally in the y direction along the side surface of the trench 14. That is, when the semiconductor substrate 12 is viewed from above, each source layer 30 extends parallel to the longitudinal direction of the trench 14, extending from one end to the other end in the longitudinal direction of the trench 14.

[0015] Each contact layer 32 is a p-type layer with a high concentration of p-type impurities. Each contact layer 32 is disposed in an area that partially includes the upper surface 12a of the semiconductor substrate 12. Each contact layer 32 is disposed between two corresponding source layers 30. Each contact layer 32 is in ohmic contact with the source electrode 22. Each contact layer 32 extends longitudinally in the y direction. That is, when the semiconductor substrate 12 is viewed from above, each contact layer 32 extends parallel to the longitudinal direction of the trench 14, extending from one end to the other end of the longitudinal direction of the trench 14.

[0016] The body layer 34 is a p-type layer having a lower concentration of p-type impurities than the contact layer 32. The body layer 34 is disposed below the source layers 30 and the contact layers 32. The body layer 34 contacts the source layers 30 and the contact layers 32 from below. The body layer 34 contacts the gate insulating film 16 on the side surface of the trench 14 located below the source layer 30. The body layer 34 faces the gate electrode 18 with the gate insulating film 16 interposed therebetween.

[0017] Each p-type trench lower layer 35 is a p-type layer disposed below the corresponding trench 14. As will be described later, each p-type trench lower layer 35 may be formed in the same ion implantation process as the body layer 34. In this case, the concentration profiles of the p-type impurities in the depth direction of each p-type trench lower layer 35 and the body layer 34 are the same, and the depth from the bottom surface of the corresponding trench 14 to the lower surface of each p-type trench lower layer 35 is the same as the depth from the upper surface 12a of the semiconductor substrate 12 to the lower surface of the body layer 34. In this example, each p-type trench lower layer 35 is in contact with the gate insulating film 16 covering the bottom surface of the corresponding trench 14. As shown in FIG. 3 , when the semiconductor substrate 12 is viewed from above, each p-type trench lower layer 35 extends long along the longitudinal direction of the corresponding trench 14 (the y direction in this example) and continuously extends from one end to the other end of the longitudinal direction of the trench 14.

[0018] Each p-type deep layer 36 is a p-type layer that protrudes downward from the lower surface of the body layer 34. The p-type impurity concentration of each p-type deep layer 36 is higher than that of the body layer 34 and lower than that of the contact layer 32. As shown in FIG. 4 , when the semiconductor substrate 12 is viewed from above, each p-type deep layer 36 extends elongately in the x direction, perpendicular to the longitudinal direction of the trench 14 (in this example, the y direction). The p-type deep layers 36 are arranged spaced apart from each other in the y direction. In the y-z cross section, the p-type deep layers 36 have a shape that is elongated in the z direction. That is, the dimension of each p-type deep layer 36 in the z direction (i.e., the height of each p-type deep layer 36) is greater than the dimension of each p-type deep layer 36 in the y direction (i.e., the width of each p-type deep layer 36). Each p-type deep layer 36 extends from the lower surface of the body layer 34 to a depth below the bottom surface of each trench 14. Each p-type deep layer 36 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. Also, as shown in FIG. 3, each p-type deep layer 36 contacts the p-type trench lower layer 35 located below the trench 14 so as to intersect with it.

[0019] Each n-type deep layer 37 is an n-type layer protruding downward from the lower surface of the body layer 34. The n-type impurity concentration of each n-type deep layer 37 is higher than the n-type impurity concentration of the drift layer 38. The n-type impurity concentration of each n-type deep layer 37 is lower than the p-type impurity concentration of each p-type deep layer 36. Alternatively, each n-type deep layer 37 may have the same n-type impurity concentration as the drift layer 38. As shown in FIGS. 1, 2, and 5, each n-type deep layer 37 is disposed in a corresponding one of a plurality of intervals defined by adjacent p-type deep layers 36. When the semiconductor substrate 12 is viewed from above as shown in FIG. 4, each n-type deep layer 37 extends elongatedly in the x-direction and is perpendicular to the longitudinal direction of the trench 14 (the y-direction in this example). Each n-type deep layer 37 contacts the side surfaces of the p-type deep layers 36 on both sides. In the y-z cross section, the n-type deep layer 37 has a shape elongated in the z-direction. That is, the dimension of the n-type deep layer 37 in the z direction (i.e., the height of the n-type deep layer 37) is greater than the dimension of the n-type deep layer 37 in the y direction (i.e., the lateral width of the n-type deep layer 37). In this embodiment, the height of the n-type deep layer 37 is equal to the height of the p-type deep layer 36. Note that, in this specification, taking into account variations in the ion implantation process, the height of the n-type deep layer 37 and the height of the p-type deep layer 36 are considered to be the same as long as the difference in height between the n-type deep layer 37 and the p-type deep layer 36 is within 3%, and the lateral width of the n-type deep layer 37 is approximately equal to the lateral width of the p-type deep layer 36. As shown in FIGS. 1, 2, and 5, each n-type deep layer 37 extends from the lower surface of the body layer 34 to a position below the bottom surface of each trench 14. Each n-type deep layer 37 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. As shown in FIG. 3, each n-type deep layer 37 is in contact with a p-type trench lower layer 35 disposed below the trench 14 so as to intersect with the p-type trench lower layer 35 .

[0020] The drift layer 38 is an n-type layer disposed below the multiple p-type deep layers 36 and the multiple n-type deep layers 37. The concentration of n-type impurities in the drift layer 38 is lower than the concentration of n-type impurities in the n-type deep layers 37. The drift layer 38 contacts the n-type deep layers 37 from below.

[0021] Each n-type high-concentration layer 39 is an n-type layer that contacts the entire lower surface of the corresponding p-type deep layer 36. The n-type impurity concentration of each n-type high-concentration layer 39 is higher than the n-type impurity concentration of the drift layer 38. The n-type impurity concentration of each n-type high-concentration layer 39 may be lower than the n-type impurity concentration of the n-type deep layer 37. Each n-type high-concentration layer 39 is disposed between the drift layer 38 and the p-type deep layer 36, separating the drift layer 38 from the p-type deep layer 36. Each n-type high-concentration layer 39 is partially provided so as to contact the lower surface of the p-type deep layer 36, but is not provided so as to cover at least a portion of the lower surface of the n-type deep layer 37. In other words, each n-type high-concentration layer 39 does not extend continuously between adjacent p-type deep layers 36, but is divided below the n-type deep layer 37. Therefore, the n-type deep layer 37 and the drift layer 38 are in contact with each other in the region between adjacent n-type heavily doped layers 39. When the semiconductor substrate 12 is viewed from above, each n-type heavily doped layer 39 extends longitudinally along the longitudinal direction of the corresponding p-type deep layer 36 (the y direction in this example), and extends continuously from one end of the p-type deep layer 36 to the other end in the longitudinal direction. Furthermore, as shown in FIG. 5 , each n-type heavily doped layer 39 is also in contact with the lower surface of the p-type trench lower layer 35 that intersects with the corresponding p-type deep layer 36, and is disposed between the drift layer 38 and the p-type trench lower layer 35. Note that adjacent n-type heavily doped layers 39 may be connected to each other below the p-type trench lower layer 35. In this example, the n-type heavily doped layer 39 may extend in the y direction along the lower surface of the p-type trench lower layer 35, and may be formed to separate the drift layer 38 from the p-type trench lower layer 35.

[0022] The drain layer 40 is an n-type layer having a higher concentration of n-type impurities than the drift layer 38 and the n-type deep layer 37. The drain layer 40 is in contact with the drift layer 38 from below. The drain layer 40 is disposed in an area including the lower surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0023] Next, the operation of the semiconductor device 10 will be described. The semiconductor device 10 is used with a higher potential applied to the drain electrode 24 than to the source electrode 22. When a potential equal to or greater than the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16. The channel connects the source layer 30 and the n-type deep layer 37. As a result, electrons flow from the source layer 30 to the drain layer 40 via the channel, the n-type deep layer 37, and the drift layer 38. In other words, the semiconductor device 10 is turned on. When the potential of each gate electrode 18 is reduced from a value equal to or greater than the gate threshold to a value less than the gate threshold, the channel disappears and the flow of electrons stops. In other words, the semiconductor device 10 is turned off.

[0024] Without the n-type heavily doped layer 39, a depletion layer would expand from the p-type deep layer 36 toward the drift layer 38 when the semiconductor device 10 is turned on. In particular, if the depletion layer expands toward the drift layer 38 below the n-type deep layer 37, the current path would narrow, potentially increasing on-resistance. This increase in on-resistance is known as the JFET effect. In contrast, the semiconductor device 10 includes the n-type heavily doped layer 39 in contact with the lower surface of the p-type deep layer 36, thereby preventing the depletion layer from expanding from the p-type deep layer 36 toward the drift layer 38. This ensures a wide current path, allowing the semiconductor device 10 to exhibit low on-resistance. The thickness of the n-type heavily doped layer 39 may be greater than the thickness of the depletion layer generated by the built-in potential at the p-n junction between the p-type deep layer 36 and the n-type heavily doped layer 39. This effectively suppresses the JFET effect. Furthermore, the n-type high concentration layer 39 is provided partially below the p-type deep layer 36, but is not provided at least partially below the n-type deep layer 37, and is not formed continuously in the surface direction of the semiconductor substrate 12. In this way, the n-type high concentration layer 39 is provided partially, which also suppresses a decrease in the breakdown voltage of the semiconductor device 10. The semiconductor device 10 can achieve both low on-resistance and high breakdown voltage.

[0025] 6, the n-type high-concentration layers 39 are selectively disposed at both widthwise ends of the underside of the corresponding p-type deep layer 36, and are not in contact with the entire underside of the p-type deep layer 36. Even with this modification, when the semiconductor device 10 is turned on, it is possible to prevent the depletion layer from spreading from the p-type deep layer 36 toward the drift layer 38 below the n-type deep layer 37. Furthermore, because a portion of the p-type deep layer 36 is in contact with the drift layer 38, when the semiconductor device 10 is turned off, the depletion layer spreads well from the p-type deep layer 36 to the drift layer 38. Therefore, with this modification, the breakdown voltage can be improved.

[0026] 7, the lateral width of the n-type heavily doped layer 39 is larger than the lateral width of the corresponding p-type deep layer 36, so that the n-type heavily doped layer 39 contacts not only the entire lower surface of the corresponding p-type deep layer 36 but also the n-type deep layer 37 adjacent to the corresponding p-type deep layer 36. According to this example, when the semiconductor device 10 is turned on, the depletion layer can be effectively prevented from expanding from the p-type deep layer 36 toward the drift layer 38.

[0027] In the modification shown in FIG. 8 , the p-type deep layer 36 extends below the n-type deep layer 37. The n-type high-concentration layer 39 contacts not only the entire lower surface of the p-type deep layer 36 but also the side surfaces of the p-type deep layer 36 below the n-type deep layer 37. When the p-type deep layer 36 extends below the n-type deep layer 37, the breakdown voltage of the semiconductor device 10 is improved. Furthermore, since the n-type high-concentration layer 39 is also disposed on the side surfaces of the p-type deep layer 36, even if the p-type deep layer 36 extends below the n-type deep layer 37, it is possible to suppress the expansion of a depletion layer from the p-type deep layer 36 toward the drift layer 38 below the n-type deep layer 37 when the semiconductor device 10 is turned on. This modification further improves the trade-off between on-resistance and breakdown voltage. Note that, in this modification, the n-type high-concentration layer 39 may not be provided on a portion of the lower surface of the p-type deep layer 36, as shown in FIG. 6 , and the p-type deep layer 36 and the drift layer 38 may be formed to be in contact with each other.

[0028] Next, a description will be given of a method for manufacturing the semiconductor device 10. The semiconductor device 10 is manufactured from a semiconductor substrate entirely composed of the drain layer 40. First, as shown in Fig. 9, an n-type epitaxial layer 50 is formed on the drain layer 40 using epitaxial growth technology.

[0029] 10 , an n-type layer 60 is formed by introducing n-type impurities into a predetermined depth range away from the surface of the epitaxial layer 50 using ion implantation technology. The part of the epitaxial layer 50 below the n-type layer 60 becomes the drift layer 38.

[0030] Next, as shown in FIG. 11, a mask 52 having an opening is patterned on the epitaxial layer 50 .

[0031] Next, as shown in FIG. 12, an n-type impurity is introduced into the upper part of the drift layer 38 through the openings in the mask 52 using an ion implantation technique, thereby forming an n-type high concentration layer 39.

[0032] 13, p-type impurities are introduced into parts of the n-type layer 60 through the openings in the mask 52 using ion implantation technology to form a plurality of p-type deep layers 36. The parts of the n-type layer 60 where the plurality of p-type deep layers 36 are not formed become a plurality of n-type deep layers 37. In this specification, the process of forming the plurality of p-type deep layers 36 and the plurality of n-type deep layers 37 among the processes illustrated in FIGS. 10 to 13 is an example of a deep layer formation process. After the plurality of p-type deep layers 36 are formed, the mask 52 is removed.

[0033] In this example, the mask 52 serves as both a mask for ion implantation to form the n-type high-concentration layer 39 and a mask for ion implantation to form the p-type deep layer 36. This reduces the number of steps and reduces manufacturing costs. The n-type high-concentration layer 39 may be formed after the p-type deep layer 36 is formed. The n-type high-concentration layer 39 of the modified example shown in FIG. 6 can be formed by performing ion implantation obliquely at a predetermined angle with respect to the upper surface of the epitaxial layer 50 when forming the n-type high-concentration layer 39. The n-type high-concentration layer 39 of the modified example shown in FIG. 7 can be formed without using the mask 52, by making the opening width of the mask for ion implantation to form the n-type high-concentration layer 39 larger than the opening width of the mask for ion implantation to form the p-type deep layer 36.

[0034] Next, as shown in FIG. 14, the source layer 30 and the contact layer 32 are formed by introducing n-type impurities and p-type impurities into the surface layer of the epitaxial layer 50 using ion implantation technology.

[0035] 15 , etching is used to form trenches 14 that extend from the surface of the epitaxial layer 50 to the n-type deep layers 37 and the p-type deep layers 36. The depth of the trenches 14 is adjusted so as not to exceed the n-type deep layers 37 and the p-type deep layers 36. When the epitaxial layer 50 is viewed from above, the trenches 14 intersect with a plurality of p-type deep layers 36 and a plurality of n-type deep layers 37.

[0036] 16 , ion implantation is used to introduce p-type impurities in multiple stages toward the surface of the epitaxial layer 50, thereby forming a body layer 34 and a p-type trench lower layer 35. The body layer 34 is formed above the n-type deep layer 37 and the p-type deep layer 36, and below the source layer 30 and the contact layer 32. The p-type trench lower layer 35 is formed below the bottom surface of the trench 14.

[0037] Thereafter, the trench 14, the gate insulating film 16, the gate electrode 18, the interlayer insulating film 20, the source electrode 22, and the drain electrode 24 are formed, thereby completing the semiconductor device 10.

[0038] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility.

Claims

1. A semiconductor device (10), a semiconductor substrate (12) having a trench (14) formed on its upper surface; a gate insulating film (16) covering the inner surface of the trench; a gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; The semiconductor substrate is an n-type source layer (30) in contact with the gate insulating film on the side surface of the trench; a p-type body layer (34) in contact with the gate insulating film on the side surface of the trench located below the source layer; a plurality of p-type deep layers (36), each extending from the body layer to a position below a bottom surface of the trench, and extending along a first direction when the semiconductor substrate is viewed from above, and arranged at intervals from one another in a second direction perpendicular to the first direction; a plurality of n-type deep layers (37), each of which is disposed at a corresponding one of a plurality of intervals defined between adjacent ones of the p-type deep layers, and which contact the gate insulating film at the side of the trench located below the body layer; an n-type drift layer (38) disposed below the plurality of p-type deep layers and the plurality of n-type deep layers and in contact with the plurality of n-type deep layers; an n-type high concentration layer (39) in contact with at least a portion of a lower surface of a corresponding one of the plurality of p-type deep layers, the n-type high concentration layer having a higher concentration of n-type impurities than the drift layer.

2. 2 . The semiconductor device according to claim 1 , wherein the n-type high concentration layer is in contact with at least both end portions in the second direction of the lower surface of the corresponding p-type deep layer.

3. 3. The semiconductor device according to claim 2, wherein said n-type heavily doped layer is in contact with the entire lower surface of said corresponding p-type deep layer.

4. 4. The semiconductor device of claim 3, wherein the width of the n-type high concentration layer in the second direction is greater than the width of the p-type deep layer in the second direction, thereby causing the n-type high concentration layer to contact the n-type deep layer adjacent to the p-type deep layer.

5. 5. The semiconductor device according to claim 1, wherein the plurality of p-type deep layers extend below the plurality of n-type deep layers.

6. 6. The semiconductor device according to claim 5, wherein the n-type high concentration layer also contacts a side surface of the p-type deep layer located below the plurality of n-type deep layers.

7. 7. The semiconductor device according to claim 1, wherein the n-type high concentration layer has a lower concentration of n-type impurities than the plurality of n-type deep layers.

8. A method for manufacturing a semiconductor device (10), comprising: a deep layer formation step of forming a plurality of p-type deep layers (36) and a plurality of n-type deep layers (37) in an n-type epitaxial layer (50), wherein each of the plurality of p-type deep layers extends along a first direction when the epitaxial layer is viewed from above and is arranged at intervals from each other in a second direction perpendicular to the first direction, and each of the plurality of n-type deep layers is arranged in a corresponding one of a plurality of intervals defined between adjacent p-type deep layers; an n-type heavily doped layer forming step of forming an n-type heavily doped layer in contact with at least a portion of a lower surface of a corresponding one of the plurality of p-type deep layers, the n-type heavily doped layer having a higher concentration of n-type impurities than the epitaxial layer; A method for manufacturing a semiconductor device, comprising:

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein a mask for ion implantation for forming the plurality of p-type deep layers in the deep layer formation step is common to a mask for ion implantation for forming the n-type high concentration layer in the n-type high concentration layer formation step.

10. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the opening width in the second direction of a mask for ion implantation to form the n-type high concentration layer in the n-type high concentration layer formation process is larger than the opening width in the second direction of a mask for ion implantation to form the plurality of p-type deep layers in the deep layer formation process.

11. 11. The method for manufacturing a semiconductor device according to claim 8, wherein in the n-type heavily doped layer forming step, the n-type heavily doped layer is formed by using an oblique ion implantation technique.

12. 12. The method for manufacturing a semiconductor device according to claim 8, wherein the n-type high concentration layer has a lower n-type impurity concentration than the plurality of n-type deep layers.

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