Printed circuit board

Abstract

To provide a printed circuit board including a via with a new structure, and a manufacturing method for the same.SOLUTION: A printed circuit board includes an insulating layer including a via hole, and a via disposed in the via hole of the insulating layer. The via includes a connection part disposed in the via hole of the insulating layer, a first pad disposed on an upper surface of the insulating layer and an upper surface of the connection part, and a second pad disposed on a lower surface of the insulating layer and a lower surface of the connection part. The upper surface of the connection part has a shape depressed downward. The lower surface of the connection part has a shape depressed upward. A lower surface of the first pad has a convex shape corresponding to the upper surface of the connection part. An upper surface of the second pad has a convex shape corresponding to the lower surface of the connection part.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The embodiments relate to a printed circuit board and a method for manufacturing the same. [Background technology]

[0002] Electronic components are becoming smaller, lighter, and more integrated, and the line width of circuits is becoming finer. Furthermore, as semiconductor chip design rules are integrated to the nanometer scale, The circuit line width of the package substrate or printed circuit board on which the conductive chip is mounted is several micrometers. The particles are finer than the normal size.

[0003] In order to increase the circuit integration density of printed circuit boards, that is, to reduce the circuit line width, Various methods have been proposed. After copper plating, etching is performed to form a pattern. In order to prevent the loss of circuit line width during the process, SAP (sem i-additive process and Amsef (MSAP; modified EMI-additive process) and other processes have been proposed.

[0004] After that, in order to realize finer circuit patterns, copper foil is embedded in the insulating layer. Embedded Trace Substrate (hereinafter referred to as "ETS") The ETS method is used in the industry. The ETS method forms a copper foil circuit on the surface of an insulating layer. Instead, it is manufactured in an embedded form in an insulating layer, eliminating circuit loss due to etching. This is advantageous for miniaturizing the circuit pitch.

[0005] Meanwhile, to meet the recent demand for wireless data traffic, improved 5G (5th generation) Efforts are underway to develop 5G or pre-5G communication systems. Therefore, the 5G communication system uses ultra-high frequency (mmWave) to achieve high data transmission rates. ) band (sub6Giga (6GHz), 28Giga (28GHz), 38Giga (38GHz), or Use a frequency higher than this.

[0006] This reduces the path loss of radio waves in the ultra-high frequency band and increases the transmission distance of radio waves. Therefore, 5G communication systems will require beamforming, large-scale distribution, and Massive MIMO, array antenna In this frequency band, several hundred active amplifiers with wavelengths are used. Considering that the antenna consists of a 1000 Watts (Watts) and a 1000 Watts (Watts), the antenna system becomes relatively large.

[0007] Such antennas and AP modules are patterned onto printed circuit boards or Low losses on the printed circuit board are very important because the active amplifier The antenna system consists of multiple boards, namely, the antenna board, the antenna power supply board, the transmitter / receiver board, One transceiver board and one baseband board must be integrated into one compact unit. This means:

[0008] On the other hand, recently, printed circuit boards containing large area vias have been developed to improve heat dissipation and shielding properties. Large area vias are made by filling large diameter via holes with metal material. However, filling the inside of the large diameter via hole with a metal material This is not easy, and as a result, conventional large-area vias have a surface that is recessed toward the inside of the via hole. The dimple area includes a via hole when additional lamination is performed. This can affect hole processing, which in turn affects the reliability of the printed circuit board. This will happen. Summary of the Invention [Problem to be solved by the invention]

[0009] In an embodiment, a printed circuit board including a via with a new structure and a method for manufacturing the same are provided. do.

[0010] In the embodiment, a plurality of via holes are arranged in a multi-layer structure in the via hole. The present invention provides a printed circuit board including vias and a method for manufacturing the same.

[0011] In the proposed embodiment, the technical problem to be solved is the technical problem mentioned above. The present invention is not limited to the above-mentioned technical problems, and other technical problems not mentioned can be understood from the following description of the technology to which the embodiments belong. It will be clearly understood by those of ordinary skill in the art. [Means for solving the problem]

[0012] The printed circuit board according to the embodiment includes an insulating layer including a via hole, and a via hole in the insulating layer. a via hole disposed in the insulating layer, the via hole being a connecting portion disposed in the insulating layer; a first pad disposed on an upper surface of the insulating layer and an upper surface of the connecting portion; and a second pad disposed below the lower surface of the connecting portion, has a shape recessed downward, and the lower surface of the connecting portion has a shape recessed upward, The lower surface of the first pad includes a convex shape corresponding to the upper surface of the connecting portion, and the second pad The upper surface of the pad includes a convex shape corresponding to the lower surface of the connecting portion.

[0013] The printed circuit board has a through hole between the inner wall of the via hole and the connecting portion, and a through hole between the insulating layer and the connecting portion. a seed layer disposed between the first pad and the insulating layer and between the second pad and the insulating layer; nothing.

[0014] In addition, a first portion of the upper surface of the connecting portion is positioned lower than an upper surface of the insulating layer, and the connecting A first portion of the lower surface of the portion is located higher than the lower surface of the insulating layer.

[0015] In addition, a second portion of the upper surface of the connecting portion is positioned higher than an upper surface of the insulating layer, and A second portion of the lower surface of the portion is located lower than the lower surface of the insulating layer.

[0016] In addition, a second portion of the upper surface of the connecting portion is positioned higher than a lower surface of the first pad, A second portion of the lower surface of the connecting portion is located lower than the upper surface of the second pad.

[0017] The distance from the upper surface of the insulating layer to the first portion of the upper surface of the coupling portion is a thickness ranging from 5% to 40% of the thickness of the insulating layer to a first portion of the lower surface of the connecting portion; The distance at this point is in the range of 5% to 40% of the thickness of the insulating layer.

[0018] The connecting portion includes an X-shape.

[0019] The second portion of the upper surface of the coupling portion is a portion of the upper surface of the seed layer disposed on the upper surface of the insulating layer. and the lower surface of the first pad, and a second portion of the lower surface of the connecting portion is located between the insulating layer The second pad is located between the lower surface of the seed layer disposed on the lower surface and the upper surface of the second pad.

[0020] In addition, each of the first pad and the second pad is located on the upper surface or the lower surface of the insulating layer. a first region disposed on the surface; and a second region disposed in the via hole and located on the upper surface or the lower surface of the connecting portion. The second region includes a protrusion corresponding to the surface.

[0021] Meanwhile, the printed circuit board according to the embodiment includes a first insulating layer including a first via hole and a second via hole. a second insulating layer including a first via and disposed on the first insulating layer; a first via disposed in the via hole of the second insulating layer; and a second via disposed in the second via hole of the second insulating layer. a second via having a lower surface in contact with the upper surface of the first via and an upper surface in contact with the lower surface of the first via; a first connecting portion recessed in a side direction; and a second insulating layer disposed on the second insulating layer and facing an upper surface of the first connecting portion. The lower surface of the first pad is convex downward to correspond to the first pad.

[0022] a third insulating layer including a third via hole and disposed under the first insulating layer; a third via disposed in the third via hole of the third insulating layer, the third via having an upper surface a second connecting portion having a bottom surface that is in contact with a bottom surface of the first via and a bottom surface that is recessed upward; and a second pad having an upper surface that is convex upward so as to correspond to the lower surface of the first connecting portion; Includes do.

[0023] In addition, a first portion of the upper surface of the first connection portion is located lower than an upper surface of the second insulating layer, The second portion of the upper surface of the first connecting portion is formed on the upper surface of the second insulating layer and the lower surface of the first pad. It is located higher than

[0024] In addition, a first portion of the lower surface of the second connection portion is positioned higher than a lower surface of the third insulating layer, The second portion of the lower surface of the second connecting portion is formed on the lower surface of the third insulating layer and the upper surface of the second pad. is located lower than

[0025] Meanwhile, a method for manufacturing a printed circuit board according to an embodiment includes preparing an insulating layer, forming via holes on the insulating layer, and forming a seed layer on the surface of the insulating layer and on the inner wall of the via hole; A first mask having a first opening region exposing the via hole is disposed on the seed layer, Plating is performed based on the seed layer to form a via connection portion that fills a portion of the via hole. the first mask is removed, and a second opening region is formed on the seed layer to expose the connecting portion. A second mask having a thickness of 1000 nm is placed on the seed layer, and plating is performed on the remaining via holes. forming a pad protruding above the surface of the insulating layer while filling a portion of the insulating layer; removing the second mask; a width of the first opening region is smaller than a top width of the via hole; The upper surface of the connecting portion includes a shape recessed downward, and the lower surface of the pad corresponds to the upper surface of the connecting portion. This includes convex shapes.

[0026] The width of the first opening region of the first mask is 80% to 100% of the upper width of the via hole. It has a level of 95%.

[0027] In addition, a first portion of the upper surface of the connecting portion is positioned lower than an upper surface of the insulating layer, and the connecting A second portion of the upper surface of the portion is located higher than the upper surface of the insulating layer.

[0028] Additionally, the second portion of the upper surface of the connecting portion is positioned higher than the lower surface of the pad. [Effects of the Invention]

[0029] According to this embodiment, in the case of a conventional large area via, plating of a large diameter via hole is Although there are some limitations, by changing the plating method, it is possible to achieve large diameter via holes for large area vias. This breaks the restrictions on plating of large diameter via holes, making it possible to safely plate large diameter via holes. Furthermore, according to this embodiment, the via plating can be performed more efficiently than with the existing method. This ensures uniformity of the laser beam after additional lamination, ensuring quality reliability. It can be preserved.

[0030] In addition, conventionally, it was necessary to stabilize the plating inside the via hole between the thickness of the insulating layer and the size of the via hole. However, in this embodiment, the inside of the via hole This breaks down design constraints for achieving a highly reliable plating state. This allows for improved design freedom. By increasing the It can be completely shielded and improves heat dissipation properties in areas where heat dissipation is required. It is possible. [Brief explanation of the drawings]

[0031] [Figure 1a] FIG. 10 is a diagram showing a printed circuit board according to a comparative example. [Figure 1b] FIG. 10 is a diagram showing a printed circuit board according to a comparative example. [Figure 2] 1A-1C show various examples of via shapes or sizes. [Figure 3] FIG. 10 is a diagram for explaining a dimple region shown in a comparative example. [Figure 4] FIG. 1 is a diagram showing a printed circuit board according to a first embodiment. [Figure 5] FIG. 5 is an enlarged view of a via in the printed circuit board of FIG. 4. [Figure 6]5A to 5C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 4 in the order of steps. [Figure 7] 5A to 5C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 4 in the order of steps. [Figure 8] 5A to 5C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 4 in the order of steps. [Figure 9] 5A to 5C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 4 in the order of steps. [Figure 10] 5A to 5C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 4 in the order of steps. [Figure 11] 5A to 5C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 4 in the order of steps. [Figure 12] 5A to 5C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 4 in the order of steps. [Figure 13] 5A to 5C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 4 in the order of steps. [Figure 14] FIG. 10 is a diagram showing a printed circuit board according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, the embodiments disclosed in this specification will be described in detail with reference to the accompanying drawings. Regardless of the surface number, identical or similar components are given the same reference numerals, and the same reference numerals are used for the same components. The suffix "module" for the components used in the following description will be omitted. The terms "rule" and "division" are either given with consideration only to the ease of drafting the specification, or are used interchangeably. They do not have any meaning or role that is distinct from each other. In describing the embodiments disclosed in this specification, specific explanations of related prior art are provided. If it is determined that the details may obscure the gist of the embodiments disclosed in this specification, Further, the accompanying drawings are provided for easy understanding of the embodiments disclosed in this specification. The accompanying drawings are merely for the purpose of illustrating the technical features disclosed in this specification. The concept is not limited, and all modifications, equivalents, or equivalents that fall within the concept and technical scope of the present invention are included. It should be understood to include alternatives.

[0033] Ordinal terms such as second, first, etc. may be used to describe various components. However, the components are not limited by the terms. It is used only to distinguish it from its constituent elements.

[0034] When an element is referred to as being "coupled" or "connected" to another element, When installed, it may be directly coupled or connected to other components. However, it should be understood that there may be other components in between. On the other hand, when a component is "directly connected" or "directly connected" to another component, When it is said that something is "connected" to another, it should be understood that there are no other intervening components. It would be.

[0035] A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0036] In this application, terms such as "comprises" or "has" refer to features described in the specification, The presence of numbers, steps, actions, components, parts, or any combination thereof to specify one or more other features, numbers, steps, movements, The existence or possibility of addition of any work, component, part, or combination thereof is not known in advance. It should be understood that this does not exclude.

[0037] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0038] 1a and 1b are diagrams showing a printed circuit board according to a comparative example.

[0039] Referring to FIG. 1 a, a printed circuit board 10 according to the comparative example includes an insulating layer 11 .

[0040] The printed circuit board 10 includes a circuit pattern 12 and a via 13 .

[0041] The circuit pattern 12 is formed on at least one of the upper and lower surfaces of the insulating layer 11. The vias 13 penetrate the insulating layer 11 and are arranged in different layers. The circuit patterns are then connected.

[0042] At this time, the via 13 is connected to the first pad 14 disposed on the upper surface of the insulating layer 11, a second pad 16 disposed on the lower surface of the layer 11, and a second pad 16 disposed within the insulating layer 11; It includes a connecting portion 15 that connects the first pad 14 and the second pad 16 together.

[0043] The first pad 14 and the second pad 16 are provided on the upper and lower surfaces of the insulating layer 11. It can also be said that the circuit pattern 12 is arranged.

[0044] The connecting portion 15 is formed by connecting the inside of a via hole (not shown) formed in the insulating layer 11 with metal. Preferably, the connecting portion 15 is formed by filling the via hole with a material. The inside of the tube is plated with a metal material.

[0045] The upper or lower surface of the connecting portion 15 has a first width w1. For example, the first width w1 is 80 That is, the diameter of the upper or lower region of the connecting portion 15 is 80 μm or less. The via hole is formed by filling a via hole formed to a predetermined size with a metal material. The upper and lower surfaces of the connecting portion 15, the upper surface of the first pad 14, and the second pad 16 The lower surface is substantially flat. The upper surface of the pad 14 and the lower surface of the second pad 16 are flush with the upper or lower surface of the insulating layer 11. is placed on the surface.

[0046] On the other hand, recently, in order to improve the performance of vias, which play a role in heat dissipation, shielding, and signal transmission, In addition, the size of the via hole has been significantly increased, and as a result, the size of the via hole and via has also increased. also tends to be larger.

[0047] Referring to FIG. 1b, a printed circuit board 20 according to the comparative example includes an insulating layer 21.

[0048] The printed circuit board 20 includes a circuit pattern 22 and a via 23 .

[0049] The circuit pattern 22 is formed on at least one of the upper and lower surfaces of the insulating layer 21. The vias 23 penetrate the insulating layer 21 and are arranged in different layers. The resulting circuit patterns are then connected.

[0050] At this time, the via 23 is connected to the first pad 24 disposed on the upper surface of the insulating layer 21, a second pad 26 disposed on the underside of the insulating layer 21; It includes a connecting portion 25 that connects the first pad 24 and the second pad 26 together.

[0051] The first pad 24 and the second pad 26 are provided on the upper and lower surfaces of the insulating layer 21. It can also be said that the circuit pattern 22 is arranged.

[0052] The connecting portion 25 is formed by connecting the inside of a via hole (not shown) formed in the insulating layer 21 with metal. Preferably, the connecting portion 25 is formed by filling the via hole with a material. The inside of the coil is plated with a metal material.

[0053] The upper or lower surface of the connecting portion 25 has a second width w2. For example, the second width w2 is The width of the connecting portion 25 may be 100 μm or more, which is larger than the first width w1. A via hole formed with a diameter of 100 μm or more in the upper or lower region is filled with a metal material. In this case, the upper and lower surfaces of the connecting portion 25, The upper surface of the first pad 24 and the lower surface of the second pad 26 are substantially curved. The upper and lower surfaces of the connecting portion 25, the upper surface of the first pad 24, and the second pad 26 The lower surface may include a concave shape that is concave in the upward or downward direction. The via 23 may include a dimple area.

[0054] In other words, when the via hole size is processed to a diameter of 100 μm or more, the via fill ( Fill) plating is not performed smoothly, and the above-mentioned concave dimple area DP occurs. do.

[0055] FIG. 2 shows various examples of via shapes or sizes.

[0056] Referring to FIG. 2(a), the connecting portion 15 has a first width w1 The cross-sectional shape may include a circular cross-sectional shape having a

[0057] As shown in FIG. 2(b), the connecting portion 25 has a circular shape having a second width w2 of 100 μm or more in diameter. The cross-sectional shape may include:

[0058] As shown in FIG. 2(c), the connecting portion 25A has a first width w1 as a diameter in the first direction. An elliptical cross-sectional shape or a bar shape having a diameter in the second direction of 100 μm or more and a third width w3 may include:

[0059] FIG. 3 is a diagram illustrating the dimple region shown in the comparative example.

[0060] Referring to FIG. 3, in the case of a relatively small via such as that shown in FIG. 2(a), The plating is smooth all over the entire area of the rod.

[0061] However, when the diameter of the via hole exceeds 100 μm, as in Figure 2 (b) and (c), However, via fill plating is not performed smoothly, and the top of the via is plated downward as shown in Figure 3(a). There is a dimple area DR1 in the via hole, or the upper and lower parts of the via hole are The upper and lower portions of the groove have dimple regions DR2 and DR3 recessed downward and upward, respectively. do.

[0062] When the depth of the dimple regions DR1, DR2, and DR3 is 10 μm or more, It is judged as good and cannot be used, or when additional lamination is performed after the core layer of the printed circuit board is formed This causes a problem that via holes cannot be formed smoothly in this region.

[0063] On the other hand, in recent years, in order to improve the performance of vias, which play a role in heat dissipation, shielding, and signal transmission, , the size of the via hole has increased significantly, and the size of the via hole and via has also increased accordingly. In the example, the above-mentioned large via of 10 μm or more In this case, the entire area of the via hole is uniformly plated, thereby A printed circuit board with a new structure that can remove the dimple area of the board and a manufacturing method thereof are provided. I try to.

[0064] FIG. 4 is a diagram showing a printed circuit board according to a first embodiment, and FIG. 5 is a diagram showing the printed circuit board of FIG. FIG.

[0065] 4 and 5, the printed circuit board 100 includes an insulating layer 110, a seed layer 120, and a , circuit pattern 130, and via 140.

[0066] The insulating layer 110 is a substrate on which a rewiring-enabled electric circuit is arranged, and has a surface Includes all printed wiring boards and insulating substrates made of insulating materials on which circuit patterns can be formed. It can be done.

[0067] When the printed circuit board 100 has a multi-layer structure, the insulating layer 110 is It can refer to the insulating layer arranged in the center among a plurality of insulating layers having a multi-layer structure. Preferably, the insulating layer 110 is one of the plurality of insulating layers. PTH (Plated Through Hole) means an insulating layer in which vias are formed. It is possible.

[0068] For example, the insulating layer 110 can be rigid or flexible. The insulating layer 110 may comprise glass or plastic. Layer 110 is made of soda lime glass or aluminosilicate. Chemically strengthened / semi-strengthened glass such as gate glass or polyimide , PI), polyethylene terephthalate (polyethylene terephth alate, PET), propylene glycol (PPG), polycarbonate (PC), etc. The material may comprise a toughened or ductile plastic, or may comprise sapphire.

[0069] In addition, the insulating layer 110 may include an optically isotropic film. The insulating layer 110 is made of COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), light isotropic polycarbonate (pol Polycarbonate (PC) or optical isotropic polymethyl methacrylate (PMMA) It can include:

[0070] In addition, the insulating layer 110 may be partially curved. The insulating layer 110 may bend, with some parts having flat surfaces and other parts having curved surfaces. In detail, the insulating layer 110 has a curved edge or a random curvature. It has a curved surface and can bend or bend.

[0071] In addition, the insulating layer 110 is made of a flexible substrate having a flexible property. The insulating layer 110 may be a curved or bent plate. In this case, the insulating layer 110 may be formed on the substrate according to the circuit design. ,The electrical wiring connecting the circuit components is expressed as a wiring diagram, and the electrical conductor is reproduced on the insulating material. The insulating layer 110 can also be used as a wiring layer for mounting electrical components and connecting them in a circuit. A wire can be formed, and components can be mechanically fixed other than the electrical connection function of the components. can be done.

[0072] A circuit pattern 130 may be disposed on the surface of the insulating layer 110. For example, A plurality of circuit patterns 130 are arranged on the upper surface of the insulating layer 110 at regular intervals. For example, the insulating layer 110 may have a plurality of circular holes spaced apart from each other at regular intervals on the lower surface thereof. A tract pattern 130 may be arranged.

[0073] The insulating layer 110 may have a thickness of 20 μm to 500 μm. The insulating layer 110 may have a thickness of 40 μm to 400 μm. For example, the insulating layer 110 may have a thickness of 60 μm to 250 μm. When the thickness of the insulating layer 110 is less than 20 μm, the circuit pattern 130 is formed on the surface of the insulating layer 110. If the thickness of the insulating layer 110 exceeds 500 μm, The overall thickness of the printed circuit board 100 may increase.

[0074] On the other hand, the circuit pattern 130 is a wiring for transmitting an electrical signal. The circuit pattern 130 may be formed of a highly conductive metal material. For this purpose, the circuit pattern 130 may be formed of gold (Au). , silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc ( The circuit pattern may be formed of at least one metal material selected from the group consisting of Zn, Zn, and Zn. The 130 is made of gold (Au), silver (Ag), platinum (Pt), and titanium ( At least one metal selected from the group consisting of Ti, tin (Sn), copper (Cu), and zinc (Zn) The circuit pattern 13 may be formed of a paste containing a metal or a solder paste. 0 can be formed from copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0075] The circuit pattern 130 is formed by an additive process, which is a typical manufacturing process for printed circuit boards. Subtractive process, Subtractive P process), MSAP (Modified Semi Additive Proc. ess), and SAP (Semi-Additive Process) methods are also possible. Therefore, detailed explanations will be omitted here.

[0076] Meanwhile, the seed layer 120 is disposed between the insulating layer 110 and the circuit pattern 130. The seed layer 120 can be selectively omitted. When the pattern 130 is formed by electrolytic plating, the insulating layer 110 and the circuit pattern The seed layer 120 may be disposed between the circuit pattern 130. If is formed by electroless plating, the seed layer 120 may be omitted.

[0077] As a result, a circuit pattern layer including the circuit pattern 130 and the seed layer 120 is formed. The circuit pattern layer may have a thickness in the range of 10 μm to 25 μm. Preferably, the circuit pattern layer includes a circuit pattern 130 and the seed layer 120. The total thickness of the circuit pattern 130 and the seed layer 120 is in the range of 10 μm to 25 μm. The circuit pattern layer may have only the circuit pattern 130. If included, the thickness of the circuit pattern 130 may range from 10 μm to 25 μm. Cut.

[0078] The via 140 may be disposed in the insulating layer 110. The via 140 may be disposed in the insulating layer 110. Preferably, the via 140 is disposed through the insulating layer 110. The circuit patterns 130 disposed on the upper and lower surfaces of the At this time, the circuit patterns connected by the vias 140 function as electrical signal transmitters. signal pattern for the signal shielding function, and shielding pattern for the heat dissipation function. The heat dissipation pattern may be, but is not limited to, any of the above.

[0079] The vias 140 may be disposed through the top and bottom surfaces of the insulating layer 110. The vias 140 are formed between the circuit pattern 130 disposed on the upper surface of the insulating layer 110 and the insulating layer 110. 10 and the circuit pattern disposed on the bottom surface of the substrate 10 can be electrically connected.

[0080] The via 140 includes a connecting portion 141, a first pad 142, and a second pad 143. It is possible.

[0081] The first pad 142 and the second pad 143 are connected to the upper surface of the insulating layer 110 and Preferably, the first pad 142 and the second pad 143 may be one of the circuit pattern layers. The second pads 143 are formed by the circuit patterns disposed on the upper and lower surfaces of the insulating layer 110. The term "circuit pattern" refers to a circuit pattern connected to the connection portion 141 of the via 140 in the circuit 130. can be done.

[0082] In the insulating layer 110, one end is connected to the first pad 142 and the other end is connected to the second pad 143. A connecting portion 141 may be arranged to be connected to the rod 143 .

[0083] The connecting portion 141 may be disposed in a via hole formed in the insulating layer 110. Preferably, the connecting portion 141 fills a part of a via hole formed in the insulating layer 110. It can be formed by filling.

[0084] That is, the connecting portion 141 is formed by the entire via hole formed in the insulating layer 110. It may be formed by filling only a part of the cavity.

[0085] As a result, the connecting portion 141 may have a curved surface rather than a flat surface. Preferably, the upper surface of the connecting portion 141 may include a shape that is recessed downward. The lower surface of the connecting portion 141 may have a recessed shape in the upward direction. The length of the upper surface of the connection part 141 is greater than the width of the upper portion of the via hole formed in the insulating layer 110. That is, the upper surface of the connecting portion 141 may have a curved surface. Therefore, the length of the upper surface of the connecting portion 141 may be greater than the width of the upper portion of the via hole. .

[0086] A portion of the upper surface of the connecting portion 141 may be located lower than the upper surface of the insulating layer 110. For example, the central region of the upper surface of the connecting portion 141 is lower than the upper surface of the insulating layer 110. That is, the connecting portion 141 may have a recess formed on the upper surface. Therefore, the length of the lower surface of the connecting portion 141 is equal to the length of the via hole formed in the insulating layer 110. That is, the lower surface of the connecting portion 141 may have a curved surface. Therefore, the length of the lower surface of the connecting portion 141 is greater than the width of the lower portion of the via hole. This sometimes happens.

[0087] In addition, a part of the lower surface of the connecting portion 141 is positioned higher than the lower surface of the insulating layer 110. For example, the central region of the lower surface of the connecting portion 141 may be thicker than the lower surface of the insulating layer 110. That is, the connecting portion 141 may have a recess formed on the bottom surface. do.

[0088] Thus, the connecting portion 141 may have recesses formed on the upper and lower surfaces thereof, and the entire connecting portion 141 may have recesses formed on the upper and lower surfaces thereof. The shape may essentially include an "X" shape.

[0089] Specifically, the via hole is formed by a first region located at the center of the insulating layer 110 and a second region located at the center of the insulating layer 110. A second region located above the insulating layer 110 above the first region, and a second region located above the insulating layer 110 below the first region. 10 and a third region located below the first region of the via hole. The entire area of the via hole can be filled with the connecting portion 141. The second and third regions may be filled with the connecting portions 141 only in part.

[0090] Meanwhile, the recess formed on the upper surface of the connecting portion 141 is a first recess from the upper surface of the insulating layer 110. The recess formed on the lower surface of the connecting portion 141 may have a depth D1. The insulating layer 110 may be formed to have a second depth D2 from the lower surface thereof.

[0091] In this case, the first depth D1 may be equal to the second depth D2. The first depth D1 may be 0.95 to 1.05 times the second depth D2.

[0092] The first depth D1 may have a level of 5% to 40% of the thickness of the insulating layer 110. For example, the first depth D1 may be set to a level of 10% to 20% of the thickness of the insulating layer 110. The first depth D1 may be less than 5% of the thickness of the insulating layer 110. In this case, the thickness of the protruding region of the connecting portion 141 (described later) increases, and thus the first pad In addition, the thickness of the insulating layer 110 may be increased. If the dimple area is larger than 40%, the dimple area will be may occur.

[0093] The second depth D2 has a thickness of 5% to 40% of the thickness of the insulating layer 110. For example, the second depth D2 can be set to 10% to 20% of the thickness of the insulating layer 110. The second depth D2 may be 5% of the thickness of the insulating layer 110. If the thickness is less than 1 / 2 mm, the thickness of the protruding region of the connecting portion 141 (described later) increases, and thus the The thickness of the second pad 143 may be increased. If the thickness is larger than 40% of the thickness of the second pad 143, the thickness of the second pad 143 may be increased. Simple areas may occur.

[0094] Meanwhile, the first pad 142 may be disposed on the upper surface of the insulating layer 110 .

[0095] Preferably, the seed layer 142 is disposed between the first pad 142 and the upper surface of the insulating layer 110. A seed layer 120 may be further disposed. The seed layer 120 may be formed between the first pad 142 and the insulating layer. The seed layer 120 may be disposed between the upper surface of the rim layer 110 and the via hole. Preferably, the seed layer 120 is disposed on the inner wall of the via hole. It can be disposed between the side surface of the connecting portion 141.

[0096] The lower surface of the first pad 142 may contact the upper surface of the connecting portion 141. As a result, the lower surface of the first pad 142 includes a shape corresponding to the upper surface of the connecting portion 141. Specifically, the lower surface of the first pad 142 is in contact with the upper surface of the connecting portion 141. For example, the first pad 142 may have a curved surface having a curvature corresponding to the connecting portion. The upper surface of 141 may have a protrusion corresponding to the recess.

[0097] As a result, at least a portion of the lower surface of the first pad 142 is covered with the seed layer 120. For example, a portion of the lower surface of the first pad 142 may be located lower than the upper surface. The first pad 14 may be located lower than the top surface of the insulating layer 110. For example, the first pad 14 A part of the lower surface of the connecting portion 141 may be located lower than the upper surface of the connecting portion 141. For example, A part of the lower surface of the first pad 142 is positioned lower than the end of the upper surface of the connecting portion 141. Specifically, the center of the lower surface of the first pad 142 is 41.

[0098] As a result, a part of the upper surface of the connecting portion 141 is larger than a part of the lower surface of the first pad 142. In addition, another part of the upper surface of the connecting portion 141 may be positioned higher than the first connecting portion 141. It may be located lower than other portions of the underside of the pad 142 .

[0099] Meanwhile, the second pad 143 may be disposed on the lower surface of the insulating layer 110 .

[0100] Preferably, the seed layer 1 is formed between the second pad 143 and the lower surface of the insulating layer 110. The seed layer 120 may be formed in front of the second pad 143. The insulating layer 110 may be disposed between the insulating layer 110 and the lower surface thereof.

[0101] The upper surface of the second pad 143 may contact the lower surface of the connecting portion 141. The upper surface of the second pad 143 may have a shape corresponding to the lower surface of the connecting portion 141. Specifically, the upper surface of the second pad 143 corresponds to the lower surface of the connecting portion 141. For example, the second pad 143 may be a curved surface having a curvature. The surface may have protrusions corresponding to the recesses formed thereon.

[0102] As a result, at least a part of the upper surface of the second pad 143 is covered with the seed layer 120. For example, a portion of the upper surface of the second pad 142 may be located higher than the lower surface. The second pad 143 may be located higher than the lower surface of the insulating layer 110. A part of the upper surface may be located higher than the lower surface of the connecting portion 141. For example, A part of the lower surface of the second pad 143 is positioned higher than the end of the lower surface of the connecting portion 141. Specifically, the center of the upper surface of the second pad 143 is located at the center of the connecting portion 142. It can be located higher than the edge of the lower surface.

[0103] As a result, a part of the lower surface of the connecting portion 141 is larger than a part of the upper surface of the second pad 143. In addition, another part of the lower surface of the connecting portion 141 may be located lower than the second connecting portion 141. It may be located higher than other parts of the top surface of the pad 143 .

[0104] As described above, in the embodiment, in the process of forming the via 140, the insulating layer 110 Instead of filling the entire via hole at once, fill some of the via holes as described above. After forming the connecting portion 141, the insulating layer is formed by filling the remaining portion of the via hole. The first pad 142 and the second pad 143 protrude from the upper and lower surfaces of the layer 110, respectively. The groove 143 is formed.

[0105] According to this embodiment, in the case of a conventional large-area via, plating of a large-diameter via hole is However, by changing the plating method, it is possible to increase the diameter of large area vias. It is possible to break the restrictions on via hole plating, which allows for the development of large diameter via holes. Furthermore, according to this embodiment, plating can be performed stably compared to the existing method. It is possible to ensure uniformity of via plating, and quality reliability is improved by improving the laser quality after additional lamination. Reliability can be ensured.

[0106] In addition, conventionally, it was necessary to stabilize the plating inside the via hole between the thickness of the insulating layer and the size of the via hole. However, in this embodiment, the inside of the via hole This breaks down design constraints for achieving a highly reliable plating state. This allows for improved design freedom. By increasing the It can be completely shielded and improves heat dissipation properties in areas where heat dissipation is required. It is possible.

[0107] 5, a part of the upper surface of the connecting portion 141 is higher than the upper surface of the insulating layer 110. For example, a portion of the upper surface of the connection portion 141 may be located higher than the seed layer. It can be positioned higher than the top surface of 120.

[0108] That is, the connecting portion 141 is disposed in a via hole formed in the insulating layer 110. and a first region 141a formed on the seed layer 120. a second region 141b disposed on the second region 141b, and a second region 141b disposed on the second region 141b, the upper surface of which is and a third region 141c located higher than the upper surface of the insulating layer 110. At this time, the third region 141c is the largest region of the entire region of the connecting portion 141. It can also be said to be a protruding area that protrudes outside the hole.

[0109] Although not specifically shown in FIG. 5, a part of the lower surface of the connecting portion 141 is For example, the lower surface of the connecting portion 141 may be located lower than the lower surface of the insulating layer 110. A portion of the seed layer 120 may be located lower than the lower surface of the seed layer 120. The lower surface of the connection portion 141 is also provided with a layer under the lower surface of the insulating layer 110 and the lower surface of the seed layer 120. It may include a raised protruding region.

[0110] A method for manufacturing the printed circuit board shown in FIG. 4 will be described in detail below.

[0111] 6 to 13 are diagrams showing the manufacturing method of the printed circuit board shown in FIG. 4 in the order of steps.

[0112] First, referring to FIG. 6(a), the insulating layer 110 that serves as the base of the printed circuit board is prepared. do.

[0113] As shown in FIG. 6(b), a metal layer 115 is laminated on the surface of the insulating layer 110. The metal layer 115 is formed by electrolessly plating a metal containing copper onto the surface of the insulating layer 110. The metal layer 115 may be formed by electroless plating on the insulating layer 110. Unlike the conventional method, the use of CCL (Copper Clad Laminate) It can also be done as follows.

[0114] In the following, the insulating layer 110 on which the metal layer 115 is not formed is used. A method for manufacturing the printed circuit board 100 according to the present invention will be described. However, the present invention is not limited to this. The following steps are performed in the state where the metal layer 115 is formed as shown in FIG. 6(b). In this case, the metal is not provided between the upper / lower surface of the insulating layer 110 and the seed layer 120 described later. However, the metal layer 115 may be disposed on the inner wall of the via hole. 115 may not be deposited and only the seed layer 120 may be deposited.

[0115] Next, referring to FIG. 7, at least one via hole VH1 is formed in the insulating layer 110. The via hole VH1 penetrates the upper and lower surfaces of the insulating layer 110. At this time, the via hole VH1 can be formed through the insulating layer 110. The via hole VH1 can be formed in the upper and lower regions, respectively. A first via groove (not shown) formed in the upper region of the insulating layer 110 and a first via groove (not shown) formed in the insulating layer 110 This can be formed by combining a second via groove (not shown) formed in the lower region of the first via groove. As a result, the width of the via hole VH1 gradually decreases from the center toward the upper and lower sides. For example, the via hole VH1 may have an hourglass shape. This can be done.

[0116] Next, as shown in FIG. 8, a step of forming the seed layer 120 on the insulating layer 110 is performed. It is possible to do so.

[0117] The seed layer 120 is formed on the upper surface of the insulating layer 110 and on the inner wall of the via hole VH1. can be formed.

[0118] The seed layer 120 is formed on the upper surface of the insulating layer 110 and the upper surface of the insulating layer 110 by chemical copper plating. It can be formed on the inner wall of the hole VH1.

[0119] Next, as shown in FIG. 9, the connecting portion 141 is formed inside the via hole VH1. A step of forming a first mask M1 for this purpose can be performed.

[0120] The first mask M1 is formed on the seed layer 120 disposed on the upper surface of the insulating layer 110. The first mask M1 may be formed on the lower surface of the insulating layer 110. It may be disposed below the seed layer 120 .

[0121] The first mask M1 is formed by the insulating layer 110. The seed layer 120 is disposed to cover the surface of the seed layer 120 and expose the portion where the connecting portion 141 is to be formed. The first opening region OR1 may include a first opening region OR2.

[0122] Preferably, the first mask M1 has a first opening area exposing the via hole VH1. In this case, the via hole VH1 and the first opening region OR 1 may be at least partially aligned in the vertical direction.

[0123] At this time, the first opening region OR1 of the first mask M1 is the entire area of the via hole VH1. In other words, the first mask M1 can expose only a part of the area. It may be disposed so as to cover a part of the via hole VH1.

[0124] That is, the width of the first opening region OR1 is smaller than the width of the via hole VH1. There is a saying.

[0125] Specifically, the first opening region of the first mask M1 disposed on the insulating layer 110 OR1 may be smaller than the top width of the via hole VH1. A part of the upper region of the hole VH1 may be exposed by the first opening region OR1. The remaining part may be covered by the first mask M1.

[0126] In addition, the first opening region OR1 of the first mask M1 disposed under the insulating layer 110 may be smaller than the bottom width of the via hole VH1. A portion of the lower region of the hole VH1 may be exposed by the first opening region OR1, The remaining part may be covered by the first mask M1.

[0127] That is, the first mask M1 has a first portion disposed on the seed layer 120 and a front portion. a second portion extending from the first portion and not in contact with the seed layer (120) and the insulating layer (110); The second portion of the first mask M1 may be floated on the via hole. ing).

[0128] At this time, the width W2 of the second portion is determined based on the width W3 of the via hole VH1. The depth of the recess of the connecting portion 141 is determined. When the thickness of the protruding region of the connecting portion 141 increases and the width W2 of the second portion decreases, The depth of the recess of the connecting portion 141 increases, and the thickness of the protruding region increases. In this case, the thickness of the first pad 142 may be increased accordingly. As the depth increases, there is a corresponding dimple area in the first pad 142. As a result, in the embodiment, the width W2 of the second portion is The width W2 of the second portion is set to 5% to 20% of the upper or lower width. is less than 5% of the upper width or the lower width of the via hole VH1, the first pad 14 2, a dimple region may be present. If the protruding area of the connecting portion 141 is larger than 20% of the upper or lower width of the loop VH1, The thickness of the first pad 142 or the second pad 143 increases. Furthermore, the overall thickness of the printed circuit board 100 may increase.

[0129] In other words, the width of the first opening region OR1 is equal to or smaller than the top width of the via hole VH1. It can have a level of 80% to 95% of the bottom width.

[0130] Next, referring to FIG. 10, electrolytic plating is performed based on the seed layer 120 to form the vias. The connecting portion 141 of the via 140 is formed in the hole VH1.

[0131] The connecting portion 141 is made of copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel ( The electrode may be formed of any metal material selected from the group consisting of nickel (Ni), palladium (Pd), and zinc (Cu).

[0132] At this time, the connecting portion 141 is disposed in a via hole formed in the insulating layer 110. Preferably, the connection portion 141 is a via hole formed in the insulating layer 110. It may be formed by filling a portion of the hole.

[0133] That is, the connecting portion 141 is formed by the entire via hole formed in the insulating layer 110. It may be formed by filling only a part of the cavity.

[0134] As a result, the connecting portion 141 may have a curved surface rather than a flat surface. Preferably, the upper surface of the connecting portion 141 may include a shape that is recessed downward. The lower surface of the connecting portion 141 may have a recessed shape in the upward direction. The length of the upper surface of the connection part 141 is greater than the width of the upper portion of the via hole formed in the insulating layer 110. That is, the upper surface of the connecting portion 141 may have a curved surface. Therefore, the length of the upper surface of the connecting portion 141 is greater than the width of the upper portion of the via hole. There is a saying.

[0135] A portion of the upper surface of the connecting portion 141 may be located lower than the upper surface of the insulating layer 110. For example, the central region of the upper surface of the connecting portion 141 may be thicker than the upper surface of the insulating layer 110. That is, the connecting portion 141 may have a recess formed on the upper surface thereof. Therefore, the length of the lower surface of the connecting portion 141 is equal to the length of the via hole formed in the insulating layer 110. That is, the lower surface of the connecting portion 141 may have a curved surface. Therefore, the length of the lower surface of the connecting portion 141 can be set to be equal to the lower width of the via hole. It may be larger than that.

[0136] In addition, a part of the lower surface of the connecting portion 141 is positioned higher than the lower surface of the insulating layer 110. For example, the central region of the lower surface of the connecting portion 141 may be formed on the lower surface of the insulating layer 110. That is, the connecting portion 141 has a recess formed on the bottom surface thereof. It is possible.

[0137] As a result, the connecting portion 141 has recesses formed on the upper and lower surfaces thereof. and may include an overall "X" shape.

[0138] Specifically, the via hole is formed by a first region located at the center of the insulating layer 110 and a second region located at the center of the insulating layer 110. A second region located above the insulating layer 110 above the first region, and a second region located above the insulating layer 110 below the first region. 10 and a third region located below the first region of the via hole. The entire area of the via hole can be filled with the connecting portion 141. The second and third regions may be filled with the connecting portions 141 only in part.

[0139] Meanwhile, the recess formed on the upper surface of the connecting portion 141 is a first recess from the upper surface of the insulating layer 110. The recess formed on the lower surface of the connecting portion 141 may have a depth D1. The insulating layer 110 may be formed to have a second depth D2 from the lower surface thereof.

[0140] In this case, the first depth D1 may be equal to the second depth D2. The first depth D1 may be 0.95 to 1.05 times the second depth D2.

[0141] The first depth D1 has a thickness of 5% to 40% of the thickness of the insulating layer 110. For example, the first depth D1 may be 10% to 20% of the thickness of the insulating layer 110. The first depth D1 may be 5 times the thickness of the insulating layer 110. %, the thickness of the protruding region of the connecting portion 141 described later increases, and The thickness of the first pad 142 may be increased. If the thickness is greater than 40% of the thickness of 110, the thickness of the first pad 142 will be increased. Simple areas may occur.

[0142] The second depth D2 has a thickness of 5% to 40% of the thickness of the insulating layer 110. For example, the second depth D2 can be set to 10% to 20% of the thickness of the insulating layer 110. The second depth D2 may be 5% of the thickness of the insulating layer 110. If the thickness is less than 1 / 2 mm, the thickness of the protruding region of the connecting portion 141 (described later) increases, and thus the The thickness of the second pad 143 may be increased. If the thickness is larger than 40% of the thickness of the second pad 143, the thickness of the second pad 143 may be increased. Simple areas may occur.

[0143] Meanwhile, the connecting portion 141 is formed on the surface of the insulating layer 110 and the surface of the seed layer 120. This is because the second portion of the first mask M1 may include a protruding region protruding from the front Unlike the first portion, the second portion is not supported on the seed layer 120 but floats. This is because the device is positioned so that the

[0144] As a result, a part of the upper surface of the connecting portion 141 is positioned higher than the upper surface of the insulating layer 110. For example, a part of the upper surface of the connection portion 141 may be formed on the seed layer 120. It can be positioned higher than the surface.

[0145] In addition, a part of the lower surface of the connecting portion 141 is located lower than the lower surface of the insulating layer 110. For example, a part of the lower surface of the connection portion 141 may be thicker than the lower surface of the seed layer 120. That is, the insulating layer 11 can be positioned lower than the lower surface of the connecting portion 141. 0 and a protruding region protruding below the lower surface of the seed layer 120.

[0146] Next, referring to FIG. 11, the first mask M1 disposed on the seed layer 120 is Then, the circuit pattern 130, the first pad 142, and the like are formed on the seed layer 120. and a second mask having a second opening area OR2 exposing an area where the second pad 143 is to be formed. Form M2.

[0147] The second mask M2 is formed on the seed layer 120 disposed on the upper surface of the insulating layer 110. The seed layer 110 may be disposed on the lower surface of the insulating layer 110. It can also be placed below 120.

[0148] The second opening region OR2 is a region on the upper surface of the seed layer 120 where the circuit pattern 130 is formed. This may expose the area where the material is to be processed.

[0149] The second opening region OR2 is formed on the upper surface of the seed layer 120 so as to cover the first pad 142. and may expose the area where the second pad 143 is to be formed.

[0150] The second opening region OR2 exposes the upper and lower regions of the connecting portion 141. Sometimes I do.

[0151] Next, referring to FIG. 12, the second mask M2 is exposed through the second opening region OR2. A circuit pattern 130, a first pad 142, and a second pad 143 are formed on the seed layer 120 and the connecting portion 141. and the second pad 143 is formed.

[0152] Next, as shown in FIG. 13, the second mask M2 can be removed. The seed layer 120 disposed on the insulating layer 110 includes a circuit pattern 130, a first pattern the remaining portion excluding the portion disposed in the area overlapping with the pad 142 and the second pad 143 A step of removing the

[0153] According to this embodiment, in the case of a conventional large area via, plating of a large diameter via hole is Although there are some limitations, by changing the plating method, it is possible to achieve large diameter via holes for large area vias. This breaks the restrictions on plating of large diameter via holes, making it possible to safely plate large diameter via holes. Furthermore, according to this embodiment, the via plating can be performed more efficiently than with the existing method. This ensures uniformity of the laser beam after additional lamination, ensuring quality reliability. It can be preserved.

[0154] In addition, conventionally, it was necessary to stabilize the plating inside the via hole between the thickness of the insulating layer and the size of the via hole. However, in this embodiment, the inside of the via hole This breaks down design constraints for achieving a highly reliable plating state. This allows for improved design freedom. By increasing the It can be completely shielded and improves heat dissipation properties in areas where heat dissipation is required. It is possible.

[0155] FIG. 14 is a diagram showing a printed circuit board according to the second embodiment.

[0156] Referring to FIG. 14, the printed circuit board 100A includes a first insulating layer 110, a second insulating layer 170, and a , a third insulating layer 180, a first via 140, a second via 150, a third via 160, and a circuit pattern 130 , seed layer 120 , first protective layer 190 , and second protective layer 195 .

[0157] In FIG. 14, the same reference numerals are used to designate the substantially same components as those in FIG. 4. Therefore, a detailed description of this will be omitted.

[0158] Referring to FIG. 14, the printed circuit board 100A has a multi-layer structure. The first insulating layer 110 located in the center is covered with a seed layer 120, a circuit pattern 130, and a small number of At least one first via 140 is included. The at least one first via 140 is It includes a first pad 142, a second pad 143, and a connecting portion 141.

[0159] Here, the first insulating layer 110, the seed layer 120, the circuit pattern 130 and the first via 140 has already been described with reference to FIGS. 4 and 5 above, so a detailed description thereof will be omitted.

[0160] A second insulating layer 170 is disposed on the first insulating layer 110. A third insulating layer 18 0 is disposed below the first insulating layer 110.

[0161] The second insulating layer 170 is formed by insulating a circuit pattern 1 disposed on the upper surface of the first insulating layer 110. 30 and may be disposed over the first pad 142 of the first via 140 .

[0162] The third insulating layer 180 is formed by insulating a circuit pattern 1 disposed on the lower surface of the first insulating layer 110. 30 and may be disposed over the second pad 143 of the first via 140 .

[0163] On the other hand, although not shown in FIG. 14, the upper and front surfaces of the second insulating layer 170 A circuit pattern may be disposed on the lower surface of each of the third insulating layers 180 .

[0164] The second insulating layer 170 has a second via 150 disposed therethrough. The second via 150 may be formed in a circuit board having a lower surface disposed on the upper surface of the first insulating layer 110. It may be connected to the turn 130 or the first pad 142 .

[0165] The second via 150 may have a shape corresponding to that of the first via 140. However, the first via 140 is a PTH (Plated Through Hole) via. In contrast, the second via 150 is a BVH (Blind Via Hole). e) via. Thus, the second via 150 is different from the first via 140, It may contain only one pad.

[0166] Specifically, the second via 150 includes a second seed layer 151, a second coupling portion 152, and a third The second connection part 152 may include a pad 153. The lower surface of the second connection part 152 may be connected to the first via 140. The upper surface of the second connecting portion 152 may be connected to the first pad 142 of the third pad. 153.

[0167] The second connection portion 152 is formed by a via hole formed in the second insulating layer 170. Therefore, the upper surface of the second connection part 152 may be formed by filling only a part of the The second connecting portion 152 may have a recessed shape in the side direction. The thickness may be greater than the top width of the via hole formed in the second insulating layer 170 . That is, the upper surface of the second connection part 152 may have a curved surface, thereby The length of the upper surface of the second connecting portion 152 is equal to the width of the upper portion of the via hole formed in the second insulating layer 170. It may be larger than that.

[0168] A portion of the upper surface of the second connection part 152 is located lower than the upper surface of the second insulating layer 170. For example, the central region of the upper surface of the second connection part 152 may be formed by the second insulating layer 170. That is, the second connecting portion 152 may be recessed on the upper surface. A section can be formed.

[0169] That is, the second connecting portion 152 may have a recess formed on the upper surface thereof, thereby forming a "V" shape. " shape.

[0170] Specifically, the via hole formed in the second insulating layer 170 is formed under the second insulating layer 170. a first region located on the side of the second insulating layer 170 and a second region located on the upper side of the second insulating layer 170 on the first region; The first insulating layer 170 may include a via hole. The entire area of one region may be filled with the second connecting portion 152. The second region of the via hole formed in the second insulating layer 170 is only partially connected to the second connecting portion 1 52.

[0171] Meanwhile, the recess formed on the upper surface of the second connection part 152 is formed on the upper surface of the second insulating layer 170. The grooves may be formed to have a certain depth.

[0172] The depth of the recess of the second connection part 152 is 5% to 40% of the thickness of the second insulating layer 170. For example, the depth of the recess of the second connection portion 152 may be The thickness of the second connection layer 170 may be 10% to 20% of the thickness of the insulating layer 170. When the depth of the recess of the second insulating layer 170 is less than 5% of the thickness of the second connecting portion 152, The thickness of the protruding area of the third pad 152 is increased, and thus the thickness of the third pad 153 is increased. In addition, the depth of the recess of the second connection part 152 is 4 times the thickness of the second insulating layer 170. If it is greater than 0%, a dimple area may exist in the third pad 152.

[0173] Meanwhile, the third pad 153 may be disposed on the upper surface of the second insulating layer 170. For example, a second seed layer 151 is formed between the third pad 153 and the upper surface of the second insulating layer 170. The second seed layer 151 may further include the third pad 153 and the second insulating layer. The second seed layer 151 may be disposed between the upper surface of the edge layer 170 and the via hole. The inner wall of the cylinder may be disposed thereon.

[0174] The lower surface of the third pad 153 may contact the upper surface of the second connecting part 152 . Therefore, the lower surface of the third pad 153 corresponds to the upper surface of the second connecting portion 152. Specifically, the lower surface of the third pad 153 may have a shape similar to that of the second connecting portion 1. For example, the third pad 153 may be a curved surface having a curvature corresponding to the upper surface of the third pad 152. The upper surface of the second connecting portion 152 may have a protrusion corresponding to the recess.

[0175] As a result, at least a part of the lower surface of the third pad 153 is covered with the second seed layer 15 For example, a part of the lower surface of the third pad 153 may be located lower than the upper surface of the third pad 153. may be located lower than the top surface of the second insulating layer 170. For example, A part of the lower surface of the rod 153 may be positioned lower than the upper surface of the second connecting portion 152. For example, a part of the lower surface of the third pad 153 is connected to the end of the upper surface of the second connecting part 152. Specifically, the central portion of the lower surface of the third pad 153 may be located lower than the central portion of the lower surface of the third pad 153. may be located lower than the end of the upper surface of the second connecting part 152.

[0176] As a result, a part of the upper surface of the second connecting portion 152 is in contact with a part of the lower surface of the third pad 153. In addition, another part of the upper surface of the second connecting part 152 may be located higher than the upper part. The third pad 153 may be positioned lower than another portion of the lower surface thereof.

[0177] The third via 160 may have a shape corresponding to that of the second via 150. That is, the first via 140 is a PTH (Plated Through Hole) via. In contrast, the second via 150 and the third via 160 are BVH (Blind Via Hole) structures. As a result, the third via 160 is connected to the second via 150. , and may contain only one pad.

[0178] Specifically, the third via 160 includes a third seed layer 161, a third coupling portion 162, and a fourth The third connection part 162 may include a pad 163. The top surface of the third connection part 162 may be connected to the first via 140. The second pad 143 may be connected to the second pad 143.

[0179] The third connection portion 162 is formed by a via hole formed in the third insulating layer 180. Therefore, the lower surface of the third connecting portion 162 may be formed by filling only a part of the upper surface. The third connecting portion 162 may have a recessed shape in the side direction. The thickness may be greater than the top width of the via hole formed in the third insulating layer 180 . That is, the lower surface of the third connecting portion 162 may have a curved surface, thereby The length of the bottom surface of the connecting portion 162 is longer than the bottom width of the via hole formed in the third insulating layer 180. Sometimes it can be even bigger.

[0180] A portion of the lower surface of the third connection part 162 is positioned higher than the lower surface of the third insulating layer 180. For example, the central region of the lower surface of the third connection part 162 may be formed by the third insulating layer 180. That is, the third connecting portion 162 may be positioned higher than the lower surface of the A section can be formed.

[0181] That is, the third connecting portion 162 may have a recess formed on the lower surface thereof, thereby It may include an "inverted V" shape.

[0182] Specifically, the via hole formed in the third insulating layer 180 is a first region located on the side of the third insulating layer 180 and a second region located below the first region and the third insulating layer 180; The third insulating layer 180 may include a via hole formed in the third insulating layer 180. The entire area of one region may be filled with the third connecting portion 162. The second region of the via hole formed in the third insulating layer 180 is only partially connected to the third connecting portion 1 62.

[0183] Meanwhile, the recess formed on the lower surface of the third connection part 162 is formed on the lower surface of the third insulating layer 180. The grooves may be formed to have a certain depth.

[0184] The depth of the recess of the third connection part 162 is 5% to 40% of the thickness of the third insulating layer 180. For example, the depth of the recess of the third connecting portion 162 may be The thickness of the third insulating layer 180 may be 10% to 20% of the thickness of the third insulating layer 180. When the depth of the recess of the connecting portion 162 is less than 5% of the thickness of the third insulating layer 180, The thickness of the protruding region of the connecting portion 162 increases, and the thickness of the fourth pad 163 increases accordingly. In addition, the depth of the recess of the third connection part 162 may be greater than the thickness of the third insulating layer 180. If the thickness is greater than 40%, a dimple area may be present in the fourth pad 162. do.

[0185] Meanwhile, the fourth pad 163 may be disposed on the lower surface of the third insulating layer 180. In other words, a third seed layer 162 is formed between the fourth pad 163 and the lower surface of the third insulating layer 180. The third seed layer 161 may further include the fourth pad 163 and the The third seed layer 161 may be disposed between the bottom surface of the third insulating layer 180 and the bottom surface of the third insulating layer 180. It may be disposed on the inner wall of a via hole formed in the edge layer 180 .

[0186] An upper surface of the fourth pad 163 may contact a lower surface of the third connecting part 162 . As a result, the upper surface of the fourth pad 163 has a shape corresponding to the lower surface of the third connecting portion 162. Specifically, the upper surface of the fourth pad 163 may have a shape similar to that of the third connecting portion 1. For example, the fourth pad 163 may have a curved surface having a curvature corresponding to the lower surface of the fourth pad 163. The lower surface of the third connecting portion 162 may have a protrusion corresponding to the recess.

[0187] As a result, at least a part of the upper surface of the fourth pad 163 is covered with the third seed layer 16 For example, a part of the upper surface of the fourth pad 163 may be located higher than the lower surface of the fourth pad 163. may be located higher than the bottom surface of the third insulating layer 180. For example, A part of the upper surface of the rod 163 may be positioned higher than the lower surface of the third connecting portion 162. For example, a part of the upper surface of the fourth pad 163 is connected to the end of the lower surface of the third connecting part 162. Specifically, the central portion of the upper surface of the fourth pad 163 may be located higher than the may be positioned higher than the end of the lower surface of the third connecting part 162.

[0188] As a result, a part of the lower surface of the third connecting portion 162 is in contact with a part of the upper surface of the fourth pad 163. In addition, another part of the lower surface of the third connecting part 162 may be located lower than the lower part. The fourth pad 163 may be positioned higher than other portions of the upper surface thereof.

[0189] Meanwhile, a portion of the upper surface of the second connection part 152 is positioned higher than the upper surface of the second insulating layer 170. For example, a part of the upper surface of the second connection part 152 may be formed on the second seed layer 1. 51.

[0190] Preferably, a part of the upper surface of the second connecting portion 152 is located at a position slightly larger than the lower surface of the third pad 153. That is, the second connection part 152 can be disposed higher than the second insulating layer 17. 0 and a protruding region protruding upward from the second seed layer 151.

[0191] Similarly, a part of the lower surface of the third connection part 162 is in contact with the lower surface of the third insulating layer 180. For example, a part of the lower surface of the third connecting portion 162 may be located lower than the It may be located lower than the bottom surface of the third seed layer 161 .

[0192] Preferably, a part of the lower surface of the third connecting portion 162 is located higher than the upper surface of the fourth pad 163. That is, the third connection part 162 may be positioned lower than the third insulating layer 18. 0 and the third seed layer 161 may include a protruding region protruding downward from the third seed layer 161.

[0193] According to this embodiment, in the case of a conventional large-area via, plating of a large-diameter via hole is However, by changing the plating method, it is possible to increase the diameter of large area vias. It is possible to break the restrictions on via hole plating, which allows for the development of large diameter via holes. Furthermore, according to this embodiment, plating can be performed stably compared to the existing method. It is possible to ensure uniformity of via plating, and quality reliability is improved by improving the laser quality after additional lamination. Reliability can be ensured.

[0194] In addition, conventionally, it was necessary to stabilize the plating inside the via hole between the thickness of the insulating layer and the size of the via hole. However, in this embodiment, the inside of the via hole This breaks down design constraints for achieving a highly reliable plating state. This allows for improved design freedom. By increasing the It can be completely shielded and improves heat dissipation properties in areas where heat dissipation is required. It is possible.

Claims

1. an insulating layer including a via hole; a via disposed in a via hole of the insulating layer; The via is a connecting portion disposed in the via hole of the insulating layer; a first pad disposed on an upper surface of the insulating layer and an upper surface of the coupling portion; a second pad disposed below the lower surface of the insulating layer and the lower surface of the connecting portion; an upper surface of the connecting portion includes a shape recessed downward; The lower surface of the connecting portion includes a shape recessed upward, a lower surface of the first pad includes a convex shape corresponding to an upper surface of the connecting portion; the upper surface of the second pad has a convex shape corresponding to the lower surface of the connecting portion; 。

2. Between the inner wall of the via hole and the connecting portion, between the insulating layer and the first pad, and 2. The print head of claim 1, further comprising a seed layer disposed between the insulating layer and the second pad. Printed circuit board.

3. a first portion of an upper surface of the connecting portion is located lower than an upper surface of the insulating layer; 2. The method according to claim 1, wherein a first portion of the lower surface of the connecting portion is positioned higher than a lower surface of the insulating layer. The printed circuit board.

4. a second portion of the upper surface of the coupling portion is positioned higher than an upper surface of the insulating layer; 4. The method according to claim 3, wherein the second portion of the lower surface of the connecting portion is positioned lower than the lower surface of the insulating layer. The printed circuit board.

5. a second portion of the upper surface of the connecting portion is positioned higher than a lower surface of the first pad; 5. The method of claim 4, wherein the second portion of the lower surface of the connecting portion is located lower than the upper surface of the second pad. The printed circuit board according to claim 1.

6. The distance from the upper surface of the insulating layer to the first portion of the upper surface of the coupling portion is a thickness in the range of 5% to 40% of the thickness of the insulating layer; The distance from the lower surface of the insulating layer to the first portion of the lower surface of the coupling portion is 2. The printed circuit board of claim 1, wherein the thickness of the insulating layer is in the range of 5% to 40%.

7. The printed circuit board of claim 1 , wherein the connecting portion comprises an X-shape.

8. The second portion of the upper surface of the connecting portion is formed between the upper surface of the seed layer disposed on the upper surface of the insulating layer and the and a lower surface of the first pad. The second portion of the lower surface of the connecting portion is formed between the lower surface of the seed layer disposed on the lower surface of the insulating layer and the The printed circuit board according to claim 2 , wherein the second pad is positioned between the first pad and the upper surface of the second pad.

9. Each of the first pad and the second pad includes: a first region disposed on an upper surface or a lower surface of the insulating layer; a second protrusion disposed in the via hole and corresponding to the upper or lower surface of the connecting portion; The printed circuit board of claim 1 comprising a region.

10. a first insulating layer including a first via hole; a second insulating layer including a second via hole and disposed on the first insulating layer; a first via disposed in the first via hole of the first insulating layer; a second via disposed in the second via hole of the second insulating layer; The second via is a first connecting portion having a lower surface in contact with an upper surface of the first via and an upper surface recessed downward; a first connecting portion disposed on the second insulating layer, the first connecting portion having a lower surface facing downward and corresponding to the upper surface of the first connecting portion; a printed circuit board including a first pad having a convex shape;

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