Complementary metal-oxide-semiconductor circuit and a manufacturing method for the same, and electronic device including complementary metal-oxide-semiconductor circuit

Abstract

To provide a CMOS circuit exhibiting excellent characteristics, and an electronic device including this CMOS circuit.SOLUTION: A complementary metal-oxide-semiconductor circuit includes an n-type metal oxide film semiconductor thin film transistor and a p-type metal oxide film semiconductor thin film transistor. Each of the n-type metal oxide film semiconductor thin film transistor and the p-type metal oxide film semiconductor thin film transistor includes a semiconductor film, a gate insulating film on the semiconductor film, a gate electrode on the gate insulating film, an interlayer insulating film on the gate electrode, and a pair of terminals existing on the interlayer insulating film and electrically connected to the semiconductor film. The semiconductor film of the p-type metal oxide film semiconductor thin film transistor includes fluorine ions.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a complementary metal oxide semiconductor circuit and a method for fabricating the same, or to an electronic device including a complementary metal oxide semiconductor circuit. [Background technology]

[0002] A complementary metal oxide semiconductor circuit (hereinafter also referred to as a CMOS circuit) is a circuit including a p-type metal oxide semiconductor transistor and an n-type metal oxide semiconductor transistor electrically connected to each other, and is incorporated into various electronic devices. CMOS circuits are fabricated using a so-called photolithography process. Patent Document 1 discloses a method for reducing the number of steps in the photolithography process for fabricating a p-type metal oxide semiconductor thin film transistor (hereinafter also referred to as a pMOSTFT) and an n-type metal oxide semiconductor thin film transistor (hereinafter also referred to as an nMOSTFT) on a substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-113151 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to provide a CMOS circuit having a novel structure. Alternatively, an object of one embodiment of the present invention is to provide a CMOS circuit exhibiting excellent characteristics and an electronic device including this CMOS circuit. Alternatively, an object of one embodiment of the present invention is to provide a method for manufacturing the CMOS circuit. Alternatively, an object of one embodiment of the present invention is to provide a method for manufacturing a CMOS circuit at low cost. [Means for solving the problem]

[0005] One embodiment of the present invention is a complementary metal oxide semiconductor circuit. The complementary metal oxide semiconductor circuit includes an n-type metal oxide semiconductor thin film transistor and a p-type metal oxide semiconductor thin film transistor. Each of the n-type metal oxide semiconductor thin film transistor and the p-type metal oxide semiconductor thin film transistor includes a semiconductor film, a gate insulating film on the semiconductor film, a gate electrode on the gate insulating film, an interlayer insulating film on the gate electrode, and a pair of terminals located on the interlayer insulating film and electrically connected to the semiconductor film. The semiconductor film of the p-type metal oxide semiconductor thin film transistor contains fluorine ions.

[0006] One embodiment of the present invention is an electronic device including a complementary metal oxide semiconductor circuit. The complementary metal oxide semiconductor circuit includes an n-type metal oxide semiconductor thin film transistor and a p-type metal oxide semiconductor thin film transistor. Each of the n-type metal oxide semiconductor thin film transistor and the p-type metal oxide semiconductor thin film transistor includes a semiconductor film, a gate insulating film on the semiconductor film, a gate electrode on the gate insulating film, an interlayer insulating film on the gate electrode, and a pair of terminals located on the interlayer insulating film and electrically connected to the semiconductor film. The semiconductor film of the p-type metal oxide semiconductor thin film transistor contains fluorine ions.

[0007] One embodiment of the present invention is a method for fabricating a complementary metal oxide semiconductor circuit, the method including: forming an undercoat on a substrate; forming a first semiconductor film and a second semiconductor film on the undercoat; doping both ends of the first semiconductor film with a first dopant that imparts n-type conductivity while masking an area between the second semiconductor film and both ends of the first semiconductor film; doping both ends of the second semiconductor film with a second dopant that imparts p-type conductivity while masking an area between the first semiconductor film and both ends of the second semiconductor film; The method includes forming a gate insulating film on the second semiconductor film, forming, on the gate insulating film, a first gate electrode that overlaps with the first semiconductor film and exposes both end portions of the first semiconductor film, and a second gate electrode that overlaps with the second semiconductor film and exposes both end portions of the first semiconductor film, forming an interlayer insulating film that covers the first gate electrode and the second gate electrode, and forming, on the interlayer insulating film, a pair of terminals that are electrically connected to the first semiconductor film and a pair of terminals that are electrically connected to the second semiconductor film. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic end view of a CMOS circuit according to one embodiment of the present invention; [Figure 2] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 3] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 4] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 5] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 6] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 7] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 8]1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 9] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 10] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 11] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 12] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 13] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 14] 1A to 1C are schematic end views illustrating a method for fabricating a CMOS circuit according to one embodiment of the present invention. [Figure 15] 1 is a schematic top view of an electronic device according to an embodiment of the present invention. [Figure 16] 1 is a schematic end view of an electronic device according to one embodiment of the present invention. [Figure 17] 5A to 5C are schematic end views showing a method for fabricating a pMOS TFT of a comparative example. [Figure 18] 5A to 5C are schematic end views showing a method for fabricating a pMOS TFT of a comparative example. [Figure 19A] 10 is a Vg-Id curve of a pMOS TFT of a comparative example. [Figure 19B] 1 shows the Vg-Id curve of a pMOS TFT according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, various embodiments of the present invention will be described with reference to the drawings, etc. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and should not be construed as being limited to the description of the embodiments exemplified below.

[0010] In order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same function as those described in the previous drawings may be given the same reference numerals, and duplicated explanations may be omitted. This reference numeral is used to collectively represent multiple identical or similar structures, and when these are individually represented, a hyphen and a natural number are added after the reference numeral.

[0011] In this specification and claims, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0012] In this specification and claims, the expression "a structure exposed from another structure" means a state in which a part of a structure is not covered by another structure, and includes a state in which the part not covered by another structure is covered by yet another structure. The state expressed by this expression also includes a state in which a structure is not in contact with another structure.

[0013] In the present invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from films formed as the same layer in the same process, and have substantially the same layer structure, the same material, and the same morphology. Therefore, these multiple films are defined as existing in the same layer.

[0014] First Embodiment In this embodiment, a CMOS circuit according to one embodiment of the present invention and a method for manufacturing the same will be described.

[0015] 1. CMOS circuit structure FIG. 1 shows a schematic end view of a CMOS circuit 110. As shown in FIG. 1, the CMOS circuit 110 includes an nMOS TFT 120 and a pMOS TFT 130 provided on a substrate 100 via an undercoat 102. The nMOS TFT 120 includes a semiconductor film 122, a gate insulating film 104 on the semiconductor film 122, a gate electrode 124 on the gate insulating film 104, an interlayer insulating film 106 covering the gate electrode 124, and a pair of terminals 126 and 128 provided on the interlayer insulating film 106 and electrically connected to the semiconductor film 122. One of the pair of terminals 126 and 128 functions as a source electrode and the other as a drain electrode. Similarly, the pMOS TFT 130 includes a semiconductor film 132, a gate insulating film 104 on the semiconductor film 132, a gate electrode 134 on the gate insulating film 104, the interlayer insulating film 106 covering the gate electrode 134, and a pair of terminals 136 and 138 provided on the interlayer insulating film 106 and electrically connected to the semiconductor film 132. One of the pair of terminals 136 and 138 functions as a source electrode and the other as a drain electrode. The gate insulating film 104 and the interlayer insulating film 106 are shared by the nMOS TFT 120 and the pMOS TFT 130. These configurations will be described below.

[0016] (1) Substrate and undercoat The substrate 100 is a base material that provides a surface for constructing the CMOS circuit 110 and also imparts mechanical strength to the electronic device in which the CMOS circuit 110 is incorporated. Examples of the substrate 100 include a glass substrate and a quartz substrate, but other substrates that contain polymers such as polyimide, silicon substrates, gallium substrates, and sapphire substrates may also be used. The substrate 100 may be flexible.

[0017] The undercoat 102 is a protective film that prevents impurities such as metal ions contained in the substrate 100 from penetrating into the CMOS circuit 110, and is composed of one or more films containing a silicon-containing inorganic compound such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. The thickness of the undercoat 102 can be determined arbitrarily and may be selected appropriately from the range of 50 nm to 1000 nm, for example. Depending on the fabrication method of the CMOS circuit 110, which will be described later, the undercoat 102 may contain fluorine ions. Alternatively, the undercoat 102 may contain boron ions and fluorine ions.

[0018] (2) Semiconductor film The semiconductor film 122 constituting the nMOS TFT 120 is a film containing silicon and having a polycrystalline morphology. The thickness of the semiconductor film 122 may be selected, for example, from a range of 20 nm to 100 nm. The semiconductor film 122 has a channel region 122a overlapping with the gate electrode 124 in the normal direction of the substrate 100, a pair of low-concentration impurity regions 122b sandwiching the channel region 122a, and a pair of source / drain regions 122c sandwiching the low-concentration impurity region 122b. The channel region 122a contains a dopant that imparts p-type conductivity (e.g., boron ions or aluminum ions). Meanwhile, the low-concentration impurity regions 122b and the source / drain regions 122c contain, in addition to a dopant that imparts p-type conductivity, a dopant that imparts n-type conductivity at a higher concentration than the dopant that imparts p-type conductivity (e.g., phosphorus ions, arsenic ions, antimony ions, nitrogen ions, etc.). Compared to the lightly doped region 122b, the source / drain region 122c has a higher dopant concentration, and therefore the source / drain region 122c has a higher conductivity than the lightly doped region 122b. The source / drain region 122c is also called a heavily doped region.

[0019] Similarly, the semiconductor film 132 constituting the pMOS TFT 130 also contains silicon and has a polycrystalline morphology. As described below, the semiconductor films 122 and 132 are obtained by simultaneously crystallizing amorphous silicon films formed in the same process, and therefore have substantially the same thickness and morphology. The semiconductor film 132 also has a channel region 132a overlapping with the gate electrode 134 in the direction normal to the substrate 100, a pair of low-concentration impurity regions 132b sandwiching the channel region 132a, and a pair of source / drain regions (also called high-concentration impurity regions) 132c sandwiching the low-concentration impurity region 132b. The channel region 132a and the low-concentration impurity regions 132b contain dopants that impart p-type conductivity as described above. However, unlike the nMOS TFT 120, the source / drain regions 132c contain fluorine ions as well as boron ions. In the semiconductor film 132, fluorine ions may be selectively contained in the source-drain region 132c without being contained in the low-concentration impurity region 132b, or may be contained in both the source-drain region 132c and the low-concentration impurity region 132b. When fluorine ions are contained in both the source-drain region 132c and the low-concentration impurity region 132b, the fluorine ion concentration may be substantially the same in the low-concentration impurity region 132b and the source-drain region 132c, or the fluorine ion concentration in the latter may be higher than that in the former. The fluorine ion concentration in the source-drain region 132c may be, for example, 1×10 18 atoms / cm 3 5x10 or more 20 atoms / cm 3 The source / drain regions 132c have a higher dopant concentration than the lightly doped regions 132b, which causes the source / drain regions 132c to exhibit higher conductivity than the lightly doped regions 132b.

[0020] (3) Gate insulating film The gate insulating film 104 is composed of one or more films containing the above-mentioned silicon-containing inorganic compound. The thickness of the gate insulating film 104 may be selected, for example, from the range of 2 nm to 200 nm. Alternatively, the gate insulating film 104 may be composed so as to contain a so-called high-k material such as hafnium silicate, nitrogen-containing hafnium silicate, hafnium oxide, nitrogen-doped hafnium aluminate, or yttrium oxide.

[0021] (4) Gate electrode The gate electrodes 124 and 134 contain a metal (zero-valent metal) such as molybdenum, tungsten, titanium, aluminum, or copper, or an alloy containing at least one of these metals, and are provided to overlap the channel regions 124a and 132a, respectively. In the nMOS TFT 120, the low-concentration impurity region 122b and the source / drain region 122c are exposed from the gate electrode 124. Similarly, in the pMOS TFT 130, the low-concentration impurity region 132b and the source / drain region 132c are exposed from the gate electrode 134. As described below, the gate electrodes 124 and 134 can exist in the same layer, so their composition and thickness are substantially the same. The thickness of the gate electrodes 124 and 134 may be, for example, 20 nm to 500 nm.

[0022] (5) Interlayer insulating film The interlayer insulating film 106 is configured to electrically insulate the pair of terminals 126, 128 from the gate electrode 124, and the pair of terminals 136, 138 from the gate electrode 134, and can be configured with one or more films containing the silicon-containing inorganic compound described above. The thickness of the interlayer insulating film 106 is also arbitrary and may be selected appropriately from the range of 100 nm to 1000 nm, for example.

[0023] (6) Terminal Like the gate electrodes 124 and 134, the pair of terminals 126 and 128 and the pair of terminals 136 and 138 also contain the above-mentioned metal or alloy and are electrically connected to the semiconductor films 122 and 132 through openings in the interlayer insulating film 106. Although not shown, portions of the terminals 126 and 128 may overlap with the gate electrode 124. Similarly, portions of the terminals 136 and 138 may overlap with the gate electrode 134. Since these terminals 126, 128, 136, and 138 can also exist in the same layer, they have substantially the same composition and thickness. The thicknesses of the terminals 126, 128, 136, and 138 may be, for example, 20 nm to 500 nm. Although not shown in FIG. 1, one of the terminals 126 and 128 is electrically connected to one of the terminals 136 and 138.

[0024] The fabrication method for the CMOS circuit 110 will be described later. Due to this fabrication method, the semiconductor films 122 and 132 constituting the nMOS TFT 120 and pMOS TFT 130 are both less damaged during dopant implantation and have fewer crystal defects. Therefore, the characteristics of the nMOS TFT 120 and pMOS TFT 130, particularly the S value indicating the subthreshold characteristics, are small. Furthermore, damage to the gate insulating film 104 caused by dopant implantation is also reduced, reducing defects at the interface between the gate insulating film 104 and the semiconductor film 122 and at the interface between the gate insulating film 104 and the semiconductor film 132. As a result, the nMOS TFT 120 and pMOS TFT 130 exhibit excellent characteristics and high reliability. Therefore, various circuits, including the CMOS circuit 110, can also exhibit excellent characteristics and high reliability.

[0025] 2. CMOS circuit fabrication method A method for fabricating the CMOS circuit 110 will now be described.

[0026] (1) Formation of semiconductor film First, an undercoat 102 is formed on a substrate 100, and then multiple island-shaped polysilicon films are formed on the undercoat 102 to form the semiconductor films 122 and 132 that constitute the nMOS TFT 120 and pMOS TFT 130, respectively (FIG. 2). Since the steps up to this point can be performed using known methods, detailed explanations will be omitted. Briefly, the undercoat 102 is formed on the substrate 100 using a chemical vapor deposition (CVD) method, sputtering method, or the like. Then, an amorphous silicon film is formed on the undercoat 102 using a CVD method. The amorphous silicon film is subjected to a heat treatment or laser irradiation, which converts the amorphous silicon film into a polysilicon film. The polysilicon film is then patterned by photolithography to obtain the semiconductor films 122 and 132.

[0027] (2) Formation of the channel region Thereafter, the semiconductor films 122 and 132 are p-doped (FIG. 3). In this process, a mass-separated ion implanter is used to implant boron ions (B + ) and aluminum ions (Al 3+ ) may be implanted into the semiconductor films 122 and 132. When the dopant is boron ions, the dose is, for example, 1×10 11 atoms / cm 2 More than 1×10 13 atoms / cm 2 Thereafter, the semiconductor film 132 is protected by a resist film 140 (FIG. 4), and a dopant that imparts p-type conductivity, such as boron ions, is further implanted into the semiconductor film 122 that provides the nMOS TFT 120 (FIG. 5). The dose at this time is, for example, 5×10 when the dopant is boron ions. 11 atoms / cm 2 5x10 or more 12 atoms / cm 2 The resist film 140 is then removed by ashing or the like. The semiconductor films 122 and 132 may be heat-treated to activate the doped ions. Through the above steps, the semiconductor films 122 and 132 have the compositions of the channel regions 122a and 132a, respectively.

[0028] (3) Formation of source and drain regions Subsequently, source / drain regions 122c and 132c are formed in the semiconductor films 122 and 132, respectively. Specifically, as shown in FIG. 6, a resist film 142 is formed to cover the entire semiconductor film 132 and further cover a portion of the semiconductor film 122. The resist film 142 is provided on the semiconductor film 122 so as to expose the portions where the source / drain regions 122c will be formed. As a result, the resist film 142 exposes both ends of the semiconductor film 122 and masks the regions sandwiched between these ends and the entire semiconductor film 132.

[0029] Thereafter, an ion implantation apparatus is used to implant a dopant that imparts n-type conductivity, such as phosphorus ions (FIG. 6). As a result, the dopant is selectively and directly implanted into both ends of the semiconductor film 122 exposed from the resist film 142, without going through other structures (e.g., the gate insulating film 104), resulting in the formation of a pair of source / drain regions 122c sandwiching a channel region 122a (FIG. 7). Thereafter, the resist film 142 is removed, and a heat treatment is performed, if necessary, to activate the dopant.

[0030] 8, a resist film 144 is formed to cover the entire semiconductor film 122 and to cover a portion of the semiconductor film 132. The resist film 144 is provided on the semiconductor film 132 so as to expose the portions where the source-drain regions 132c will be formed. As a result, the resist film 144 exposes both ends of the semiconductor film 132 and masks the regions sandwiched between these ends and the entire semiconductor film 122.

[0031] Then, using an ion implanter, a dopant that imparts p-type conductivity is implanted (Figure 8). The dopant used at this time is an ion containing boron and fluorine, specifically BF + and / or BF2 + , BF3 +In this manner, dopants are selectively and directly implanted into both ends of the semiconductor film 132 exposed from the resist film 144 without going through other structures (e.g., the gate insulating film 104, etc.), resulting in the formation of a pair of source-drain regions 132c sandwiching a channel region 132a (FIG. 9). The source-drain regions 132c contain fluorine ions as well as boron ions. Note that during the ion implantation, dopants may also be implanted into the undercoat 102 exposed from the semiconductor film 132. As a result, boron ions and / or fluorine ions may also be contained in the undercoat 102. The resist film 144 is then removed by ashing or the like. If necessary, a heat treatment may be performed to activate the dopants.

[0032] In the above description, the source / drain region 122c is formed first, and then the source / drain region 132c is formed, but the source / drain region 132c may be formed first, and then the source / drain region 122c may be formed.

[0033] As described above, in the doping for forming the source / drain regions 122c and 132c, ions are directly implanted into the semiconductor films 122 and 132 without passing through other components such as the gate insulating film 104, so the dose can be made small. For example, the dose can be made small by 1×10 14 atoms / cm 2 More than 1×10 15 atoms / cm 2Ion implantation can be performed as follows. Furthermore, because ion implantation is performed directly, the ion acceleration voltage can be kept low, thereby suppressing damage to the semiconductor films 122 and 132 due to ion implantation. Furthermore, because the gate insulating film 104 is not formed in this process, defect formation at the interface between the gate insulating film 104 and the semiconductor film 122 and at the interface between the gate insulating film 104 and the semiconductor film 132 due to ion implantation can also be ignored. These features contribute to improving the characteristics and reliability of the CMOS circuit 110. Furthermore, since the load on the ion implantation equipment is reduced and the ion implantation time can be shortened, the life of the ion implantation equipment can be extended and the frequency and cost of maintenance can be reduced. Therefore, the CMOS circuit 110 can be manufactured at low cost.

[0034] (4) Formation of gate insulating film and gate electrode Next, a gate insulating film 104 is formed to cover the semiconductor films 122 and 132, and then gate electrodes 124 and 134 are formed on the gate insulating film 104 so as to overlap the semiconductor films 122 and 132, respectively ( FIG. 10 ). The gate insulating film 104 and the gate electrodes 124 and 134 can be formed by applying known methods, and detailed descriptions thereof will be omitted. Briefly, the gate insulating film 104 may be formed by applying a CVD method using a tetraalkoxysilane, such as tetraethoxysilane, as a raw material. The gate electrodes 124 and 134 may be formed by forming a film containing the above-described metal or alloy on the gate insulating film 104 using a CVD method or a sputtering method, and then patterning the film by photolithography. The gate electrode 124 does not overlap the source / drain regions 122c, and is provided so as to be separated from the source / drain regions 122c when viewed from the top of the substrate 100. Similarly, the gate electrode 134 does not overlap the source / drain region 132c, and is provided so as to be spaced apart from the source / drain region 132c when viewed from above the substrate 100.

[0035] (5) Formation of low-concentration impurity regions After this, low-concentration impurity regions 122b and 132b are formed. Specifically, as shown in FIG. 11, a resist film 146 is formed to cover the semiconductor film 132, and a dopant that imparts n-type conductivity is implanted into the semiconductor film 132 through the gate insulating film 104 using an ion implanter. At this time, since the gate electrode 124 also functions as a mask, the dopant is implanted not only into the source / drain region 122c but also into the region overlapping with the gate electrode 124 (i.e., the channel region 122a) and between the source / drain region 122c. As a result, together with the channel region 122a, low-concentration impurity regions 122b, which have a lower ion concentration than the source / drain region 122c, are formed between the channel region 122a and the source / drain region 122c (FIG. 12). The dopant used at this time may be the same as or different from the dopant used to form the source / drain region 122c.

[0036] Thereafter, the resist film 146 is removed, and a resist film 148 is formed to cover the semiconductor film 122. Furthermore, using an ion implantation device, a dopant that imparts p-type conductivity is implanted into the semiconductor film 132 through the gate insulating film 104 (FIG. 13). At this time, since the gate electrode 134 also functions as a mask, the dopant is implanted not only into the source / drain region 132c, but also into the region overlapping with the gate electrode 134 (i.e., the channel region 132a) and between the source / drain region 132c. The dopant used here may be the same as or different from the dopant used to form the source / drain region 132c. Therefore, the dopant may be boron ions or aluminum ions, or BF + or BF2 + , BF3 + By the above process, the channel region 132a and the low-concentration impurity regions 132b, which have a lower ion concentration than the source / drain regions 132c, are formed between the channel region 132a and the source / drain regions 132c (FIG. 14). Thereafter, the resist film 148 is removed.

[0037] In the above description, the low-concentration impurity region 122b is formed after the low-concentration impurity region 132b, but the order of their formation is not limited thereto, and the latter may be formed first, followed by the former. Furthermore, if necessary, a heat treatment may be performed to activate the dopant.

[0038] (6) Formation of interlayer insulating film and terminals Thereafter, the interlayer insulating film 106 and the terminals 126, 128, 136, and 138 are formed, thereby completing the CMOS circuit 110 shown in FIG. The interlayer insulating film 106 and the terminals 126, 128, 136, and 138 can be formed using known methods, and therefore detailed description thereof will be omitted. Briefly, the interlayer insulating film 106 is formed using a CVD method so as to cover the gate electrodes 124 and 134 and the gate insulating film 104. The interlayer insulating film 106 and the gate insulating film 104 are then etched to form openings that expose portions of the source / drain regions 122c and 132c. Furthermore, a metal film containing the above-described metal or alloy is formed on the interlayer insulating film 106 to fill the openings, and the metal film is then processed by photolithography to form the terminals 126, 128, 136, and 138.

[0039] As described above, in the method for forming the CMOS circuit 110 according to one embodiment of the present invention, ions are implanted into the semiconductor films 122 and 132 without passing through the gate insulating film 104 during doping to form the source / drain regions 122c and 132c. This reduces the acceleration voltage and dose of dopant ions, thereby reducing ion implantation damage to the semiconductor films 122 and 132. Furthermore, because doping through the gate insulating film 104 is limited to the process of forming the low-concentration impurity regions 122b and 132b, the probability of defect generation at the interface between the gate insulating film 104 and the semiconductor film 122 or the interface between the gate insulating film 104 and the semiconductor film 132 is low. These features make it possible to provide an nMOS TFT 120, a pMOS TFT 130, and a CMOS circuit 110 including these TFTs, which have excellent characteristics and high reliability.

[0040] Second Embodiment In this embodiment, an electronic device including the CMOS circuit 110 described in the first embodiment will be described. Descriptions of configurations that are the same as or similar to the configuration described in the first embodiment may be omitted.

[0041] There are no restrictions on the electronic device that includes the CMOS circuit 110, and examples thereof include display devices such as liquid crystal display devices and electroluminescent display devices, and photoelectric conversion devices exemplified by imaging devices. Hereinafter, an electroluminescent display device in which organic electroluminescent elements are provided as display elements will be described as an example of a display device.

[0042] FIG. 15 shows a schematic top view of a display device 200, an electronic device according to an embodiment of the present invention. As shown in FIG. 15, the display device 200 includes a substrate 202 on which various patterned insulating films, semiconductor films, and conductive films are laminated. By appropriately laminating these films, a plurality of pixels 220 and drive circuits for driving the pixels 220 (scanning line drive circuit 204, signal line drive circuit 206), etc., are formed on the substrate 202. A counter substrate (not shown in FIG. 15) is provided on the pixels 220, the scanning line drive circuit 204, and the signal line drive circuit 206, and the pixels 220, the scanning line drive circuit 204, and the signal line drive circuit 206 are sealed and protected by the substrate 202 and the counter substrate. A plurality of terminals 208 formed of conductive films are provided on the substrate 202, and the terminals 208 are electrically connected to an external circuit (not shown) via a connector 210, such as a flexible printed circuit (FPC) board. Various signals and power sources for displaying images are supplied from an external circuit to the scanning line driving circuit 204 and the signal line driving circuit 206 via terminals 208. Note that either the scanning line driving circuit 204 or the signal line driving circuit 206, or both, do not need to be formed directly on the substrate 202; a driving circuit formed on a substrate (such as a semiconductor substrate) different from the substrate 202 may be provided on the substrate 202 or a connector.

[0043] The CMOS circuit 110 may be incorporated into any of the scanning line driving circuit 204, the signal line driving circuit 206, and the pixel 220. As an example, FIG. 16 shows a schematic end view of a portion of a pixel 220 incorporating the CMOS circuit 110. As shown in FIG. 16, an undercoat 102 is provided on a substrate 202 corresponding to the substrate 100, and the CMOS circuit 110 is provided on the undercoat 102. A planarization film 224 is provided on the CMOS circuit 110 to absorb irregularities caused by the CMOS circuit 110 and provide a flat surface. As an optional configuration, a protective insulating film 222 may be provided between the CMOS circuit 110 and the planarization film 224 to prevent impurities from entering through the planarization film 224.

[0044] An opening exposing one terminal 128 of the nMOS TFT 120 is formed in the planarization film 224 and the protective insulating film 222, and a pixel electrode 240 is electrically connected to the terminal 128 via this opening either directly or via a connection electrode 226 of any configuration. In each pixel 220, an additional capacitance electrode 230 may be provided on the planarization film 224, and the pixel electrode 240 may be disposed thereon via a capacitance insulating film 232. This allows an additional capacitance to be formed by the additional capacitance electrode 230, the capacitance insulating film 232, and the pixel electrode 240, and by using this additional capacitance, the potential of various signals such as video signals supplied from the signal line driving circuit 206 can be more reliably maintained.

[0045] The organic electroluminescent element, which is a display element, is composed of a pixel electrode 240, a common electrode 250 on the pixel electrode 240, and multiple functional layers between them. There is no limit to the number or type of functional layers, and a charge injection layer, a charge transport layer, a charge blocking layer, an exciton blocking layer, an emissive layer, etc. may be used as appropriate. For ease of viewing, Figure 15 shows a hole transport layer 242, an emissive layer 244, and an electron transport layer 246. Note that a bank 228 is provided at the end of the pixel electrode 240, which electrically insulates adjacent pixels 220 and prevents disconnection of the functional layers.

[0046] A sealing film 260 for protecting the organic electroluminescent element can be provided on the organic electroluminescent element. A light-shielding film 262 for covering the gap between adjacent pixels 220, an overcoat 264 for covering the light-shielding film 262, and the like can be provided on the opposing substrate 212.

[0047] As described in the first embodiment, the CMOS circuit 110 exhibits excellent characteristics and high reliability, and therefore, by incorporating the CMOS circuit 110 into the scanning line driving circuit 204 and / or the signal line driving circuit 206, the display device 200 can achieve a high operating speed. Furthermore, by incorporating the CMOS circuit 110 into the pixels 220, a circuit with excellent switching characteristics can be constructed in each pixel 220. [Example]

[0048] In the following example, a pMOS TFT included in a CMOS circuit according to one embodiment of the present invention was fabricated, and the results of evaluating its characteristics will be described.

[0049] 1. Fabrication of pMOS TFTs The pMOS TFT was fabricated by the method described in the first embodiment. Specifically, a silicon nitride film (50 nm) and a silicon oxide film (100 nm) were sequentially formed on a glass substrate using the CVD method to form an undercoat, and an amorphous silicon film (50 nm) was then formed on top of that using the CVD method. The amorphous silicon was shaped into a rectangular shape by photolithography. A linearly processed excimer laser was irradiated onto the shaped amorphous silicon to form a semiconductor film containing polysilicon. Then, an ion implanter was used to implant boron ions with an energy of 5 keV at a dose of 1 × 10 12 atoms / cm 2 The semiconductor film was then implanted with ions so that the following condition was met, and then heat treatment was carried out.

[0050] Subsequently, a resist film is formed on the semiconductor film so as to expose both ends of the semiconductor film, and an ion implantation apparatus is used to implant BF2 with an energy of 10 keV onto both ends exposed from the resist film. + Dose amount 5 x 1014 atoms / cm 2 After removing the resist film, heat treatment was performed, and then a silicon oxide film with a thickness of 100 nm was formed as a gate insulating film using the CVD method. Furthermore, a gate electrode containing an alloy of molybdenum and tantalum was formed with a thickness of 250 nm on the gate insulating film. After that, using the gate electrode as a mask, boron ions with an energy of 52 keV were implanted into the semiconductor film at a dose of 3 × 10 13 atoms / cm 2 The mixture was poured so that the temperature became 100°C, and then heat treatment was carried out.

[0051] After that, a silicon oxide film was formed as an interlayer insulating film by CVD to cover the gate electrode and gate insulating film. The interlayer insulating film was dry etched to form openings, and a pair of terminals containing an alloy of molybdenum and tantalum was formed on the openings to fabricate the pMOS TFT of this example.

[0052] 2. Preparation of Comparative Example As a comparative example, a thin film transistor having the same structure as the pMOS TFT of the example was fabricated. However, unlike the example, after the first boron ion doping, a gate insulating film and a gate electrode were formed, and then two boron ion dopings were performed. Specifically, as shown in FIG. 17, a semiconductor film 150 containing polysilicon formed on an undercoat 102 provided on a substrate 100, which is a glass substrate as in the example, was doped with boron ions having an energy of 5 keV at a dose of 1×10 using an ion implantation device. 12 atoms / cm 2 After the heat treatment, a silicon oxide film having a thickness of 100 nm was formed as the gate insulating film 104 by using the CVD method, and a gate electrode 152 containing an alloy of molybdenum and tantalum was formed on top of the silicon oxide film. After that, using the gate electrode 124 as a mask, boron ions having an energy of 52 keV were implanted into the semiconductor film 150 at a dose of 3×10 13 atoms / cm 2 At this stage, a channel region 150a is formed in the region overlapping with the gate electrode 124.

[0053] 18, a resist film 154 is formed to cover the gate electrode 124 and a part of the portion exposed from the gate electrode 152, and a high dose (3×10 15 atoms / cm 2 ) was implanted. As a result, source / drain regions 150c were formed in the portions exposed from the resist film 154, and low-concentration impurity regions 150b were formed in the regions covered by the resist film 154 but not overlapping with the gate electrode 152 (i.e., the regions sandwiched between the channel region 150a and the source / drain regions 150c). After removing the resist film 154, a heat treatment was performed to obtain a pMOS TFT of the comparative example.

[0054] 3. Evaluation V of pMOS TFTs of the comparative example and the example g -I d Curve (Source-Drain Voltage (V SD 19A and 19B, respectively. These results show that the S value of the example is improved compared to the comparative example.

[0055] The above results show that by applying the method for fabricating a CMOS circuit according to one embodiment of the present invention, it is possible to provide a pMOS TFT having excellent switching characteristics.

[0056] The above-described embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies the design of a display device of each embodiment, or adds or omits processes or modifies conditions, such a display device is included in the scope of the present invention as long as it includes the gist of the present invention.

[0057] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0058] 100: substrate, 102: undercoat, 104: gate insulating film, 106: interlayer insulating film, 110: circuit, 120: nMOS TFT, 122: semiconductor film, 122a: channel region, 122b: low concentration impurity region, 122c: source / drain region, 124: gate electrode, 124a: channel region, 126: terminal, 128: terminal, 130: pMOS TFT, 132: semiconductor film, 132a: channel region, 132b: low concentration impurity region, 132c: source / drain region, 134: gate electrode, 136: terminal, 138: terminal, 140: resist film, 142: resist film, 144: resist film, 146: resist film, 148: resist film resist film, 150: semiconductor film, 150a: channel region, 150b: low concentration impurity region, 150c: source / drain region, 152: gate electrode, 154: resist film, 200: display device, 202: substrate, 204: scanning line driving circuit, 206: signal line driving circuit, 208: terminal, 210: connector, 212: opposing substrate, 220: pixel, 222: protective insulating film, 224: planarizing film, 226: connecting electrode, 228: bank, 230: storage capacitor electrode, 232: capacitor insulating film, 240: pixel electrode, 242: hole transport layer, 244: light emitting layer, 246: electron transport layer, 250: common electrode, 260: sealing film, 262: light shielding film, 264: overcoat

Claims

1. Including an n-type metal oxide semiconductor thin film transistor and a p-type metal oxide semiconductor thin film transistor, Each of the n-type metal oxide semiconductor thin film transistor and the p-type metal oxide semiconductor thin film transistor is Semiconductor film, a gate insulating film on the semiconductor film; The gate electrode on the gate insulating film an interlayer insulating film on the gate electrode; and a pair of terminals located on the interlayer insulating film and electrically connected to the semiconductor film; The semiconductor film of the p-type metal oxide semiconductor thin film transistor includes fluorine ions.

2. In each of the n-type metal oxide semiconductor thin film transistor and the p-type metal oxide semiconductor thin film transistor, the semiconductor film is a channel region overlapping the gate electrode; a pair of low-concentration impurity regions sandwiching the channel region; 2. The complementary metal oxide semiconductor circuit of claim 1, further comprising a pair of source / drain regions sandwiching said pair of lightly doped regions.

3. The concentration of the fluorine ions in the semiconductor film of the p-type metal oxide semiconductor thin film transistor is 1×10 １５ atoms / cm ３ 1x10 or more ２０ atoms / cm ３ 2. The complementary metal oxide semiconductor circuit of claim 1, wherein:

4. 3. The complementary metal oxide semiconductor circuit of claim 2, wherein the fluorine ions are selectively contained in the source / drain regions of the p-type metal oxide semiconductor thin film transistor.

5. Further comprising an undercoat below the n-type metal oxide semiconductor thin film transistor and the p-type metal oxide semiconductor thin film transistor; 2. The complementary metal oxide semiconductor circuit of claim 1, wherein said undercoat comprises said fluorine ions.

6. a complementary metal oxide semiconductor circuit; the complementary metal oxide semiconductor circuit includes an n-type metal oxide semiconductor thin film transistor and a p-type metal oxide semiconductor thin film transistor; Each of the n-type metal oxide semiconductor thin film transistor and the p-type metal oxide semiconductor thin film transistor is Semiconductor film, a gate insulating film on the semiconductor film; The gate electrode on the gate insulating film an interlayer insulating film on the gate electrode; and a pair of terminals located on the interlayer insulating film and electrically connected to the semiconductor film; The electronic device, wherein the semiconductor film of the p-type metal oxide semiconductor thin film transistor contains fluorine ions.

7. In each of the n-type metal oxide semiconductor thin film transistor and the p-type metal oxide semiconductor thin film transistor, the semiconductor film is a channel region overlapping the gate electrode; a pair of low-concentration impurity regions sandwiching the channel region; 7. The electronic device according to claim 6, further comprising source and drain regions sandwiching the pair of low concentration impurity regions.

8. The concentration of the fluorine ions in the semiconductor film of the p-type metal oxide semiconductor thin film transistor is 1×10 １５ atoms / cm ３ 1x10 or more ２０ atoms / cm ３ 7. The electronic device of claim 6, wherein:

9. 8. The electronic device according to claim 7, wherein the fluorine ions are selectively contained in the source / drain regions of the p-type metal oxide semiconductor thin film transistor.

10. Further comprising an undercoat below the n-type metal oxide semiconductor thin film transistor and the p-type metal oxide semiconductor thin film transistor; The electronic device of claim 6 , wherein the undercoat contains the fluorine ions.

11. The electronic device according to claim 6 , wherein the electronic device is a display device.

12. forming an undercoat on the substrate; forming a first semiconductor film and a second semiconductor film on the undercoat; doping the end portions of the first semiconductor film with a first dopant that imparts n-type conductivity while masking a region between the end portions of the second semiconductor film and the first semiconductor film; doping the end portions of the second semiconductor film with a second dopant that imparts p-type conductivity while masking a region between the end portions of the first semiconductor film and the second semiconductor film; forming a gate insulating film on the first semiconductor film and the second semiconductor film; forming a first gate electrode on the gate insulating film, the first gate electrode overlapping the first semiconductor film and exposing both end portions of the first semiconductor film, and a second gate electrode overlapping the second semiconductor film and exposing both end portions of the first semiconductor film; forming an interlayer insulating film covering the first gate electrode and the second gate electrode; and forming a pair of terminals electrically connected to the first semiconductor film and a pair of terminals electrically connected to the second semiconductor film on the interlayer insulating film.

13. The method of claim 12 , wherein the second dopant comprises boron and fluorine.

14. The second dopant is BF ２＋ Ion and BF ２ ＋ The method of claim 12 , further comprising at least one of:

15. doping the first semiconductor film with a third dopant that imparts n-type conductivity using the first gate electrode as a mask; and 13. The method of claim 12, further comprising doping the second semiconductor film with a fourth dopant that imparts p-type conductivity using the second gate electrode as a mask.

16. 16. The method of claim 15, wherein the second dopant and the fourth dopant are the same.

17. 13. The method of claim 12, further comprising doping the first semiconductor film and the second dopant with a fifth dopant that imparts p-type conductivity prior to the doping with the first dopant and the second dopant.

18. The doping with the second dopant is carried out so that the concentration of fluorine ions in the second semiconductor film is 1×10 １５ atoms / cm ３ 1x10 or more ２０ atoms / cm ３ 14. The method of claim 13, wherein the method is carried out as follows:

Images